3 * BRIEF MODULE DESCRIPTION
4 * The Descriptor Based DMA channel manager that first appeared
5 * on the Au1550. I started with dma.c, but I think all that is
6 * left is this initial comment :-)
8 * Copyright 2004 Embedded Edge, LLC
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
33 #include <linux/kernel.h>
34 #include <linux/errno.h>
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <linux/spinlock.h>
38 #include <linux/string.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/module.h>
42 #include <asm/mach-au1x00/au1000.h>
43 #include <asm/mach-au1x00/au1xxx_dbdma.h>
44 #include <asm/system.h>
47 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
50 * The Descriptor Based DMA supports up to 16 channels.
52 * There are 32 devices defined. We keep an internal structure
53 * of devices using these channels, along with additional
56 * We allocate the descriptors and allow access to them through various
57 * functions. The drivers allocate the data buffers and assign them
60 static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock);
62 /* I couldn't find a macro that did this......
64 #define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1))
66 static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE;
67 static int dbdma_initialized=0;
68 static void au1xxx_dbdma_init(void);
70 static dbdev_tab_t dbdev_tab[] = {
71 #ifdef CONFIG_SOC_AU1550
73 { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
74 { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
75 { DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 },
76 { DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 },
79 { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
80 { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
81 { DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 },
82 { DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 },
85 { DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 },
86 { DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 },
87 { DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 },
88 { DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 },
89 { DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 },
90 { DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 },
93 { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },
94 { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },
97 { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 },
98 { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },
101 { DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 },
102 { DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 },
105 { DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 },
106 { DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 },
108 { DSCR_CMD0_PCI_WRITE, 0, 0, 0, 0x00000000, 0, 0 }, /* PCI */
109 { DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */
112 { DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
113 { DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
116 { DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
117 { DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
119 #endif /* CONFIG_SOC_AU1550 */
121 #ifdef CONFIG_SOC_AU1200
122 { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
123 { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
124 { DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 },
125 { DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 },
127 { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
128 { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
130 { DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
131 { DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
132 { DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
133 { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
135 { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },
136 { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },
137 { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 },
138 { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 },
140 { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },
141 { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },
143 { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 },
144 { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x11a0001c, 0, 0 },
145 { DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
147 { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 },
148 { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x11b0001c, 0, 0 },
149 { DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
151 { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 },
152 { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 },
153 { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 },
154 { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
156 { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
158 #endif // CONFIG_SOC_AU1200
160 { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
161 { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
163 /* Provide 16 user definable device types */
164 { 0, 0, 0, 0, 0, 0, 0 },
165 { 0, 0, 0, 0, 0, 0, 0 },
166 { 0, 0, 0, 0, 0, 0, 0 },
167 { 0, 0, 0, 0, 0, 0, 0 },
168 { 0, 0, 0, 0, 0, 0, 0 },
169 { 0, 0, 0, 0, 0, 0, 0 },
170 { 0, 0, 0, 0, 0, 0, 0 },
171 { 0, 0, 0, 0, 0, 0, 0 },
172 { 0, 0, 0, 0, 0, 0, 0 },
173 { 0, 0, 0, 0, 0, 0, 0 },
174 { 0, 0, 0, 0, 0, 0, 0 },
175 { 0, 0, 0, 0, 0, 0, 0 },
176 { 0, 0, 0, 0, 0, 0, 0 },
177 { 0, 0, 0, 0, 0, 0, 0 },
178 { 0, 0, 0, 0, 0, 0, 0 },
179 { 0, 0, 0, 0, 0, 0, 0 },
182 #define DBDEV_TAB_SIZE (sizeof(dbdev_tab) / sizeof(dbdev_tab_t))
184 static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS];
187 find_dbdev_id (u32 id)
191 for (i = 0; i < DBDEV_TAB_SIZE; ++i) {
199 void * au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp)
201 return phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
203 EXPORT_SYMBOL(au1xxx_ddma_get_nextptr_virt);
206 au1xxx_ddma_add_device(dbdev_tab_t *dev)
210 static u16 new_id=0x1000;
212 p = find_dbdev_id(0);
215 memcpy(p, dev, sizeof(dbdev_tab_t));
216 p->dev_id = DSCR_DEV2CUSTOM_ID(new_id,dev->dev_id);
220 printk("add_device: id:%x flags:%x padd:%x\n",
221 p->dev_id, p->dev_flags, p->dev_physaddr );
227 EXPORT_SYMBOL(au1xxx_ddma_add_device);
229 /* Allocate a channel and return a non-zero descriptor if successful.
232 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
233 void (*callback)(int, void *, struct pt_regs *), void *callparam)
239 dbdev_tab_t *stp, *dtp;
243 /* We do the intialization on the first channel allocation.
244 * We have to wait because of the interrupt handler initialization
245 * which can't be done successfully during board set up.
247 if (!dbdma_initialized)
249 dbdma_initialized = 1;
251 if ((stp = find_dbdev_id(srcid)) == NULL) return 0;
252 if ((dtp = find_dbdev_id(destid)) == NULL) return 0;
257 /* Check to see if we can get both channels.
259 spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
260 if (!(stp->dev_flags & DEV_FLAGS_INUSE) ||
261 (stp->dev_flags & DEV_FLAGS_ANYUSE)) {
263 stp->dev_flags |= DEV_FLAGS_INUSE;
264 if (!(dtp->dev_flags & DEV_FLAGS_INUSE) ||
265 (dtp->dev_flags & DEV_FLAGS_ANYUSE)) {
266 /* Got destination */
267 dtp->dev_flags |= DEV_FLAGS_INUSE;
270 /* Can't get dest. Release src.
272 stp->dev_flags &= ~DEV_FLAGS_INUSE;
279 spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
282 /* Let's see if we can allocate a channel for it.
286 spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
287 for (i=0; i<NUM_DBDMA_CHANS; i++) {
288 if (chan_tab_ptr[i] == NULL) {
289 /* If kmalloc fails, it is caught below same
290 * as a channel not available.
292 ctp = kmalloc(sizeof(chan_tab_t), GFP_ATOMIC);
293 chan_tab_ptr[i] = ctp;
297 spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
300 memset(ctp, 0, sizeof(chan_tab_t));
301 ctp->chan_index = chan = i;
302 dcp = DDMA_CHANNEL_BASE;
303 dcp += (0x0100 * chan);
304 ctp->chan_ptr = (au1x_dma_chan_t *)dcp;
305 cp = (au1x_dma_chan_t *)dcp;
307 ctp->chan_dest = dtp;
308 ctp->chan_callback = callback;
309 ctp->chan_callparam = callparam;
311 /* Initialize channel configuration.
314 if (stp->dev_intlevel)
316 if (stp->dev_intpolarity)
318 if (dtp->dev_intlevel)
320 if (dtp->dev_intpolarity)
322 if ((stp->dev_flags & DEV_FLAGS_SYNC) ||
323 (dtp->dev_flags & DEV_FLAGS_SYNC))
328 /* Return a non-zero value that can be used to
329 * find the channel information in subsequent
332 rv = (u32)(&chan_tab_ptr[chan]);
335 /* Release devices */
336 stp->dev_flags &= ~DEV_FLAGS_INUSE;
337 dtp->dev_flags &= ~DEV_FLAGS_INUSE;
342 EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc);
344 /* Set the device width if source or destination is a FIFO.
345 * Should be 8, 16, or 32 bits.
348 au1xxx_dbdma_set_devwidth(u32 chanid, int bits)
352 dbdev_tab_t *stp, *dtp;
354 ctp = *((chan_tab_t **)chanid);
356 dtp = ctp->chan_dest;
359 if (stp->dev_flags & DEV_FLAGS_IN) { /* Source in fifo */
360 rv = stp->dev_devwidth;
361 stp->dev_devwidth = bits;
363 if (dtp->dev_flags & DEV_FLAGS_OUT) { /* Destination out fifo */
364 rv = dtp->dev_devwidth;
365 dtp->dev_devwidth = bits;
370 EXPORT_SYMBOL(au1xxx_dbdma_set_devwidth);
372 /* Allocate a descriptor ring, initializing as much as possible.
375 au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
378 u32 desc_base, srcid, destid;
379 u32 cmd0, cmd1, src1, dest1;
382 dbdev_tab_t *stp, *dtp;
383 au1x_ddma_desc_t *dp;
385 /* I guess we could check this to be within the
386 * range of the table......
388 ctp = *((chan_tab_t **)chanid);
390 dtp = ctp->chan_dest;
392 /* The descriptors must be 32-byte aligned. There is a
393 * possibility the allocation will give us such an address,
394 * and if we try that first we are likely to not waste larger
397 desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t),
402 if (desc_base & 0x1f) {
403 /* Lost....do it again, allocate extra, and round
406 kfree((const void *)desc_base);
407 i = entries * sizeof(au1x_ddma_desc_t);
408 i += (sizeof(au1x_ddma_desc_t) - 1);
409 if ((desc_base = (u32)kmalloc(i, GFP_KERNEL|GFP_DMA)) == 0)
412 desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t));
414 dp = (au1x_ddma_desc_t *)desc_base;
416 /* Keep track of the base descriptor.
418 ctp->chan_desc_base = dp;
420 /* Initialize the rings with as much information as we know.
423 destid = dtp->dev_id;
425 cmd0 = cmd1 = src1 = dest1 = 0;
428 cmd0 |= DSCR_CMD0_SID(srcid);
429 cmd0 |= DSCR_CMD0_DID(destid);
430 cmd0 |= DSCR_CMD0_IE | DSCR_CMD0_CV;
431 cmd0 |= DSCR_CMD0_ST(DSCR_CMD0_ST_NOCHANGE);
433 /* is it mem to mem transfer? */
434 if(((DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_THROTTLE) || (DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_ALWAYS)) &&
435 ((DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_THROTTLE) || (DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_ALWAYS))) {
436 cmd0 |= DSCR_CMD0_MEM;
439 switch (stp->dev_devwidth) {
441 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_BYTE);
444 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_HALFWORD);
448 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_WORD);
452 switch (dtp->dev_devwidth) {
454 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_BYTE);
457 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_HALFWORD);
461 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_WORD);
465 /* If the device is marked as an in/out FIFO, ensure it is
468 if (stp->dev_flags & DEV_FLAGS_IN)
469 cmd0 |= DSCR_CMD0_SN; /* Source in fifo */
470 if (dtp->dev_flags & DEV_FLAGS_OUT)
471 cmd0 |= DSCR_CMD0_DN; /* Destination out fifo */
473 /* Set up source1. For now, assume no stride and increment.
474 * A channel attribute update can change this later.
476 switch (stp->dev_tsize) {
478 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE1);
481 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE2);
484 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE4);
488 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE8);
492 /* If source input is fifo, set static address.
494 if (stp->dev_flags & DEV_FLAGS_IN) {
495 if ( stp->dev_flags & DEV_FLAGS_BURSTABLE )
496 src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST);
498 src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC);
501 if (stp->dev_physaddr)
502 src0 = stp->dev_physaddr;
504 /* Set up dest1. For now, assume no stride and increment.
505 * A channel attribute update can change this later.
507 switch (dtp->dev_tsize) {
509 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE1);
512 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE2);
515 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE4);
519 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE8);
523 /* If destination output is fifo, set static address.
525 if (dtp->dev_flags & DEV_FLAGS_OUT) {
526 if ( dtp->dev_flags & DEV_FLAGS_BURSTABLE )
527 dest1 |= DSCR_DEST1_DAM(DSCR_xAM_BURST);
529 dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC);
531 if (dtp->dev_physaddr)
532 dest0 = dtp->dev_physaddr;
535 printk("did:%x sid:%x cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
536 dtp->dev_id, stp->dev_id, cmd0, cmd1, src0, src1, dest0, dest1 );
538 for (i=0; i<entries; i++) {
539 dp->dscr_cmd0 = cmd0;
540 dp->dscr_cmd1 = cmd1;
541 dp->dscr_source0 = src0;
542 dp->dscr_source1 = src1;
543 dp->dscr_dest0 = dest0;
544 dp->dscr_dest1 = dest1;
548 dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(dp + 1));
552 /* Make last descrptor point to the first.
555 dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(ctp->chan_desc_base));
556 ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
558 return (u32)(ctp->chan_desc_base);
560 EXPORT_SYMBOL(au1xxx_dbdma_ring_alloc);
562 /* Put a source buffer into the DMA ring.
563 * This updates the source pointer and byte count. Normally used
564 * for memory to fifo transfers.
567 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags)
570 au1x_ddma_desc_t *dp;
572 /* I guess we could check this to be within the
573 * range of the table......
575 ctp = *((chan_tab_t **)chanid);
577 /* We should have multiple callers for a particular channel,
578 * an interrupt doesn't affect this pointer nor the descriptor,
579 * so no locking should be needed.
583 /* If the descriptor is valid, we are way ahead of the DMA
584 * engine, so just return an error condition.
586 if (dp->dscr_cmd0 & DSCR_CMD0_V) {
590 /* Load up buffer address and byte count.
592 dp->dscr_source0 = virt_to_phys(buf);
593 dp->dscr_cmd1 = nbytes;
595 if (flags & DDMA_FLAGS_IE)
596 dp->dscr_cmd0 |= DSCR_CMD0_IE;
597 if (flags & DDMA_FLAGS_NOIE)
598 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
601 * There is an errata on the Au1200/Au1550 parts that could result
602 * in "stale" data being DMA'd. It has to do with the snoop logic on
603 * the dache eviction buffer. NONCOHERENT_IO is on by default for
604 * these parts. If it is fixedin the future, these dma_cache_inv will
605 * just be nothing more than empty macros. See io.h.
607 dma_cache_wback_inv((unsigned long)buf, nbytes);
608 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
610 dma_cache_wback_inv((unsigned long)dp, sizeof(dp));
611 ctp->chan_ptr->ddma_dbell = 0;
613 /* Get next descriptor pointer.
615 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
617 /* return something not zero.
621 EXPORT_SYMBOL(_au1xxx_dbdma_put_source);
623 /* Put a destination buffer into the DMA ring.
624 * This updates the destination pointer and byte count. Normally used
625 * to place an empty buffer into the ring for fifo to memory transfers.
628 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags)
631 au1x_ddma_desc_t *dp;
633 /* I guess we could check this to be within the
634 * range of the table......
636 ctp = *((chan_tab_t **)chanid);
638 /* We should have multiple callers for a particular channel,
639 * an interrupt doesn't affect this pointer nor the descriptor,
640 * so no locking should be needed.
644 /* If the descriptor is valid, we are way ahead of the DMA
645 * engine, so just return an error condition.
647 if (dp->dscr_cmd0 & DSCR_CMD0_V)
650 /* Load up buffer address and byte count */
653 if (flags & DDMA_FLAGS_IE)
654 dp->dscr_cmd0 |= DSCR_CMD0_IE;
655 if (flags & DDMA_FLAGS_NOIE)
656 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
658 dp->dscr_dest0 = virt_to_phys(buf);
659 dp->dscr_cmd1 = nbytes;
661 printk("cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
662 dp->dscr_cmd0, dp->dscr_cmd1, dp->dscr_source0,
663 dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1 );
666 * There is an errata on the Au1200/Au1550 parts that could result in
667 * "stale" data being DMA'd. It has to do with the snoop logic on the
668 * dache eviction buffer. NONCOHERENT_IO is on by default for these
669 * parts. If it is fixedin the future, these dma_cache_inv will just
670 * be nothing more than empty macros. See io.h.
672 dma_cache_inv((unsigned long)buf,nbytes);
673 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
675 dma_cache_wback_inv((unsigned long)dp, sizeof(dp));
676 ctp->chan_ptr->ddma_dbell = 0;
678 /* Get next descriptor pointer.
680 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
682 /* return something not zero.
686 EXPORT_SYMBOL(_au1xxx_dbdma_put_dest);
688 /* Get a destination buffer into the DMA ring.
689 * Normally used to get a full buffer from the ring during fifo
690 * to memory transfers. This does not set the valid bit, you will
691 * have to put another destination buffer to keep the DMA going.
694 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes)
697 au1x_ddma_desc_t *dp;
700 /* I guess we could check this to be within the
701 * range of the table......
703 ctp = *((chan_tab_t **)chanid);
705 /* We should have multiple callers for a particular channel,
706 * an interrupt doesn't affect this pointer nor the descriptor,
707 * so no locking should be needed.
711 /* If the descriptor is valid, we are way ahead of the DMA
712 * engine, so just return an error condition.
714 if (dp->dscr_cmd0 & DSCR_CMD0_V)
717 /* Return buffer address and byte count.
719 *buf = (void *)(phys_to_virt(dp->dscr_dest0));
720 *nbytes = dp->dscr_cmd1;
723 /* Get next descriptor pointer.
725 ctp->get_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
727 /* return something not zero.
732 EXPORT_SYMBOL_GPL(au1xxx_dbdma_get_dest);
735 au1xxx_dbdma_stop(u32 chanid)
739 int halt_timeout = 0;
741 ctp = *((chan_tab_t **)chanid);
744 cp->ddma_cfg &= ~DDMA_CFG_EN; /* Disable channel */
746 while (!(cp->ddma_stat & DDMA_STAT_H)) {
749 if (halt_timeout > 100) {
750 printk("warning: DMA channel won't halt\n");
754 /* clear current desc valid and doorbell */
755 cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V);
758 EXPORT_SYMBOL(au1xxx_dbdma_stop);
760 /* Start using the current descriptor pointer. If the dbdma encounters
761 * a not valid descriptor, it will stop. In this case, we can just
762 * continue by adding a buffer to the list and starting again.
765 au1xxx_dbdma_start(u32 chanid)
770 ctp = *((chan_tab_t **)chanid);
772 cp->ddma_desptr = virt_to_phys(ctp->cur_ptr);
773 cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */
778 EXPORT_SYMBOL(au1xxx_dbdma_start);
781 au1xxx_dbdma_reset(u32 chanid)
784 au1x_ddma_desc_t *dp;
786 au1xxx_dbdma_stop(chanid);
788 ctp = *((chan_tab_t **)chanid);
789 ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
791 /* Run through the descriptors and reset the valid indicator.
793 dp = ctp->chan_desc_base;
796 dp->dscr_cmd0 &= ~DSCR_CMD0_V;
797 /* reset our SW status -- this is used to determine
798 * if a descriptor is in use by upper level SW. Since
799 * posting can reset 'V' bit.
802 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
803 } while (dp != ctp->chan_desc_base);
805 EXPORT_SYMBOL(au1xxx_dbdma_reset);
808 au1xxx_get_dma_residue(u32 chanid)
814 ctp = *((chan_tab_t **)chanid);
817 /* This is only valid if the channel is stopped.
819 rv = cp->ddma_bytecnt;
825 EXPORT_SYMBOL_GPL(au1xxx_get_dma_residue);
828 au1xxx_dbdma_chan_free(u32 chanid)
831 dbdev_tab_t *stp, *dtp;
833 ctp = *((chan_tab_t **)chanid);
835 dtp = ctp->chan_dest;
837 au1xxx_dbdma_stop(chanid);
839 kfree((void *)ctp->chan_desc_base);
841 stp->dev_flags &= ~DEV_FLAGS_INUSE;
842 dtp->dev_flags &= ~DEV_FLAGS_INUSE;
843 chan_tab_ptr[ctp->chan_index] = NULL;
847 EXPORT_SYMBOL(au1xxx_dbdma_chan_free);
850 dbdma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
855 au1x_ddma_desc_t *dp;
858 intstat = dbdma_gptr->ddma_intstat;
860 chan_index = au_ffs(intstat) - 1;
862 ctp = chan_tab_ptr[chan_index];
871 if (ctp->chan_callback)
872 (ctp->chan_callback)(irq, ctp->chan_callparam, regs);
874 ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
875 return IRQ_RETVAL(1);
878 static void au1xxx_dbdma_init(void)
882 dbdma_gptr->ddma_config = 0;
883 dbdma_gptr->ddma_throttle = 0;
884 dbdma_gptr->ddma_inten = 0xffff;
887 #if defined(CONFIG_SOC_AU1550)
888 irq_nr = AU1550_DDMA_INT;
889 #elif defined(CONFIG_SOC_AU1200)
890 irq_nr = AU1200_DDMA_INT;
892 #error Unknown Au1x00 SOC
895 if (request_irq(irq_nr, dbdma_interrupt, SA_INTERRUPT,
896 "Au1xxx dbdma", (void *)dbdma_gptr))
897 printk("Can't get 1550 dbdma irq");
901 au1xxx_dbdma_dump(u32 chanid)
904 au1x_ddma_desc_t *dp;
905 dbdev_tab_t *stp, *dtp;
909 ctp = *((chan_tab_t **)chanid);
911 dtp = ctp->chan_dest;
914 printk("Chan %x, stp %x (dev %d) dtp %x (dev %d) \n",
915 (u32)ctp, (u32)stp, stp - dbdev_tab, (u32)dtp, dtp - dbdev_tab);
916 printk("desc base %x, get %x, put %x, cur %x\n",
917 (u32)(ctp->chan_desc_base), (u32)(ctp->get_ptr),
918 (u32)(ctp->put_ptr), (u32)(ctp->cur_ptr));
920 printk("dbdma chan %x\n", (u32)cp);
921 printk("cfg %08x, desptr %08x, statptr %08x\n",
922 cp->ddma_cfg, cp->ddma_desptr, cp->ddma_statptr);
923 printk("dbell %08x, irq %08x, stat %08x, bytecnt %08x\n",
924 cp->ddma_dbell, cp->ddma_irq, cp->ddma_stat, cp->ddma_bytecnt);
927 /* Run through the descriptors
929 dp = ctp->chan_desc_base;
932 printk("Dp[%d]= %08x, cmd0 %08x, cmd1 %08x\n",
933 i++, (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1);
934 printk("src0 %08x, src1 %08x, dest0 %08x, dest1 %08x\n",
935 dp->dscr_source0, dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1);
936 printk("stat %08x, nxtptr %08x\n",
937 dp->dscr_stat, dp->dscr_nxtptr);
938 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
939 } while (dp != ctp->chan_desc_base);
942 /* Put a descriptor into the DMA ring.
943 * This updates the source/destination pointers and byte count.
946 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr )
949 au1x_ddma_desc_t *dp;
952 /* I guess we could check this to be within the
953 * range of the table......
955 ctp = *((chan_tab_t **)chanid);
957 /* We should have multiple callers for a particular channel,
958 * an interrupt doesn't affect this pointer nor the descriptor,
959 * so no locking should be needed.
963 /* If the descriptor is valid, we are way ahead of the DMA
964 * engine, so just return an error condition.
966 if (dp->dscr_cmd0 & DSCR_CMD0_V)
969 /* Load up buffer addresses and byte count.
971 dp->dscr_dest0 = dscr->dscr_dest0;
972 dp->dscr_source0 = dscr->dscr_source0;
973 dp->dscr_dest1 = dscr->dscr_dest1;
974 dp->dscr_source1 = dscr->dscr_source1;
975 dp->dscr_cmd1 = dscr->dscr_cmd1;
976 nbytes = dscr->dscr_cmd1;
977 /* Allow the caller to specifiy if an interrupt is generated */
978 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
979 dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V;
980 ctp->chan_ptr->ddma_dbell = 0;
982 /* Get next descriptor pointer.
984 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
986 /* return something not zero.
991 #endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */