git.oblomov.eu Git - linux-2.6/blob - drivers/video/savage/savagefb_driver.c

   1 /*
   2  * linux/drivers/video/savagefb.c -- S3 Savage Framebuffer Driver
   3  *
   4  * Copyright (c) 2001-2002  Denis Oliver Kropp <dok@directfb.org>
   5  *                          Sven Neumann <neo@directfb.org>
   6  *
   7  *
   8  * Card specific code is based on XFree86's savage driver.
   9  * Framebuffer framework code is based on code of cyber2000fb and tdfxfb.
  10  *
  11  * This file is subject to the terms and conditions of the GNU General
  12  * Public License.  See the file COPYING in the main directory of this
  13  * archive for more details.
  14  *
  15  * 0.4.0 (neo)
  16  *  - hardware accelerated clear and move
  17  *
  18  * 0.3.2 (dok)
  19  *  - wait for vertical retrace before writing to cr67
  20  *    at the beginning of savagefb_set_par
  21  *  - use synchronization registers cr23 and cr26
  22  *
  23  * 0.3.1 (dok)
  24  *  - reset 3D engine
  25  *  - don't return alpha bits for 32bit format
  26  *
  27  * 0.3.0 (dok)
  28  *  - added WaitIdle functions for all Savage types
  29  *  - do WaitIdle before mode switching
  30  *  - code cleanup
  31  *
  32  * 0.2.0 (dok)
  33  *  - first working version
  34  *
  35  *
  36  * TODO
  37  * - clock validations in decode_var
  38  *
  39  * BUGS
  40  * - white margin on bootup
  41  *
  42  */
  43
  44 #include <linux/module.h>
  45 #include <linux/kernel.h>
  46 #include <linux/errno.h>
  47 #include <linux/string.h>
  48 #include <linux/mm.h>
  49 #include <linux/tty.h>
  50 #include <linux/slab.h>
  51 #include <linux/delay.h>
  52 #include <linux/fb.h>
  53 #include <linux/pci.h>
  54 #include <linux/init.h>
  55 #include <linux/console.h>
  56
  57 #include <asm/io.h>
  58 #include <asm/irq.h>
  59 #include <asm/pgtable.h>
  60 #include <asm/system.h>
  61 #include <asm/uaccess.h>
  62
  63 #ifdef CONFIG_MTRR
  64 #include <asm/mtrr.h>
  65 #endif
  66
  67 #include "savagefb.h"
  68
  69
  70 #define SAVAGEFB_VERSION "0.4.0_2.6"
  71
  72 /* --------------------------------------------------------------------- */
  73
  74
  75 static char *mode_option __devinitdata = NULL;
  76
  77 #ifdef MODULE
  78
  79 MODULE_AUTHOR("(c) 2001-2002  Denis Oliver Kropp <dok@directfb.org>");
  80 MODULE_LICENSE("GPL");
  81 MODULE_DESCRIPTION("FBDev driver for S3 Savage PCI/AGP Chips");
  82
  83 #endif
  84
  85
  86 /* --------------------------------------------------------------------- */
  87
  88 static void vgaHWSeqReset(struct savagefb_par *par, int start)
  89 {
  90         if (start)
  91                 VGAwSEQ(0x00, 0x01, par);       /* Synchronous Reset */
  92         else
  93                 VGAwSEQ(0x00, 0x03, par);       /* End Reset */
  94 }
  95
  96 static void vgaHWProtect(struct savagefb_par *par, int on)
  97 {
  98         unsigned char tmp;
  99
 100         if (on) {
 101                 /*
 102                  * Turn off screen and disable sequencer.
 103                  */
 104                 tmp = VGArSEQ(0x01, par);
 105
 106                 vgaHWSeqReset(par, 1);          /* start synchronous reset */
 107                 VGAwSEQ(0x01, tmp | 0x20, par);/* disable the display */
 108
 109                 VGAenablePalette(par);
 110         } else {
 111                 /*
 112                  * Reenable sequencer, then turn on screen.
 113                  */
 114
 115                 tmp = VGArSEQ(0x01, par);
 116
 117                 VGAwSEQ(0x01, tmp & ~0x20, par);/* reenable display */
 118                 vgaHWSeqReset(par, 0);          /* clear synchronous reset */
 119
 120                 VGAdisablePalette(par);
 121         }
 122 }
 123
 124 static void vgaHWRestore(struct savagefb_par  *par, struct savage_reg *reg)
 125 {
 126         int i;
 127
 128         VGAwMISC(reg->MiscOutReg, par);
 129
 130         for (i = 1; i < 5; i++)
 131                 VGAwSEQ(i, reg->Sequencer[i], par);
 132
 133         /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 or
 134            CRTC[17] */
 135         VGAwCR(17, reg->CRTC[17] & ~0x80, par);
 136
 137         for (i = 0; i < 25; i++)
 138                 VGAwCR(i, reg->CRTC[i], par);
 139
 140         for (i = 0; i < 9; i++)
 141                 VGAwGR(i, reg->Graphics[i], par);
 142
 143         VGAenablePalette(par);
 144
 145         for (i = 0; i < 21; i++)
 146                 VGAwATTR(i, reg->Attribute[i], par);
 147
 148         VGAdisablePalette(par);
 149 }
 150
 151 static void vgaHWInit(struct fb_var_screeninfo *var,
 152                       struct savagefb_par            *par,
 153                       struct xtimings                *timings,
 154                       struct savage_reg              *reg)
 155 {
 156         reg->MiscOutReg = 0x23;
 157
 158         if (!(timings->sync & FB_SYNC_HOR_HIGH_ACT))
 159                 reg->MiscOutReg |= 0x40;
 160
 161         if (!(timings->sync & FB_SYNC_VERT_HIGH_ACT))
 162                 reg->MiscOutReg |= 0x80;
 163
 164         /*
 165          * Time Sequencer
 166          */
 167         reg->Sequencer[0x00] = 0x00;
 168         reg->Sequencer[0x01] = 0x01;
 169         reg->Sequencer[0x02] = 0x0F;
 170         reg->Sequencer[0x03] = 0x00;          /* Font select */
 171         reg->Sequencer[0x04] = 0x0E;          /* Misc */
 172
 173         /*
 174          * CRTC Controller
 175          */
 176         reg->CRTC[0x00] = (timings->HTotal >> 3) - 5;
 177         reg->CRTC[0x01] = (timings->HDisplay >> 3) - 1;
 178         reg->CRTC[0x02] = (timings->HSyncStart >> 3) - 1;
 179         reg->CRTC[0x03] = (((timings->HSyncEnd >> 3)  - 1) & 0x1f) | 0x80;
 180         reg->CRTC[0x04] = (timings->HSyncStart >> 3);
 181         reg->CRTC[0x05] = ((((timings->HSyncEnd >> 3) - 1) & 0x20) << 2) |
 182                 (((timings->HSyncEnd >> 3)) & 0x1f);
 183         reg->CRTC[0x06] = (timings->VTotal - 2) & 0xFF;
 184         reg->CRTC[0x07] = (((timings->VTotal - 2) & 0x100) >> 8) |
 185                 (((timings->VDisplay - 1) & 0x100) >> 7) |
 186                 ((timings->VSyncStart & 0x100) >> 6) |
 187                 (((timings->VSyncStart - 1) & 0x100) >> 5) |
 188                 0x10 |
 189                 (((timings->VTotal - 2) & 0x200) >> 4) |
 190                 (((timings->VDisplay - 1) & 0x200) >> 3) |
 191                 ((timings->VSyncStart & 0x200) >> 2);
 192         reg->CRTC[0x08] = 0x00;
 193         reg->CRTC[0x09] = (((timings->VSyncStart - 1) & 0x200) >> 4) | 0x40;
 194
 195         if (timings->dblscan)
 196                 reg->CRTC[0x09] |= 0x80;
 197
 198         reg->CRTC[0x0a] = 0x00;
 199         reg->CRTC[0x0b] = 0x00;
 200         reg->CRTC[0x0c] = 0x00;
 201         reg->CRTC[0x0d] = 0x00;
 202         reg->CRTC[0x0e] = 0x00;
 203         reg->CRTC[0x0f] = 0x00;
 204         reg->CRTC[0x10] = timings->VSyncStart & 0xff;
 205         reg->CRTC[0x11] = (timings->VSyncEnd & 0x0f) | 0x20;
 206         reg->CRTC[0x12] = (timings->VDisplay - 1) & 0xff;
 207         reg->CRTC[0x13] = var->xres_virtual >> 4;
 208         reg->CRTC[0x14] = 0x00;
 209         reg->CRTC[0x15] = (timings->VSyncStart - 1) & 0xff;
 210         reg->CRTC[0x16] = (timings->VSyncEnd - 1) & 0xff;
 211         reg->CRTC[0x17] = 0xc3;
 212         reg->CRTC[0x18] = 0xff;
 213
 214         /*
 215          * are these unnecessary?
 216          * vgaHWHBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN|KGA_ENABLE_ON_ZERO);
 217          * vgaHWVBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN|KGA_ENABLE_ON_ZERO);
 218          */
 219
 220         /*
 221          * Graphics Display Controller
 222          */
 223         reg->Graphics[0x00] = 0x00;
 224         reg->Graphics[0x01] = 0x00;
 225         reg->Graphics[0x02] = 0x00;
 226         reg->Graphics[0x03] = 0x00;
 227         reg->Graphics[0x04] = 0x00;
 228         reg->Graphics[0x05] = 0x40;
 229         reg->Graphics[0x06] = 0x05;   /* only map 64k VGA memory !!!! */
 230         reg->Graphics[0x07] = 0x0F;
 231         reg->Graphics[0x08] = 0xFF;
 232
 233
 234         reg->Attribute[0x00]  = 0x00; /* standard colormap translation */
 235         reg->Attribute[0x01]  = 0x01;
 236         reg->Attribute[0x02]  = 0x02;
 237         reg->Attribute[0x03]  = 0x03;
 238         reg->Attribute[0x04]  = 0x04;
 239         reg->Attribute[0x05]  = 0x05;
 240         reg->Attribute[0x06]  = 0x06;
 241         reg->Attribute[0x07]  = 0x07;
 242         reg->Attribute[0x08]  = 0x08;
 243         reg->Attribute[0x09]  = 0x09;
 244         reg->Attribute[0x0a] = 0x0A;
 245         reg->Attribute[0x0b] = 0x0B;
 246         reg->Attribute[0x0c] = 0x0C;
 247         reg->Attribute[0x0d] = 0x0D;
 248         reg->Attribute[0x0e] = 0x0E;
 249         reg->Attribute[0x0f] = 0x0F;
 250         reg->Attribute[0x10] = 0x41;
 251         reg->Attribute[0x11] = 0xFF;
 252         reg->Attribute[0x12] = 0x0F;
 253         reg->Attribute[0x13] = 0x00;
 254         reg->Attribute[0x14] = 0x00;
 255 }
 256
 257 /* -------------------- Hardware specific routines ------------------------- */
 258
 259 /*
 260  * Hardware Acceleration for SavageFB
 261  */
 262
 263 /* Wait for fifo space */
 264 static void
 265 savage3D_waitfifo(struct savagefb_par *par, int space)
 266 {
 267         int slots = MAXFIFO - space;
 268
 269         while ((savage_in32(0x48C00, par) & 0x0000ffff) > slots);
 270 }
 271
 272 static void
 273 savage4_waitfifo(struct savagefb_par *par, int space)
 274 {
 275         int slots = MAXFIFO - space;
 276
 277         while ((savage_in32(0x48C60, par) & 0x001fffff) > slots);
 278 }
 279
 280 static void
 281 savage2000_waitfifo(struct savagefb_par *par, int space)
 282 {
 283         int slots = MAXFIFO - space;
 284
 285         while ((savage_in32(0x48C60, par) & 0x0000ffff) > slots);
 286 }
 287
 288 /* Wait for idle accelerator */
 289 static void
 290 savage3D_waitidle(struct savagefb_par *par)
 291 {
 292         while ((savage_in32(0x48C00, par) & 0x0008ffff) != 0x80000);
 293 }
 294
 295 static void
 296 savage4_waitidle(struct savagefb_par *par)
 297 {
 298         while ((savage_in32(0x48C60, par) & 0x00a00000) != 0x00a00000);
 299 }
 300
 301 static void
 302 savage2000_waitidle(struct savagefb_par *par)
 303 {
 304         while ((savage_in32(0x48C60, par) & 0x009fffff));
 305 }
 306
 307 #ifdef CONFIG_FB_SAVAGE_ACCEL
 308 static void
 309 SavageSetup2DEngine(struct savagefb_par  *par)
 310 {
 311         unsigned long GlobalBitmapDescriptor;
 312
 313         GlobalBitmapDescriptor = 1 | 8 | BCI_BD_BW_DISABLE;
 314         BCI_BD_SET_BPP(GlobalBitmapDescriptor, par->depth);
 315         BCI_BD_SET_STRIDE(GlobalBitmapDescriptor, par->vwidth);
 316
 317         switch(par->chip) {
 318         case S3_SAVAGE3D:
 319         case S3_SAVAGE_MX:
 320                 /* Disable BCI */
 321                 savage_out32(0x48C18, savage_in32(0x48C18, par) & 0x3FF0, par);
 322                 /* Setup BCI command overflow buffer */
 323                 savage_out32(0x48C14,
 324                              (par->cob_offset >> 11) | (par->cob_index << 29),
 325                              par);
 326                 /* Program shadow status update. */
 327                 savage_out32(0x48C10, 0x78207220, par);
 328                 savage_out32(0x48C0C, 0, par);
 329                 /* Enable BCI and command overflow buffer */
 330                 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x0C, par);
 331                 break;
 332         case S3_SAVAGE4:
 333         case S3_PROSAVAGE:
 334         case S3_SUPERSAVAGE:
 335                 /* Disable BCI */
 336                 savage_out32(0x48C18, savage_in32(0x48C18, par) & 0x3FF0, par);
 337                 /* Program shadow status update */
 338                 savage_out32(0x48C10, 0x00700040, par);
 339                 savage_out32(0x48C0C, 0, par);
 340                 /* Enable BCI without the COB */
 341                 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x08, par);
 342                 break;
 343         case S3_SAVAGE2000:
 344                 /* Disable BCI */
 345                 savage_out32(0x48C18, 0, par);
 346                 /* Setup BCI command overflow buffer */
 347                 savage_out32(0x48C18,
 348                              (par->cob_offset >> 7) | (par->cob_index),
 349                              par);
 350                 /* Disable shadow status update */
 351                 savage_out32(0x48A30, 0, par);
 352                 /* Enable BCI and command overflow buffer */
 353                 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x00280000,
 354                              par);
 355                 break;
 356             default:
 357                 break;
 358         }
 359         /* Turn on 16-bit register access. */
 360         vga_out8(0x3d4, 0x31, par);
 361         vga_out8(0x3d5, 0x0c, par);
 362
 363         /* Set stride to use GBD. */
 364         vga_out8(0x3d4, 0x50, par);
 365         vga_out8(0x3d5, vga_in8(0x3d5, par) | 0xC1, par);
 366
 367         /* Enable 2D engine. */
 368         vga_out8(0x3d4, 0x40, par);
 369         vga_out8(0x3d5, 0x01, par);
 370
 371         savage_out32(MONO_PAT_0, ~0, par);
 372         savage_out32(MONO_PAT_1, ~0, par);
 373
 374         /* Setup plane masks */
 375         savage_out32(0x8128, ~0, par); /* enable all write planes */
 376         savage_out32(0x812C, ~0, par); /* enable all read planes */
 377         savage_out16(0x8134, 0x27, par);
 378         savage_out16(0x8136, 0x07, par);
 379
 380         /* Now set the GBD */
 381         par->bci_ptr = 0;
 382         par->SavageWaitFifo(par, 4);
 383
 384         BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD1);
 385         BCI_SEND(0);
 386         BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD2);
 387         BCI_SEND(GlobalBitmapDescriptor);
 388 }
 389
 390 static void savagefb_set_clip(struct fb_info *info)
 391 {
 392         struct savagefb_par *par = info->par;
 393         int cmd;
 394
 395         cmd = BCI_CMD_NOP | BCI_CMD_CLIP_NEW;
 396         par->bci_ptr = 0;
 397         par->SavageWaitFifo(par,3);
 398         BCI_SEND(cmd);
 399         BCI_SEND(BCI_CLIP_TL(0, 0));
 400         BCI_SEND(BCI_CLIP_BR(0xfff, 0xfff));
 401 }
 402 #else
 403 static void SavageSetup2DEngine(struct savagefb_par  *par) {}
 404
 405 #endif
 406
 407 static void SavageCalcClock(long freq, int min_m, int min_n1, int max_n1,
 408                             int min_n2, int max_n2, long freq_min,
 409                             long freq_max, unsigned int *mdiv,
 410                             unsigned int *ndiv, unsigned int *r)
 411 {
 412         long diff, best_diff;
 413         unsigned int m;
 414         unsigned char n1, n2, best_n1=16+2, best_n2=2, best_m=125+2;
 415
 416         if (freq < freq_min / (1 << max_n2)) {
 417                 printk(KERN_ERR "invalid frequency %ld Khz\n", freq);
 418                 freq = freq_min / (1 << max_n2);
 419         }
 420         if (freq > freq_max / (1 << min_n2)) {
 421                 printk(KERN_ERR "invalid frequency %ld Khz\n", freq);
 422                 freq = freq_max / (1 << min_n2);
 423         }
 424
 425         /* work out suitable timings */
 426         best_diff = freq;
 427
 428         for (n2=min_n2; n2<=max_n2; n2++) {
 429                 for (n1=min_n1+2; n1<=max_n1+2; n1++) {
 430                         m = (freq * n1 * (1 << n2) + HALF_BASE_FREQ) /
 431                                 BASE_FREQ;
 432                         if (m < min_m+2 || m > 127+2)
 433                                 continue;
 434                         if ((m * BASE_FREQ >= freq_min * n1) &&
 435                             (m * BASE_FREQ <= freq_max * n1)) {
 436                                 diff = freq * (1 << n2) * n1 - BASE_FREQ * m;
 437                                 if (diff < 0)
 438                                         diff = -diff;
 439                                 if (diff < best_diff) {
 440                                         best_diff = diff;
 441                                         best_m = m;
 442                                         best_n1 = n1;
 443                                         best_n2 = n2;
 444                                 }
 445                         }
 446                 }
 447         }
 448
 449         *ndiv = best_n1 - 2;
 450         *r = best_n2;
 451         *mdiv = best_m - 2;
 452 }
 453
 454 static int common_calc_clock(long freq, int min_m, int min_n1, int max_n1,
 455                              int min_n2, int max_n2, long freq_min,
 456                              long freq_max, unsigned char *mdiv,
 457                              unsigned char *ndiv)
 458 {
 459         long diff, best_diff;
 460         unsigned int m;
 461         unsigned char n1, n2;
 462         unsigned char best_n1 = 16+2, best_n2 = 2, best_m = 125+2;
 463
 464         best_diff = freq;
 465
 466         for (n2 = min_n2; n2 <= max_n2; n2++) {
 467                 for (n1 = min_n1+2; n1 <= max_n1+2; n1++) {
 468                         m = (freq * n1 * (1 << n2) + HALF_BASE_FREQ) /
 469                                 BASE_FREQ;
 470                         if (m < min_m + 2 || m > 127+2)
 471                                 continue;
 472                         if ((m * BASE_FREQ >= freq_min * n1) &&
 473                             (m * BASE_FREQ <= freq_max * n1)) {
 474                                 diff = freq * (1 << n2) * n1 - BASE_FREQ * m;
 475                                 if (diff < 0)
 476                                         diff = -diff;
 477                                 if (diff < best_diff) {
 478                                         best_diff = diff;
 479                                         best_m = m;
 480                                         best_n1 = n1;
 481                                         best_n2 = n2;
 482                                 }
 483                         }
 484                 }
 485         }
 486
 487         if (max_n1 == 63)
 488                 *ndiv = (best_n1 - 2) | (best_n2 << 6);
 489         else
 490                 *ndiv = (best_n1 - 2) | (best_n2 << 5);
 491
 492         *mdiv = best_m - 2;
 493
 494         return 0;
 495 }
 496
 497 #ifdef SAVAGEFB_DEBUG
 498 /* This function is used to debug, it prints out the contents of s3 regs */
 499
 500 static void SavagePrintRegs(void)
 501 {
 502         unsigned char i;
 503         int vgaCRIndex = 0x3d4;
 504         int vgaCRReg = 0x3d5;
 505
 506         printk(KERN_DEBUG "SR    x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE "
 507                "xF");
 508
 509         for (i = 0; i < 0x70; i++) {
 510                 if (!(i % 16))
 511                         printk(KERN_DEBUG "\nSR%xx ", i >> 4);
 512                 vga_out8(0x3c4, i, par);
 513                 printk(KERN_DEBUG " %02x", vga_in8(0x3c5, par));
 514         }
 515
 516         printk(KERN_DEBUG "\n\nCR    x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC "
 517                "xD xE xF");
 518
 519         for (i = 0; i < 0xB7; i++) {
 520                 if (!(i % 16))
 521                         printk(KERN_DEBUG "\nCR%xx ", i >> 4);
 522                 vga_out8(vgaCRIndex, i, par);
 523                 printk(KERN_DEBUG " %02x", vga_in8(vgaCRReg, par));
 524         }
 525
 526         printk(KERN_DEBUG "\n\n");
 527 }
 528 #endif
 529
 530 /* --------------------------------------------------------------------- */
 531
 532 static void savage_get_default_par(struct savagefb_par *par, struct savage_reg *reg)
 533 {
 534         unsigned char cr3a, cr53, cr66;
 535
 536         vga_out16(0x3d4, 0x4838, par);
 537         vga_out16(0x3d4, 0xa039, par);
 538         vga_out16(0x3c4, 0x0608, par);
 539
 540         vga_out8(0x3d4, 0x66, par);
 541         cr66 = vga_in8(0x3d5, par);
 542         vga_out8(0x3d5, cr66 | 0x80, par);
 543         vga_out8(0x3d4, 0x3a, par);
 544         cr3a = vga_in8(0x3d5, par);
 545         vga_out8(0x3d5, cr3a | 0x80, par);
 546         vga_out8(0x3d4, 0x53, par);
 547         cr53 = vga_in8(0x3d5, par);
 548         vga_out8(0x3d5, cr53 & 0x7f, par);
 549
 550         vga_out8(0x3d4, 0x66, par);
 551         vga_out8(0x3d5, cr66, par);
 552         vga_out8(0x3d4, 0x3a, par);
 553         vga_out8(0x3d5, cr3a, par);
 554
 555         vga_out8(0x3d4, 0x66, par);
 556         vga_out8(0x3d5, cr66, par);
 557         vga_out8(0x3d4, 0x3a, par);
 558         vga_out8(0x3d5, cr3a, par);
 559
 560         /* unlock extended seq regs */
 561         vga_out8(0x3c4, 0x08, par);
 562         reg->SR08 = vga_in8(0x3c5, par);
 563         vga_out8(0x3c5, 0x06, par);
 564
 565         /* now save all the extended regs we need */
 566         vga_out8(0x3d4, 0x31, par);
 567         reg->CR31 = vga_in8(0x3d5, par);
 568         vga_out8(0x3d4, 0x32, par);
 569         reg->CR32 = vga_in8(0x3d5, par);
 570         vga_out8(0x3d4, 0x34, par);
 571         reg->CR34 = vga_in8(0x3d5, par);
 572         vga_out8(0x3d4, 0x36, par);
 573         reg->CR36 = vga_in8(0x3d5, par);
 574         vga_out8(0x3d4, 0x3a, par);
 575         reg->CR3A = vga_in8(0x3d5, par);
 576         vga_out8(0x3d4, 0x40, par);
 577         reg->CR40 = vga_in8(0x3d5, par);
 578         vga_out8(0x3d4, 0x42, par);
 579         reg->CR42 = vga_in8(0x3d5, par);
 580         vga_out8(0x3d4, 0x45, par);
 581         reg->CR45 = vga_in8(0x3d5, par);
 582         vga_out8(0x3d4, 0x50, par);
 583         reg->CR50 = vga_in8(0x3d5, par);
 584         vga_out8(0x3d4, 0x51, par);
 585         reg->CR51 = vga_in8(0x3d5, par);
 586         vga_out8(0x3d4, 0x53, par);
 587         reg->CR53 = vga_in8(0x3d5, par);
 588         vga_out8(0x3d4, 0x58, par);
 589         reg->CR58 = vga_in8(0x3d5, par);
 590         vga_out8(0x3d4, 0x60, par);
 591         reg->CR60 = vga_in8(0x3d5, par);
 592         vga_out8(0x3d4, 0x66, par);
 593         reg->CR66 = vga_in8(0x3d5, par);
 594         vga_out8(0x3d4, 0x67, par);
 595         reg->CR67 = vga_in8(0x3d5, par);
 596         vga_out8(0x3d4, 0x68, par);
 597         reg->CR68 = vga_in8(0x3d5, par);
 598         vga_out8(0x3d4, 0x69, par);
 599         reg->CR69 = vga_in8(0x3d5, par);
 600         vga_out8(0x3d4, 0x6f, par);
 601         reg->CR6F = vga_in8(0x3d5, par);
 602
 603         vga_out8(0x3d4, 0x33, par);
 604         reg->CR33 = vga_in8(0x3d5, par);
 605         vga_out8(0x3d4, 0x86, par);
 606         reg->CR86 = vga_in8(0x3d5, par);
 607         vga_out8(0x3d4, 0x88, par);
 608         reg->CR88 = vga_in8(0x3d5, par);
 609         vga_out8(0x3d4, 0x90, par);
 610         reg->CR90 = vga_in8(0x3d5, par);
 611         vga_out8(0x3d4, 0x91, par);
 612         reg->CR91 = vga_in8(0x3d5, par);
 613         vga_out8(0x3d4, 0xb0, par);
 614         reg->CRB0 = vga_in8(0x3d5, par) | 0x80;
 615
 616         /* extended mode timing regs */
 617         vga_out8(0x3d4, 0x3b, par);
 618         reg->CR3B = vga_in8(0x3d5, par);
 619         vga_out8(0x3d4, 0x3c, par);
 620         reg->CR3C = vga_in8(0x3d5, par);
 621         vga_out8(0x3d4, 0x43, par);
 622         reg->CR43 = vga_in8(0x3d5, par);
 623         vga_out8(0x3d4, 0x5d, par);
 624         reg->CR5D = vga_in8(0x3d5, par);
 625         vga_out8(0x3d4, 0x5e, par);
 626         reg->CR5E = vga_in8(0x3d5, par);
 627         vga_out8(0x3d4, 0x65, par);
 628         reg->CR65 = vga_in8(0x3d5, par);
 629
 630         /* save seq extended regs for DCLK PLL programming */
 631         vga_out8(0x3c4, 0x0e, par);
 632         reg->SR0E = vga_in8(0x3c5, par);
 633         vga_out8(0x3c4, 0x0f, par);
 634         reg->SR0F = vga_in8(0x3c5, par);
 635         vga_out8(0x3c4, 0x10, par);
 636         reg->SR10 = vga_in8(0x3c5, par);
 637         vga_out8(0x3c4, 0x11, par);
 638         reg->SR11 = vga_in8(0x3c5, par);
 639         vga_out8(0x3c4, 0x12, par);
 640         reg->SR12 = vga_in8(0x3c5, par);
 641         vga_out8(0x3c4, 0x13, par);
 642         reg->SR13 = vga_in8(0x3c5, par);
 643         vga_out8(0x3c4, 0x29, par);
 644         reg->SR29 = vga_in8(0x3c5, par);
 645
 646         vga_out8(0x3c4, 0x15, par);
 647         reg->SR15 = vga_in8(0x3c5, par);
 648         vga_out8(0x3c4, 0x30, par);
 649         reg->SR30 = vga_in8(0x3c5, par);
 650         vga_out8(0x3c4, 0x18, par);
 651         reg->SR18 = vga_in8(0x3c5, par);
 652
 653         /* Save flat panel expansion regsters. */
 654         if (par->chip == S3_SAVAGE_MX) {
 655                 int i;
 656
 657                 for (i = 0; i < 8; i++) {
 658                         vga_out8(0x3c4, 0x54+i, par);
 659                         reg->SR54[i] = vga_in8(0x3c5, par);
 660                 }
 661         }
 662
 663         vga_out8(0x3d4, 0x66, par);
 664         cr66 = vga_in8(0x3d5, par);
 665         vga_out8(0x3d5, cr66 | 0x80, par);
 666         vga_out8(0x3d4, 0x3a, par);
 667         cr3a = vga_in8(0x3d5, par);
 668         vga_out8(0x3d5, cr3a | 0x80, par);
 669
 670         /* now save MIU regs */
 671         if (par->chip != S3_SAVAGE_MX) {
 672                 reg->MMPR0 = savage_in32(FIFO_CONTROL_REG, par);
 673                 reg->MMPR1 = savage_in32(MIU_CONTROL_REG, par);
 674                 reg->MMPR2 = savage_in32(STREAMS_TIMEOUT_REG, par);
 675                 reg->MMPR3 = savage_in32(MISC_TIMEOUT_REG, par);
 676         }
 677
 678         vga_out8(0x3d4, 0x3a, par);
 679         vga_out8(0x3d5, cr3a, par);
 680         vga_out8(0x3d4, 0x66, par);
 681         vga_out8(0x3d5, cr66, par);
 682 }
 683
 684 static void savage_set_default_par(struct savagefb_par *par,
 685                                 struct savage_reg *reg)
 686 {
 687         unsigned char cr3a, cr53, cr66;
 688
 689         vga_out16(0x3d4, 0x4838, par);
 690         vga_out16(0x3d4, 0xa039, par);
 691         vga_out16(0x3c4, 0x0608, par);
 692
 693         vga_out8(0x3d4, 0x66, par);
 694         cr66 = vga_in8(0x3d5, par);
 695         vga_out8(0x3d5, cr66 | 0x80, par);
 696         vga_out8(0x3d4, 0x3a, par);
 697         cr3a = vga_in8(0x3d5, par);
 698         vga_out8(0x3d5, cr3a | 0x80, par);
 699         vga_out8(0x3d4, 0x53, par);
 700         cr53 = vga_in8(0x3d5, par);
 701         vga_out8(0x3d5, cr53 & 0x7f, par);
 702
 703         vga_out8(0x3d4, 0x66, par);
 704         vga_out8(0x3d5, cr66, par);
 705         vga_out8(0x3d4, 0x3a, par);
 706         vga_out8(0x3d5, cr3a, par);
 707
 708         vga_out8(0x3d4, 0x66, par);
 709         vga_out8(0x3d5, cr66, par);
 710         vga_out8(0x3d4, 0x3a, par);
 711         vga_out8(0x3d5, cr3a, par);
 712
 713         /* unlock extended seq regs */
 714         vga_out8(0x3c4, 0x08, par);
 715         vga_out8(0x3c5, reg->SR08, par);
 716         vga_out8(0x3c5, 0x06, par);
 717
 718         /* now restore all the extended regs we need */
 719         vga_out8(0x3d4, 0x31, par);
 720         vga_out8(0x3d5, reg->CR31, par);
 721         vga_out8(0x3d4, 0x32, par);
 722         vga_out8(0x3d5, reg->CR32, par);
 723         vga_out8(0x3d4, 0x34, par);
 724         vga_out8(0x3d5, reg->CR34, par);
 725         vga_out8(0x3d4, 0x36, par);
 726         vga_out8(0x3d5,reg->CR36, par);
 727         vga_out8(0x3d4, 0x3a, par);
 728         vga_out8(0x3d5, reg->CR3A, par);
 729         vga_out8(0x3d4, 0x40, par);
 730         vga_out8(0x3d5, reg->CR40, par);
 731         vga_out8(0x3d4, 0x42, par);
 732         vga_out8(0x3d5, reg->CR42, par);
 733         vga_out8(0x3d4, 0x45, par);
 734         vga_out8(0x3d5, reg->CR45, par);
 735         vga_out8(0x3d4, 0x50, par);
 736         vga_out8(0x3d5, reg->CR50, par);
 737         vga_out8(0x3d4, 0x51, par);
 738         vga_out8(0x3d5, reg->CR51, par);
 739         vga_out8(0x3d4, 0x53, par);
 740         vga_out8(0x3d5, reg->CR53, par);
 741         vga_out8(0x3d4, 0x58, par);
 742         vga_out8(0x3d5, reg->CR58, par);
 743         vga_out8(0x3d4, 0x60, par);
 744         vga_out8(0x3d5, reg->CR60, par);
 745         vga_out8(0x3d4, 0x66, par);
 746         vga_out8(0x3d5, reg->CR66, par);
 747         vga_out8(0x3d4, 0x67, par);
 748         vga_out8(0x3d5, reg->CR67, par);
 749         vga_out8(0x3d4, 0x68, par);
 750         vga_out8(0x3d5, reg->CR68, par);
 751         vga_out8(0x3d4, 0x69, par);
 752         vga_out8(0x3d5, reg->CR69, par);
 753         vga_out8(0x3d4, 0x6f, par);
 754         vga_out8(0x3d5, reg->CR6F, par);
 755
 756         vga_out8(0x3d4, 0x33, par);
 757         vga_out8(0x3d5, reg->CR33, par);
 758         vga_out8(0x3d4, 0x86, par);
 759         vga_out8(0x3d5, reg->CR86, par);
 760         vga_out8(0x3d4, 0x88, par);
 761         vga_out8(0x3d5, reg->CR88, par);
 762         vga_out8(0x3d4, 0x90, par);
 763         vga_out8(0x3d5, reg->CR90, par);
 764         vga_out8(0x3d4, 0x91, par);
 765         vga_out8(0x3d5, reg->CR91, par);
 766         vga_out8(0x3d4, 0xb0, par);
 767         vga_out8(0x3d5, reg->CRB0, par);
 768
 769         /* extended mode timing regs */
 770         vga_out8(0x3d4, 0x3b, par);
 771         vga_out8(0x3d5, reg->CR3B, par);
 772         vga_out8(0x3d4, 0x3c, par);
 773         vga_out8(0x3d5, reg->CR3C, par);
 774         vga_out8(0x3d4, 0x43, par);
 775         vga_out8(0x3d5, reg->CR43, par);
 776         vga_out8(0x3d4, 0x5d, par);
 777         vga_out8(0x3d5, reg->CR5D, par);
 778         vga_out8(0x3d4, 0x5e, par);
 779         vga_out8(0x3d5, reg->CR5E, par);
 780         vga_out8(0x3d4, 0x65, par);
 781         vga_out8(0x3d5, reg->CR65, par);
 782
 783         /* save seq extended regs for DCLK PLL programming */
 784         vga_out8(0x3c4, 0x0e, par);
 785         vga_out8(0x3c5, reg->SR0E, par);
 786         vga_out8(0x3c4, 0x0f, par);
 787         vga_out8(0x3c5, reg->SR0F, par);
 788         vga_out8(0x3c4, 0x10, par);
 789         vga_out8(0x3c5, reg->SR10, par);
 790         vga_out8(0x3c4, 0x11, par);
 791         vga_out8(0x3c5, reg->SR11, par);
 792         vga_out8(0x3c4, 0x12, par);
 793         vga_out8(0x3c5, reg->SR12, par);
 794         vga_out8(0x3c4, 0x13, par);
 795         vga_out8(0x3c5, reg->SR13, par);
 796         vga_out8(0x3c4, 0x29, par);
 797         vga_out8(0x3c5, reg->SR29, par);
 798
 799         vga_out8(0x3c4, 0x15, par);
 800         vga_out8(0x3c5, reg->SR15, par);
 801         vga_out8(0x3c4, 0x30, par);
 802         vga_out8(0x3c5, reg->SR30, par);
 803         vga_out8(0x3c4, 0x18, par);
 804         vga_out8(0x3c5, reg->SR18, par);
 805
 806         /* Save flat panel expansion regsters. */
 807         if (par->chip == S3_SAVAGE_MX) {
 808                 int i;
 809
 810                 for (i = 0; i < 8; i++) {
 811                         vga_out8(0x3c4, 0x54+i, par);
 812                         vga_out8(0x3c5, reg->SR54[i], par);
 813                 }
 814         }
 815
 816         vga_out8(0x3d4, 0x66, par);
 817         cr66 = vga_in8(0x3d5, par);
 818         vga_out8(0x3d5, cr66 | 0x80, par);
 819         vga_out8(0x3d4, 0x3a, par);
 820         cr3a = vga_in8(0x3d5, par);
 821         vga_out8(0x3d5, cr3a | 0x80, par);
 822
 823         /* now save MIU regs */
 824         if (par->chip != S3_SAVAGE_MX) {
 825                 savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par);
 826                 savage_out32(MIU_CONTROL_REG, reg->MMPR1, par);
 827                 savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par);
 828                 savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par);
 829         }
 830
 831         vga_out8(0x3d4, 0x3a, par);
 832         vga_out8(0x3d5, cr3a, par);
 833         vga_out8(0x3d4, 0x66, par);
 834         vga_out8(0x3d5, cr66, par);
 835 }
 836
 837 static void savage_update_var(struct fb_var_screeninfo *var, struct fb_videomode *modedb)
 838 {
 839         var->xres = var->xres_virtual = modedb->xres;
 840         var->yres = modedb->yres;
 841         if (var->yres_virtual < var->yres)
 842             var->yres_virtual = var->yres;
 843         var->xoffset = var->yoffset = 0;
 844         var->pixclock = modedb->pixclock;
 845         var->left_margin = modedb->left_margin;
 846         var->right_margin = modedb->right_margin;
 847         var->upper_margin = modedb->upper_margin;
 848         var->lower_margin = modedb->lower_margin;
 849         var->hsync_len = modedb->hsync_len;
 850         var->vsync_len = modedb->vsync_len;
 851         var->sync = modedb->sync;
 852         var->vmode = modedb->vmode;
 853 }
 854
 855 static int savagefb_check_var(struct fb_var_screeninfo   *var,
 856                               struct fb_info *info)
 857 {
 858         struct savagefb_par *par = info->par;
 859         int memlen, vramlen, mode_valid = 0;
 860
 861         DBG("savagefb_check_var");
 862
 863         var->transp.offset = 0;
 864         var->transp.length = 0;
 865         switch (var->bits_per_pixel) {
 866         case 8:
 867                 var->red.offset = var->green.offset =
 868                         var->blue.offset = 0;
 869                 var->red.length = var->green.length =
 870                         var->blue.length = var->bits_per_pixel;
 871                 break;
 872         case 16:
 873                 var->red.offset = 11;
 874                 var->red.length = 5;
 875                 var->green.offset = 5;
 876                 var->green.length = 6;
 877                 var->blue.offset = 0;
 878                 var->blue.length = 5;
 879                 break;
 880         case 32:
 881                 var->transp.offset = 24;
 882                 var->transp.length = 8;
 883                 var->red.offset = 16;
 884                 var->red.length = 8;
 885                 var->green.offset = 8;
 886                 var->green.length = 8;
 887                 var->blue.offset = 0;
 888                 var->blue.length = 8;
 889                 break;
 890
 891         default:
 892                 return -EINVAL;
 893         }
 894
 895         if (!info->monspecs.hfmax || !info->monspecs.vfmax ||
 896             !info->monspecs.dclkmax || !fb_validate_mode(var, info))
 897                 mode_valid = 1;
 898
 899         /* calculate modeline if supported by monitor */
 900         if (!mode_valid && info->monspecs.gtf) {
 901                 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
 902                         mode_valid = 1;
 903         }
 904
 905         if (!mode_valid) {
 906                 struct fb_videomode *mode;
 907
 908                 mode = fb_find_best_mode(var, &info->modelist);
 909                 if (mode) {
 910                         savage_update_var(var, mode);
 911                         mode_valid = 1;
 912                 }
 913         }
 914
 915         if (!mode_valid && info->monspecs.modedb_len)
 916                 return -EINVAL;
 917
 918         /* Is the mode larger than the LCD panel? */
 919         if (par->SavagePanelWidth &&
 920             (var->xres > par->SavagePanelWidth ||
 921              var->yres > par->SavagePanelHeight)) {
 922                 printk(KERN_INFO "Mode (%dx%d) larger than the LCD panel "
 923                        "(%dx%d)\n", var->xres,  var->yres,
 924                        par->SavagePanelWidth,
 925                        par->SavagePanelHeight);
 926                 return -1;
 927         }
 928
 929         if (var->yres_virtual < var->yres)
 930                 var->yres_virtual = var->yres;
 931         if (var->xres_virtual < var->xres)
 932                 var->xres_virtual = var->xres;
 933
 934         vramlen = info->fix.smem_len;
 935
 936         memlen = var->xres_virtual * var->bits_per_pixel *
 937                 var->yres_virtual / 8;
 938         if (memlen > vramlen) {
 939                 var->yres_virtual = vramlen * 8 /
 940                         (var->xres_virtual * var->bits_per_pixel);
 941                 memlen = var->xres_virtual * var->bits_per_pixel *
 942                         var->yres_virtual / 8;
 943         }
 944
 945         /* we must round yres/xres down, we already rounded y/xres_virtual up
 946            if it was possible. We should return -EINVAL, but I disagree */
 947         if (var->yres_virtual < var->yres)
 948                 var->yres = var->yres_virtual;
 949         if (var->xres_virtual < var->xres)
 950                 var->xres = var->xres_virtual;
 951         if (var->xoffset + var->xres > var->xres_virtual)
 952                 var->xoffset = var->xres_virtual - var->xres;
 953         if (var->yoffset + var->yres > var->yres_virtual)
 954                 var->yoffset = var->yres_virtual - var->yres;
 955
 956         return 0;
 957 }
 958
 959
 960 static int savagefb_decode_var(struct fb_var_screeninfo   *var,
 961                                struct savagefb_par        *par,
 962                                struct savage_reg          *reg)
 963 {
 964         struct xtimings timings;
 965         int width, dclk, i, j; /*, refresh; */
 966         unsigned int m, n, r;
 967         unsigned char tmp = 0;
 968         unsigned int pixclock = var->pixclock;
 969
 970         DBG("savagefb_decode_var");
 971
 972         memset(&timings, 0, sizeof(timings));
 973
 974         if (!pixclock) pixclock = 10000;        /* 10ns = 100MHz */
 975         timings.Clock = 1000000000 / pixclock;
 976         if (timings.Clock < 1) timings.Clock = 1;
 977         timings.dblscan = var->vmode & FB_VMODE_DOUBLE;
 978         timings.interlaced = var->vmode & FB_VMODE_INTERLACED;
 979         timings.HDisplay = var->xres;
 980         timings.HSyncStart = timings.HDisplay + var->right_margin;
 981         timings.HSyncEnd = timings.HSyncStart + var->hsync_len;
 982         timings.HTotal = timings.HSyncEnd + var->left_margin;
 983         timings.VDisplay = var->yres;
 984         timings.VSyncStart = timings.VDisplay + var->lower_margin;
 985         timings.VSyncEnd = timings.VSyncStart + var->vsync_len;
 986         timings.VTotal = timings.VSyncEnd + var->upper_margin;
 987         timings.sync = var->sync;
 988
 989
 990         par->depth  = var->bits_per_pixel;
 991         par->vwidth = var->xres_virtual;
 992
 993         if (var->bits_per_pixel == 16  &&  par->chip == S3_SAVAGE3D) {
 994                 timings.HDisplay *= 2;
 995                 timings.HSyncStart *= 2;
 996                 timings.HSyncEnd *= 2;
 997                 timings.HTotal *= 2;
 998         }
 999
1000         /*
1001          * This will allocate the datastructure and initialize all of the
1002          * generic VGA registers.
1003          */
1004         vgaHWInit(var, par, &timings, reg);
1005
1006         /* We need to set CR67 whether or not we use the BIOS. */
1007
1008         dclk = timings.Clock;
1009         reg->CR67 = 0x00;
1010
1011         switch(var->bits_per_pixel) {
1012         case 8:
1013                 if ((par->chip == S3_SAVAGE2000) && (dclk >= 230000))
1014                         reg->CR67 = 0x10;       /* 8bpp, 2 pixels/clock */
1015                 else
1016                         reg->CR67 = 0x00;       /* 8bpp, 1 pixel/clock */
1017                 break;
1018         case 15:
1019                 if (S3_SAVAGE_MOBILE_SERIES(par->chip) ||
1020                     ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)))
1021                         reg->CR67 = 0x30;       /* 15bpp, 2 pixel/clock */
1022                 else
1023                         reg->CR67 = 0x20;       /* 15bpp, 1 pixels/clock */
1024                 break;
1025         case 16:
1026                 if (S3_SAVAGE_MOBILE_SERIES(par->chip) ||
1027                    ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)))
1028                         reg->CR67 = 0x50;       /* 16bpp, 2 pixel/clock */
1029                 else
1030                         reg->CR67 = 0x40;       /* 16bpp, 1 pixels/clock */
1031                 break;
1032         case 24:
1033                 reg->CR67 = 0x70;
1034                 break;
1035         case 32:
1036                 reg->CR67 = 0xd0;
1037                 break;
1038         }
1039
1040         /*
1041          * Either BIOS use is disabled, or we failed to find a suitable
1042          * match.  Fall back to traditional register-crunching.
1043          */
1044
1045         vga_out8(0x3d4, 0x3a, par);
1046         tmp = vga_in8(0x3d5, par);
1047         if (1 /*FIXME:psav->pci_burst*/)
1048                 reg->CR3A = (tmp & 0x7f) | 0x15;
1049         else
1050                 reg->CR3A = tmp | 0x95;
1051
1052         reg->CR53 = 0x00;
1053         reg->CR31 = 0x8c;
1054         reg->CR66 = 0x89;
1055
1056         vga_out8(0x3d4, 0x58, par);
1057         reg->CR58 = vga_in8(0x3d5, par) & 0x80;
1058         reg->CR58 |= 0x13;
1059
1060         reg->SR15 = 0x03 | 0x80;
1061         reg->SR18 = 0x00;
1062         reg->CR43 = reg->CR45 = reg->CR65 = 0x00;
1063
1064         vga_out8(0x3d4, 0x40, par);
1065         reg->CR40 = vga_in8(0x3d5, par) & ~0x01;
1066
1067         reg->MMPR0 = 0x010400;
1068         reg->MMPR1 = 0x00;
1069         reg->MMPR2 = 0x0808;
1070         reg->MMPR3 = 0x08080810;
1071
1072         SavageCalcClock(dclk, 1, 1, 127, 0, 4, 180000, 360000, &m, &n, &r);
1073         /* m = 107; n = 4; r = 2; */
1074
1075         if (par->MCLK <= 0) {
1076                 reg->SR10 = 255;
1077                 reg->SR11 = 255;
1078         } else {
1079                 common_calc_clock(par->MCLK, 1, 1, 31, 0, 3, 135000, 270000,
1080                                    &reg->SR11, &reg->SR10);
1081                 /*      reg->SR10 = 80; // MCLK == 286000 */
1082                 /*      reg->SR11 = 125; */
1083         }
1084
1085         reg->SR12 = (r << 6) | (n & 0x3f);
1086         reg->SR13 = m & 0xff;
1087         reg->SR29 = (r & 4) | (m & 0x100) >> 5 | (n & 0x40) >> 2;
1088
1089         if (var->bits_per_pixel < 24)
1090                 reg->MMPR0 -= 0x8000;
1091         else
1092                 reg->MMPR0 -= 0x4000;
1093
1094         if (timings.interlaced)
1095                 reg->CR42 = 0x20;
1096         else
1097                 reg->CR42 = 0x00;
1098
1099         reg->CR34 = 0x10; /* display fifo */
1100
1101         i = ((((timings.HTotal >> 3) - 5) & 0x100) >> 8) |
1102                 ((((timings.HDisplay >> 3) - 1) & 0x100) >> 7) |
1103                 ((((timings.HSyncStart >> 3) - 1) & 0x100) >> 6) |
1104                 ((timings.HSyncStart & 0x800) >> 7);
1105
1106         if ((timings.HSyncEnd >> 3) - (timings.HSyncStart >> 3) > 64)
1107                 i |= 0x08;
1108         if ((timings.HSyncEnd >> 3) - (timings.HSyncStart >> 3) > 32)
1109                 i |= 0x20;
1110
1111         j = (reg->CRTC[0] + ((i & 0x01) << 8) +
1112              reg->CRTC[4] + ((i & 0x10) << 4) + 1) / 2;
1113
1114         if (j - (reg->CRTC[4] + ((i & 0x10) << 4)) < 4) {
1115                 if (reg->CRTC[4] + ((i & 0x10) << 4) + 4 <=
1116                     reg->CRTC[0] + ((i & 0x01) << 8))
1117                         j = reg->CRTC[4] + ((i & 0x10) << 4) + 4;
1118                 else
1119                         j = reg->CRTC[0] + ((i & 0x01) << 8) + 1;
1120         }
1121
1122         reg->CR3B = j & 0xff;
1123         i |= (j & 0x100) >> 2;
1124         reg->CR3C = (reg->CRTC[0] + ((i & 0x01) << 8)) / 2;
1125         reg->CR5D = i;
1126         reg->CR5E = (((timings.VTotal - 2) & 0x400) >> 10) |
1127                 (((timings.VDisplay - 1) & 0x400) >> 9) |
1128                 (((timings.VSyncStart) & 0x400) >> 8) |
1129                 (((timings.VSyncStart) & 0x400) >> 6) | 0x40;
1130         width = (var->xres_virtual * ((var->bits_per_pixel+7) / 8)) >> 3;
1131         reg->CR91 = reg->CRTC[19] = 0xff & width;
1132         reg->CR51 = (0x300 & width) >> 4;
1133         reg->CR90 = 0x80 | (width >> 8);
1134         reg->MiscOutReg |= 0x0c;
1135
1136         /* Set frame buffer description. */
1137
1138         if (var->bits_per_pixel <= 8)
1139                 reg->CR50 = 0;
1140         else if (var->bits_per_pixel <= 16)
1141                 reg->CR50 = 0x10;
1142         else
1143                 reg->CR50 = 0x30;
1144
1145         if (var->xres_virtual <= 640)
1146                 reg->CR50 |= 0x40;
1147         else if (var->xres_virtual == 800)
1148                 reg->CR50 |= 0x80;
1149         else if (var->xres_virtual == 1024)
1150                 reg->CR50 |= 0x00;
1151         else if (var->xres_virtual == 1152)
1152                 reg->CR50 |= 0x01;
1153         else if (var->xres_virtual == 1280)
1154                 reg->CR50 |= 0xc0;
1155         else if (var->xres_virtual == 1600)
1156                 reg->CR50 |= 0x81;
1157         else
1158                 reg->CR50 |= 0xc1;      /* Use GBD */
1159
1160         if (par->chip == S3_SAVAGE2000)
1161                 reg->CR33 = 0x08;
1162         else
1163                 reg->CR33 = 0x20;
1164
1165         reg->CRTC[0x17] = 0xeb;
1166
1167         reg->CR67 |= 1;
1168
1169         vga_out8(0x3d4, 0x36, par);
1170         reg->CR36 = vga_in8(0x3d5, par);
1171         vga_out8(0x3d4, 0x68, par);
1172         reg->CR68 = vga_in8(0x3d5, par);
1173         reg->CR69 = 0;
1174         vga_out8(0x3d4, 0x6f, par);
1175         reg->CR6F = vga_in8(0x3d5, par);
1176         vga_out8(0x3d4, 0x86, par);
1177         reg->CR86 = vga_in8(0x3d5, par);
1178         vga_out8(0x3d4, 0x88, par);
1179         reg->CR88 = vga_in8(0x3d5, par) | 0x08;
1180         vga_out8(0x3d4, 0xb0, par);
1181         reg->CRB0 = vga_in8(0x3d5, par) | 0x80;
1182
1183         return 0;
1184 }
1185
1186 /* --------------------------------------------------------------------- */
1187
1188 /*
1189  *    Set a single color register. Return != 0 for invalid regno.
1190  */
1191 static int savagefb_setcolreg(unsigned        regno,
1192                               unsigned        red,
1193                               unsigned        green,
1194                               unsigned        blue,
1195                               unsigned        transp,
1196                               struct fb_info *info)
1197 {
1198         struct savagefb_par *par = info->par;
1199
1200         if (regno >= NR_PALETTE)
1201                 return -EINVAL;
1202
1203         par->palette[regno].red    = red;
1204         par->palette[regno].green  = green;
1205         par->palette[regno].blue   = blue;
1206         par->palette[regno].transp = transp;
1207
1208         switch (info->var.bits_per_pixel) {
1209         case 8:
1210                 vga_out8(0x3c8, regno, par);
1211
1212                 vga_out8(0x3c9, red   >> 10, par);
1213                 vga_out8(0x3c9, green >> 10, par);
1214                 vga_out8(0x3c9, blue  >> 10, par);
1215                 break;
1216
1217         case 16:
1218                 if (regno < 16)
1219                         ((u32 *)info->pseudo_palette)[regno] =
1220                                 ((red   & 0xf800)      ) |
1221                                 ((green & 0xfc00) >>  5) |
1222                                 ((blue  & 0xf800) >> 11);
1223                 break;
1224
1225         case 24:
1226                 if (regno < 16)
1227                         ((u32 *)info->pseudo_palette)[regno] =
1228                                 ((red    & 0xff00) <<  8) |
1229                                 ((green  & 0xff00)      ) |
1230                                 ((blue   & 0xff00) >>  8);
1231                 break;
1232         case 32:
1233                 if (regno < 16)
1234                         ((u32 *)info->pseudo_palette)[regno] =
1235                                 ((transp & 0xff00) << 16) |
1236                                 ((red    & 0xff00) <<  8) |
1237                                 ((green  & 0xff00)      ) |
1238                                 ((blue   & 0xff00) >>  8);
1239                 break;
1240
1241         default:
1242                 return 1;
1243         }
1244
1245         return 0;
1246 }
1247
1248 static void savagefb_set_par_int(struct savagefb_par  *par, struct savage_reg *reg)
1249 {
1250         unsigned char tmp, cr3a, cr66, cr67;
1251
1252         DBG("savagefb_set_par_int");
1253
1254         par->SavageWaitIdle(par);
1255
1256         vga_out8(0x3c2, 0x23, par);
1257
1258         vga_out16(0x3d4, 0x4838, par);
1259         vga_out16(0x3d4, 0xa539, par);
1260         vga_out16(0x3c4, 0x0608, par);
1261
1262         vgaHWProtect(par, 1);
1263
1264         /*
1265          * Some Savage/MX and /IX systems go nuts when trying to exit the
1266          * server after WindowMaker has displayed a gradient background.  I
1267          * haven't been able to find what causes it, but a non-destructive
1268          * switch to mode 3 here seems to eliminate the issue.
1269          */
1270
1271         VerticalRetraceWait(par);
1272         vga_out8(0x3d4, 0x67, par);
1273         cr67 = vga_in8(0x3d5, par);
1274         vga_out8(0x3d5, cr67/*par->CR67*/ & ~0x0c, par); /* no STREAMS yet */
1275
1276         vga_out8(0x3d4, 0x23, par);
1277         vga_out8(0x3d5, 0x00, par);
1278         vga_out8(0x3d4, 0x26, par);
1279         vga_out8(0x3d5, 0x00, par);
1280
1281         /* restore extended regs */
1282         vga_out8(0x3d4, 0x66, par);
1283         vga_out8(0x3d5, reg->CR66, par);
1284         vga_out8(0x3d4, 0x3a, par);
1285         vga_out8(0x3d5, reg->CR3A, par);
1286         vga_out8(0x3d4, 0x31, par);
1287         vga_out8(0x3d5, reg->CR31, par);
1288         vga_out8(0x3d4, 0x32, par);
1289         vga_out8(0x3d5, reg->CR32, par);
1290         vga_out8(0x3d4, 0x58, par);
1291         vga_out8(0x3d5, reg->CR58, par);
1292         vga_out8(0x3d4, 0x53, par);
1293         vga_out8(0x3d5, reg->CR53 & 0x7f, par);
1294
1295         vga_out16(0x3c4, 0x0608, par);
1296
1297         /* Restore DCLK registers. */
1298
1299         vga_out8(0x3c4, 0x0e, par);
1300         vga_out8(0x3c5, reg->SR0E, par);
1301         vga_out8(0x3c4, 0x0f, par);
1302         vga_out8(0x3c5, reg->SR0F, par);
1303         vga_out8(0x3c4, 0x29, par);
1304         vga_out8(0x3c5, reg->SR29, par);
1305         vga_out8(0x3c4, 0x15, par);
1306         vga_out8(0x3c5, reg->SR15, par);
1307
1308         /* Restore flat panel expansion regsters. */
1309         if (par->chip == S3_SAVAGE_MX) {
1310                 int i;
1311
1312                 for (i = 0; i < 8; i++) {
1313                         vga_out8(0x3c4, 0x54+i, par);
1314                         vga_out8(0x3c5, reg->SR54[i], par);
1315                 }
1316         }
1317
1318         vgaHWRestore (par, reg);
1319
1320         /* extended mode timing registers */
1321         vga_out8(0x3d4, 0x53, par);
1322         vga_out8(0x3d5, reg->CR53, par);
1323         vga_out8(0x3d4, 0x5d, par);
1324         vga_out8(0x3d5, reg->CR5D, par);
1325         vga_out8(0x3d4, 0x5e, par);
1326         vga_out8(0x3d5, reg->CR5E, par);
1327         vga_out8(0x3d4, 0x3b, par);
1328         vga_out8(0x3d5, reg->CR3B, par);
1329         vga_out8(0x3d4, 0x3c, par);
1330         vga_out8(0x3d5, reg->CR3C, par);
1331         vga_out8(0x3d4, 0x43, par);
1332         vga_out8(0x3d5, reg->CR43, par);
1333         vga_out8(0x3d4, 0x65, par);
1334         vga_out8(0x3d5, reg->CR65, par);
1335
1336         /* restore the desired video mode with cr67 */
1337         vga_out8(0x3d4, 0x67, par);
1338         /* following part not present in X11 driver */
1339         cr67 = vga_in8(0x3d5, par) & 0xf;
1340         vga_out8(0x3d5, 0x50 | cr67, par);
1341         udelay(10000);
1342         vga_out8(0x3d4, 0x67, par);
1343         /* end of part */
1344         vga_out8(0x3d5, reg->CR67 & ~0x0c, par);
1345
1346         /* other mode timing and extended regs */
1347         vga_out8(0x3d4, 0x34, par);
1348         vga_out8(0x3d5, reg->CR34, par);
1349         vga_out8(0x3d4, 0x40, par);
1350         vga_out8(0x3d5, reg->CR40, par);
1351         vga_out8(0x3d4, 0x42, par);
1352         vga_out8(0x3d5, reg->CR42, par);
1353         vga_out8(0x3d4, 0x45, par);
1354         vga_out8(0x3d5, reg->CR45, par);
1355         vga_out8(0x3d4, 0x50, par);
1356         vga_out8(0x3d5, reg->CR50, par);
1357         vga_out8(0x3d4, 0x51, par);
1358         vga_out8(0x3d5, reg->CR51, par);
1359
1360         /* memory timings */
1361         vga_out8(0x3d4, 0x36, par);
1362         vga_out8(0x3d5, reg->CR36, par);
1363         vga_out8(0x3d4, 0x60, par);
1364         vga_out8(0x3d5, reg->CR60, par);
1365         vga_out8(0x3d4, 0x68, par);
1366         vga_out8(0x3d5, reg->CR68, par);
1367         vga_out8(0x3d4, 0x69, par);
1368         vga_out8(0x3d5, reg->CR69, par);
1369         vga_out8(0x3d4, 0x6f, par);
1370         vga_out8(0x3d5, reg->CR6F, par);
1371
1372         vga_out8(0x3d4, 0x33, par);
1373         vga_out8(0x3d5, reg->CR33, par);
1374         vga_out8(0x3d4, 0x86, par);
1375         vga_out8(0x3d5, reg->CR86, par);
1376         vga_out8(0x3d4, 0x88, par);
1377         vga_out8(0x3d5, reg->CR88, par);
1378         vga_out8(0x3d4, 0x90, par);
1379         vga_out8(0x3d5, reg->CR90, par);
1380         vga_out8(0x3d4, 0x91, par);
1381         vga_out8(0x3d5, reg->CR91, par);
1382
1383         if (par->chip == S3_SAVAGE4) {
1384                 vga_out8(0x3d4, 0xb0, par);
1385                 vga_out8(0x3d5, reg->CRB0, par);
1386         }
1387
1388         vga_out8(0x3d4, 0x32, par);
1389         vga_out8(0x3d5, reg->CR32, par);
1390
1391         /* unlock extended seq regs */
1392         vga_out8(0x3c4, 0x08, par);
1393         vga_out8(0x3c5, 0x06, par);
1394
1395         /* Restore extended sequencer regs for MCLK. SR10 == 255 indicates
1396          * that we should leave the default SR10 and SR11 values there.
1397          */
1398         if (reg->SR10 != 255) {
1399                 vga_out8(0x3c4, 0x10, par);
1400                 vga_out8(0x3c5, reg->SR10, par);
1401                 vga_out8(0x3c4, 0x11, par);
1402                 vga_out8(0x3c5, reg->SR11, par);
1403         }
1404
1405         /* restore extended seq regs for dclk */
1406         vga_out8(0x3c4, 0x0e, par);
1407         vga_out8(0x3c5, reg->SR0E, par);
1408         vga_out8(0x3c4, 0x0f, par);
1409         vga_out8(0x3c5, reg->SR0F, par);
1410         vga_out8(0x3c4, 0x12, par);
1411         vga_out8(0x3c5, reg->SR12, par);
1412         vga_out8(0x3c4, 0x13, par);
1413         vga_out8(0x3c5, reg->SR13, par);
1414         vga_out8(0x3c4, 0x29, par);
1415         vga_out8(0x3c5, reg->SR29, par);
1416         vga_out8(0x3c4, 0x18, par);
1417         vga_out8(0x3c5, reg->SR18, par);
1418
1419         /* load new m, n pll values for dclk & mclk */
1420         vga_out8(0x3c4, 0x15, par);
1421         tmp = vga_in8(0x3c5, par) & ~0x21;
1422
1423         vga_out8(0x3c5, tmp | 0x03, par);
1424         vga_out8(0x3c5, tmp | 0x23, par);
1425         vga_out8(0x3c5, tmp | 0x03, par);
1426         vga_out8(0x3c5, reg->SR15, par);
1427         udelay(100);
1428
1429         vga_out8(0x3c4, 0x30, par);
1430         vga_out8(0x3c5, reg->SR30, par);
1431         vga_out8(0x3c4, 0x08, par);
1432         vga_out8(0x3c5, reg->SR08, par);
1433
1434         /* now write out cr67 in full, possibly starting STREAMS */
1435         VerticalRetraceWait(par);
1436         vga_out8(0x3d4, 0x67, par);
1437         vga_out8(0x3d5, reg->CR67, par);
1438
1439         vga_out8(0x3d4, 0x66, par);
1440         cr66 = vga_in8(0x3d5, par);
1441         vga_out8(0x3d5, cr66 | 0x80, par);
1442         vga_out8(0x3d4, 0x3a, par);
1443         cr3a = vga_in8(0x3d5, par);
1444         vga_out8(0x3d5, cr3a | 0x80, par);
1445
1446         if (par->chip != S3_SAVAGE_MX) {
1447                 VerticalRetraceWait(par);
1448                 savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par);
1449                 par->SavageWaitIdle(par);
1450                 savage_out32(MIU_CONTROL_REG, reg->MMPR1, par);
1451                 par->SavageWaitIdle(par);
1452                 savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par);
1453                 par->SavageWaitIdle(par);
1454                 savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par);
1455         }
1456
1457         vga_out8(0x3d4, 0x66, par);
1458         vga_out8(0x3d5, cr66, par);
1459         vga_out8(0x3d4, 0x3a, par);
1460         vga_out8(0x3d5, cr3a, par);
1461
1462         SavageSetup2DEngine(par);
1463         vgaHWProtect(par, 0);
1464 }
1465
1466 static void savagefb_update_start(struct savagefb_par      *par,
1467                                   struct fb_var_screeninfo *var)
1468 {
1469         int base;
1470
1471         base = ((var->yoffset * var->xres_virtual + (var->xoffset & ~1))
1472                 * ((var->bits_per_pixel+7) / 8)) >> 2;
1473
1474         /* now program the start address registers */
1475         vga_out16(0x3d4, (base & 0x00ff00) | 0x0c, par);
1476         vga_out16(0x3d4, ((base & 0x00ff) << 8) | 0x0d, par);
1477         vga_out8(0x3d4, 0x69, par);
1478         vga_out8(0x3d5, (base & 0x7f0000) >> 16, par);
1479 }
1480
1481
1482 static void savagefb_set_fix(struct fb_info *info)
1483 {
1484         info->fix.line_length = info->var.xres_virtual *
1485                 info->var.bits_per_pixel / 8;
1486
1487         if (info->var.bits_per_pixel == 8) {
1488                 info->fix.visual      = FB_VISUAL_PSEUDOCOLOR;
1489                 info->fix.xpanstep    = 4;
1490         } else {
1491                 info->fix.visual      = FB_VISUAL_TRUECOLOR;
1492                 info->fix.xpanstep    = 2;
1493         }
1494
1495 }
1496
1497 static int savagefb_set_par(struct fb_info *info)
1498 {
1499         struct savagefb_par *par = info->par;
1500         struct fb_var_screeninfo *var = &info->var;
1501         int err;
1502
1503         DBG("savagefb_set_par");
1504         err = savagefb_decode_var(var, par, &par->state);
1505         if (err)
1506                 return err;
1507
1508         if (par->dacSpeedBpp <= 0) {
1509                 if (var->bits_per_pixel > 24)
1510                         par->dacSpeedBpp = par->clock[3];
1511                 else if (var->bits_per_pixel >= 24)
1512                         par->dacSpeedBpp = par->clock[2];
1513                 else if ((var->bits_per_pixel > 8) && (var->bits_per_pixel < 24))
1514                         par->dacSpeedBpp = par->clock[1];
1515                 else if (var->bits_per_pixel <= 8)
1516                         par->dacSpeedBpp = par->clock[0];
1517         }
1518
1519         /* Set ramdac limits */
1520         par->maxClock = par->dacSpeedBpp;
1521         par->minClock = 10000;
1522
1523         savagefb_set_par_int(par, &par->state);
1524         fb_set_cmap(&info->cmap, info);
1525         savagefb_set_fix(info);
1526         savagefb_set_clip(info);
1527
1528         SavagePrintRegs();
1529         return 0;
1530 }
1531
1532 /*
1533  *    Pan or Wrap the Display
1534  */
1535 static int savagefb_pan_display(struct fb_var_screeninfo *var,
1536                                 struct fb_info           *info)
1537 {
1538         struct savagefb_par *par = info->par;
1539
1540         savagefb_update_start(par, var);
1541         return 0;
1542 }
1543
1544 static int savagefb_blank(int blank, struct fb_info *info)
1545 {
1546         struct savagefb_par *par = info->par;
1547         u8 sr8 = 0, srd = 0;
1548
1549         if (par->display_type == DISP_CRT) {
1550                 vga_out8(0x3c4, 0x08, par);
1551                 sr8 = vga_in8(0x3c5, par);
1552                 sr8 |= 0x06;
1553                 vga_out8(0x3c5, sr8, par);
1554                 vga_out8(0x3c4, 0x0d, par);
1555                 srd = vga_in8(0x3c5, par);
1556                 srd &= 0x03;
1557
1558                 switch (blank) {
1559                 case FB_BLANK_UNBLANK:
1560                 case FB_BLANK_NORMAL:
1561                         break;
1562                 case FB_BLANK_VSYNC_SUSPEND:
1563                         srd |= 0x10;
1564                         break;
1565                 case FB_BLANK_HSYNC_SUSPEND:
1566                         srd |= 0x40;
1567                         break;
1568                 case FB_BLANK_POWERDOWN:
1569                         srd |= 0x50;
1570                         break;
1571                 }
1572
1573                 vga_out8(0x3c4, 0x0d, par);
1574                 vga_out8(0x3c5, srd, par);
1575         }
1576
1577         if (par->display_type == DISP_LCD ||
1578             par->display_type == DISP_DFP) {
1579                 switch(blank) {
1580                 case FB_BLANK_UNBLANK:
1581                 case FB_BLANK_NORMAL:
1582                         vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */
1583                         vga_out8(0x3c5, vga_in8(0x3c5, par) | 0x10, par);
1584                         break;
1585                 case FB_BLANK_VSYNC_SUSPEND:
1586                 case FB_BLANK_HSYNC_SUSPEND:
1587                 case FB_BLANK_POWERDOWN:
1588                         vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */
1589                         vga_out8(0x3c5, vga_in8(0x3c5, par) & ~0x10, par);
1590                         break;
1591                 }
1592         }
1593
1594         return (blank == FB_BLANK_NORMAL) ? 1 : 0;
1595 }
1596
1597 static void savagefb_save_state(struct fb_info *info)
1598 {
1599         struct savagefb_par *par = info->par;
1600
1601         savage_get_default_par(par, &par->save);
1602 }
1603
1604 static void savagefb_restore_state(struct fb_info *info)
1605 {
1606         struct savagefb_par *par = info->par;
1607
1608         savagefb_blank(FB_BLANK_POWERDOWN, info);
1609         savage_set_default_par(par, &par->save);
1610         savagefb_blank(FB_BLANK_UNBLANK, info);
1611 }
1612
1613 static struct fb_ops savagefb_ops = {
1614         .owner          = THIS_MODULE,
1615         .fb_check_var   = savagefb_check_var,
1616         .fb_set_par     = savagefb_set_par,
1617         .fb_setcolreg   = savagefb_setcolreg,
1618         .fb_pan_display = savagefb_pan_display,
1619         .fb_blank       = savagefb_blank,
1620         .fb_save_state  = savagefb_save_state,
1621         .fb_restore_state = savagefb_restore_state,
1622 #if defined(CONFIG_FB_SAVAGE_ACCEL)
1623         .fb_fillrect    = savagefb_fillrect,
1624         .fb_copyarea    = savagefb_copyarea,
1625         .fb_imageblit   = savagefb_imageblit,
1626         .fb_sync        = savagefb_sync,
1627 #else
1628         .fb_fillrect    = cfb_fillrect,
1629         .fb_copyarea    = cfb_copyarea,
1630         .fb_imageblit   = cfb_imageblit,
1631 #endif
1632 };
1633
1634 /* --------------------------------------------------------------------- */
1635
1636 static struct fb_var_screeninfo __devinitdata savagefb_var800x600x8 = {
1637         .accel_flags =  FB_ACCELF_TEXT,
1638         .xres =         800,
1639         .yres =         600,
1640         .xres_virtual =  800,
1641         .yres_virtual =  600,
1642         .bits_per_pixel = 8,
1643         .pixclock =     25000,
1644         .left_margin =  88,
1645         .right_margin = 40,
1646         .upper_margin = 23,
1647         .lower_margin = 1,
1648         .hsync_len =    128,
1649         .vsync_len =    4,
1650         .sync =         FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
1651         .vmode =        FB_VMODE_NONINTERLACED
1652 };
1653
1654 static void savage_enable_mmio(struct savagefb_par *par)
1655 {
1656         unsigned char val;
1657
1658         DBG("savage_enable_mmio\n");
1659
1660         val = vga_in8(0x3c3, par);
1661         vga_out8(0x3c3, val | 0x01, par);
1662         val = vga_in8(0x3cc, par);
1663         vga_out8(0x3c2, val | 0x01, par);
1664
1665         if (par->chip >= S3_SAVAGE4) {
1666                 vga_out8(0x3d4, 0x40, par);
1667                 val = vga_in8(0x3d5, par);
1668                 vga_out8(0x3d5, val | 1, par);
1669         }
1670 }
1671
1672
1673 static void savage_disable_mmio(struct savagefb_par *par)
1674 {
1675         unsigned char val;
1676
1677         DBG("savage_disable_mmio\n");
1678
1679         if (par->chip >= S3_SAVAGE4) {
1680                 vga_out8(0x3d4, 0x40, par);
1681                 val = vga_in8(0x3d5, par);
1682                 vga_out8(0x3d5, val | 1, par);
1683         }
1684 }
1685
1686
1687 static int __devinit savage_map_mmio(struct fb_info *info)
1688 {
1689         struct savagefb_par *par = info->par;
1690         DBG("savage_map_mmio");
1691
1692         if (S3_SAVAGE3D_SERIES(par->chip))
1693                 par->mmio.pbase = pci_resource_start(par->pcidev, 0) +
1694                         SAVAGE_NEWMMIO_REGBASE_S3;
1695         else
1696                 par->mmio.pbase = pci_resource_start(par->pcidev, 0) +
1697                         SAVAGE_NEWMMIO_REGBASE_S4;
1698
1699         par->mmio.len = SAVAGE_NEWMMIO_REGSIZE;
1700
1701         par->mmio.vbase = ioremap(par->mmio.pbase, par->mmio.len);
1702         if (!par->mmio.vbase) {
1703                 printk("savagefb: unable to map memory mapped IO\n");
1704                 return -ENOMEM;
1705         } else
1706                 printk(KERN_INFO "savagefb: mapped io at %p\n",
1707                         par->mmio.vbase);
1708
1709         info->fix.mmio_start = par->mmio.pbase;
1710         info->fix.mmio_len   = par->mmio.len;
1711
1712         par->bci_base = (u32 __iomem *)(par->mmio.vbase + BCI_BUFFER_OFFSET);
1713         par->bci_ptr  = 0;
1714
1715         savage_enable_mmio(par);
1716
1717         return 0;
1718 }
1719
1720 static void savage_unmap_mmio(struct fb_info *info)
1721 {
1722         struct savagefb_par *par = info->par;
1723         DBG("savage_unmap_mmio");
1724
1725         savage_disable_mmio(par);
1726
1727         if (par->mmio.vbase) {
1728                 iounmap(par->mmio.vbase);
1729                 par->mmio.vbase = NULL;
1730         }
1731 }
1732
1733 static int __devinit savage_map_video(struct fb_info *info,
1734                                       int video_len)
1735 {
1736         struct savagefb_par *par = info->par;
1737         int resource;
1738
1739         DBG("savage_map_video");
1740
1741         if (S3_SAVAGE3D_SERIES(par->chip))
1742                 resource = 0;
1743         else
1744                 resource = 1;
1745
1746         par->video.pbase = pci_resource_start(par->pcidev, resource);
1747         par->video.len   = video_len;
1748         par->video.vbase = ioremap(par->video.pbase, par->video.len);
1749
1750         if (!par->video.vbase) {
1751                 printk("savagefb: unable to map screen memory\n");
1752                 return -ENOMEM;
1753         } else
1754                 printk(KERN_INFO "savagefb: mapped framebuffer at %p, "
1755                        "pbase == %x\n", par->video.vbase, par->video.pbase);
1756
1757         info->fix.smem_start = par->video.pbase;
1758         info->fix.smem_len   = par->video.len - par->cob_size;
1759         info->screen_base    = par->video.vbase;
1760
1761 #ifdef CONFIG_MTRR
1762         par->video.mtrr = mtrr_add(par->video.pbase, video_len,
1763                                    MTRR_TYPE_WRCOMB, 1);
1764 #endif
1765
1766         /* Clear framebuffer, it's all white in memory after boot */
1767         memset_io(par->video.vbase, 0, par->video.len);
1768
1769         return 0;
1770 }
1771
1772 static void savage_unmap_video(struct fb_info *info)
1773 {
1774         struct savagefb_par *par = info->par;
1775
1776         DBG("savage_unmap_video");
1777
1778         if (par->video.vbase) {
1779 #ifdef CONFIG_MTRR
1780                 mtrr_del(par->video.mtrr, par->video.pbase, par->video.len);
1781 #endif
1782
1783                 iounmap(par->video.vbase);
1784                 par->video.vbase = NULL;
1785                 info->screen_base = NULL;
1786         }
1787 }
1788
1789 static int savage_init_hw(struct savagefb_par *par)
1790 {
1791         unsigned char config1, m, n, n1, n2, sr8, cr3f, cr66 = 0, tmp;
1792
1793         static unsigned char RamSavage3D[] = { 8, 4, 4, 2 };
1794         static unsigned char RamSavage4[] =  { 2, 4, 8, 12, 16, 32, 64, 32 };
1795         static unsigned char RamSavageMX[] = { 2, 8, 4, 16, 8, 16, 4, 16 };
1796         static unsigned char RamSavageNB[] = { 0, 2, 4, 8, 16, 32, 2, 2 };
1797         int videoRam, videoRambytes, dvi;
1798
1799         DBG("savage_init_hw");
1800
1801         /* unprotect CRTC[0-7] */
1802         vga_out8(0x3d4, 0x11, par);
1803         tmp = vga_in8(0x3d5, par);
1804         vga_out8(0x3d5, tmp & 0x7f, par);
1805
1806         /* unlock extended regs */
1807         vga_out16(0x3d4, 0x4838, par);
1808         vga_out16(0x3d4, 0xa039, par);
1809         vga_out16(0x3c4, 0x0608, par);
1810
1811         vga_out8(0x3d4, 0x40, par);
1812         tmp = vga_in8(0x3d5, par);
1813         vga_out8(0x3d5, tmp & ~0x01, par);
1814
1815         /* unlock sys regs */
1816         vga_out8(0x3d4, 0x38, par);
1817         vga_out8(0x3d5, 0x48, par);
1818
1819         /* Unlock system registers. */
1820         vga_out16(0x3d4, 0x4838, par);
1821
1822         /* Next go on to detect amount of installed ram */
1823
1824         vga_out8(0x3d4, 0x36, par);            /* for register CR36 (CONFG_REG1), */
1825         config1 = vga_in8(0x3d5, par);    /* get amount of vram installed */
1826
1827         /* Compute the amount of video memory and offscreen memory. */
1828
1829         switch  (par->chip) {
1830         case S3_SAVAGE3D:
1831                 videoRam = RamSavage3D[(config1 & 0xC0) >> 6 ] * 1024;
1832                 break;
1833
1834         case S3_SAVAGE4:
1835                 /*
1836                  * The Savage4 has one ugly special case to consider.  On
1837                  * systems with 4 banks of 2Mx32 SDRAM, the BIOS says 4MB
1838                  * when it really means 8MB.  Why do it the same when you
1839                  * can do it different...
1840                  */
1841                 vga_out8(0x3d4, 0x68, par);     /* memory control 1 */
1842                 if ((vga_in8(0x3d5, par) & 0xC0) == (0x01 << 6))
1843                         RamSavage4[1] = 8;
1844
1845                 /*FALLTHROUGH*/
1846
1847         case S3_SAVAGE2000:
1848                 videoRam = RamSavage4[(config1 & 0xE0) >> 5] * 1024;
1849                 break;
1850
1851         case S3_SAVAGE_MX:
1852         case S3_SUPERSAVAGE:
1853                 videoRam = RamSavageMX[(config1 & 0x0E) >> 1] * 1024;
1854                 break;
1855
1856         case S3_PROSAVAGE:
1857                 videoRam = RamSavageNB[(config1 & 0xE0) >> 5] * 1024;
1858                 break;
1859
1860         default:
1861                 /* How did we get here? */
1862                 videoRam = 0;
1863                 break;
1864         }
1865
1866         videoRambytes = videoRam * 1024;
1867
1868         printk(KERN_INFO "savagefb: probed videoram:  %dk\n", videoRam);
1869
1870         /* reset graphics engine to avoid memory corruption */
1871         vga_out8(0x3d4, 0x66, par);
1872         cr66 = vga_in8(0x3d5, par);
1873         vga_out8(0x3d5, cr66 | 0x02, par);
1874         udelay(10000);
1875
1876         vga_out8(0x3d4, 0x66, par);
1877         vga_out8(0x3d5, cr66 & ~0x02, par);     /* clear reset flag */
1878         udelay(10000);
1879
1880
1881         /*
1882          * reset memory interface, 3D engine, AGP master, PCI master,
1883          * master engine unit, motion compensation/LPB
1884          */
1885         vga_out8(0x3d4, 0x3f, par);
1886         cr3f = vga_in8(0x3d5, par);
1887         vga_out8(0x3d5, cr3f | 0x08, par);
1888         udelay(10000);
1889
1890         vga_out8(0x3d4, 0x3f, par);
1891         vga_out8(0x3d5, cr3f & ~0x08, par);     /* clear reset flags */
1892         udelay(10000);
1893
1894         /* Savage ramdac speeds */
1895         par->numClocks = 4;
1896         par->clock[0] = 250000;
1897         par->clock[1] = 250000;
1898         par->clock[2] = 220000;
1899         par->clock[3] = 220000;
1900
1901         /* detect current mclk */
1902         vga_out8(0x3c4, 0x08, par);
1903         sr8 = vga_in8(0x3c5, par);
1904         vga_out8(0x3c5, 0x06, par);
1905         vga_out8(0x3c4, 0x10, par);
1906         n = vga_in8(0x3c5, par);
1907         vga_out8(0x3c4, 0x11, par);
1908         m = vga_in8(0x3c5, par);
1909         vga_out8(0x3c4, 0x08, par);
1910         vga_out8(0x3c5, sr8, par);
1911         m &= 0x7f;
1912         n1 = n & 0x1f;
1913         n2 = (n >> 5) & 0x03;
1914         par->MCLK = ((1431818 * (m+2)) / (n1+2) / (1 << n2) + 50) / 100;
1915         printk(KERN_INFO "savagefb: Detected current MCLK value of %d kHz\n",
1916                 par->MCLK);
1917
1918         /* check for DVI/flat panel */
1919         dvi = 0;
1920
1921         if (par->chip == S3_SAVAGE4) {
1922                 unsigned char sr30 = 0x00;
1923
1924                 vga_out8(0x3c4, 0x30, par);
1925                 /* clear bit 1 */
1926                 vga_out8(0x3c5, vga_in8(0x3c5, par) & ~0x02, par);
1927                 sr30 = vga_in8(0x3c5, par);
1928                 if (sr30 & 0x02 /*0x04 */) {
1929                         dvi = 1;
1930                         printk("savagefb: Digital Flat Panel Detected\n");
1931                 }
1932         }
1933
1934         if (S3_SAVAGE_MOBILE_SERIES(par->chip) && !par->crtonly)
1935                 par->display_type = DISP_LCD;
1936         else if (dvi || (par->chip == S3_SAVAGE4 && par->dvi))
1937                 par->display_type = DISP_DFP;
1938         else
1939                 par->display_type = DISP_CRT;
1940
1941         /* Check LCD panel parrmation */
1942
1943         if (par->display_type == DISP_LCD) {
1944                 unsigned char cr6b = VGArCR(0x6b, par);
1945
1946                 int panelX = (VGArSEQ(0x61, par) +
1947                               ((VGArSEQ(0x66, par) & 0x02) << 7) + 1) * 8;
1948                 int panelY = (VGArSEQ(0x69, par) +
1949                               ((VGArSEQ(0x6e, par) & 0x70) << 4) + 1);
1950
1951                 char * sTechnology = "Unknown";
1952
1953                 /* OK, I admit it.  I don't know how to limit the max dot clock
1954                  * for LCD panels of various sizes.  I thought I copied the
1955                  * formula from the BIOS, but many users have parrmed me of
1956                  * my folly.
1957                  *
1958                  * Instead, I'll abandon any attempt to automatically limit the
1959                  * clock, and add an LCDClock option to XF86Config.  Some day,
1960                  * I should come back to this.
1961                  */
1962
1963                 enum ACTIVE_DISPLAYS { /* These are the bits in CR6B */
1964                         ActiveCRT = 0x01,
1965                         ActiveLCD = 0x02,
1966                         ActiveTV = 0x04,
1967                         ActiveCRT2 = 0x20,
1968                         ActiveDUO = 0x80
1969                 };
1970
1971                 if ((VGArSEQ(0x39, par) & 0x03) == 0) {
1972                         sTechnology = "TFT";
1973                 } else if ((VGArSEQ(0x30, par) & 0x01) == 0) {
1974                         sTechnology = "DSTN";
1975                 } else  {
1976                         sTechnology = "STN";
1977                 }
1978
1979                 printk(KERN_INFO "savagefb: %dx%d %s LCD panel detected %s\n",
1980                        panelX, panelY, sTechnology,
1981                        cr6b & ActiveLCD ? "and active" : "but not active");
1982
1983                 if (cr6b & ActiveLCD)   {
1984                         /*
1985                          * If the LCD is active and panel expansion is enabled,
1986                          * we probably want to kill the HW cursor.
1987                          */
1988
1989                         printk(KERN_INFO "savagefb: Limiting video mode to "
1990                                 "%dx%d\n", panelX, panelY);
1991
1992                         par->SavagePanelWidth = panelX;
1993                         par->SavagePanelHeight = panelY;
1994
1995                 } else
1996                         par->display_type = DISP_CRT;
1997         }
1998
1999         savage_get_default_par(par, &par->state);
2000         par->save = par->state;
2001
2002         if (S3_SAVAGE4_SERIES(par->chip)) {
2003                 /*
2004                  * The Savage4 and ProSavage have COB coherency bugs which
2005                  * render the buffer useless.  We disable it.
2006                  */
2007                 par->cob_index = 2;
2008                 par->cob_size = 0x8000 << par->cob_index;
2009                 par->cob_offset = videoRambytes;
2010         } else {
2011                 /* We use 128kB for the COB on all chips. */
2012
2013                 par->cob_index  = 7;
2014                 par->cob_size   = 0x400 << par->cob_index;
2015                 par->cob_offset = videoRambytes - par->cob_size;
2016         }
2017
2018         return videoRambytes;
2019 }
2020
2021 static int __devinit savage_init_fb_info(struct fb_info *info,
2022                                          struct pci_dev *dev,
2023                                          const struct pci_device_id *id)
2024 {
2025         struct savagefb_par *par = info->par;
2026         int err = 0;
2027
2028         par->pcidev  = dev;
2029
2030         info->fix.type     = FB_TYPE_PACKED_PIXELS;
2031         info->fix.type_aux         = 0;
2032         info->fix.ypanstep         = 1;
2033         info->fix.ywrapstep   = 0;
2034         info->fix.accel       = id->driver_data;
2035
2036         switch (info->fix.accel) {
2037         case FB_ACCEL_SUPERSAVAGE:
2038                 par->chip = S3_SUPERSAVAGE;
2039                 snprintf(info->fix.id, 16, "SuperSavage");
2040                 break;
2041         case FB_ACCEL_SAVAGE4:
2042                 par->chip = S3_SAVAGE4;
2043                 snprintf(info->fix.id, 16, "Savage4");
2044                 break;
2045         case FB_ACCEL_SAVAGE3D:
2046                 par->chip = S3_SAVAGE3D;
2047                 snprintf(info->fix.id, 16, "Savage3D");
2048                 break;
2049         case FB_ACCEL_SAVAGE3D_MV:
2050                 par->chip = S3_SAVAGE3D;
2051                 snprintf(info->fix.id, 16, "Savage3D-MV");
2052                 break;
2053         case FB_ACCEL_SAVAGE2000:
2054                 par->chip = S3_SAVAGE2000;
2055                 snprintf(info->fix.id, 16, "Savage2000");
2056                 break;
2057         case FB_ACCEL_SAVAGE_MX_MV:
2058                 par->chip = S3_SAVAGE_MX;
2059                 snprintf(info->fix.id, 16, "Savage/MX-MV");
2060                 break;
2061         case FB_ACCEL_SAVAGE_MX:
2062                 par->chip = S3_SAVAGE_MX;
2063                 snprintf(info->fix.id, 16, "Savage/MX");
2064                 break;
2065         case FB_ACCEL_SAVAGE_IX_MV:
2066                 par->chip = S3_SAVAGE_MX;
2067                 snprintf(info->fix.id, 16, "Savage/IX-MV");
2068                 break;
2069         case FB_ACCEL_SAVAGE_IX:
2070                 par->chip = S3_SAVAGE_MX;
2071                 snprintf(info->fix.id, 16, "Savage/IX");
2072                 break;
2073         case FB_ACCEL_PROSAVAGE_PM:
2074                 par->chip = S3_PROSAVAGE;
2075                 snprintf(info->fix.id, 16, "ProSavagePM");
2076                 break;
2077         case FB_ACCEL_PROSAVAGE_KM:
2078                 par->chip = S3_PROSAVAGE;
2079                 snprintf(info->fix.id, 16, "ProSavageKM");
2080                 break;
2081         case FB_ACCEL_S3TWISTER_P:
2082                 par->chip = S3_PROSAVAGE;
2083                 snprintf(info->fix.id, 16, "TwisterP");
2084                 break;
2085         case FB_ACCEL_S3TWISTER_K:
2086                 par->chip = S3_PROSAVAGE;
2087                 snprintf(info->fix.id, 16, "TwisterK");
2088                 break;
2089         case FB_ACCEL_PROSAVAGE_DDR:
2090                 par->chip = S3_PROSAVAGE;
2091                 snprintf(info->fix.id, 16, "ProSavageDDR");
2092                 break;
2093         case FB_ACCEL_PROSAVAGE_DDRK:
2094                 par->chip = S3_PROSAVAGE;
2095                 snprintf(info->fix.id, 16, "ProSavage8");
2096                 break;
2097         }
2098
2099         if (S3_SAVAGE3D_SERIES(par->chip)) {
2100                 par->SavageWaitIdle = savage3D_waitidle;
2101                 par->SavageWaitFifo = savage3D_waitfifo;
2102         } else if (S3_SAVAGE4_SERIES(par->chip) ||
2103                    S3_SUPERSAVAGE == par->chip) {
2104                 par->SavageWaitIdle = savage4_waitidle;
2105                 par->SavageWaitFifo = savage4_waitfifo;
2106         } else {
2107                 par->SavageWaitIdle = savage2000_waitidle;
2108                 par->SavageWaitFifo = savage2000_waitfifo;
2109         }
2110
2111         info->var.nonstd      = 0;
2112         info->var.activate    = FB_ACTIVATE_NOW;
2113         info->var.width       = -1;
2114         info->var.height      = -1;
2115         info->var.accel_flags = 0;
2116
2117         info->fbops          = &savagefb_ops;
2118         info->flags          = FBINFO_DEFAULT |
2119                                FBINFO_HWACCEL_YPAN |
2120                                FBINFO_HWACCEL_XPAN;
2121
2122         info->pseudo_palette = par->pseudo_palette;
2123
2124 #if defined(CONFIG_FB_SAVAGE_ACCEL)
2125         /* FIFO size + padding for commands */
2126         info->pixmap.addr = kmalloc(8*1024, GFP_KERNEL);
2127
2128         err = -ENOMEM;
2129         if (info->pixmap.addr) {
2130                 memset(info->pixmap.addr, 0, 8*1024);
2131                 info->pixmap.size = 8*1024;
2132                 info->pixmap.scan_align = 4;
2133                 info->pixmap.buf_align = 4;
2134                 info->pixmap.access_align = 32;
2135
2136                 err = fb_alloc_cmap(&info->cmap, NR_PALETTE, 0);
2137                 if (!err)
2138                 info->flags |= FBINFO_HWACCEL_COPYAREA |
2139                                FBINFO_HWACCEL_FILLRECT |
2140                                FBINFO_HWACCEL_IMAGEBLIT;
2141         }
2142 #endif
2143         return err;
2144 }
2145
2146 /* --------------------------------------------------------------------- */
2147
2148 static int __devinit savagefb_probe(struct pci_dev* dev,
2149                                     const struct pci_device_id* id)
2150 {
2151         struct fb_info *info;
2152         struct savagefb_par *par;
2153         u_int h_sync, v_sync;
2154         int err, lpitch;
2155         int video_len;
2156
2157         DBG("savagefb_probe");
2158         SavagePrintRegs();
2159
2160         info = framebuffer_alloc(sizeof(struct savagefb_par), &dev->dev);
2161         if (!info)
2162                 return -ENOMEM;
2163         par = info->par;
2164         err = pci_enable_device(dev);
2165         if (err)
2166                 goto failed_enable;
2167
2168         if ((err = pci_request_regions(dev, "savagefb"))) {
2169                 printk(KERN_ERR "cannot request PCI regions\n");
2170                 goto failed_enable;
2171         }
2172
2173         err = -ENOMEM;
2174
2175         if ((err = savage_init_fb_info(info, dev, id)))
2176                 goto failed_init;
2177
2178         err = savage_map_mmio(info);
2179         if (err)
2180                 goto failed_mmio;
2181
2182         video_len = savage_init_hw(par);
2183         /* FIXME: cant be negative */
2184         if (video_len < 0) {
2185                 err = video_len;
2186                 goto failed_mmio;
2187         }
2188
2189         err = savage_map_video(info, video_len);
2190         if (err)
2191                 goto failed_video;
2192
2193         INIT_LIST_HEAD(&info->modelist);
2194 #if defined(CONFIG_FB_SAVAGE_I2C)
2195         savagefb_create_i2c_busses(info);
2196         savagefb_probe_i2c_connector(info, &par->edid);
2197         fb_edid_to_monspecs(par->edid, &info->monspecs);
2198         kfree(par->edid);
2199         fb_videomode_to_modelist(info->monspecs.modedb,
2200                                  info->monspecs.modedb_len,
2201                                  &info->modelist);
2202 #endif
2203         info->var = savagefb_var800x600x8;
2204
2205         if (mode_option) {
2206                 fb_find_mode(&info->var, info, mode_option,
2207                              info->monspecs.modedb, info->monspecs.modedb_len,
2208                              NULL, 8);
2209         } else if (info->monspecs.modedb != NULL) {
2210                 struct fb_videomode *modedb;
2211
2212                 modedb = fb_find_best_display(&info->monspecs,
2213                                               &info->modelist);
2214                 savage_update_var(&info->var, modedb);
2215         }
2216
2217         /* maximize virtual vertical length */
2218         lpitch = info->var.xres_virtual*((info->var.bits_per_pixel + 7) >> 3);
2219         info->var.yres_virtual = info->fix.smem_len/lpitch;
2220
2221         if (info->var.yres_virtual < info->var.yres)
2222                 goto failed;
2223
2224 #if defined(CONFIG_FB_SAVAGE_ACCEL)
2225         /*
2226          * The clipping coordinates are masked with 0xFFF, so limit our
2227          * virtual resolutions to these sizes.
2228          */
2229         if (info->var.yres_virtual > 0x1000)
2230                 info->var.yres_virtual = 0x1000;
2231
2232         if (info->var.xres_virtual > 0x1000)
2233                 info->var.xres_virtual = 0x1000;
2234 #endif
2235         savagefb_check_var(&info->var, info);
2236         savagefb_set_fix(info);
2237
2238         /*
2239          * Calculate the hsync and vsync frequencies.  Note that
2240          * we split the 1e12 constant up so that we can preserve
2241          * the precision and fit the results into 32-bit registers.
2242          *  (1953125000 * 512 = 1e12)
2243          */
2244         h_sync = 1953125000 / info->var.pixclock;
2245         h_sync = h_sync * 512 / (info->var.xres + info->var.left_margin +
2246                                  info->var.right_margin +
2247                                  info->var.hsync_len);
2248         v_sync = h_sync / (info->var.yres + info->var.upper_margin +
2249                            info->var.lower_margin + info->var.vsync_len);
2250
2251         printk(KERN_INFO "savagefb v" SAVAGEFB_VERSION ": "
2252                "%dkB VRAM, using %dx%d, %d.%03dkHz, %dHz\n",
2253                info->fix.smem_len >> 10,
2254                info->var.xres, info->var.yres,
2255                h_sync / 1000, h_sync % 1000, v_sync);
2256
2257
2258         fb_destroy_modedb(info->monspecs.modedb);
2259         info->monspecs.modedb = NULL;
2260
2261         err = register_framebuffer(info);
2262         if (err < 0)
2263                 goto failed;
2264
2265         printk(KERN_INFO "fb: S3 %s frame buffer device\n",
2266                info->fix.id);
2267
2268         /*
2269          * Our driver data
2270          */
2271         pci_set_drvdata(dev, info);
2272
2273         return 0;
2274
2275  failed:
2276 #ifdef CONFIG_FB_SAVAGE_I2C
2277         savagefb_delete_i2c_busses(info);
2278 #endif
2279         fb_alloc_cmap(&info->cmap, 0, 0);
2280         savage_unmap_video(info);
2281  failed_video:
2282         savage_unmap_mmio(info);
2283  failed_mmio:
2284         kfree(info->pixmap.addr);
2285  failed_init:
2286         pci_release_regions(dev);
2287  failed_enable:
2288         framebuffer_release(info);
2289
2290         return err;
2291 }
2292
2293 static void __devexit savagefb_remove(struct pci_dev *dev)
2294 {
2295         struct fb_info *info = pci_get_drvdata(dev);
2296
2297         DBG("savagefb_remove");
2298
2299         if (info) {
2300                 /*
2301                  * If unregister_framebuffer fails, then
2302                  * we will be leaving hooks that could cause
2303                  * oopsen laying around.
2304                  */
2305                 if (unregister_framebuffer(info))
2306                         printk(KERN_WARNING "savagefb: danger danger! "
2307                                "Oopsen imminent!\n");
2308
2309 #ifdef CONFIG_FB_SAVAGE_I2C
2310                 savagefb_delete_i2c_busses(info);
2311 #endif
2312                 fb_alloc_cmap(&info->cmap, 0, 0);
2313                 savage_unmap_video(info);
2314                 savage_unmap_mmio(info);
2315                 kfree(info->pixmap.addr);
2316                 pci_release_regions(dev);
2317                 framebuffer_release(info);
2318
2319                 /*
2320                  * Ensure that the driver data is no longer
2321                  * valid.
2322                  */
2323                 pci_set_drvdata(dev, NULL);
2324         }
2325 }
2326
2327 static int savagefb_suspend(struct pci_dev* dev, pm_message_t state)
2328 {
2329         struct fb_info *info = pci_get_drvdata(dev);
2330         struct savagefb_par *par = info->par;
2331
2332         DBG("savagefb_suspend");
2333
2334
2335         par->pm_state = state.event;
2336
2337         /*
2338          * For PM_EVENT_FREEZE, do not power down so the console
2339          * can remain active.
2340          */
2341         if (state.event == PM_EVENT_FREEZE) {
2342                 dev->dev.power.power_state = state;
2343                 return 0;
2344         }
2345
2346         acquire_console_sem();
2347         fb_set_suspend(info, 1);
2348
2349         if (info->fbops->fb_sync)
2350                 info->fbops->fb_sync(info);
2351
2352         savagefb_blank(FB_BLANK_POWERDOWN, info);
2353         savage_set_default_par(par, &par->save);
2354         savage_disable_mmio(par);
2355         pci_save_state(dev);
2356         pci_disable_device(dev);
2357         pci_set_power_state(dev, pci_choose_state(dev, state));
2358         release_console_sem();
2359
2360         return 0;
2361 }
2362
2363 static int savagefb_resume(struct pci_dev* dev)
2364 {
2365         struct fb_info *info = pci_get_drvdata(dev);
2366         struct savagefb_par *par = info->par;
2367         int cur_state = par->pm_state;
2368
2369         DBG("savage_resume");
2370
2371         par->pm_state = PM_EVENT_ON;
2372
2373         /*
2374          * The adapter was not powered down coming back from a
2375          * PM_EVENT_FREEZE.
2376          */
2377         if (cur_state == PM_EVENT_FREEZE) {
2378                 pci_set_power_state(dev, PCI_D0);
2379                 return 0;
2380         }
2381
2382         acquire_console_sem();
2383
2384         pci_set_power_state(dev, PCI_D0);
2385         pci_restore_state(dev);
2386
2387         if (pci_enable_device(dev))
2388                 DBG("err");
2389
2390         pci_set_master(dev);
2391         savage_enable_mmio(par);
2392         savage_init_hw(par);
2393         savagefb_set_par(info);
2394         fb_set_suspend(info, 0);
2395         savagefb_blank(FB_BLANK_UNBLANK, info);
2396         release_console_sem();
2397
2398         return 0;
2399 }
2400
2401
2402 static struct pci_device_id savagefb_devices[] __devinitdata = {
2403         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX128,
2404          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2405
2406         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX64,
2407          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2408
2409         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX64C,
2410          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2411
2412         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX128SDR,
2413          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2414
2415         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX128DDR,
2416          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2417
2418         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX64SDR,
2419          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2420
2421         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX64DDR,
2422          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2423
2424         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IXCSDR,
2425          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2426
2427         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IXCDDR,
2428          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2429
2430         {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE4,
2431          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE4},
2432
2433         {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE3D,
2434          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE3D},
2435
2436         {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE3D_MV,
2437          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE3D_MV},
2438
2439         {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE2000,
2440          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE2000},
2441
2442         {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_MX_MV,
2443          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_MX_MV},
2444
2445         {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_MX,
2446          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_MX},
2447
2448         {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_IX_MV,
2449          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_IX_MV},
2450
2451         {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_IX,
2452          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_IX},
2453
2454         {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_PM,
2455          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_PM},
2456
2457         {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_KM,
2458          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_KM},
2459
2460         {PCI_VENDOR_ID_S3, PCI_CHIP_S3TWISTER_P,
2461          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_S3TWISTER_P},
2462
2463         {PCI_VENDOR_ID_S3, PCI_CHIP_S3TWISTER_K,
2464          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_S3TWISTER_K},
2465
2466         {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_DDR,
2467          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_DDR},
2468
2469         {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_DDRK,
2470          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_DDRK},
2471
2472         {0, 0, 0, 0, 0, 0, 0}
2473 };
2474
2475 MODULE_DEVICE_TABLE(pci, savagefb_devices);
2476
2477 static struct pci_driver savagefb_driver = {
2478         .name =     "savagefb",
2479         .id_table = savagefb_devices,
2480         .probe =    savagefb_probe,
2481         .suspend =  savagefb_suspend,
2482         .resume =   savagefb_resume,
2483         .remove =   __devexit_p(savagefb_remove)
2484 };
2485
2486 /* **************************** exit-time only **************************** */
2487
2488 static void __exit savage_done(void)
2489 {
2490         DBG("savage_done");
2491         pci_unregister_driver(&savagefb_driver);
2492 }
2493
2494
2495 /* ************************* init in-kernel code ************************** */
2496
2497 static int __init savagefb_setup(char *options)
2498 {
2499 #ifndef MODULE
2500         char *this_opt;
2501
2502         if (!options || !*options)
2503                 return 0;
2504
2505         while ((this_opt = strsep(&options, ",")) != NULL) {
2506                 mode_option = this_opt;
2507         }
2508 #endif /* !MODULE */
2509         return 0;
2510 }
2511
2512 static int __init savagefb_init(void)
2513 {
2514         char *option;
2515
2516         DBG("savagefb_init");
2517
2518         if (fb_get_options("savagefb", &option))
2519                 return -ENODEV;
2520
2521         savagefb_setup(option);
2522         return pci_register_driver(&savagefb_driver);
2523
2524 }
2525
2526 module_init(savagefb_init);
2527 module_exit(savage_done);
2528
2529 module_param(mode_option, charp, 0);
2530 MODULE_PARM_DESC(mode_option, "Specify initial video mode");