git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "core.h"
  19 #include "reg.h"
  20 #include "hw.h"
  21
  22 #define ATH_PCI_VERSION "0.1"
  23
  24 static char *dev_info = "ath9k";
  25
  26 MODULE_AUTHOR("Atheros Communications");
  27 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  28 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  29 MODULE_LICENSE("Dual BSD/GPL");
  30
  31 static struct pci_device_id ath_pci_id_table[] __devinitdata = {
  32         { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI   */
  33         { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
  34         { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI   */
  35         { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI   */
  36         { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
  37         { 0 }
  38 };
  39
  40 static void ath_detach(struct ath_softc *sc);
  41
  42 /* return bus cachesize in 4B word units */
  43
  44 static void bus_read_cachesize(struct ath_softc *sc, int *csz)
  45 {
  46         u8 u8tmp;
  47
  48         pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u8 *)&u8tmp);
  49         *csz = (int)u8tmp;
  50
  51         /*
  52          * This check was put in to avoid "unplesant" consequences if
  53          * the bootrom has not fully initialized all PCI devices.
  54          * Sometimes the cache line size register is not set
  55          */
  56
  57         if (*csz == 0)
  58                 *csz = DEFAULT_CACHELINE >> 2;   /* Use the default size */
  59 }
  60
  61 static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode)
  62 {
  63         sc->sc_curmode = mode;
  64         /*
  65          * All protection frames are transmited at 2Mb/s for
  66          * 11g, otherwise at 1Mb/s.
  67          * XXX select protection rate index from rate table.
  68          */
  69         sc->sc_protrix = (mode == ATH9K_MODE_11G ? 1 : 0);
  70 }
  71
  72 static enum wireless_mode ath_chan2mode(struct ath9k_channel *chan)
  73 {
  74         if (chan->chanmode == CHANNEL_A)
  75                 return ATH9K_MODE_11A;
  76         else if (chan->chanmode == CHANNEL_G)
  77                 return ATH9K_MODE_11G;
  78         else if (chan->chanmode == CHANNEL_B)
  79                 return ATH9K_MODE_11B;
  80         else if (chan->chanmode == CHANNEL_A_HT20)
  81                 return ATH9K_MODE_11NA_HT20;
  82         else if (chan->chanmode == CHANNEL_G_HT20)
  83                 return ATH9K_MODE_11NG_HT20;
  84         else if (chan->chanmode == CHANNEL_A_HT40PLUS)
  85                 return ATH9K_MODE_11NA_HT40PLUS;
  86         else if (chan->chanmode == CHANNEL_A_HT40MINUS)
  87                 return ATH9K_MODE_11NA_HT40MINUS;
  88         else if (chan->chanmode == CHANNEL_G_HT40PLUS)
  89                 return ATH9K_MODE_11NG_HT40PLUS;
  90         else if (chan->chanmode == CHANNEL_G_HT40MINUS)
  91                 return ATH9K_MODE_11NG_HT40MINUS;
  92
  93         WARN_ON(1); /* should not get here */
  94
  95         return ATH9K_MODE_11B;
  96 }
  97
  98 static void ath_update_txpow(struct ath_softc *sc)
  99 {
 100         struct ath_hal *ah = sc->sc_ah;
 101         u32 txpow;
 102
 103         if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
 104                 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
 105                 /* read back in case value is clamped */
 106                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
 107                 sc->sc_curtxpow = txpow;
 108         }
 109 }
 110
 111 static u8 parse_mpdudensity(u8 mpdudensity)
 112 {
 113         /*
 114          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
 115          *   0 for no restriction
 116          *   1 for 1/4 us
 117          *   2 for 1/2 us
 118          *   3 for 1 us
 119          *   4 for 2 us
 120          *   5 for 4 us
 121          *   6 for 8 us
 122          *   7 for 16 us
 123          */
 124         switch (mpdudensity) {
 125         case 0:
 126                 return 0;
 127         case 1:
 128         case 2:
 129         case 3:
 130                 /* Our lower layer calculations limit our precision to
 131                    1 microsecond */
 132                 return 1;
 133         case 4:
 134                 return 2;
 135         case 5:
 136                 return 4;
 137         case 6:
 138                 return 8;
 139         case 7:
 140                 return 16;
 141         default:
 142                 return 0;
 143         }
 144 }
 145
 146 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
 147 {
 148         struct ath_rate_table *rate_table = NULL;
 149         struct ieee80211_supported_band *sband;
 150         struct ieee80211_rate *rate;
 151         int i, maxrates;
 152
 153         switch (band) {
 154         case IEEE80211_BAND_2GHZ:
 155                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
 156                 break;
 157         case IEEE80211_BAND_5GHZ:
 158                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
 159                 break;
 160         default:
 161                 break;
 162         }
 163
 164         if (rate_table == NULL)
 165                 return;
 166
 167         sband = &sc->sbands[band];
 168         rate = sc->rates[band];
 169
 170         if (rate_table->rate_cnt > ATH_RATE_MAX)
 171                 maxrates = ATH_RATE_MAX;
 172         else
 173                 maxrates = rate_table->rate_cnt;
 174
 175         for (i = 0; i < maxrates; i++) {
 176                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
 177                 rate[i].hw_value = rate_table->info[i].ratecode;
 178                 sband->n_bitrates++;
 179                 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
 180                         rate[i].bitrate / 10, rate[i].hw_value);
 181         }
 182 }
 183
 184 static int ath_setup_channels(struct ath_softc *sc)
 185 {
 186         struct ath_hal *ah = sc->sc_ah;
 187         int nchan, i, a = 0, b = 0;
 188         u8 regclassids[ATH_REGCLASSIDS_MAX];
 189         u32 nregclass = 0;
 190         struct ieee80211_supported_band *band_2ghz;
 191         struct ieee80211_supported_band *band_5ghz;
 192         struct ieee80211_channel *chan_2ghz;
 193         struct ieee80211_channel *chan_5ghz;
 194         struct ath9k_channel *c;
 195
 196         /* Fill in ah->ah_channels */
 197         if (!ath9k_regd_init_channels(ah, ATH_CHAN_MAX, (u32 *)&nchan,
 198                                       regclassids, ATH_REGCLASSIDS_MAX,
 199                                       &nregclass, CTRY_DEFAULT, false, 1)) {
 200                 u32 rd = ah->ah_currentRD;
 201                 DPRINTF(sc, ATH_DBG_FATAL,
 202                         "Unable to collect channel list; "
 203                         "regdomain likely %u country code %u\n",
 204                         rd, CTRY_DEFAULT);
 205                 return -EINVAL;
 206         }
 207
 208         band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
 209         band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
 210         chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
 211         chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
 212
 213         for (i = 0; i < nchan; i++) {
 214                 c = &ah->ah_channels[i];
 215                 if (IS_CHAN_2GHZ(c)) {
 216                         chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
 217                         chan_2ghz[a].center_freq = c->channel;
 218                         chan_2ghz[a].max_power = c->maxTxPower;
 219
 220                         if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
 221                                 chan_2ghz[a].flags |= IEEE80211_CHAN_NO_IBSS;
 222                         if (c->channelFlags & CHANNEL_PASSIVE)
 223                                 chan_2ghz[a].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 224
 225                         band_2ghz->n_channels = ++a;
 226
 227                         DPRINTF(sc, ATH_DBG_CONFIG, "2MHz channel: %d, "
 228                                 "channelFlags: 0x%x\n",
 229                                 c->channel, c->channelFlags);
 230                 } else if (IS_CHAN_5GHZ(c)) {
 231                         chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
 232                         chan_5ghz[b].center_freq = c->channel;
 233                         chan_5ghz[b].max_power = c->maxTxPower;
 234
 235                         if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
 236                                 chan_5ghz[b].flags |= IEEE80211_CHAN_NO_IBSS;
 237                         if (c->channelFlags & CHANNEL_PASSIVE)
 238                                 chan_5ghz[b].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 239
 240                         band_5ghz->n_channels = ++b;
 241
 242                         DPRINTF(sc, ATH_DBG_CONFIG, "5MHz channel: %d, "
 243                                 "channelFlags: 0x%x\n",
 244                                 c->channel, c->channelFlags);
 245                 }
 246         }
 247
 248         return 0;
 249 }
 250
 251 /*
 252  * Set/change channels.  If the channel is really being changed, it's done
 253  * by reseting the chip.  To accomplish this we must first cleanup any pending
 254  * DMA, then restart stuff.
 255 */
 256 static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
 257 {
 258         struct ath_hal *ah = sc->sc_ah;
 259         bool fastcc = true, stopped;
 260
 261         if (sc->sc_flags & SC_OP_INVALID)
 262                 return -EIO;
 263
 264         if (hchan->channel != sc->sc_ah->ah_curchan->channel ||
 265             hchan->channelFlags != sc->sc_ah->ah_curchan->channelFlags ||
 266             (sc->sc_flags & SC_OP_CHAINMASK_UPDATE) ||
 267             (sc->sc_flags & SC_OP_FULL_RESET)) {
 268                 int status;
 269                 /*
 270                  * This is only performed if the channel settings have
 271                  * actually changed.
 272                  *
 273                  * To switch channels clear any pending DMA operations;
 274                  * wait long enough for the RX fifo to drain, reset the
 275                  * hardware at the new frequency, and then re-enable
 276                  * the relevant bits of the h/w.
 277                  */
 278                 ath9k_hw_set_interrupts(ah, 0);
 279                 ath_draintxq(sc, false);
 280                 stopped = ath_stoprecv(sc);
 281
 282                 /* XXX: do not flush receive queue here. We don't want
 283                  * to flush data frames already in queue because of
 284                  * changing channel. */
 285
 286                 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
 287                         fastcc = false;
 288
 289                 DPRINTF(sc, ATH_DBG_CONFIG,
 290                         "(%u MHz) -> (%u MHz), cflags:%x, chanwidth: %d\n",
 291                         sc->sc_ah->ah_curchan->channel,
 292                         hchan->channel, hchan->channelFlags, sc->tx_chan_width);
 293
 294                 spin_lock_bh(&sc->sc_resetlock);
 295                 if (!ath9k_hw_reset(ah, hchan, sc->tx_chan_width,
 296                                     sc->sc_tx_chainmask, sc->sc_rx_chainmask,
 297                                     sc->sc_ht_extprotspacing, fastcc, &status)) {
 298                         DPRINTF(sc, ATH_DBG_FATAL,
 299                                 "Unable to reset channel %u (%uMhz) "
 300                                 "flags 0x%x hal status %u\n",
 301                                 ath9k_hw_mhz2ieee(ah, hchan->channel,
 302                                                   hchan->channelFlags),
 303                                 hchan->channel, hchan->channelFlags, status);
 304                         spin_unlock_bh(&sc->sc_resetlock);
 305                         return -EIO;
 306                 }
 307                 spin_unlock_bh(&sc->sc_resetlock);
 308
 309                 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
 310                 sc->sc_flags &= ~SC_OP_FULL_RESET;
 311
 312                 if (ath_startrecv(sc) != 0) {
 313                         DPRINTF(sc, ATH_DBG_FATAL,
 314                                 "Unable to restart recv logic\n");
 315                         return -EIO;
 316                 }
 317
 318                 ath_setcurmode(sc, ath_chan2mode(hchan));
 319                 ath_update_txpow(sc);
 320                 ath9k_hw_set_interrupts(ah, sc->sc_imask);
 321         }
 322         return 0;
 323 }
 324
 325 /*
 326  *  This routine performs the periodic noise floor calibration function
 327  *  that is used to adjust and optimize the chip performance.  This
 328  *  takes environmental changes (location, temperature) into account.
 329  *  When the task is complete, it reschedules itself depending on the
 330  *  appropriate interval that was calculated.
 331  */
 332 static void ath_ani_calibrate(unsigned long data)
 333 {
 334         struct ath_softc *sc;
 335         struct ath_hal *ah;
 336         bool longcal = false;
 337         bool shortcal = false;
 338         bool aniflag = false;
 339         unsigned int timestamp = jiffies_to_msecs(jiffies);
 340         u32 cal_interval;
 341
 342         sc = (struct ath_softc *)data;
 343         ah = sc->sc_ah;
 344
 345         /*
 346         * don't calibrate when we're scanning.
 347         * we are most likely not on our home channel.
 348         */
 349         if (sc->rx_filter & FIF_BCN_PRBRESP_PROMISC)
 350                 return;
 351
 352         /* Long calibration runs independently of short calibration. */
 353         if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
 354                 longcal = true;
 355                 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
 356                 sc->sc_ani.sc_longcal_timer = timestamp;
 357         }
 358
 359         /* Short calibration applies only while sc_caldone is false */
 360         if (!sc->sc_ani.sc_caldone) {
 361                 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
 362                     ATH_SHORT_CALINTERVAL) {
 363                         shortcal = true;
 364                         DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
 365                         sc->sc_ani.sc_shortcal_timer = timestamp;
 366                         sc->sc_ani.sc_resetcal_timer = timestamp;
 367                 }
 368         } else {
 369                 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
 370                     ATH_RESTART_CALINTERVAL) {
 371                         ath9k_hw_reset_calvalid(ah, ah->ah_curchan,
 372                                                 &sc->sc_ani.sc_caldone);
 373                         if (sc->sc_ani.sc_caldone)
 374                                 sc->sc_ani.sc_resetcal_timer = timestamp;
 375                 }
 376         }
 377
 378         /* Verify whether we must check ANI */
 379         if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
 380            ATH_ANI_POLLINTERVAL) {
 381                 aniflag = true;
 382                 sc->sc_ani.sc_checkani_timer = timestamp;
 383         }
 384
 385         /* Skip all processing if there's nothing to do. */
 386         if (longcal || shortcal || aniflag) {
 387                 /* Call ANI routine if necessary */
 388                 if (aniflag)
 389                         ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
 390                                              ah->ah_curchan);
 391
 392                 /* Perform calibration if necessary */
 393                 if (longcal || shortcal) {
 394                         bool iscaldone = false;
 395
 396                         if (ath9k_hw_calibrate(ah, ah->ah_curchan,
 397                                                sc->sc_rx_chainmask, longcal,
 398                                                &iscaldone)) {
 399                                 if (longcal)
 400                                         sc->sc_ani.sc_noise_floor =
 401                                                 ath9k_hw_getchan_noise(ah,
 402                                                                ah->ah_curchan);
 403
 404                                 DPRINTF(sc, ATH_DBG_ANI,
 405                                         "calibrate chan %u/%x nf: %d\n",
 406                                         ah->ah_curchan->channel,
 407                                         ah->ah_curchan->channelFlags,
 408                                         sc->sc_ani.sc_noise_floor);
 409                         } else {
 410                                 DPRINTF(sc, ATH_DBG_ANY,
 411                                         "calibrate chan %u/%x failed\n",
 412                                         ah->ah_curchan->channel,
 413                                         ah->ah_curchan->channelFlags);
 414                         }
 415                         sc->sc_ani.sc_caldone = iscaldone;
 416                 }
 417         }
 418
 419         /*
 420         * Set timer interval based on previous results.
 421         * The interval must be the shortest necessary to satisfy ANI,
 422         * short calibration and long calibration.
 423         */
 424
 425         cal_interval = ATH_ANI_POLLINTERVAL;
 426         if (!sc->sc_ani.sc_caldone)
 427                 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
 428
 429         mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 430 }
 431
 432 /*
 433  * Update tx/rx chainmask. For legacy association,
 434  * hard code chainmask to 1x1, for 11n association, use
 435  * the chainmask configuration.
 436  */
 437 static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 438 {
 439         sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
 440         if (is_ht) {
 441                 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
 442                 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
 443         } else {
 444                 sc->sc_tx_chainmask = 1;
 445                 sc->sc_rx_chainmask = 1;
 446         }
 447
 448         DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
 449                 sc->sc_tx_chainmask, sc->sc_rx_chainmask);
 450 }
 451
 452 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 453 {
 454         struct ath_node *an;
 455
 456         an = (struct ath_node *)sta->drv_priv;
 457
 458         if (sc->sc_flags & SC_OP_TXAGGR)
 459                 ath_tx_node_init(sc, an);
 460
 461         an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
 462                              sta->ht_cap.ampdu_factor);
 463         an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 464 }
 465
 466 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 467 {
 468         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 469
 470         if (sc->sc_flags & SC_OP_TXAGGR)
 471                 ath_tx_node_cleanup(sc, an);
 472 }
 473
 474 static void ath9k_tasklet(unsigned long data)
 475 {
 476         struct ath_softc *sc = (struct ath_softc *)data;
 477         u32 status = sc->sc_intrstatus;
 478
 479         if (status & ATH9K_INT_FATAL) {
 480                 /* need a chip reset */
 481                 ath_reset(sc, false);
 482                 return;
 483         } else {
 484
 485                 if (status &
 486                     (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 487                         spin_lock_bh(&sc->sc_rxflushlock);
 488                         ath_rx_tasklet(sc, 0);
 489                         spin_unlock_bh(&sc->sc_rxflushlock);
 490                 }
 491                 /* XXX: optimize this */
 492                 if (status & ATH9K_INT_TX)
 493                         ath_tx_tasklet(sc);
 494         }
 495
 496         /* re-enable hardware interrupt */
 497         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
 498 }
 499
 500 static irqreturn_t ath_isr(int irq, void *dev)
 501 {
 502         struct ath_softc *sc = dev;
 503         struct ath_hal *ah = sc->sc_ah;
 504         enum ath9k_int status;
 505         bool sched = false;
 506
 507         do {
 508                 if (sc->sc_flags & SC_OP_INVALID) {
 509                         /*
 510                          * The hardware is not ready/present, don't
 511                          * touch anything. Note this can happen early
 512                          * on if the IRQ is shared.
 513                          */
 514                         return IRQ_NONE;
 515                 }
 516                 if (!ath9k_hw_intrpend(ah)) {   /* shared irq, not for us */
 517                         return IRQ_NONE;
 518                 }
 519
 520                 /*
 521                  * Figure out the reason(s) for the interrupt.  Note
 522                  * that the hal returns a pseudo-ISR that may include
 523                  * bits we haven't explicitly enabled so we mask the
 524                  * value to insure we only process bits we requested.
 525                  */
 526                 ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 527
 528                 status &= sc->sc_imask; /* discard unasked-for bits */
 529
 530                 /*
 531                  * If there are no status bits set, then this interrupt was not
 532                  * for me (should have been caught above).
 533                  */
 534                 if (!status)
 535                         return IRQ_NONE;
 536
 537                 sc->sc_intrstatus = status;
 538
 539                 if (status & ATH9K_INT_FATAL) {
 540                         /* need a chip reset */
 541                         sched = true;
 542                 } else if (status & ATH9K_INT_RXORN) {
 543                         /* need a chip reset */
 544                         sched = true;
 545                 } else {
 546                         if (status & ATH9K_INT_SWBA) {
 547                                 /* schedule a tasklet for beacon handling */
 548                                 tasklet_schedule(&sc->bcon_tasklet);
 549                         }
 550                         if (status & ATH9K_INT_RXEOL) {
 551                                 /*
 552                                  * NB: the hardware should re-read the link when
 553                                  *     RXE bit is written, but it doesn't work
 554                                  *     at least on older hardware revs.
 555                                  */
 556                                 sched = true;
 557                         }
 558
 559                         if (status & ATH9K_INT_TXURN)
 560                                 /* bump tx trigger level */
 561                                 ath9k_hw_updatetxtriglevel(ah, true);
 562                         /* XXX: optimize this */
 563                         if (status & ATH9K_INT_RX)
 564                                 sched = true;
 565                         if (status & ATH9K_INT_TX)
 566                                 sched = true;
 567                         if (status & ATH9K_INT_BMISS)
 568                                 sched = true;
 569                         /* carrier sense timeout */
 570                         if (status & ATH9K_INT_CST)
 571                                 sched = true;
 572                         if (status & ATH9K_INT_MIB) {
 573                                 /*
 574                                  * Disable interrupts until we service the MIB
 575                                  * interrupt; otherwise it will continue to
 576                                  * fire.
 577                                  */
 578                                 ath9k_hw_set_interrupts(ah, 0);
 579                                 /*
 580                                  * Let the hal handle the event. We assume
 581                                  * it will clear whatever condition caused
 582                                  * the interrupt.
 583                                  */
 584                                 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
 585                                 ath9k_hw_set_interrupts(ah, sc->sc_imask);
 586                         }
 587                         if (status & ATH9K_INT_TIM_TIMER) {
 588                                 if (!(ah->ah_caps.hw_caps &
 589                                       ATH9K_HW_CAP_AUTOSLEEP)) {
 590                                         /* Clear RxAbort bit so that we can
 591                                          * receive frames */
 592                                         ath9k_hw_setrxabort(ah, 0);
 593                                         sched = true;
 594                                 }
 595                         }
 596                 }
 597         } while (0);
 598
 599         if (sched) {
 600                 /* turn off every interrupt except SWBA */
 601                 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
 602                 tasklet_schedule(&sc->intr_tq);
 603         }
 604
 605         return IRQ_HANDLED;
 606 }
 607
 608 static int ath_get_channel(struct ath_softc *sc,
 609                            struct ieee80211_channel *chan)
 610 {
 611         int i;
 612
 613         for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
 614                 if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
 615                         return i;
 616         }
 617
 618         return -1;
 619 }
 620
 621 /* ext_chan_offset: (-1, 0, 1) (below, none, above) */
 622
 623 static u32 ath_get_extchanmode(struct ath_softc *sc,
 624                                struct ieee80211_channel *chan,
 625                                int ext_chan_offset,
 626                                enum ath9k_ht_macmode tx_chan_width)
 627 {
 628         u32 chanmode = 0;
 629
 630         switch (chan->band) {
 631         case IEEE80211_BAND_2GHZ:
 632                 if ((ext_chan_offset == 0) &&
 633                     (tx_chan_width == ATH9K_HT_MACMODE_20))
 634                         chanmode = CHANNEL_G_HT20;
 635                 if ((ext_chan_offset == 1) &&
 636                     (tx_chan_width == ATH9K_HT_MACMODE_2040))
 637                         chanmode = CHANNEL_G_HT40PLUS;
 638                 if ((ext_chan_offset == -1) &&
 639                     (tx_chan_width == ATH9K_HT_MACMODE_2040))
 640                         chanmode = CHANNEL_G_HT40MINUS;
 641                 break;
 642         case IEEE80211_BAND_5GHZ:
 643                 if ((ext_chan_offset == 0) &&
 644                     (tx_chan_width == ATH9K_HT_MACMODE_20))
 645                         chanmode = CHANNEL_A_HT20;
 646                 if ((ext_chan_offset == 1) &&
 647                     (tx_chan_width == ATH9K_HT_MACMODE_2040))
 648                         chanmode = CHANNEL_A_HT40PLUS;
 649                 if ((ext_chan_offset == -1) &&
 650                     (tx_chan_width == ATH9K_HT_MACMODE_2040))
 651                         chanmode = CHANNEL_A_HT40MINUS;
 652                 break;
 653         default:
 654                 break;
 655         }
 656
 657         return chanmode;
 658 }
 659
 660 static void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot)
 661 {
 662         ath9k_hw_keyreset(sc->sc_ah, keyix);
 663         if (freeslot)
 664                 clear_bit(keyix, sc->sc_keymap);
 665 }
 666
 667 static int ath_keyset(struct ath_softc *sc, u16 keyix,
 668                struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
 669 {
 670         bool status;
 671
 672         status = ath9k_hw_set_keycache_entry(sc->sc_ah,
 673                 keyix, hk, mac, false);
 674
 675         return status != false;
 676 }
 677
 678 static int ath_setkey_tkip(struct ath_softc *sc,
 679                            struct ieee80211_key_conf *key,
 680                            struct ath9k_keyval *hk,
 681                            const u8 *addr)
 682 {
 683         u8 *key_rxmic = NULL;
 684         u8 *key_txmic = NULL;
 685
 686         key_txmic = key->key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
 687         key_rxmic = key->key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
 688
 689         if (addr == NULL) {
 690                 /* Group key installation */
 691                 memcpy(hk->kv_mic,  key_rxmic, sizeof(hk->kv_mic));
 692                 return ath_keyset(sc, key->keyidx, hk, addr);
 693         }
 694         if (!sc->sc_splitmic) {
 695                 /*
 696                  * data key goes at first index,
 697                  * the hal handles the MIC keys at index+64.
 698                  */
 699                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 700                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
 701                 return ath_keyset(sc, key->keyidx, hk, addr);
 702         }
 703         /*
 704          * TX key goes at first index, RX key at +32.
 705          * The hal handles the MIC keys at index+64.
 706          */
 707         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 708         if (!ath_keyset(sc, key->keyidx, hk, NULL)) {
 709                 /* Txmic entry failed. No need to proceed further */
 710                 DPRINTF(sc, ATH_DBG_KEYCACHE,
 711                         "Setting TX MIC Key Failed\n");
 712                 return 0;
 713         }
 714
 715         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 716         /* XXX delete tx key on failure? */
 717         return ath_keyset(sc, key->keyidx+32, hk, addr);
 718 }
 719
 720 static int ath_key_config(struct ath_softc *sc,
 721                           const u8 *addr,
 722                           struct ieee80211_key_conf *key)
 723 {
 724         struct ieee80211_vif *vif;
 725         struct ath9k_keyval hk;
 726         const u8 *mac = NULL;
 727         int ret = 0;
 728         enum nl80211_iftype opmode;
 729
 730         memset(&hk, 0, sizeof(hk));
 731
 732         switch (key->alg) {
 733         case ALG_WEP:
 734                 hk.kv_type = ATH9K_CIPHER_WEP;
 735                 break;
 736         case ALG_TKIP:
 737                 hk.kv_type = ATH9K_CIPHER_TKIP;
 738                 break;
 739         case ALG_CCMP:
 740                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
 741                 break;
 742         default:
 743                 return -EINVAL;
 744         }
 745
 746         hk.kv_len  = key->keylen;
 747         memcpy(hk.kv_val, key->key, key->keylen);
 748
 749         if (!sc->sc_vaps[0])
 750                 return -EIO;
 751
 752         vif = sc->sc_vaps[0];
 753         opmode = vif->type;
 754
 755         /*
 756          *  Strategy:
 757          *   For _M_STA mc tx, we will not setup a key at all since we never
 758          *   tx mc.
 759          *   _M_STA mc rx, we will use the keyID.
 760          *   for _M_IBSS mc tx, we will use the keyID, and no macaddr.
 761          *   for _M_IBSS mc rx, we will alloc a slot and plumb the mac of the
 762          *   peer node. BUT we will plumb a cleartext key so that we can do
 763          *   perSta default key table lookup in software.
 764          */
 765         if (is_broadcast_ether_addr(addr)) {
 766                 switch (opmode) {
 767                 case NL80211_IFTYPE_STATION:
 768                         /* default key:  could be group WPA key
 769                          * or could be static WEP key */
 770                         mac = NULL;
 771                         break;
 772                 case NL80211_IFTYPE_ADHOC:
 773                         break;
 774                 case NL80211_IFTYPE_AP:
 775                         break;
 776                 default:
 777                         ASSERT(0);
 778                         break;
 779                 }
 780         } else {
 781                 mac = addr;
 782         }
 783
 784         if (key->alg == ALG_TKIP)
 785                 ret = ath_setkey_tkip(sc, key, &hk, mac);
 786         else
 787                 ret = ath_keyset(sc, key->keyidx, &hk, mac);
 788
 789         if (!ret)
 790                 return -EIO;
 791
 792         return 0;
 793 }
 794
 795 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
 796 {
 797         int freeslot;
 798
 799         freeslot = (key->keyidx >= 4) ? 1 : 0;
 800         ath_key_reset(sc, key->keyidx, freeslot);
 801 }
 802
 803 static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
 804 {
 805 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3       /* 2 ^ 16 */
 806 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6          /* 8 usec */
 807
 808         ht_info->ht_supported = true;
 809         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 810                        IEEE80211_HT_CAP_SM_PS |
 811                        IEEE80211_HT_CAP_SGI_40 |
 812                        IEEE80211_HT_CAP_DSSSCCK40;
 813
 814         ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
 815         ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
 816         /* set up supported mcs set */
 817         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 818         ht_info->mcs.rx_mask[0] = 0xff;
 819         ht_info->mcs.rx_mask[1] = 0xff;
 820         ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
 821 }
 822
 823 static void ath9k_ht_conf(struct ath_softc *sc,
 824                           struct ieee80211_bss_conf *bss_conf)
 825 {
 826         if (sc->hw->conf.ht.enabled) {
 827                 if (bss_conf->ht.width_40_ok)
 828                         sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
 829                 else
 830                         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
 831
 832                 ath9k_hw_set11nmac2040(sc->sc_ah, sc->tx_chan_width);
 833
 834                 DPRINTF(sc, ATH_DBG_CONFIG,
 835                         "BSS Changed HT, chanwidth: %d\n", sc->tx_chan_width);
 836         }
 837 }
 838
 839 static inline int ath_sec_offset(u8 ext_offset)
 840 {
 841         if (ext_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE)
 842                 return 0;
 843         else if (ext_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
 844                 return 1;
 845         else if (ext_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
 846                 return -1;
 847
 848         return 0;
 849 }
 850
 851 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 852                                  struct ieee80211_vif *vif,
 853                                  struct ieee80211_bss_conf *bss_conf)
 854 {
 855         struct ieee80211_hw *hw = sc->hw;
 856         struct ieee80211_channel *curchan = hw->conf.channel;
 857         struct ath_vap *avp = (void *)vif->drv_priv;
 858         int pos;
 859
 860         if (bss_conf->assoc) {
 861                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d\n", bss_conf->aid);
 862
 863                 /* New association, store aid */
 864                 if (avp->av_opmode == ATH9K_M_STA) {
 865                         sc->sc_curaid = bss_conf->aid;
 866                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
 867                                                sc->sc_curaid);
 868                 }
 869
 870                 /* Configure the beacon */
 871                 ath_beacon_config(sc, 0);
 872                 sc->sc_flags |= SC_OP_BEACONS;
 873
 874                 /* Reset rssi stats */
 875                 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
 876                 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
 877                 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
 878                 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
 879
 880                 /* Update chainmask */
 881                 ath_update_chainmask(sc, hw->conf.ht.enabled);
 882
 883                 DPRINTF(sc, ATH_DBG_CONFIG,
 884                         "bssid %pM aid 0x%x\n",
 885                         sc->sc_curbssid, sc->sc_curaid);
 886
 887                 pos = ath_get_channel(sc, curchan);
 888                 if (pos == -1) {
 889                         DPRINTF(sc, ATH_DBG_FATAL,
 890                                 "Invalid channel: %d\n", curchan->center_freq);
 891                         return;
 892                 }
 893
 894                 if (hw->conf.ht.enabled) {
 895                         int offset =
 896                                 ath_sec_offset(bss_conf->ht.secondary_channel_offset);
 897                         sc->tx_chan_width = (bss_conf->ht.width_40_ok) ?
 898                                 ATH9K_HT_MACMODE_2040 : ATH9K_HT_MACMODE_20;
 899
 900                         sc->sc_ah->ah_channels[pos].chanmode =
 901                                 ath_get_extchanmode(sc, curchan,
 902                                                     offset, sc->tx_chan_width);
 903                 } else {
 904                         sc->sc_ah->ah_channels[pos].chanmode =
 905                                 (curchan->band == IEEE80211_BAND_2GHZ) ?
 906                                 CHANNEL_G : CHANNEL_A;
 907                 }
 908
 909                 /* set h/w channel */
 910                 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
 911                         DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel: %d\n",
 912                                 curchan->center_freq);
 913
 914                 /* Start ANI */
 915                 mod_timer(&sc->sc_ani.timer,
 916                         jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 917
 918         } else {
 919                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
 920                 sc->sc_curaid = 0;
 921         }
 922 }
 923
 924 /********************************/
 925 /*       LED functions          */
 926 /********************************/
 927
 928 static void ath_led_brightness(struct led_classdev *led_cdev,
 929                                enum led_brightness brightness)
 930 {
 931         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
 932         struct ath_softc *sc = led->sc;
 933
 934         switch (brightness) {
 935         case LED_OFF:
 936                 if (led->led_type == ATH_LED_ASSOC ||
 937                     led->led_type == ATH_LED_RADIO)
 938                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 939                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 940                                 (led->led_type == ATH_LED_RADIO) ? 1 :
 941                                 !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
 942                 break;
 943         case LED_FULL:
 944                 if (led->led_type == ATH_LED_ASSOC)
 945                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
 946                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
 947                 break;
 948         default:
 949                 break;
 950         }
 951 }
 952
 953 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
 954                             char *trigger)
 955 {
 956         int ret;
 957
 958         led->sc = sc;
 959         led->led_cdev.name = led->name;
 960         led->led_cdev.default_trigger = trigger;
 961         led->led_cdev.brightness_set = ath_led_brightness;
 962
 963         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
 964         if (ret)
 965                 DPRINTF(sc, ATH_DBG_FATAL,
 966                         "Failed to register led:%s", led->name);
 967         else
 968                 led->registered = 1;
 969         return ret;
 970 }
 971
 972 static void ath_unregister_led(struct ath_led *led)
 973 {
 974         if (led->registered) {
 975                 led_classdev_unregister(&led->led_cdev);
 976                 led->registered = 0;
 977         }
 978 }
 979
 980 static void ath_deinit_leds(struct ath_softc *sc)
 981 {
 982         ath_unregister_led(&sc->assoc_led);
 983         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 984         ath_unregister_led(&sc->tx_led);
 985         ath_unregister_led(&sc->rx_led);
 986         ath_unregister_led(&sc->radio_led);
 987         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
 988 }
 989
 990 static void ath_init_leds(struct ath_softc *sc)
 991 {
 992         char *trigger;
 993         int ret;
 994
 995         /* Configure gpio 1 for output */
 996         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
 997                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
 998         /* LED off, active low */
 999         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1000
1001         trigger = ieee80211_get_radio_led_name(sc->hw);
1002         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1003                 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
1004         ret = ath_register_led(sc, &sc->radio_led, trigger);
1005         sc->radio_led.led_type = ATH_LED_RADIO;
1006         if (ret)
1007                 goto fail;
1008
1009         trigger = ieee80211_get_assoc_led_name(sc->hw);
1010         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1011                 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
1012         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1013         sc->assoc_led.led_type = ATH_LED_ASSOC;
1014         if (ret)
1015                 goto fail;
1016
1017         trigger = ieee80211_get_tx_led_name(sc->hw);
1018         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1019                 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
1020         ret = ath_register_led(sc, &sc->tx_led, trigger);
1021         sc->tx_led.led_type = ATH_LED_TX;
1022         if (ret)
1023                 goto fail;
1024
1025         trigger = ieee80211_get_rx_led_name(sc->hw);
1026         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1027                 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
1028         ret = ath_register_led(sc, &sc->rx_led, trigger);
1029         sc->rx_led.led_type = ATH_LED_RX;
1030         if (ret)
1031                 goto fail;
1032
1033         return;
1034
1035 fail:
1036         ath_deinit_leds(sc);
1037 }
1038
1039 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1040
1041 /*******************/
1042 /*      Rfkill     */
1043 /*******************/
1044
1045 static void ath_radio_enable(struct ath_softc *sc)
1046 {
1047         struct ath_hal *ah = sc->sc_ah;
1048         int status;
1049
1050         spin_lock_bh(&sc->sc_resetlock);
1051         if (!ath9k_hw_reset(ah, ah->ah_curchan,
1052                             sc->tx_chan_width,
1053                             sc->sc_tx_chainmask,
1054                             sc->sc_rx_chainmask,
1055                             sc->sc_ht_extprotspacing,
1056                             false, &status)) {
1057                 DPRINTF(sc, ATH_DBG_FATAL,
1058                         "Unable to reset channel %u (%uMhz) "
1059                         "flags 0x%x hal status %u\n",
1060                         ath9k_hw_mhz2ieee(ah,
1061                                           ah->ah_curchan->channel,
1062                                           ah->ah_curchan->channelFlags),
1063                         ah->ah_curchan->channel,
1064                         ah->ah_curchan->channelFlags, status);
1065         }
1066         spin_unlock_bh(&sc->sc_resetlock);
1067
1068         ath_update_txpow(sc);
1069         if (ath_startrecv(sc) != 0) {
1070                 DPRINTF(sc, ATH_DBG_FATAL,
1071                         "Unable to restart recv logic\n");
1072                 return;
1073         }
1074
1075         if (sc->sc_flags & SC_OP_BEACONS)
1076                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1077
1078         /* Re-Enable  interrupts */
1079         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1080
1081         /* Enable LED */
1082         ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1083                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1084         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1085
1086         ieee80211_wake_queues(sc->hw);
1087 }
1088
1089 static void ath_radio_disable(struct ath_softc *sc)
1090 {
1091         struct ath_hal *ah = sc->sc_ah;
1092         int status;
1093
1094
1095         ieee80211_stop_queues(sc->hw);
1096
1097         /* Disable LED */
1098         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1099         ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1100
1101         /* Disable interrupts */
1102         ath9k_hw_set_interrupts(ah, 0);
1103
1104         ath_draintxq(sc, false);        /* clear pending tx frames */
1105         ath_stoprecv(sc);               /* turn off frame recv */
1106         ath_flushrecv(sc);              /* flush recv queue */
1107
1108         spin_lock_bh(&sc->sc_resetlock);
1109         if (!ath9k_hw_reset(ah, ah->ah_curchan,
1110                             sc->tx_chan_width,
1111                             sc->sc_tx_chainmask,
1112                             sc->sc_rx_chainmask,
1113                             sc->sc_ht_extprotspacing,
1114                             false, &status)) {
1115                 DPRINTF(sc, ATH_DBG_FATAL,
1116                         "Unable to reset channel %u (%uMhz) "
1117                         "flags 0x%x hal status %u\n",
1118                         ath9k_hw_mhz2ieee(ah,
1119                                 ah->ah_curchan->channel,
1120                                 ah->ah_curchan->channelFlags),
1121                         ah->ah_curchan->channel,
1122                         ah->ah_curchan->channelFlags, status);
1123         }
1124         spin_unlock_bh(&sc->sc_resetlock);
1125
1126         ath9k_hw_phy_disable(ah);
1127         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1128 }
1129
1130 static bool ath_is_rfkill_set(struct ath_softc *sc)
1131 {
1132         struct ath_hal *ah = sc->sc_ah;
1133
1134         return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1135                                   ah->ah_rfkill_polarity;
1136 }
1137
1138 /* h/w rfkill poll function */
1139 static void ath_rfkill_poll(struct work_struct *work)
1140 {
1141         struct ath_softc *sc = container_of(work, struct ath_softc,
1142                                             rf_kill.rfkill_poll.work);
1143         bool radio_on;
1144
1145         if (sc->sc_flags & SC_OP_INVALID)
1146                 return;
1147
1148         radio_on = !ath_is_rfkill_set(sc);
1149
1150         /*
1151          * enable/disable radio only when there is a
1152          * state change in RF switch
1153          */
1154         if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1155                 enum rfkill_state state;
1156
1157                 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1158                         state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1159                                 : RFKILL_STATE_HARD_BLOCKED;
1160                 } else if (radio_on) {
1161                         ath_radio_enable(sc);
1162                         state = RFKILL_STATE_UNBLOCKED;
1163                 } else {
1164                         ath_radio_disable(sc);
1165                         state = RFKILL_STATE_HARD_BLOCKED;
1166                 }
1167
1168                 if (state == RFKILL_STATE_HARD_BLOCKED)
1169                         sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1170                 else
1171                         sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1172
1173                 rfkill_force_state(sc->rf_kill.rfkill, state);
1174         }
1175
1176         queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1177                            msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1178 }
1179
1180 /* s/w rfkill handler */
1181 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1182 {
1183         struct ath_softc *sc = data;
1184
1185         switch (state) {
1186         case RFKILL_STATE_SOFT_BLOCKED:
1187                 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1188                     SC_OP_RFKILL_SW_BLOCKED)))
1189                         ath_radio_disable(sc);
1190                 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1191                 return 0;
1192         case RFKILL_STATE_UNBLOCKED:
1193                 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1194                         sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1195                         if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1196                                 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1197                                         "radio as it is disabled by h/w\n");
1198                                 return -EPERM;
1199                         }
1200                         ath_radio_enable(sc);
1201                 }
1202                 return 0;
1203         default:
1204                 return -EINVAL;
1205         }
1206 }
1207
1208 /* Init s/w rfkill */
1209 static int ath_init_sw_rfkill(struct ath_softc *sc)
1210 {
1211         sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1212                                              RFKILL_TYPE_WLAN);
1213         if (!sc->rf_kill.rfkill) {
1214                 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1215                 return -ENOMEM;
1216         }
1217
1218         snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1219                 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
1220         sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1221         sc->rf_kill.rfkill->data = sc;
1222         sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1223         sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1224         sc->rf_kill.rfkill->user_claim_unsupported = 1;
1225
1226         return 0;
1227 }
1228
1229 /* Deinitialize rfkill */
1230 static void ath_deinit_rfkill(struct ath_softc *sc)
1231 {
1232         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1233                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1234
1235         if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1236                 rfkill_unregister(sc->rf_kill.rfkill);
1237                 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1238                 sc->rf_kill.rfkill = NULL;
1239         }
1240 }
1241
1242 static int ath_start_rfkill_poll(struct ath_softc *sc)
1243 {
1244         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1245                 queue_delayed_work(sc->hw->workqueue,
1246                                    &sc->rf_kill.rfkill_poll, 0);
1247
1248         if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1249                 if (rfkill_register(sc->rf_kill.rfkill)) {
1250                         DPRINTF(sc, ATH_DBG_FATAL,
1251                                 "Unable to register rfkill\n");
1252                         rfkill_free(sc->rf_kill.rfkill);
1253
1254                         /* Deinitialize the device */
1255                         ath_detach(sc);
1256                         if (sc->pdev->irq)
1257                                 free_irq(sc->pdev->irq, sc);
1258                         pci_iounmap(sc->pdev, sc->mem);
1259                         pci_release_region(sc->pdev, 0);
1260                         pci_disable_device(sc->pdev);
1261                         ieee80211_free_hw(sc->hw);
1262                         return -EIO;
1263                 } else {
1264                         sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1265                 }
1266         }
1267
1268         return 0;
1269 }
1270 #endif /* CONFIG_RFKILL */
1271
1272 static void ath_detach(struct ath_softc *sc)
1273 {
1274         struct ieee80211_hw *hw = sc->hw;
1275         int i = 0;
1276
1277         DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1278
1279 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1280         ath_deinit_rfkill(sc);
1281 #endif
1282         ath_deinit_leds(sc);
1283
1284         ieee80211_unregister_hw(hw);
1285
1286         ath_rate_control_unregister();
1287
1288         ath_rx_cleanup(sc);
1289         ath_tx_cleanup(sc);
1290
1291         tasklet_kill(&sc->intr_tq);
1292         tasklet_kill(&sc->bcon_tasklet);
1293
1294         if (!(sc->sc_flags & SC_OP_INVALID))
1295                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1296
1297         /* cleanup tx queues */
1298         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1299                 if (ATH_TXQ_SETUP(sc, i))
1300                         ath_tx_cleanupq(sc, &sc->sc_txq[i]);
1301
1302         ath9k_hw_detach(sc->sc_ah);
1303         ath9k_exit_debug(sc);
1304 }
1305
1306 static int ath_init(u16 devid, struct ath_softc *sc)
1307 {
1308         struct ath_hal *ah = NULL;
1309         int status;
1310         int error = 0, i;
1311         int csz = 0;
1312
1313         /* XXX: hardware will not be ready until ath_open() being called */
1314         sc->sc_flags |= SC_OP_INVALID;
1315
1316         if (ath9k_init_debug(sc) < 0)
1317                 printk(KERN_ERR "Unable to create debugfs files\n");
1318
1319         spin_lock_init(&sc->sc_resetlock);
1320         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1321         tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1322                      (unsigned long)sc);
1323
1324         /*
1325          * Cache line size is used to size and align various
1326          * structures used to communicate with the hardware.
1327          */
1328         bus_read_cachesize(sc, &csz);
1329         /* XXX assert csz is non-zero */
1330         sc->sc_cachelsz = csz << 2;     /* convert to bytes */
1331
1332         ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1333         if (ah == NULL) {
1334                 DPRINTF(sc, ATH_DBG_FATAL,
1335                         "Unable to attach hardware; HAL status %u\n", status);
1336                 error = -ENXIO;
1337                 goto bad;
1338         }
1339         sc->sc_ah = ah;
1340
1341         /* Get the hardware key cache size. */
1342         sc->sc_keymax = ah->ah_caps.keycache_size;
1343         if (sc->sc_keymax > ATH_KEYMAX) {
1344                 DPRINTF(sc, ATH_DBG_KEYCACHE,
1345                         "Warning, using only %u entries in %u key cache\n",
1346                         ATH_KEYMAX, sc->sc_keymax);
1347                 sc->sc_keymax = ATH_KEYMAX;
1348         }
1349
1350         /*
1351          * Reset the key cache since some parts do not
1352          * reset the contents on initial power up.
1353          */
1354         for (i = 0; i < sc->sc_keymax; i++)
1355                 ath9k_hw_keyreset(ah, (u16) i);
1356         /*
1357          * Mark key cache slots associated with global keys
1358          * as in use.  If we knew TKIP was not to be used we
1359          * could leave the +32, +64, and +32+64 slots free.
1360          * XXX only for splitmic.
1361          */
1362         for (i = 0; i < IEEE80211_WEP_NKID; i++) {
1363                 set_bit(i, sc->sc_keymap);
1364                 set_bit(i + 32, sc->sc_keymap);
1365                 set_bit(i + 64, sc->sc_keymap);
1366                 set_bit(i + 32 + 64, sc->sc_keymap);
1367         }
1368
1369         /* Collect the channel list using the default country code */
1370
1371         error = ath_setup_channels(sc);
1372         if (error)
1373                 goto bad;
1374
1375         /* default to MONITOR mode */
1376         sc->sc_ah->ah_opmode = ATH9K_M_MONITOR;
1377
1378         /* Setup rate tables */
1379
1380         ath_rate_attach(sc);
1381         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1382         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1383
1384         /*
1385          * Allocate hardware transmit queues: one queue for
1386          * beacon frames and one data queue for each QoS
1387          * priority.  Note that the hal handles reseting
1388          * these queues at the needed time.
1389          */
1390         sc->sc_bhalq = ath_beaconq_setup(ah);
1391         if (sc->sc_bhalq == -1) {
1392                 DPRINTF(sc, ATH_DBG_FATAL,
1393                         "Unable to setup a beacon xmit queue\n");
1394                 error = -EIO;
1395                 goto bad2;
1396         }
1397         sc->sc_cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1398         if (sc->sc_cabq == NULL) {
1399                 DPRINTF(sc, ATH_DBG_FATAL,
1400                         "Unable to setup CAB xmit queue\n");
1401                 error = -EIO;
1402                 goto bad2;
1403         }
1404
1405         sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1406         ath_cabq_update(sc);
1407
1408         for (i = 0; i < ARRAY_SIZE(sc->sc_haltype2q); i++)
1409                 sc->sc_haltype2q[i] = -1;
1410
1411         /* Setup data queues */
1412         /* NB: ensure BK queue is the lowest priority h/w queue */
1413         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1414                 DPRINTF(sc, ATH_DBG_FATAL,
1415                         "Unable to setup xmit queue for BK traffic\n");
1416                 error = -EIO;
1417                 goto bad2;
1418         }
1419
1420         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1421                 DPRINTF(sc, ATH_DBG_FATAL,
1422                         "Unable to setup xmit queue for BE traffic\n");
1423                 error = -EIO;
1424                 goto bad2;
1425         }
1426         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1427                 DPRINTF(sc, ATH_DBG_FATAL,
1428                         "Unable to setup xmit queue for VI traffic\n");
1429                 error = -EIO;
1430                 goto bad2;
1431         }
1432         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1433                 DPRINTF(sc, ATH_DBG_FATAL,
1434                         "Unable to setup xmit queue for VO traffic\n");
1435                 error = -EIO;
1436                 goto bad2;
1437         }
1438
1439         /* Initializes the noise floor to a reasonable default value.
1440          * Later on this will be updated during ANI processing. */
1441
1442         sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1443         setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1444
1445         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1446                                    ATH9K_CIPHER_TKIP, NULL)) {
1447                 /*
1448                  * Whether we should enable h/w TKIP MIC.
1449                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1450                  * report WMM capable, so it's always safe to turn on
1451                  * TKIP MIC in this case.
1452                  */
1453                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1454                                        0, 1, NULL);
1455         }
1456
1457         /*
1458          * Check whether the separate key cache entries
1459          * are required to handle both tx+rx MIC keys.
1460          * With split mic keys the number of stations is limited
1461          * to 27 otherwise 59.
1462          */
1463         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1464                                    ATH9K_CIPHER_TKIP, NULL)
1465             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1466                                       ATH9K_CIPHER_MIC, NULL)
1467             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1468                                       0, NULL))
1469                 sc->sc_splitmic = 1;
1470
1471         /* turn on mcast key search if possible */
1472         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1473                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1474                                              1, NULL);
1475
1476         sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1477         sc->sc_config.txpowlimit_override = 0;
1478
1479         /* 11n Capabilities */
1480         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1481                 sc->sc_flags |= SC_OP_TXAGGR;
1482                 sc->sc_flags |= SC_OP_RXAGGR;
1483         }
1484
1485         sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1486         sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1487
1488         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1489         sc->sc_defant = ath9k_hw_getdefantenna(ah);
1490
1491         ath9k_hw_getmac(ah, sc->sc_myaddr);
1492         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1493                 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1494                 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1495                 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1496         }
1497
1498         sc->sc_slottime = ATH9K_SLOT_TIME_9;    /* default to short slot time */
1499
1500         /* initialize beacon slots */
1501         for (i = 0; i < ARRAY_SIZE(sc->sc_bslot); i++)
1502                 sc->sc_bslot[i] = ATH_IF_ID_ANY;
1503
1504         /* save MISC configurations */
1505         sc->sc_config.swBeaconProcess = 1;
1506
1507 #ifdef CONFIG_SLOW_ANT_DIV
1508         /* range is 40 - 255, we use something in the middle */
1509         ath_slow_ant_div_init(&sc->sc_antdiv, sc, 0x127);
1510 #endif
1511
1512         /* setup channels and rates */
1513
1514         sc->sbands[IEEE80211_BAND_2GHZ].channels =
1515                 sc->channels[IEEE80211_BAND_2GHZ];
1516         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1517                 sc->rates[IEEE80211_BAND_2GHZ];
1518         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1519
1520         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
1521                 sc->sbands[IEEE80211_BAND_5GHZ].channels =
1522                         sc->channels[IEEE80211_BAND_5GHZ];
1523                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1524                         sc->rates[IEEE80211_BAND_5GHZ];
1525                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1526         }
1527
1528         return 0;
1529 bad2:
1530         /* cleanup tx queues */
1531         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1532                 if (ATH_TXQ_SETUP(sc, i))
1533                         ath_tx_cleanupq(sc, &sc->sc_txq[i]);
1534 bad:
1535         if (ah)
1536                 ath9k_hw_detach(ah);
1537
1538         return error;
1539 }
1540
1541 static int ath_attach(u16 devid, struct ath_softc *sc)
1542 {
1543         struct ieee80211_hw *hw = sc->hw;
1544         int error = 0;
1545
1546         DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1547
1548         error = ath_init(devid, sc);
1549         if (error != 0)
1550                 return error;
1551
1552         /* get mac address from hardware and set in mac80211 */
1553
1554         SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
1555
1556         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1557                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1558                 IEEE80211_HW_SIGNAL_DBM |
1559                 IEEE80211_HW_AMPDU_AGGREGATION;
1560
1561         hw->wiphy->interface_modes =
1562                 BIT(NL80211_IFTYPE_AP) |
1563                 BIT(NL80211_IFTYPE_STATION) |
1564                 BIT(NL80211_IFTYPE_ADHOC);
1565
1566         hw->queues = 4;
1567         hw->max_rates = 4;
1568         hw->max_rate_tries = ATH_11N_TXMAXTRY;
1569         hw->sta_data_size = sizeof(struct ath_node);
1570         hw->vif_data_size = sizeof(struct ath_vap);
1571
1572         /* Register rate control */
1573         hw->rate_control_algorithm = "ath9k_rate_control";
1574         error = ath_rate_control_register();
1575         if (error != 0) {
1576                 DPRINTF(sc, ATH_DBG_FATAL,
1577                         "Unable to register rate control algorithm: %d\n", error);
1578                 ath_rate_control_unregister();
1579                 goto bad;
1580         }
1581
1582         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1583                 setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1584                 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1585                         setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1586         }
1587
1588         hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1589         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1590                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1591                         &sc->sbands[IEEE80211_BAND_5GHZ];
1592
1593         /* initialize tx/rx engine */
1594         error = ath_tx_init(sc, ATH_TXBUF);
1595         if (error != 0)
1596                 goto detach;
1597
1598         error = ath_rx_init(sc, ATH_RXBUF);
1599         if (error != 0)
1600                 goto detach;
1601
1602 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1603         /* Initialze h/w Rfkill */
1604         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1605                 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1606
1607         /* Initialize s/w rfkill */
1608         if (ath_init_sw_rfkill(sc))
1609                 goto detach;
1610 #endif
1611
1612         error = ieee80211_register_hw(hw);
1613         if (error != 0) {
1614                 ath_rate_control_unregister();
1615                 goto bad;
1616         }
1617
1618         /* Initialize LED control */
1619         ath_init_leds(sc);
1620
1621         return 0;
1622 detach:
1623         ath_detach(sc);
1624 bad:
1625         return error;
1626 }
1627
1628 int ath_reset(struct ath_softc *sc, bool retry_tx)
1629 {
1630         struct ath_hal *ah = sc->sc_ah;
1631         int status;
1632         int error = 0;
1633
1634         ath9k_hw_set_interrupts(ah, 0);
1635         ath_draintxq(sc, retry_tx);
1636         ath_stoprecv(sc);
1637         ath_flushrecv(sc);
1638
1639         spin_lock_bh(&sc->sc_resetlock);
1640         if (!ath9k_hw_reset(ah, sc->sc_ah->ah_curchan,
1641                             sc->tx_chan_width,
1642                             sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1643                             sc->sc_ht_extprotspacing, false, &status)) {
1644                 DPRINTF(sc, ATH_DBG_FATAL,
1645                         "Unable to reset hardware; hal status %u\n", status);
1646                 error = -EIO;
1647         }
1648         spin_unlock_bh(&sc->sc_resetlock);
1649
1650         if (ath_startrecv(sc) != 0)
1651                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1652
1653         /*
1654          * We may be doing a reset in response to a request
1655          * that changes the channel so update any state that
1656          * might change as a result.
1657          */
1658         ath_setcurmode(sc, ath_chan2mode(sc->sc_ah->ah_curchan));
1659
1660         ath_update_txpow(sc);
1661
1662         if (sc->sc_flags & SC_OP_BEACONS)
1663                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1664
1665         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1666
1667         if (retry_tx) {
1668                 int i;
1669                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1670                         if (ATH_TXQ_SETUP(sc, i)) {
1671                                 spin_lock_bh(&sc->sc_txq[i].axq_lock);
1672                                 ath_txq_schedule(sc, &sc->sc_txq[i]);
1673                                 spin_unlock_bh(&sc->sc_txq[i].axq_lock);
1674                         }
1675                 }
1676         }
1677
1678         return error;
1679 }
1680
1681 /*
1682  *  This function will allocate both the DMA descriptor structure, and the
1683  *  buffers it contains.  These are used to contain the descriptors used
1684  *  by the system.
1685 */
1686 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1687                       struct list_head *head, const char *name,
1688                       int nbuf, int ndesc)
1689 {
1690 #define DS2PHYS(_dd, _ds)                                               \
1691         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1692 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1693 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1694
1695         struct ath_desc *ds;
1696         struct ath_buf *bf;
1697         int i, bsize, error;
1698
1699         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1700                 name, nbuf, ndesc);
1701
1702         /* ath_desc must be a multiple of DWORDs */
1703         if ((sizeof(struct ath_desc) % 4) != 0) {
1704                 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1705                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1706                 error = -ENOMEM;
1707                 goto fail;
1708         }
1709
1710         dd->dd_name = name;
1711         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1712
1713         /*
1714          * Need additional DMA memory because we can't use
1715          * descriptors that cross the 4K page boundary. Assume
1716          * one skipped descriptor per 4K page.
1717          */
1718         if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1719                 u32 ndesc_skipped =
1720                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1721                 u32 dma_len;
1722
1723                 while (ndesc_skipped) {
1724                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1725                         dd->dd_desc_len += dma_len;
1726
1727                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1728                 };
1729         }
1730
1731         /* allocate descriptors */
1732         dd->dd_desc = pci_alloc_consistent(sc->pdev,
1733                               dd->dd_desc_len,
1734                               &dd->dd_desc_paddr);
1735         if (dd->dd_desc == NULL) {
1736                 error = -ENOMEM;
1737                 goto fail;
1738         }
1739         ds = dd->dd_desc;
1740         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1741                 dd->dd_name, ds, (u32) dd->dd_desc_len,
1742                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1743
1744         /* allocate buffers */
1745         bsize = sizeof(struct ath_buf) * nbuf;
1746         bf = kmalloc(bsize, GFP_KERNEL);
1747         if (bf == NULL) {
1748                 error = -ENOMEM;
1749                 goto fail2;
1750         }
1751         memset(bf, 0, bsize);
1752         dd->dd_bufptr = bf;
1753
1754         INIT_LIST_HEAD(head);
1755         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1756                 bf->bf_desc = ds;
1757                 bf->bf_daddr = DS2PHYS(dd, ds);
1758
1759                 if (!(sc->sc_ah->ah_caps.hw_caps &
1760                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1761                         /*
1762                          * Skip descriptor addresses which can cause 4KB
1763                          * boundary crossing (addr + length) with a 32 dword
1764                          * descriptor fetch.
1765                          */
1766                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1767                                 ASSERT((caddr_t) bf->bf_desc <
1768                                        ((caddr_t) dd->dd_desc +
1769                                         dd->dd_desc_len));
1770
1771                                 ds += ndesc;
1772                                 bf->bf_desc = ds;
1773                                 bf->bf_daddr = DS2PHYS(dd, ds);
1774                         }
1775                 }
1776                 list_add_tail(&bf->list, head);
1777         }
1778         return 0;
1779 fail2:
1780         pci_free_consistent(sc->pdev,
1781                 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1782 fail:
1783         memset(dd, 0, sizeof(*dd));
1784         return error;
1785 #undef ATH_DESC_4KB_BOUND_CHECK
1786 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1787 #undef DS2PHYS
1788 }
1789
1790 void ath_descdma_cleanup(struct ath_softc *sc,
1791                          struct ath_descdma *dd,
1792                          struct list_head *head)
1793 {
1794         pci_free_consistent(sc->pdev,
1795                 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1796
1797         INIT_LIST_HEAD(head);
1798         kfree(dd->dd_bufptr);
1799         memset(dd, 0, sizeof(*dd));
1800 }
1801
1802 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1803 {
1804         int qnum;
1805
1806         switch (queue) {
1807         case 0:
1808                 qnum = sc->sc_haltype2q[ATH9K_WME_AC_VO];
1809                 break;
1810         case 1:
1811                 qnum = sc->sc_haltype2q[ATH9K_WME_AC_VI];
1812                 break;
1813         case 2:
1814                 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE];
1815                 break;
1816         case 3:
1817                 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BK];
1818                 break;
1819         default:
1820                 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE];
1821                 break;
1822         }
1823
1824         return qnum;
1825 }
1826
1827 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1828 {
1829         int qnum;
1830
1831         switch (queue) {
1832         case ATH9K_WME_AC_VO:
1833                 qnum = 0;
1834                 break;
1835         case ATH9K_WME_AC_VI:
1836                 qnum = 1;
1837                 break;
1838         case ATH9K_WME_AC_BE:
1839                 qnum = 2;
1840                 break;
1841         case ATH9K_WME_AC_BK:
1842                 qnum = 3;
1843                 break;
1844         default:
1845                 qnum = -1;
1846                 break;
1847         }
1848
1849         return qnum;
1850 }
1851
1852 /**********************/
1853 /* mac80211 callbacks */
1854 /**********************/
1855
1856 static int ath9k_start(struct ieee80211_hw *hw)
1857 {
1858         struct ath_softc *sc = hw->priv;
1859         struct ieee80211_channel *curchan = hw->conf.channel;
1860         struct ath9k_channel *init_channel;
1861         int error = 0, pos, status;
1862
1863         DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1864                 "initial channel: %d MHz\n", curchan->center_freq);
1865
1866         /* setup initial channel */
1867
1868         pos = ath_get_channel(sc, curchan);
1869         if (pos == -1) {
1870                 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n", curchan->center_freq);
1871                 error = -EINVAL;
1872                 goto error;
1873         }
1874
1875         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1876         sc->sc_ah->ah_channels[pos].chanmode =
1877                 (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
1878         init_channel = &sc->sc_ah->ah_channels[pos];
1879
1880         /* Reset SERDES registers */
1881         ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1882
1883         /*
1884          * The basic interface to setting the hardware in a good
1885          * state is ``reset''.  On return the hardware is known to
1886          * be powered up and with interrupts disabled.  This must
1887          * be followed by initialization of the appropriate bits
1888          * and then setup of the interrupt mask.
1889          */
1890         spin_lock_bh(&sc->sc_resetlock);
1891         if (!ath9k_hw_reset(sc->sc_ah, init_channel,
1892                             sc->tx_chan_width,
1893                             sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1894                             sc->sc_ht_extprotspacing, false, &status)) {
1895                 DPRINTF(sc, ATH_DBG_FATAL,
1896                         "Unable to reset hardware; hal status %u "
1897                         "(freq %u flags 0x%x)\n", status,
1898                         init_channel->channel, init_channel->channelFlags);
1899                 error = -EIO;
1900                 spin_unlock_bh(&sc->sc_resetlock);
1901                 goto error;
1902         }
1903         spin_unlock_bh(&sc->sc_resetlock);
1904
1905         /*
1906          * This is needed only to setup initial state
1907          * but it's best done after a reset.
1908          */
1909         ath_update_txpow(sc);
1910
1911         /*
1912          * Setup the hardware after reset:
1913          * The receive engine is set going.
1914          * Frame transmit is handled entirely
1915          * in the frame output path; there's nothing to do
1916          * here except setup the interrupt mask.
1917          */
1918         if (ath_startrecv(sc) != 0) {
1919                 DPRINTF(sc, ATH_DBG_FATAL,
1920                         "Unable to start recv logic\n");
1921                 error = -EIO;
1922                 goto error;
1923         }
1924
1925         /* Setup our intr mask. */
1926         sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1927                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1928                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1929
1930         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1931                 sc->sc_imask |= ATH9K_INT_GTT;
1932
1933         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1934                 sc->sc_imask |= ATH9K_INT_CST;
1935
1936         /*
1937          * Enable MIB interrupts when there are hardware phy counters.
1938          * Note we only do this (at the moment) for station mode.
1939          */
1940         if (ath9k_hw_phycounters(sc->sc_ah) &&
1941             ((sc->sc_ah->ah_opmode == ATH9K_M_STA) ||
1942              (sc->sc_ah->ah_opmode == ATH9K_M_IBSS)))
1943                 sc->sc_imask |= ATH9K_INT_MIB;
1944         /*
1945          * Some hardware processes the TIM IE and fires an
1946          * interrupt when the TIM bit is set.  For hardware
1947          * that does, if not overridden by configuration,
1948          * enable the TIM interrupt when operating as station.
1949          */
1950         if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
1951             (sc->sc_ah->ah_opmode == ATH9K_M_STA) &&
1952             !sc->sc_config.swBeaconProcess)
1953                 sc->sc_imask |= ATH9K_INT_TIM;
1954
1955         ath_setcurmode(sc, ath_chan2mode(init_channel));
1956
1957         sc->sc_flags &= ~SC_OP_INVALID;
1958
1959         /* Disable BMISS interrupt when we're not associated */
1960         sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1961         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1962
1963         ieee80211_wake_queues(sc->hw);
1964
1965 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1966         error = ath_start_rfkill_poll(sc);
1967 #endif
1968
1969 error:
1970         return error;
1971 }
1972
1973 static int ath9k_tx(struct ieee80211_hw *hw,
1974                     struct sk_buff *skb)
1975 {
1976         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1977         struct ath_softc *sc = hw->priv;
1978         struct ath_tx_control txctl;
1979         int hdrlen, padsize;
1980
1981         memset(&txctl, 0, sizeof(struct ath_tx_control));
1982
1983         /*
1984          * As a temporary workaround, assign seq# here; this will likely need
1985          * to be cleaned up to work better with Beacon transmission and virtual
1986          * BSSes.
1987          */
1988         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1989                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1990                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1991                         sc->seq_no += 0x10;
1992                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1993                 hdr->seq_ctrl |= cpu_to_le16(sc->seq_no);
1994         }
1995
1996         /* Add the padding after the header if this is not already done */
1997         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1998         if (hdrlen & 3) {
1999                 padsize = hdrlen % 4;
2000                 if (skb_headroom(skb) < padsize)
2001                         return -1;
2002                 skb_push(skb, padsize);
2003                 memmove(skb->data, skb->data + padsize, hdrlen);
2004         }
2005
2006         /* Check if a tx queue is available */
2007
2008         txctl.txq = ath_test_get_txq(sc, skb);
2009         if (!txctl.txq)
2010                 goto exit;
2011
2012         DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2013
2014         if (ath_tx_start(sc, skb, &txctl) != 0) {
2015                 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2016                 goto exit;
2017         }
2018
2019         return 0;
2020 exit:
2021         dev_kfree_skb_any(skb);
2022         return 0;
2023 }
2024
2025 static void ath9k_stop(struct ieee80211_hw *hw)
2026 {
2027         struct ath_softc *sc = hw->priv;
2028
2029         if (sc->sc_flags & SC_OP_INVALID) {
2030                 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2031                 return;
2032         }
2033
2034         DPRINTF(sc, ATH_DBG_CONFIG, "Cleaning up\n");
2035
2036         ieee80211_stop_queues(sc->hw);
2037
2038         /* make sure h/w will not generate any interrupt
2039          * before setting the invalid flag. */
2040         ath9k_hw_set_interrupts(sc->sc_ah, 0);
2041
2042         if (!(sc->sc_flags & SC_OP_INVALID)) {
2043                 ath_draintxq(sc, false);
2044                 ath_stoprecv(sc);
2045                 ath9k_hw_phy_disable(sc->sc_ah);
2046         } else
2047                 sc->sc_rxlink = NULL;
2048
2049 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2050         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2051                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2052 #endif
2053         /* disable HAL and put h/w to sleep */
2054         ath9k_hw_disable(sc->sc_ah);
2055         ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2056
2057         sc->sc_flags |= SC_OP_INVALID;
2058
2059         DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2060 }
2061
2062 static int ath9k_add_interface(struct ieee80211_hw *hw,
2063                                struct ieee80211_if_init_conf *conf)
2064 {
2065         struct ath_softc *sc = hw->priv;
2066         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2067         int ic_opmode = 0;
2068
2069         /* Support only vap for now */
2070
2071         if (sc->sc_nvaps)
2072                 return -ENOBUFS;
2073
2074         switch (conf->type) {
2075         case NL80211_IFTYPE_STATION:
2076                 ic_opmode = ATH9K_M_STA;
2077                 break;
2078         case NL80211_IFTYPE_ADHOC:
2079                 ic_opmode = ATH9K_M_IBSS;
2080                 break;
2081         case NL80211_IFTYPE_AP:
2082                 ic_opmode = ATH9K_M_HOSTAP;
2083                 break;
2084         default:
2085                 DPRINTF(sc, ATH_DBG_FATAL,
2086                         "Interface type %d not yet supported\n", conf->type);
2087                 return -EOPNOTSUPP;
2088         }
2089
2090         DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode);
2091
2092         /* Set the VAP opmode */
2093         avp->av_opmode = ic_opmode;
2094         avp->av_bslot = -1;
2095
2096         if (ic_opmode == ATH9K_M_HOSTAP)
2097                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2098
2099         sc->sc_vaps[0] = conf->vif;
2100         sc->sc_nvaps++;
2101
2102         /* Set the device opmode */
2103         sc->sc_ah->ah_opmode = ic_opmode;
2104
2105         if (conf->type == NL80211_IFTYPE_AP) {
2106                 /* TODO: is this a suitable place to start ANI for AP mode? */
2107                 /* Start ANI */
2108                 mod_timer(&sc->sc_ani.timer,
2109                           jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2110         }
2111
2112         return 0;
2113 }
2114
2115 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2116                                    struct ieee80211_if_init_conf *conf)
2117 {
2118         struct ath_softc *sc = hw->priv;
2119         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2120
2121         DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2122
2123 #ifdef CONFIG_SLOW_ANT_DIV
2124         ath_slow_ant_div_stop(&sc->sc_antdiv);
2125 #endif
2126         /* Stop ANI */
2127         del_timer_sync(&sc->sc_ani.timer);
2128
2129         /* Reclaim beacon resources */
2130         if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP ||
2131             sc->sc_ah->ah_opmode == ATH9K_M_IBSS) {
2132                 ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
2133                 ath_beacon_return(sc, avp);
2134         }
2135
2136         sc->sc_flags &= ~SC_OP_BEACONS;
2137
2138         sc->sc_vaps[0] = NULL;
2139         sc->sc_nvaps--;
2140 }
2141
2142 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2143 {
2144         struct ath_softc *sc = hw->priv;
2145         struct ieee80211_conf *conf = &hw->conf;
2146
2147         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2148                 struct ieee80211_channel *curchan = hw->conf.channel;
2149                 int pos;
2150
2151                 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2152                         curchan->center_freq);
2153
2154                 pos = ath_get_channel(sc, curchan);
2155                 if (pos == -1) {
2156                         DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n",
2157                                 curchan->center_freq);
2158                         return -EINVAL;
2159                 }
2160
2161                 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
2162                 sc->sc_ah->ah_channels[pos].chanmode =
2163                         (curchan->band == IEEE80211_BAND_2GHZ) ?
2164                         CHANNEL_G : CHANNEL_A;
2165
2166                 if ((sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP) &&
2167                     (conf->ht.enabled)) {
2168                         sc->tx_chan_width = (!!conf->ht.sec_chan_offset) ?
2169                                 ATH9K_HT_MACMODE_2040 : ATH9K_HT_MACMODE_20;
2170
2171                         sc->sc_ah->ah_channels[pos].chanmode =
2172                                 ath_get_extchanmode(sc, curchan,
2173                                                     conf->ht.sec_chan_offset,
2174                                                     sc->tx_chan_width);
2175                 }
2176
2177                 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) {
2178                         DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2179                         return -EINVAL;
2180                 }
2181         }
2182
2183         if (changed & IEEE80211_CONF_CHANGE_HT)
2184                 ath_update_chainmask(sc, conf->ht.enabled);
2185
2186         if (changed & IEEE80211_CONF_CHANGE_POWER)
2187                 sc->sc_config.txpowlimit = 2 * conf->power_level;
2188
2189         return 0;
2190 }
2191
2192 static int ath9k_config_interface(struct ieee80211_hw *hw,
2193                                   struct ieee80211_vif *vif,
2194                                   struct ieee80211_if_conf *conf)
2195 {
2196         struct ath_softc *sc = hw->priv;
2197         struct ath_hal *ah = sc->sc_ah;
2198         struct ath_vap *avp = (void *)vif->drv_priv;
2199         u32 rfilt = 0;
2200         int error, i;
2201
2202         /* TODO: Need to decide which hw opmode to use for multi-interface
2203          * cases */
2204         if (vif->type == NL80211_IFTYPE_AP &&
2205             ah->ah_opmode != ATH9K_M_HOSTAP) {
2206                 ah->ah_opmode = ATH9K_M_HOSTAP;
2207                 ath9k_hw_setopmode(ah);
2208                 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2209                 /* Request full reset to get hw opmode changed properly */
2210                 sc->sc_flags |= SC_OP_FULL_RESET;
2211         }
2212
2213         if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2214             !is_zero_ether_addr(conf->bssid)) {
2215                 switch (vif->type) {
2216                 case NL80211_IFTYPE_STATION:
2217                 case NL80211_IFTYPE_ADHOC:
2218                         /* Set BSSID */
2219                         memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2220                         sc->sc_curaid = 0;
2221                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2222                                                sc->sc_curaid);
2223
2224                         /* Set aggregation protection mode parameters */
2225                         sc->sc_config.ath_aggr_prot = 0;
2226
2227                         DPRINTF(sc, ATH_DBG_CONFIG,
2228                                 "RX filter 0x%x bssid %pM aid 0x%x\n",
2229                                 rfilt, sc->sc_curbssid, sc->sc_curaid);
2230
2231                         /* need to reconfigure the beacon */
2232                         sc->sc_flags &= ~SC_OP_BEACONS ;
2233
2234                         break;
2235                 default:
2236                         break;
2237                 }
2238         }
2239
2240         if ((conf->changed & IEEE80211_IFCC_BEACON) &&
2241             ((vif->type == NL80211_IFTYPE_ADHOC) ||
2242              (vif->type == NL80211_IFTYPE_AP))) {
2243                 /*
2244                  * Allocate and setup the beacon frame.
2245                  *
2246                  * Stop any previous beacon DMA.  This may be
2247                  * necessary, for example, when an ibss merge
2248                  * causes reconfiguration; we may be called
2249                  * with beacon transmission active.
2250                  */
2251                 ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
2252
2253                 error = ath_beacon_alloc(sc, 0);
2254                 if (error != 0)
2255                         return error;
2256
2257                 ath_beacon_sync(sc, 0);
2258         }
2259
2260         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2261         if ((avp->av_opmode != ATH9K_M_STA)) {
2262                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2263                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2264                                 ath9k_hw_keysetmac(sc->sc_ah,
2265                                                    (u16)i,
2266                                                    sc->sc_curbssid);
2267         }
2268
2269         /* Only legacy IBSS for now */
2270         if (vif->type == NL80211_IFTYPE_ADHOC)
2271                 ath_update_chainmask(sc, 0);
2272
2273         return 0;
2274 }
2275
2276 #define SUPPORTED_FILTERS                       \
2277         (FIF_PROMISC_IN_BSS |                   \
2278         FIF_ALLMULTI |                          \
2279         FIF_CONTROL |                           \
2280         FIF_OTHER_BSS |                         \
2281         FIF_BCN_PRBRESP_PROMISC |               \
2282         FIF_FCSFAIL)
2283
2284 /* FIXME: sc->sc_full_reset ? */
2285 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2286                                    unsigned int changed_flags,
2287                                    unsigned int *total_flags,
2288                                    int mc_count,
2289                                    struct dev_mc_list *mclist)
2290 {
2291         struct ath_softc *sc = hw->priv;
2292         u32 rfilt;
2293
2294         changed_flags &= SUPPORTED_FILTERS;
2295         *total_flags &= SUPPORTED_FILTERS;
2296
2297         sc->rx_filter = *total_flags;
2298         rfilt = ath_calcrxfilter(sc);
2299         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2300
2301         if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2302                 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2303                         ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2304         }
2305
2306         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx_filter);
2307 }
2308
2309 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2310                              struct ieee80211_vif *vif,
2311                              enum sta_notify_cmd cmd,
2312                              struct ieee80211_sta *sta)
2313 {
2314         struct ath_softc *sc = hw->priv;
2315
2316         switch (cmd) {
2317         case STA_NOTIFY_ADD:
2318                 ath_node_attach(sc, sta);
2319                 break;
2320         case STA_NOTIFY_REMOVE:
2321                 ath_node_detach(sc, sta);
2322                 break;
2323         default:
2324                 break;
2325         }
2326 }
2327
2328 static int ath9k_conf_tx(struct ieee80211_hw *hw,
2329                          u16 queue,
2330                          const struct ieee80211_tx_queue_params *params)
2331 {
2332         struct ath_softc *sc = hw->priv;
2333         struct ath9k_tx_queue_info qi;
2334         int ret = 0, qnum;
2335
2336         if (queue >= WME_NUM_AC)
2337                 return 0;
2338
2339         qi.tqi_aifs = params->aifs;
2340         qi.tqi_cwmin = params->cw_min;
2341         qi.tqi_cwmax = params->cw_max;
2342         qi.tqi_burstTime = params->txop;
2343         qnum = ath_get_hal_qnum(queue, sc);
2344
2345         DPRINTF(sc, ATH_DBG_CONFIG,
2346                 "Configure tx [queue/halq] [%d/%d],  "
2347                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2348                 queue, qnum, params->aifs, params->cw_min,
2349                 params->cw_max, params->txop);
2350
2351         ret = ath_txq_update(sc, qnum, &qi);
2352         if (ret)
2353                 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2354
2355         return ret;
2356 }
2357
2358 static int ath9k_set_key(struct ieee80211_hw *hw,
2359                          enum set_key_cmd cmd,
2360                          const u8 *local_addr,
2361                          const u8 *addr,
2362                          struct ieee80211_key_conf *key)
2363 {
2364         struct ath_softc *sc = hw->priv;
2365         int ret = 0;
2366
2367         DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
2368
2369         switch (cmd) {
2370         case SET_KEY:
2371                 ret = ath_key_config(sc, addr, key);
2372                 if (!ret) {
2373                         set_bit(key->keyidx, sc->sc_keymap);
2374                         key->hw_key_idx = key->keyidx;
2375                         /* push IV and Michael MIC generation to stack */
2376                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2377                         if (key->alg == ALG_TKIP)
2378                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2379                 }
2380                 break;
2381         case DISABLE_KEY:
2382                 ath_key_delete(sc, key);
2383                 clear_bit(key->keyidx, sc->sc_keymap);
2384                 break;
2385         default:
2386                 ret = -EINVAL;
2387         }
2388
2389         return ret;
2390 }
2391
2392 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2393                                    struct ieee80211_vif *vif,
2394                                    struct ieee80211_bss_conf *bss_conf,
2395                                    u32 changed)
2396 {
2397         struct ath_softc *sc = hw->priv;
2398
2399         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2400                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2401                         bss_conf->use_short_preamble);
2402                 if (bss_conf->use_short_preamble)
2403                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2404                 else
2405                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2406         }
2407
2408         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2409                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2410                         bss_conf->use_cts_prot);
2411                 if (bss_conf->use_cts_prot &&
2412                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2413                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2414                 else
2415                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2416         }
2417
2418         if (changed & BSS_CHANGED_HT)
2419                 ath9k_ht_conf(sc, bss_conf);
2420
2421         if (changed & BSS_CHANGED_ASSOC) {
2422                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2423                         bss_conf->assoc);
2424                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2425         }
2426 }
2427
2428 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2429 {
2430         u64 tsf;
2431         struct ath_softc *sc = hw->priv;
2432         struct ath_hal *ah = sc->sc_ah;
2433
2434         tsf = ath9k_hw_gettsf64(ah);
2435
2436         return tsf;
2437 }
2438
2439 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2440 {
2441         struct ath_softc *sc = hw->priv;
2442         struct ath_hal *ah = sc->sc_ah;
2443
2444         ath9k_hw_reset_tsf(ah);
2445 }
2446
2447 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2448                        enum ieee80211_ampdu_mlme_action action,
2449                        struct ieee80211_sta *sta,
2450                        u16 tid, u16 *ssn)
2451 {
2452         struct ath_softc *sc = hw->priv;
2453         int ret = 0;
2454
2455         switch (action) {
2456         case IEEE80211_AMPDU_RX_START:
2457                 if (!(sc->sc_flags & SC_OP_RXAGGR))
2458                         ret = -ENOTSUPP;
2459                 break;
2460         case IEEE80211_AMPDU_RX_STOP:
2461                 break;
2462         case IEEE80211_AMPDU_TX_START:
2463                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2464                 if (ret < 0)
2465                         DPRINTF(sc, ATH_DBG_FATAL,
2466                                 "Unable to start TX aggregation\n");
2467                 else
2468                         ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2469                 break;
2470         case IEEE80211_AMPDU_TX_STOP:
2471                 ret = ath_tx_aggr_stop(sc, sta, tid);
2472                 if (ret < 0)
2473                         DPRINTF(sc, ATH_DBG_FATAL,
2474                                 "Unable to stop TX aggregation\n");
2475
2476                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2477                 break;
2478         case IEEE80211_AMPDU_TX_RESUME:
2479                 ath_tx_aggr_resume(sc, sta, tid);
2480                 break;
2481         default:
2482                 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2483         }
2484
2485         return ret;
2486 }
2487
2488 static int ath9k_no_fragmentation(struct ieee80211_hw *hw, u32 value)
2489 {
2490         return -EOPNOTSUPP;
2491 }
2492
2493 static struct ieee80211_ops ath9k_ops = {
2494         .tx                 = ath9k_tx,
2495         .start              = ath9k_start,
2496         .stop               = ath9k_stop,
2497         .add_interface      = ath9k_add_interface,
2498         .remove_interface   = ath9k_remove_interface,
2499         .config             = ath9k_config,
2500         .config_interface   = ath9k_config_interface,
2501         .configure_filter   = ath9k_configure_filter,
2502         .sta_notify         = ath9k_sta_notify,
2503         .conf_tx            = ath9k_conf_tx,
2504         .bss_info_changed   = ath9k_bss_info_changed,
2505         .set_key            = ath9k_set_key,
2506         .get_tsf            = ath9k_get_tsf,
2507         .reset_tsf          = ath9k_reset_tsf,
2508         .ampdu_action       = ath9k_ampdu_action,
2509         .set_frag_threshold = ath9k_no_fragmentation,
2510 };
2511
2512 static struct {
2513         u32 version;
2514         const char * name;
2515 } ath_mac_bb_names[] = {
2516         { AR_SREV_VERSION_5416_PCI,     "5416" },
2517         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2518         { AR_SREV_VERSION_9100,         "9100" },
2519         { AR_SREV_VERSION_9160,         "9160" },
2520         { AR_SREV_VERSION_9280,         "9280" },
2521         { AR_SREV_VERSION_9285,         "9285" }
2522 };
2523
2524 static struct {
2525         u16 version;
2526         const char * name;
2527 } ath_rf_names[] = {
2528         { 0,                            "5133" },
2529         { AR_RAD5133_SREV_MAJOR,        "5133" },
2530         { AR_RAD5122_SREV_MAJOR,        "5122" },
2531         { AR_RAD2133_SREV_MAJOR,        "2133" },
2532         { AR_RAD2122_SREV_MAJOR,        "2122" }
2533 };
2534
2535 /*
2536  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2537  */
2538 static const char *
2539 ath_mac_bb_name(u32 mac_bb_version)
2540 {
2541         int i;
2542
2543         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2544                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2545                         return ath_mac_bb_names[i].name;
2546                 }
2547         }
2548
2549         return "????";
2550 }
2551
2552 /*
2553  * Return the RF name. "????" is returned if the RF is unknown.
2554  */
2555 static const char *
2556 ath_rf_name(u16 rf_version)
2557 {
2558         int i;
2559
2560         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2561                 if (ath_rf_names[i].version == rf_version) {
2562                         return ath_rf_names[i].name;
2563                 }
2564         }
2565
2566         return "????";
2567 }
2568
2569 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2570 {
2571         void __iomem *mem;
2572         struct ath_softc *sc;
2573         struct ieee80211_hw *hw;
2574         u8 csz;
2575         u32 val;
2576         int ret = 0;
2577         struct ath_hal *ah;
2578
2579         if (pci_enable_device(pdev))
2580                 return -EIO;
2581
2582         ret =  pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2583
2584         if (ret) {
2585                 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
2586                 goto bad;
2587         }
2588
2589         ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2590
2591         if (ret) {
2592                 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
2593                         "DMA enable failed\n");
2594                 goto bad;
2595         }
2596
2597         /*
2598          * Cache line size is used to size and align various
2599          * structures used to communicate with the hardware.
2600          */
2601         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
2602         if (csz == 0) {
2603                 /*
2604                  * Linux 2.4.18 (at least) writes the cache line size
2605                  * register as a 16-bit wide register which is wrong.
2606                  * We must have this setup properly for rx buffer
2607                  * DMA to work so force a reasonable value here if it
2608                  * comes up zero.
2609                  */
2610                 csz = L1_CACHE_BYTES / sizeof(u32);
2611                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
2612         }
2613         /*
2614          * The default setting of latency timer yields poor results,
2615          * set it to the value used by other systems. It may be worth
2616          * tweaking this setting more.
2617          */
2618         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
2619
2620         pci_set_master(pdev);
2621
2622         /*
2623          * Disable the RETRY_TIMEOUT register (0x41) to keep
2624          * PCI Tx retries from interfering with C3 CPU state.
2625          */
2626         pci_read_config_dword(pdev, 0x40, &val);
2627         if ((val & 0x0000ff00) != 0)
2628                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2629
2630         ret = pci_request_region(pdev, 0, "ath9k");
2631         if (ret) {
2632                 dev_err(&pdev->dev, "PCI memory region reserve error\n");
2633                 ret = -ENODEV;
2634                 goto bad;
2635         }
2636
2637         mem = pci_iomap(pdev, 0, 0);
2638         if (!mem) {
2639                 printk(KERN_ERR "PCI memory map error\n") ;
2640                 ret = -EIO;
2641                 goto bad1;
2642         }
2643
2644         hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
2645         if (hw == NULL) {
2646                 printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
2647                 goto bad2;
2648         }
2649
2650         SET_IEEE80211_DEV(hw, &pdev->dev);
2651         pci_set_drvdata(pdev, hw);
2652
2653         sc = hw->priv;
2654         sc->hw = hw;
2655         sc->pdev = pdev;
2656         sc->mem = mem;
2657
2658         if (ath_attach(id->device, sc) != 0) {
2659                 ret = -ENODEV;
2660                 goto bad3;
2661         }
2662
2663         /* setup interrupt service routine */
2664
2665         if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
2666                 printk(KERN_ERR "%s: request_irq failed\n",
2667                         wiphy_name(hw->wiphy));
2668                 ret = -EIO;
2669                 goto bad4;
2670         }
2671
2672         ah = sc->sc_ah;
2673         printk(KERN_INFO
2674                "%s: Atheros AR%s MAC/BB Rev:%x "
2675                "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
2676                wiphy_name(hw->wiphy),
2677                ath_mac_bb_name(ah->ah_macVersion),
2678                ah->ah_macRev,
2679                ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
2680                ah->ah_phyRev,
2681                (unsigned long)mem, pdev->irq);
2682
2683         return 0;
2684 bad4:
2685         ath_detach(sc);
2686 bad3:
2687         ieee80211_free_hw(hw);
2688 bad2:
2689         pci_iounmap(pdev, mem);
2690 bad1:
2691         pci_release_region(pdev, 0);
2692 bad:
2693         pci_disable_device(pdev);
2694         return ret;
2695 }
2696
2697 static void ath_pci_remove(struct pci_dev *pdev)
2698 {
2699         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2700         struct ath_softc *sc = hw->priv;
2701
2702         ath_detach(sc);
2703         if (pdev->irq)
2704                 free_irq(pdev->irq, sc);
2705         pci_iounmap(pdev, sc->mem);
2706         pci_release_region(pdev, 0);
2707         pci_disable_device(pdev);
2708         ieee80211_free_hw(hw);
2709 }
2710
2711 #ifdef CONFIG_PM
2712
2713 static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2714 {
2715         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2716         struct ath_softc *sc = hw->priv;
2717
2718         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2719
2720 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2721         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2722                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2723 #endif
2724
2725         pci_save_state(pdev);
2726         pci_disable_device(pdev);
2727         pci_set_power_state(pdev, 3);
2728
2729         return 0;
2730 }
2731
2732 static int ath_pci_resume(struct pci_dev *pdev)
2733 {
2734         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2735         struct ath_softc *sc = hw->priv;
2736         u32 val;
2737         int err;
2738
2739         err = pci_enable_device(pdev);
2740         if (err)
2741                 return err;
2742         pci_restore_state(pdev);
2743         /*
2744          * Suspend/Resume resets the PCI configuration space, so we have to
2745          * re-disable the RETRY_TIMEOUT register (0x41) to keep
2746          * PCI Tx retries from interfering with C3 CPU state
2747          */
2748         pci_read_config_dword(pdev, 0x40, &val);
2749         if ((val & 0x0000ff00) != 0)
2750                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2751
2752         /* Enable LED */
2753         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
2754                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2755         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2756
2757 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2758         /*
2759          * check the h/w rfkill state on resume
2760          * and start the rfkill poll timer
2761          */
2762         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2763                 queue_delayed_work(sc->hw->workqueue,
2764                                    &sc->rf_kill.rfkill_poll, 0);
2765 #endif
2766
2767         return 0;
2768 }
2769
2770 #endif /* CONFIG_PM */
2771
2772 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
2773
2774 static struct pci_driver ath_pci_driver = {
2775         .name       = "ath9k",
2776         .id_table   = ath_pci_id_table,
2777         .probe      = ath_pci_probe,
2778         .remove     = ath_pci_remove,
2779 #ifdef CONFIG_PM
2780         .suspend    = ath_pci_suspend,
2781         .resume     = ath_pci_resume,
2782 #endif /* CONFIG_PM */
2783 };
2784
2785 static int __init init_ath_pci(void)
2786 {
2787         printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
2788
2789         if (pci_register_driver(&ath_pci_driver) < 0) {
2790                 printk(KERN_ERR
2791                         "ath_pci: No devices found, driver not installed.\n");
2792                 pci_unregister_driver(&ath_pci_driver);
2793                 return -ENODEV;
2794         }
2795
2796         return 0;
2797 }
2798 module_init(init_ath_pci);
2799
2800 static void __exit exit_ath_pci(void)
2801 {
2802         pci_unregister_driver(&ath_pci_driver);
2803         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2804 }
2805 module_exit(exit_ath_pci);