2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
4 * Copyright (C) 2001 Ralf Baechle
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 * Routines for generic manipulation of the interrupts found on the MIPS
21 * The interrupt controller is located in the South Bridge a PIIX4 device
22 * with two internal 82C95 interrupt controllers.
24 #include <linux/init.h>
25 #include <linux/irq.h>
26 #include <linux/sched.h>
27 #include <linux/slab.h>
28 #include <linux/interrupt.h>
29 #include <linux/kernel_stat.h>
30 #include <linux/random.h>
32 #include <asm/i8259.h>
33 #include <asm/irq_cpu.h>
35 #include <asm/mips-boards/malta.h>
36 #include <asm/mips-boards/maltaint.h>
37 #include <asm/mips-boards/piix4.h>
38 #include <asm/gt64120.h>
39 #include <asm/mips-boards/generic.h>
40 #include <asm/mips-boards/msc01_pci.h>
41 #include <asm/msc01_ic.h>
43 extern void mips_timer_interrupt(void);
45 static DEFINE_SPINLOCK(mips_irq_lock);
47 static inline int mips_pcibios_iack(void)
53 * Determine highest priority pending interrupt by performing
54 * a PCI Interrupt Acknowledge cycle.
56 switch(mips_revision_corid) {
57 case MIPS_REVISION_CORID_CORE_MSC:
58 case MIPS_REVISION_CORID_CORE_FPGA2:
59 case MIPS_REVISION_CORID_CORE_FPGA3:
60 case MIPS_REVISION_CORID_CORE_24K:
61 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
62 MSC_READ(MSC01_PCI_IACK, irq);
65 case MIPS_REVISION_CORID_QED_RM5261:
66 case MIPS_REVISION_CORID_CORE_LV:
67 case MIPS_REVISION_CORID_CORE_FPGA:
68 case MIPS_REVISION_CORID_CORE_FPGAR2:
69 irq = GT_READ(GT_PCI0_IACK_OFS);
72 case MIPS_REVISION_CORID_BONITO64:
73 case MIPS_REVISION_CORID_CORE_20K:
74 case MIPS_REVISION_CORID_CORE_EMUL_BON:
75 /* The following will generate a PCI IACK cycle on the
76 * Bonito controller. It's a little bit kludgy, but it
77 * was the easiest way to implement it in hardware at
80 BONITO_PCIMAP_CFG = 0x20000;
82 /* Flush Bonito register block */
83 dummy = BONITO_PCIMAP_CFG;
86 irq = *(volatile u32 *)(_pcictrl_bonito_pcicfg);
89 BONITO_PCIMAP_CFG = 0;
92 printk("Unknown Core card, don't know the system controller.\n");
98 static inline int get_int(void)
102 spin_lock_irqsave(&mips_irq_lock, flags);
104 irq = mips_pcibios_iack();
107 * The only way we can decide if an interrupt is spurious
108 * is by checking the 8259 registers. This needs a spinlock
109 * on an SMP system, so leave it up to the generic code...
112 spin_unlock_irqrestore(&mips_irq_lock, flags);
117 static void malta_hw0_irqdispatch(struct pt_regs *regs)
123 return; /* interrupt has already been cleared */
126 do_IRQ(MALTA_INT_BASE+irq, regs);
129 void corehi_irqdispatch(struct pt_regs *regs)
131 unsigned int intrcause,datalo,datahi;
132 unsigned int pcimstat, intisr, inten, intpol, intedge, intsteer, pcicmd, pcibadaddr;
134 printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
135 printk("epc : %08lx\nStatus: %08lx\nCause : %08lx\nbadVaddr : %08lx\n"
136 , regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr);
138 /* Read all the registers and then print them as there is a
139 problem with interspersed printk's upsetting the Bonito controller.
140 Do it for the others too.
143 switch(mips_revision_corid) {
144 case MIPS_REVISION_CORID_CORE_MSC:
145 case MIPS_REVISION_CORID_CORE_FPGA2:
146 case MIPS_REVISION_CORID_CORE_FPGA3:
147 case MIPS_REVISION_CORID_CORE_24K:
148 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
151 case MIPS_REVISION_CORID_QED_RM5261:
152 case MIPS_REVISION_CORID_CORE_LV:
153 case MIPS_REVISION_CORID_CORE_FPGA:
154 case MIPS_REVISION_CORID_CORE_FPGAR2:
155 intrcause = GT_READ(GT_INTRCAUSE_OFS);
156 datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
157 datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
158 printk("GT_INTRCAUSE = %08x\n", intrcause);
159 printk("GT_CPUERR_ADDR = %02x%08x\n", datahi, datalo);
161 case MIPS_REVISION_CORID_BONITO64:
162 case MIPS_REVISION_CORID_CORE_20K:
163 case MIPS_REVISION_CORID_CORE_EMUL_BON:
164 pcibadaddr = BONITO_PCIBADADDR;
165 pcimstat = BONITO_PCIMSTAT;
166 intisr = BONITO_INTISR;
167 inten = BONITO_INTEN;
168 intpol = BONITO_INTPOL;
169 intedge = BONITO_INTEDGE;
170 intsteer = BONITO_INTSTEER;
171 pcicmd = BONITO_PCICMD;
172 printk("BONITO_INTISR = %08x\n", intisr);
173 printk("BONITO_INTEN = %08x\n", inten);
174 printk("BONITO_INTPOL = %08x\n", intpol);
175 printk("BONITO_INTEDGE = %08x\n", intedge);
176 printk("BONITO_INTSTEER = %08x\n", intsteer);
177 printk("BONITO_PCICMD = %08x\n", pcicmd);
178 printk("BONITO_PCIBADADDR = %08x\n", pcibadaddr);
179 printk("BONITO_PCIMSTAT = %08x\n", pcimstat);
184 die("CoreHi interrupt", regs);
187 static inline int clz(unsigned long x)
201 * Version of ffs that only looks at bits 12..15.
203 static inline unsigned int irq_ffs(unsigned int pending)
205 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
206 return -clz(pending) + 31 - CAUSEB_IP;
234 * IRQs on the Malta board look basically (barring software IRQs which we
235 * don't use at all and all external interrupt sources are combined together
236 * on hardware interrupt 0 (MIPS IRQ 2)) like:
240 * 0 Software (ignored)
241 * 1 Software (ignored)
242 * 2 Combined hardware interrupt (hw0)
243 * 3 Hardware (ignored)
244 * 4 Hardware (ignored)
245 * 5 Hardware (ignored)
246 * 6 Hardware (ignored)
247 * 7 R4k timer (what we use)
249 * We handle the IRQ according to _our_ priority which is:
251 * Highest ---- R4k Timer
252 * Lowest ---- Combined hardware interrupt
254 * then we just return, if multiple IRQs are pending then we will just take
255 * another exception, big deal.
258 asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
260 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
263 irq = irq_ffs(pending);
265 if (irq == MIPSCPU_INT_I8259A)
266 malta_hw0_irqdispatch(regs);
268 do_IRQ(MIPSCPU_INT_BASE + irq, regs);
270 spurious_interrupt(regs);
273 static struct irqaction i8259irq = {
274 .handler = no_action,
275 .name = "XT-PIC cascade"
278 static struct irqaction corehi_irqaction = {
279 .handler = no_action,
283 msc_irqmap_t __initdata msc_irqmap[] = {
284 {MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0},
285 {MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0},
287 int __initdata msc_nr_irqs = sizeof(msc_irqmap)/sizeof(msc_irqmap_t);
289 msc_irqmap_t __initdata msc_eicirqmap[] = {
290 {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0},
291 {MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0},
292 {MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0},
293 {MSC01E_INT_SMI, MSC01_IRQ_LEVEL, 0},
294 {MSC01E_INT_COREHI, MSC01_IRQ_LEVEL, 0},
295 {MSC01E_INT_CORELO, MSC01_IRQ_LEVEL, 0},
296 {MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0},
297 {MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0},
298 {MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0},
299 {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0}
301 int __initdata msc_nr_eicirqs = sizeof(msc_eicirqmap)/sizeof(msc_irqmap_t);
303 void __init arch_init_irq(void)
308 mips_cpu_irq_init (MIPSCPU_INT_BASE);
310 switch(mips_revision_corid) {
311 case MIPS_REVISION_CORID_CORE_MSC:
312 case MIPS_REVISION_CORID_CORE_FPGA2:
313 case MIPS_REVISION_CORID_CORE_FPGA3:
314 case MIPS_REVISION_CORID_CORE_24K:
315 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
317 init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
319 init_msc_irqs (MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
323 set_vi_handler (MSC01E_INT_I8259A, malta_hw0_irqdispatch);
324 set_vi_handler (MSC01E_INT_COREHI, corehi_irqdispatch);
325 setup_irq (MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
326 setup_irq (MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
328 else if (cpu_has_vint) {
329 set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
330 set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch);
331 #ifdef CONFIG_MIPS_MT_SMTC
332 setup_irq_smtc (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq,
333 (0x100 << MIPSCPU_INT_I8259A));
334 setup_irq_smtc (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI,
335 &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI));
337 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
338 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
339 #endif /* CONFIG_MIPS_MT_SMTC */
342 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
343 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);