git.oblomov.eu Git - linux-2.6/blob - drivers/net/gianfar.c

   1 /*
   2  * drivers/net/gianfar.c
   3  *
   4  * Gianfar Ethernet Driver
   5  * This driver is designed for the non-CPM ethernet controllers
   6  * on the 85xx and 83xx family of integrated processors
   7  * Based on 8260_io/fcc_enet.c
   8  *
   9  * Author: Andy Fleming
  10  * Maintainer: Kumar Gala
  11  *
  12  * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
  13  * Copyright (c) 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through platform_device.  Structures which
  29  *  define the configuration needed by the board are defined in a
  30  *  board structure in arch/ppc/platforms (though I do not
  31  *  discount the possibility that other architectures could one
  32  *  day be supported.
  33  *
  34  *  The Gianfar Ethernet Controller uses a ring of buffer
  35  *  descriptors.  The beginning is indicated by a register
  36  *  pointing to the physical address of the start of the ring.
  37  *  The end is determined by a "wrap" bit being set in the
  38  *  last descriptor of the ring.
  39  *
  40  *  When a packet is received, the RXF bit in the
  41  *  IEVENT register is set, triggering an interrupt when the
  42  *  corresponding bit in the IMASK register is also set (if
  43  *  interrupt coalescing is active, then the interrupt may not
  44  *  happen immediately, but will wait until either a set number
  45  *  of frames or amount of time have passed).  In NAPI, the
  46  *  interrupt handler will signal there is work to be done, and
  47  *  exit.  Without NAPI, the packet(s) will be handled
  48  *  immediately.  Both methods will start at the last known empty
  49  *  descriptor, and process every subsequent descriptor until there
  50  *  are none left with data (NAPI will stop after a set number of
  51  *  packets to give time to other tasks, but will eventually
  52  *  process all the packets).  The data arrives inside a
  53  *  pre-allocated skb, and so after the skb is passed up to the
  54  *  stack, a new skb must be allocated, and the address field in
  55  *  the buffer descriptor must be updated to indicate this new
  56  *  skb.
  57  *
  58  *  When the kernel requests that a packet be transmitted, the
  59  *  driver starts where it left off last time, and points the
  60  *  descriptor at the buffer which was passed in.  The driver
  61  *  then informs the DMA engine that there are packets ready to
  62  *  be transmitted.  Once the controller is finished transmitting
  63  *  the packet, an interrupt may be triggered (under the same
  64  *  conditions as for reception, but depending on the TXF bit).
  65  *  The driver then cleans up the buffer.
  66  */
  67
  68 #include <linux/kernel.h>
  69 #include <linux/string.h>
  70 #include <linux/errno.h>
  71 #include <linux/unistd.h>
  72 #include <linux/slab.h>
  73 #include <linux/interrupt.h>
  74 #include <linux/init.h>
  75 #include <linux/delay.h>
  76 #include <linux/netdevice.h>
  77 #include <linux/etherdevice.h>
  78 #include <linux/skbuff.h>
  79 #include <linux/if_vlan.h>
  80 #include <linux/spinlock.h>
  81 #include <linux/mm.h>
  82 #include <linux/platform_device.h>
  83 #include <linux/ip.h>
  84 #include <linux/tcp.h>
  85 #include <linux/udp.h>
  86 #include <linux/in.h>
  87
  88 #include <asm/io.h>
  89 #include <asm/irq.h>
  90 #include <asm/uaccess.h>
  91 #include <linux/module.h>
  92 #include <linux/dma-mapping.h>
  93 #include <linux/crc32.h>
  94 #include <linux/mii.h>
  95 #include <linux/phy.h>
  96
  97 #include "gianfar.h"
  98 #include "gianfar_mii.h"
  99
 100 #define TX_TIMEOUT      (1*HZ)
 101 #undef BRIEF_GFAR_ERRORS
 102 #undef VERBOSE_GFAR_ERRORS
 103
 104 #ifdef CONFIG_GFAR_NAPI
 105 #define RECEIVE(x) netif_receive_skb(x)
 106 #else
 107 #define RECEIVE(x) netif_rx(x)
 108 #endif
 109
 110 const char gfar_driver_name[] = "Gianfar Ethernet";
 111 const char gfar_driver_version[] = "1.3";
 112
 113 static int gfar_enet_open(struct net_device *dev);
 114 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 115 static void gfar_timeout(struct net_device *dev);
 116 static int gfar_close(struct net_device *dev);
 117 struct sk_buff *gfar_new_skb(struct net_device *dev);
 118 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
 119                 struct sk_buff *skb);
 120 static int gfar_set_mac_address(struct net_device *dev);
 121 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 122 static irqreturn_t gfar_error(int irq, void *dev_id);
 123 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 124 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 125 static void adjust_link(struct net_device *dev);
 126 static void init_registers(struct net_device *dev);
 127 static int init_phy(struct net_device *dev);
 128 static int gfar_probe(struct platform_device *pdev);
 129 static int gfar_remove(struct platform_device *pdev);
 130 static void free_skb_resources(struct gfar_private *priv);
 131 static void gfar_set_multi(struct net_device *dev);
 132 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 133 static void gfar_configure_serdes(struct net_device *dev);
 134 #ifdef CONFIG_GFAR_NAPI
 135 static int gfar_poll(struct napi_struct *napi, int budget);
 136 #endif
 137 #ifdef CONFIG_NET_POLL_CONTROLLER
 138 static void gfar_netpoll(struct net_device *dev);
 139 #endif
 140 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
 141 static int gfar_clean_tx_ring(struct net_device *dev);
 142 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int length);
 143 static void gfar_vlan_rx_register(struct net_device *netdev,
 144                                 struct vlan_group *grp);
 145 void gfar_halt(struct net_device *dev);
 146 #ifdef CONFIG_PM
 147 static void gfar_halt_nodisable(struct net_device *dev);
 148 #endif
 149 void gfar_start(struct net_device *dev);
 150 static void gfar_clear_exact_match(struct net_device *dev);
 151 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
 152
 153 extern const struct ethtool_ops gfar_ethtool_ops;
 154
 155 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 156 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 157 MODULE_LICENSE("GPL");
 158
 159 /* Returns 1 if incoming frames use an FCB */
 160 static inline int gfar_uses_fcb(struct gfar_private *priv)
 161 {
 162         return (priv->vlan_enable || priv->rx_csum_enable);
 163 }
 164
 165 /* Set up the ethernet device structure, private data,
 166  * and anything else we need before we start */
 167 static int gfar_probe(struct platform_device *pdev)
 168 {
 169         u32 tempval;
 170         struct net_device *dev = NULL;
 171         struct gfar_private *priv = NULL;
 172         struct gianfar_platform_data *einfo;
 173         struct resource *r;
 174         int err = 0;
 175         DECLARE_MAC_BUF(mac);
 176
 177         einfo = (struct gianfar_platform_data *) pdev->dev.platform_data;
 178
 179         if (NULL == einfo) {
 180                 printk(KERN_ERR "gfar %d: Missing additional data!\n",
 181                        pdev->id);
 182
 183                 return -ENODEV;
 184         }
 185
 186         /* Create an ethernet device instance */
 187         dev = alloc_etherdev(sizeof (*priv));
 188
 189         if (NULL == dev)
 190                 return -ENOMEM;
 191
 192         priv = netdev_priv(dev);
 193         priv->dev = dev;
 194
 195         /* Set the info in the priv to the current info */
 196         priv->einfo = einfo;
 197
 198         /* fill out IRQ fields */
 199         if (einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 200                 priv->interruptTransmit = platform_get_irq_byname(pdev, "tx");
 201                 priv->interruptReceive = platform_get_irq_byname(pdev, "rx");
 202                 priv->interruptError = platform_get_irq_byname(pdev, "error");
 203                 if (priv->interruptTransmit < 0 || priv->interruptReceive < 0 || priv->interruptError < 0)
 204                         goto regs_fail;
 205         } else {
 206                 priv->interruptTransmit = platform_get_irq(pdev, 0);
 207                 if (priv->interruptTransmit < 0)
 208                         goto regs_fail;
 209         }
 210
 211         /* get a pointer to the register memory */
 212         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 213         priv->regs = ioremap(r->start, sizeof (struct gfar));
 214
 215         if (NULL == priv->regs) {
 216                 err = -ENOMEM;
 217                 goto regs_fail;
 218         }
 219
 220         spin_lock_init(&priv->txlock);
 221         spin_lock_init(&priv->rxlock);
 222         spin_lock_init(&priv->bflock);
 223
 224         platform_set_drvdata(pdev, dev);
 225
 226         /* Stop the DMA engine now, in case it was running before */
 227         /* (The firmware could have used it, and left it running). */
 228         /* To do this, we write Graceful Receive Stop and Graceful */
 229         /* Transmit Stop, and then wait until the corresponding bits */
 230         /* in IEVENT indicate the stops have completed. */
 231         tempval = gfar_read(&priv->regs->dmactrl);
 232         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
 233         gfar_write(&priv->regs->dmactrl, tempval);
 234
 235         tempval = gfar_read(&priv->regs->dmactrl);
 236         tempval |= (DMACTRL_GRS | DMACTRL_GTS);
 237         gfar_write(&priv->regs->dmactrl, tempval);
 238
 239         while (!(gfar_read(&priv->regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC)))
 240                 cpu_relax();
 241
 242         /* Reset MAC layer */
 243         gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
 244
 245         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
 246         gfar_write(&priv->regs->maccfg1, tempval);
 247
 248         /* Initialize MACCFG2. */
 249         gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
 250
 251         /* Initialize ECNTRL */
 252         gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
 253
 254         /* Copy the station address into the dev structure, */
 255         memcpy(dev->dev_addr, einfo->mac_addr, MAC_ADDR_LEN);
 256
 257         /* Set the dev->base_addr to the gfar reg region */
 258         dev->base_addr = (unsigned long) (priv->regs);
 259
 260         SET_NETDEV_DEV(dev, &pdev->dev);
 261
 262         /* Fill in the dev structure */
 263         dev->open = gfar_enet_open;
 264         dev->hard_start_xmit = gfar_start_xmit;
 265         dev->tx_timeout = gfar_timeout;
 266         dev->watchdog_timeo = TX_TIMEOUT;
 267 #ifdef CONFIG_GFAR_NAPI
 268         netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
 269 #endif
 270 #ifdef CONFIG_NET_POLL_CONTROLLER
 271         dev->poll_controller = gfar_netpoll;
 272 #endif
 273         dev->stop = gfar_close;
 274         dev->change_mtu = gfar_change_mtu;
 275         dev->mtu = 1500;
 276         dev->set_multicast_list = gfar_set_multi;
 277
 278         dev->ethtool_ops = &gfar_ethtool_ops;
 279
 280         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
 281                 priv->rx_csum_enable = 1;
 282                 dev->features |= NETIF_F_IP_CSUM;
 283         } else
 284                 priv->rx_csum_enable = 0;
 285
 286         priv->vlgrp = NULL;
 287
 288         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
 289                 dev->vlan_rx_register = gfar_vlan_rx_register;
 290
 291                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
 292
 293                 priv->vlan_enable = 1;
 294         }
 295
 296         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
 297                 priv->extended_hash = 1;
 298                 priv->hash_width = 9;
 299
 300                 priv->hash_regs[0] = &priv->regs->igaddr0;
 301                 priv->hash_regs[1] = &priv->regs->igaddr1;
 302                 priv->hash_regs[2] = &priv->regs->igaddr2;
 303                 priv->hash_regs[3] = &priv->regs->igaddr3;
 304                 priv->hash_regs[4] = &priv->regs->igaddr4;
 305                 priv->hash_regs[5] = &priv->regs->igaddr5;
 306                 priv->hash_regs[6] = &priv->regs->igaddr6;
 307                 priv->hash_regs[7] = &priv->regs->igaddr7;
 308                 priv->hash_regs[8] = &priv->regs->gaddr0;
 309                 priv->hash_regs[9] = &priv->regs->gaddr1;
 310                 priv->hash_regs[10] = &priv->regs->gaddr2;
 311                 priv->hash_regs[11] = &priv->regs->gaddr3;
 312                 priv->hash_regs[12] = &priv->regs->gaddr4;
 313                 priv->hash_regs[13] = &priv->regs->gaddr5;
 314                 priv->hash_regs[14] = &priv->regs->gaddr6;
 315                 priv->hash_regs[15] = &priv->regs->gaddr7;
 316
 317         } else {
 318                 priv->extended_hash = 0;
 319                 priv->hash_width = 8;
 320
 321                 priv->hash_regs[0] = &priv->regs->gaddr0;
 322                 priv->hash_regs[1] = &priv->regs->gaddr1;
 323                 priv->hash_regs[2] = &priv->regs->gaddr2;
 324                 priv->hash_regs[3] = &priv->regs->gaddr3;
 325                 priv->hash_regs[4] = &priv->regs->gaddr4;
 326                 priv->hash_regs[5] = &priv->regs->gaddr5;
 327                 priv->hash_regs[6] = &priv->regs->gaddr6;
 328                 priv->hash_regs[7] = &priv->regs->gaddr7;
 329         }
 330
 331         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
 332                 priv->padding = DEFAULT_PADDING;
 333         else
 334                 priv->padding = 0;
 335
 336         if (dev->features & NETIF_F_IP_CSUM)
 337                 dev->hard_header_len += GMAC_FCB_LEN;
 338
 339         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
 340         priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
 341         priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
 342
 343         priv->txcoalescing = DEFAULT_TX_COALESCE;
 344         priv->txcount = DEFAULT_TXCOUNT;
 345         priv->txtime = DEFAULT_TXTIME;
 346         priv->rxcoalescing = DEFAULT_RX_COALESCE;
 347         priv->rxcount = DEFAULT_RXCOUNT;
 348         priv->rxtime = DEFAULT_RXTIME;
 349
 350         /* Enable most messages by default */
 351         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
 352
 353         err = register_netdev(dev);
 354
 355         if (err) {
 356                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
 357                                 dev->name);
 358                 goto register_fail;
 359         }
 360
 361         /* Create all the sysfs files */
 362         gfar_init_sysfs(dev);
 363
 364         /* Print out the device info */
 365         printk(KERN_INFO DEVICE_NAME "%s\n",
 366                dev->name, print_mac(mac, dev->dev_addr));
 367
 368         /* Even more device info helps when determining which kernel */
 369         /* provided which set of benchmarks. */
 370 #ifdef CONFIG_GFAR_NAPI
 371         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
 372 #else
 373         printk(KERN_INFO "%s: Running with NAPI disabled\n", dev->name);
 374 #endif
 375         printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
 376                dev->name, priv->rx_ring_size, priv->tx_ring_size);
 377
 378         return 0;
 379
 380 register_fail:
 381         iounmap(priv->regs);
 382 regs_fail:
 383         free_netdev(dev);
 384         return err;
 385 }
 386
 387 static int gfar_remove(struct platform_device *pdev)
 388 {
 389         struct net_device *dev = platform_get_drvdata(pdev);
 390         struct gfar_private *priv = netdev_priv(dev);
 391
 392         platform_set_drvdata(pdev, NULL);
 393
 394         iounmap(priv->regs);
 395         free_netdev(dev);
 396
 397         return 0;
 398 }
 399
 400 #ifdef CONFIG_PM
 401 static int gfar_suspend(struct platform_device *pdev, pm_message_t state)
 402 {
 403         struct net_device *dev = platform_get_drvdata(pdev);
 404         struct gfar_private *priv = netdev_priv(dev);
 405         unsigned long flags;
 406         u32 tempval;
 407
 408         int magic_packet = priv->wol_en &&
 409                 (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
 410
 411         netif_device_detach(dev);
 412
 413         if (netif_running(dev)) {
 414                 spin_lock_irqsave(&priv->txlock, flags);
 415                 spin_lock(&priv->rxlock);
 416
 417                 gfar_halt_nodisable(dev);
 418
 419                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
 420                 tempval = gfar_read(&priv->regs->maccfg1);
 421
 422                 tempval &= ~MACCFG1_TX_EN;
 423
 424                 if (!magic_packet)
 425                         tempval &= ~MACCFG1_RX_EN;
 426
 427                 gfar_write(&priv->regs->maccfg1, tempval);
 428
 429                 spin_unlock(&priv->rxlock);
 430                 spin_unlock_irqrestore(&priv->txlock, flags);
 431
 432 #ifdef CONFIG_GFAR_NAPI
 433                 napi_disable(&priv->napi);
 434 #endif
 435
 436                 if (magic_packet) {
 437                         /* Enable interrupt on Magic Packet */
 438                         gfar_write(&priv->regs->imask, IMASK_MAG);
 439
 440                         /* Enable Magic Packet mode */
 441                         tempval = gfar_read(&priv->regs->maccfg2);
 442                         tempval |= MACCFG2_MPEN;
 443                         gfar_write(&priv->regs->maccfg2, tempval);
 444                 } else {
 445                         phy_stop(priv->phydev);
 446                 }
 447         }
 448
 449         return 0;
 450 }
 451
 452 static int gfar_resume(struct platform_device *pdev)
 453 {
 454         struct net_device *dev = platform_get_drvdata(pdev);
 455         struct gfar_private *priv = netdev_priv(dev);
 456         unsigned long flags;
 457         u32 tempval;
 458         int magic_packet = priv->wol_en &&
 459                 (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
 460
 461         if (!netif_running(dev)) {
 462                 netif_device_attach(dev);
 463                 return 0;
 464         }
 465
 466         if (!magic_packet && priv->phydev)
 467                 phy_start(priv->phydev);
 468
 469         /* Disable Magic Packet mode, in case something
 470          * else woke us up.
 471          */
 472
 473         spin_lock_irqsave(&priv->txlock, flags);
 474         spin_lock(&priv->rxlock);
 475
 476         tempval = gfar_read(&priv->regs->maccfg2);
 477         tempval &= ~MACCFG2_MPEN;
 478         gfar_write(&priv->regs->maccfg2, tempval);
 479
 480         gfar_start(dev);
 481
 482         spin_unlock(&priv->rxlock);
 483         spin_unlock_irqrestore(&priv->txlock, flags);
 484
 485         netif_device_attach(dev);
 486
 487 #ifdef CONFIG_GFAR_NAPI
 488         napi_enable(&priv->napi);
 489 #endif
 490
 491         return 0;
 492 }
 493 #else
 494 #define gfar_suspend NULL
 495 #define gfar_resume NULL
 496 #endif
 497
 498 /* Reads the controller's registers to determine what interface
 499  * connects it to the PHY.
 500  */
 501 static phy_interface_t gfar_get_interface(struct net_device *dev)
 502 {
 503         struct gfar_private *priv = netdev_priv(dev);
 504         u32 ecntrl = gfar_read(&priv->regs->ecntrl);
 505
 506         if (ecntrl & ECNTRL_SGMII_MODE)
 507                 return PHY_INTERFACE_MODE_SGMII;
 508
 509         if (ecntrl & ECNTRL_TBI_MODE) {
 510                 if (ecntrl & ECNTRL_REDUCED_MODE)
 511                         return PHY_INTERFACE_MODE_RTBI;
 512                 else
 513                         return PHY_INTERFACE_MODE_TBI;
 514         }
 515
 516         if (ecntrl & ECNTRL_REDUCED_MODE) {
 517                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
 518                         return PHY_INTERFACE_MODE_RMII;
 519                 else {
 520                         phy_interface_t interface = priv->einfo->interface;
 521
 522                         /*
 523                          * This isn't autodetected right now, so it must
 524                          * be set by the device tree or platform code.
 525                          */
 526                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
 527                                 return PHY_INTERFACE_MODE_RGMII_ID;
 528
 529                         return PHY_INTERFACE_MODE_RGMII;
 530                 }
 531         }
 532
 533         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
 534                 return PHY_INTERFACE_MODE_GMII;
 535
 536         return PHY_INTERFACE_MODE_MII;
 537 }
 538
 539
 540 /* Initializes driver's PHY state, and attaches to the PHY.
 541  * Returns 0 on success.
 542  */
 543 static int init_phy(struct net_device *dev)
 544 {
 545         struct gfar_private *priv = netdev_priv(dev);
 546         uint gigabit_support =
 547                 priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
 548                 SUPPORTED_1000baseT_Full : 0;
 549         struct phy_device *phydev;
 550         char phy_id[BUS_ID_SIZE];
 551         phy_interface_t interface;
 552
 553         priv->oldlink = 0;
 554         priv->oldspeed = 0;
 555         priv->oldduplex = -1;
 556
 557         snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, priv->einfo->bus_id, priv->einfo->phy_id);
 558
 559         interface = gfar_get_interface(dev);
 560
 561         phydev = phy_connect(dev, phy_id, &adjust_link, 0, interface);
 562
 563         if (interface == PHY_INTERFACE_MODE_SGMII)
 564                 gfar_configure_serdes(dev);
 565
 566         if (IS_ERR(phydev)) {
 567                 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
 568                 return PTR_ERR(phydev);
 569         }
 570
 571         /* Remove any features not supported by the controller */
 572         phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
 573         phydev->advertising = phydev->supported;
 574
 575         priv->phydev = phydev;
 576
 577         return 0;
 578 }
 579
 580 /*
 581  * Initialize TBI PHY interface for communicating with the
 582  * SERDES lynx PHY on the chip.  We communicate with this PHY
 583  * through the MDIO bus on each controller, treating it as a
 584  * "normal" PHY at the address found in the TBIPA register.  We assume
 585  * that the TBIPA register is valid.  Either the MDIO bus code will set
 586  * it to a value that doesn't conflict with other PHYs on the bus, or the
 587  * value doesn't matter, as there are no other PHYs on the bus.
 588  */
 589 static void gfar_configure_serdes(struct net_device *dev)
 590 {
 591         struct gfar_private *priv = netdev_priv(dev);
 592         struct gfar_mii __iomem *regs =
 593                         (void __iomem *)&priv->regs->gfar_mii_regs;
 594         int tbipa = gfar_read(&priv->regs->tbipa);
 595
 596         /* Single clk mode, mii mode off(for serdes communication) */
 597         gfar_local_mdio_write(regs, tbipa, MII_TBICON, TBICON_CLK_SELECT);
 598
 599         gfar_local_mdio_write(regs, tbipa, MII_ADVERTISE,
 600                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
 601                         ADVERTISE_1000XPSE_ASYM);
 602
 603         gfar_local_mdio_write(regs, tbipa, MII_BMCR, BMCR_ANENABLE |
 604                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
 605 }
 606
 607 static void init_registers(struct net_device *dev)
 608 {
 609         struct gfar_private *priv = netdev_priv(dev);
 610
 611         /* Clear IEVENT */
 612         gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
 613
 614         /* Initialize IMASK */
 615         gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
 616
 617         /* Init hash registers to zero */
 618         gfar_write(&priv->regs->igaddr0, 0);
 619         gfar_write(&priv->regs->igaddr1, 0);
 620         gfar_write(&priv->regs->igaddr2, 0);
 621         gfar_write(&priv->regs->igaddr3, 0);
 622         gfar_write(&priv->regs->igaddr4, 0);
 623         gfar_write(&priv->regs->igaddr5, 0);
 624         gfar_write(&priv->regs->igaddr6, 0);
 625         gfar_write(&priv->regs->igaddr7, 0);
 626
 627         gfar_write(&priv->regs->gaddr0, 0);
 628         gfar_write(&priv->regs->gaddr1, 0);
 629         gfar_write(&priv->regs->gaddr2, 0);
 630         gfar_write(&priv->regs->gaddr3, 0);
 631         gfar_write(&priv->regs->gaddr4, 0);
 632         gfar_write(&priv->regs->gaddr5, 0);
 633         gfar_write(&priv->regs->gaddr6, 0);
 634         gfar_write(&priv->regs->gaddr7, 0);
 635
 636         /* Zero out the rmon mib registers if it has them */
 637         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
 638                 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
 639
 640                 /* Mask off the CAM interrupts */
 641                 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
 642                 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
 643         }
 644
 645         /* Initialize the max receive buffer length */
 646         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
 647
 648         /* Initialize the Minimum Frame Length Register */
 649         gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
 650 }
 651
 652
 653 #ifdef CONFIG_PM
 654 /* Halt the receive and transmit queues */
 655 static void gfar_halt_nodisable(struct net_device *dev)
 656 {
 657         struct gfar_private *priv = netdev_priv(dev);
 658         struct gfar __iomem *regs = priv->regs;
 659         u32 tempval;
 660
 661         /* Mask all interrupts */
 662         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 663
 664         /* Clear all interrupts */
 665         gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
 666
 667         /* Stop the DMA, and wait for it to stop */
 668         tempval = gfar_read(&priv->regs->dmactrl);
 669         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
 670             != (DMACTRL_GRS | DMACTRL_GTS)) {
 671                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
 672                 gfar_write(&priv->regs->dmactrl, tempval);
 673
 674                 while (!(gfar_read(&priv->regs->ievent) &
 675                          (IEVENT_GRSC | IEVENT_GTSC)))
 676                         cpu_relax();
 677         }
 678 }
 679 #endif
 680
 681 /* Halt the receive and transmit queues */
 682 void gfar_halt(struct net_device *dev)
 683 {
 684         struct gfar_private *priv = netdev_priv(dev);
 685         struct gfar __iomem *regs = priv->regs;
 686         u32 tempval;
 687
 688         /* Disable Rx and Tx */
 689         tempval = gfar_read(&regs->maccfg1);
 690         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
 691         gfar_write(&regs->maccfg1, tempval);
 692 }
 693
 694 void stop_gfar(struct net_device *dev)
 695 {
 696         struct gfar_private *priv = netdev_priv(dev);
 697         struct gfar __iomem *regs = priv->regs;
 698         unsigned long flags;
 699
 700         phy_stop(priv->phydev);
 701
 702         /* Lock it down */
 703         spin_lock_irqsave(&priv->txlock, flags);
 704         spin_lock(&priv->rxlock);
 705
 706         gfar_halt(dev);
 707
 708         spin_unlock(&priv->rxlock);
 709         spin_unlock_irqrestore(&priv->txlock, flags);
 710
 711         /* Free the IRQs */
 712         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 713                 free_irq(priv->interruptError, dev);
 714                 free_irq(priv->interruptTransmit, dev);
 715                 free_irq(priv->interruptReceive, dev);
 716         } else {
 717                 free_irq(priv->interruptTransmit, dev);
 718         }
 719
 720         free_skb_resources(priv);
 721
 722         dma_free_coherent(&dev->dev,
 723                         sizeof(struct txbd8)*priv->tx_ring_size
 724                         + sizeof(struct rxbd8)*priv->rx_ring_size,
 725                         priv->tx_bd_base,
 726                         gfar_read(&regs->tbase0));
 727 }
 728
 729 /* If there are any tx skbs or rx skbs still around, free them.
 730  * Then free tx_skbuff and rx_skbuff */
 731 static void free_skb_resources(struct gfar_private *priv)
 732 {
 733         struct rxbd8 *rxbdp;
 734         struct txbd8 *txbdp;
 735         int i;
 736
 737         /* Go through all the buffer descriptors and free their data buffers */
 738         txbdp = priv->tx_bd_base;
 739
 740         for (i = 0; i < priv->tx_ring_size; i++) {
 741
 742                 if (priv->tx_skbuff[i]) {
 743                         dma_unmap_single(&priv->dev->dev, txbdp->bufPtr,
 744                                         txbdp->length,
 745                                         DMA_TO_DEVICE);
 746                         dev_kfree_skb_any(priv->tx_skbuff[i]);
 747                         priv->tx_skbuff[i] = NULL;
 748                 }
 749
 750                 txbdp++;
 751         }
 752
 753         kfree(priv->tx_skbuff);
 754
 755         rxbdp = priv->rx_bd_base;
 756
 757         /* rx_skbuff is not guaranteed to be allocated, so only
 758          * free it and its contents if it is allocated */
 759         if(priv->rx_skbuff != NULL) {
 760                 for (i = 0; i < priv->rx_ring_size; i++) {
 761                         if (priv->rx_skbuff[i]) {
 762                                 dma_unmap_single(&priv->dev->dev, rxbdp->bufPtr,
 763                                                 priv->rx_buffer_size,
 764                                                 DMA_FROM_DEVICE);
 765
 766                                 dev_kfree_skb_any(priv->rx_skbuff[i]);
 767                                 priv->rx_skbuff[i] = NULL;
 768                         }
 769
 770                         rxbdp->status = 0;
 771                         rxbdp->length = 0;
 772                         rxbdp->bufPtr = 0;
 773
 774                         rxbdp++;
 775                 }
 776
 777                 kfree(priv->rx_skbuff);
 778         }
 779 }
 780
 781 void gfar_start(struct net_device *dev)
 782 {
 783         struct gfar_private *priv = netdev_priv(dev);
 784         struct gfar __iomem *regs = priv->regs;
 785         u32 tempval;
 786
 787         /* Enable Rx and Tx in MACCFG1 */
 788         tempval = gfar_read(&regs->maccfg1);
 789         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
 790         gfar_write(&regs->maccfg1, tempval);
 791
 792         /* Initialize DMACTRL to have WWR and WOP */
 793         tempval = gfar_read(&priv->regs->dmactrl);
 794         tempval |= DMACTRL_INIT_SETTINGS;
 795         gfar_write(&priv->regs->dmactrl, tempval);
 796
 797         /* Make sure we aren't stopped */
 798         tempval = gfar_read(&priv->regs->dmactrl);
 799         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
 800         gfar_write(&priv->regs->dmactrl, tempval);
 801
 802         /* Clear THLT/RHLT, so that the DMA starts polling now */
 803         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
 804         gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
 805
 806         /* Unmask the interrupts we look for */
 807         gfar_write(&regs->imask, IMASK_DEFAULT);
 808 }
 809
 810 /* Bring the controller up and running */
 811 int startup_gfar(struct net_device *dev)
 812 {
 813         struct txbd8 *txbdp;
 814         struct rxbd8 *rxbdp;
 815         dma_addr_t addr = 0;
 816         unsigned long vaddr;
 817         int i;
 818         struct gfar_private *priv = netdev_priv(dev);
 819         struct gfar __iomem *regs = priv->regs;
 820         int err = 0;
 821         u32 rctrl = 0;
 822         u32 attrs = 0;
 823
 824         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 825
 826         /* Allocate memory for the buffer descriptors */
 827         vaddr = (unsigned long) dma_alloc_coherent(&dev->dev,
 828                         sizeof (struct txbd8) * priv->tx_ring_size +
 829                         sizeof (struct rxbd8) * priv->rx_ring_size,
 830                         &addr, GFP_KERNEL);
 831
 832         if (vaddr == 0) {
 833                 if (netif_msg_ifup(priv))
 834                         printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
 835                                         dev->name);
 836                 return -ENOMEM;
 837         }
 838
 839         priv->tx_bd_base = (struct txbd8 *) vaddr;
 840
 841         /* enet DMA only understands physical addresses */
 842         gfar_write(&regs->tbase0, addr);
 843
 844         /* Start the rx descriptor ring where the tx ring leaves off */
 845         addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
 846         vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
 847         priv->rx_bd_base = (struct rxbd8 *) vaddr;
 848         gfar_write(&regs->rbase0, addr);
 849
 850         /* Setup the skbuff rings */
 851         priv->tx_skbuff =
 852             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
 853                                         priv->tx_ring_size, GFP_KERNEL);
 854
 855         if (NULL == priv->tx_skbuff) {
 856                 if (netif_msg_ifup(priv))
 857                         printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
 858                                         dev->name);
 859                 err = -ENOMEM;
 860                 goto tx_skb_fail;
 861         }
 862
 863         for (i = 0; i < priv->tx_ring_size; i++)
 864                 priv->tx_skbuff[i] = NULL;
 865
 866         priv->rx_skbuff =
 867             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
 868                                         priv->rx_ring_size, GFP_KERNEL);
 869
 870         if (NULL == priv->rx_skbuff) {
 871                 if (netif_msg_ifup(priv))
 872                         printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
 873                                         dev->name);
 874                 err = -ENOMEM;
 875                 goto rx_skb_fail;
 876         }
 877
 878         for (i = 0; i < priv->rx_ring_size; i++)
 879                 priv->rx_skbuff[i] = NULL;
 880
 881         /* Initialize some variables in our dev structure */
 882         priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
 883         priv->cur_rx = priv->rx_bd_base;
 884         priv->skb_curtx = priv->skb_dirtytx = 0;
 885         priv->skb_currx = 0;
 886
 887         /* Initialize Transmit Descriptor Ring */
 888         txbdp = priv->tx_bd_base;
 889         for (i = 0; i < priv->tx_ring_size; i++) {
 890                 txbdp->status = 0;
 891                 txbdp->length = 0;
 892                 txbdp->bufPtr = 0;
 893                 txbdp++;
 894         }
 895
 896         /* Set the last descriptor in the ring to indicate wrap */
 897         txbdp--;
 898         txbdp->status |= TXBD_WRAP;
 899
 900         rxbdp = priv->rx_bd_base;
 901         for (i = 0; i < priv->rx_ring_size; i++) {
 902                 struct sk_buff *skb;
 903
 904                 skb = gfar_new_skb(dev);
 905
 906                 if (!skb) {
 907                         printk(KERN_ERR "%s: Can't allocate RX buffers\n",
 908                                         dev->name);
 909
 910                         goto err_rxalloc_fail;
 911                 }
 912
 913                 priv->rx_skbuff[i] = skb;
 914
 915                 gfar_new_rxbdp(dev, rxbdp, skb);
 916
 917                 rxbdp++;
 918         }
 919
 920         /* Set the last descriptor in the ring to wrap */
 921         rxbdp--;
 922         rxbdp->status |= RXBD_WRAP;
 923
 924         /* If the device has multiple interrupts, register for
 925          * them.  Otherwise, only register for the one */
 926         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 927                 /* Install our interrupt handlers for Error,
 928                  * Transmit, and Receive */
 929                 if (request_irq(priv->interruptError, gfar_error,
 930                                 0, "enet_error", dev) < 0) {
 931                         if (netif_msg_intr(priv))
 932                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
 933                                         dev->name, priv->interruptError);
 934
 935                         err = -1;
 936                         goto err_irq_fail;
 937                 }
 938
 939                 if (request_irq(priv->interruptTransmit, gfar_transmit,
 940                                 0, "enet_tx", dev) < 0) {
 941                         if (netif_msg_intr(priv))
 942                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
 943                                         dev->name, priv->interruptTransmit);
 944
 945                         err = -1;
 946
 947                         goto tx_irq_fail;
 948                 }
 949
 950                 if (request_irq(priv->interruptReceive, gfar_receive,
 951                                 0, "enet_rx", dev) < 0) {
 952                         if (netif_msg_intr(priv))
 953                                 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
 954                                                 dev->name, priv->interruptReceive);
 955
 956                         err = -1;
 957                         goto rx_irq_fail;
 958                 }
 959         } else {
 960                 if (request_irq(priv->interruptTransmit, gfar_interrupt,
 961                                 0, "gfar_interrupt", dev) < 0) {
 962                         if (netif_msg_intr(priv))
 963                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
 964                                         dev->name, priv->interruptError);
 965
 966                         err = -1;
 967                         goto err_irq_fail;
 968                 }
 969         }
 970
 971         phy_start(priv->phydev);
 972
 973         /* Configure the coalescing support */
 974         if (priv->txcoalescing)
 975                 gfar_write(&regs->txic,
 976                            mk_ic_value(priv->txcount, priv->txtime));
 977         else
 978                 gfar_write(&regs->txic, 0);
 979
 980         if (priv->rxcoalescing)
 981                 gfar_write(&regs->rxic,
 982                            mk_ic_value(priv->rxcount, priv->rxtime));
 983         else
 984                 gfar_write(&regs->rxic, 0);
 985
 986         if (priv->rx_csum_enable)
 987                 rctrl |= RCTRL_CHECKSUMMING;
 988
 989         if (priv->extended_hash) {
 990                 rctrl |= RCTRL_EXTHASH;
 991
 992                 gfar_clear_exact_match(dev);
 993                 rctrl |= RCTRL_EMEN;
 994         }
 995
 996         if (priv->vlan_enable)
 997                 rctrl |= RCTRL_VLAN;
 998
 999         if (priv->padding) {
1000                 rctrl &= ~RCTRL_PAL_MASK;
1001                 rctrl |= RCTRL_PADDING(priv->padding);
1002         }
1003
1004         /* Init rctrl based on our settings */
1005         gfar_write(&priv->regs->rctrl, rctrl);
1006
1007         if (dev->features & NETIF_F_IP_CSUM)
1008                 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
1009
1010         /* Set the extraction length and index */
1011         attrs = ATTRELI_EL(priv->rx_stash_size) |
1012                 ATTRELI_EI(priv->rx_stash_index);
1013
1014         gfar_write(&priv->regs->attreli, attrs);
1015
1016         /* Start with defaults, and add stashing or locking
1017          * depending on the approprate variables */
1018         attrs = ATTR_INIT_SETTINGS;
1019
1020         if (priv->bd_stash_en)
1021                 attrs |= ATTR_BDSTASH;
1022
1023         if (priv->rx_stash_size != 0)
1024                 attrs |= ATTR_BUFSTASH;
1025
1026         gfar_write(&priv->regs->attr, attrs);
1027
1028         gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
1029         gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
1030         gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
1031
1032         /* Start the controller */
1033         gfar_start(dev);
1034
1035         return 0;
1036
1037 rx_irq_fail:
1038         free_irq(priv->interruptTransmit, dev);
1039 tx_irq_fail:
1040         free_irq(priv->interruptError, dev);
1041 err_irq_fail:
1042 err_rxalloc_fail:
1043 rx_skb_fail:
1044         free_skb_resources(priv);
1045 tx_skb_fail:
1046         dma_free_coherent(&dev->dev,
1047                         sizeof(struct txbd8)*priv->tx_ring_size
1048                         + sizeof(struct rxbd8)*priv->rx_ring_size,
1049                         priv->tx_bd_base,
1050                         gfar_read(&regs->tbase0));
1051
1052         return err;
1053 }
1054
1055 /* Called when something needs to use the ethernet device */
1056 /* Returns 0 for success. */
1057 static int gfar_enet_open(struct net_device *dev)
1058 {
1059 #ifdef CONFIG_GFAR_NAPI
1060         struct gfar_private *priv = netdev_priv(dev);
1061 #endif
1062         int err;
1063
1064 #ifdef CONFIG_GFAR_NAPI
1065         napi_enable(&priv->napi);
1066 #endif
1067
1068         /* Initialize a bunch of registers */
1069         init_registers(dev);
1070
1071         gfar_set_mac_address(dev);
1072
1073         err = init_phy(dev);
1074
1075         if(err) {
1076 #ifdef CONFIG_GFAR_NAPI
1077                 napi_disable(&priv->napi);
1078 #endif
1079                 return err;
1080         }
1081
1082         err = startup_gfar(dev);
1083         if (err) {
1084 #ifdef CONFIG_GFAR_NAPI
1085                 napi_disable(&priv->napi);
1086 #endif
1087                 return err;
1088         }
1089
1090         netif_start_queue(dev);
1091
1092         return err;
1093 }
1094
1095 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb, struct txbd8 *bdp)
1096 {
1097         struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
1098
1099         memset(fcb, 0, GMAC_FCB_LEN);
1100
1101         return fcb;
1102 }
1103
1104 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1105 {
1106         u8 flags = 0;
1107
1108         /* If we're here, it's a IP packet with a TCP or UDP
1109          * payload.  We set it to checksum, using a pseudo-header
1110          * we provide
1111          */
1112         flags = TXFCB_DEFAULT;
1113
1114         /* Tell the controller what the protocol is */
1115         /* And provide the already calculated phcs */
1116         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1117                 flags |= TXFCB_UDP;
1118                 fcb->phcs = udp_hdr(skb)->check;
1119         } else
1120                 fcb->phcs = tcp_hdr(skb)->check;
1121
1122         /* l3os is the distance between the start of the
1123          * frame (skb->data) and the start of the IP hdr.
1124          * l4os is the distance between the start of the
1125          * l3 hdr and the l4 hdr */
1126         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1127         fcb->l4os = skb_network_header_len(skb);
1128
1129         fcb->flags = flags;
1130 }
1131
1132 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1133 {
1134         fcb->flags |= TXFCB_VLN;
1135         fcb->vlctl = vlan_tx_tag_get(skb);
1136 }
1137
1138 /* This is called by the kernel when a frame is ready for transmission. */
1139 /* It is pointed to by the dev->hard_start_xmit function pointer */
1140 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1141 {
1142         struct gfar_private *priv = netdev_priv(dev);
1143         struct txfcb *fcb = NULL;
1144         struct txbd8 *txbdp;
1145         u16 status;
1146         unsigned long flags;
1147
1148         /* Update transmit stats */
1149         dev->stats.tx_bytes += skb->len;
1150
1151         /* Lock priv now */
1152         spin_lock_irqsave(&priv->txlock, flags);
1153
1154         /* Point at the first free tx descriptor */
1155         txbdp = priv->cur_tx;
1156
1157         /* Clear all but the WRAP status flags */
1158         status = txbdp->status & TXBD_WRAP;
1159
1160         /* Set up checksumming */
1161         if (likely((dev->features & NETIF_F_IP_CSUM)
1162                         && (CHECKSUM_PARTIAL == skb->ip_summed))) {
1163                 fcb = gfar_add_fcb(skb, txbdp);
1164                 status |= TXBD_TOE;
1165                 gfar_tx_checksum(skb, fcb);
1166         }
1167
1168         if (priv->vlan_enable &&
1169                         unlikely(priv->vlgrp && vlan_tx_tag_present(skb))) {
1170                 if (unlikely(NULL == fcb)) {
1171                         fcb = gfar_add_fcb(skb, txbdp);
1172                         status |= TXBD_TOE;
1173                 }
1174
1175                 gfar_tx_vlan(skb, fcb);
1176         }
1177
1178         /* Set buffer length and pointer */
1179         txbdp->length = skb->len;
1180         txbdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1181                         skb->len, DMA_TO_DEVICE);
1182
1183         /* Save the skb pointer so we can free it later */
1184         priv->tx_skbuff[priv->skb_curtx] = skb;
1185
1186         /* Update the current skb pointer (wrapping if this was the last) */
1187         priv->skb_curtx =
1188             (priv->skb_curtx + 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1189
1190         /* Flag the BD as interrupt-causing */
1191         status |= TXBD_INTERRUPT;
1192
1193         /* Flag the BD as ready to go, last in frame, and  */
1194         /* in need of CRC */
1195         status |= (TXBD_READY | TXBD_LAST | TXBD_CRC);
1196
1197         dev->trans_start = jiffies;
1198
1199         /* The powerpc-specific eieio() is used, as wmb() has too strong
1200          * semantics (it requires synchronization between cacheable and
1201          * uncacheable mappings, which eieio doesn't provide and which we
1202          * don't need), thus requiring a more expensive sync instruction.  At
1203          * some point, the set of architecture-independent barrier functions
1204          * should be expanded to include weaker barriers.
1205          */
1206
1207         eieio();
1208         txbdp->status = status;
1209
1210         /* If this was the last BD in the ring, the next one */
1211         /* is at the beginning of the ring */
1212         if (txbdp->status & TXBD_WRAP)
1213                 txbdp = priv->tx_bd_base;
1214         else
1215                 txbdp++;
1216
1217         /* If the next BD still needs to be cleaned up, then the bds
1218            are full.  We need to tell the kernel to stop sending us stuff. */
1219         if (txbdp == priv->dirty_tx) {
1220                 netif_stop_queue(dev);
1221
1222                 dev->stats.tx_fifo_errors++;
1223         }
1224
1225         /* Update the current txbd to the next one */
1226         priv->cur_tx = txbdp;
1227
1228         /* Tell the DMA to go go go */
1229         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1230
1231         /* Unlock priv */
1232         spin_unlock_irqrestore(&priv->txlock, flags);
1233
1234         return 0;
1235 }
1236
1237 /* Stops the kernel queue, and halts the controller */
1238 static int gfar_close(struct net_device *dev)
1239 {
1240         struct gfar_private *priv = netdev_priv(dev);
1241
1242 #ifdef CONFIG_GFAR_NAPI
1243         napi_disable(&priv->napi);
1244 #endif
1245
1246         stop_gfar(dev);
1247
1248         /* Disconnect from the PHY */
1249         phy_disconnect(priv->phydev);
1250         priv->phydev = NULL;
1251
1252         netif_stop_queue(dev);
1253
1254         return 0;
1255 }
1256
1257 /* Changes the mac address if the controller is not running. */
1258 static int gfar_set_mac_address(struct net_device *dev)
1259 {
1260         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1261
1262         return 0;
1263 }
1264
1265
1266 /* Enables and disables VLAN insertion/extraction */
1267 static void gfar_vlan_rx_register(struct net_device *dev,
1268                 struct vlan_group *grp)
1269 {
1270         struct gfar_private *priv = netdev_priv(dev);
1271         unsigned long flags;
1272         u32 tempval;
1273
1274         spin_lock_irqsave(&priv->rxlock, flags);
1275
1276         priv->vlgrp = grp;
1277
1278         if (grp) {
1279                 /* Enable VLAN tag insertion */
1280                 tempval = gfar_read(&priv->regs->tctrl);
1281                 tempval |= TCTRL_VLINS;
1282
1283                 gfar_write(&priv->regs->tctrl, tempval);
1284
1285                 /* Enable VLAN tag extraction */
1286                 tempval = gfar_read(&priv->regs->rctrl);
1287                 tempval |= RCTRL_VLEX;
1288                 gfar_write(&priv->regs->rctrl, tempval);
1289         } else {
1290                 /* Disable VLAN tag insertion */
1291                 tempval = gfar_read(&priv->regs->tctrl);
1292                 tempval &= ~TCTRL_VLINS;
1293                 gfar_write(&priv->regs->tctrl, tempval);
1294
1295                 /* Disable VLAN tag extraction */
1296                 tempval = gfar_read(&priv->regs->rctrl);
1297                 tempval &= ~RCTRL_VLEX;
1298                 gfar_write(&priv->regs->rctrl, tempval);
1299         }
1300
1301         spin_unlock_irqrestore(&priv->rxlock, flags);
1302 }
1303
1304 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1305 {
1306         int tempsize, tempval;
1307         struct gfar_private *priv = netdev_priv(dev);
1308         int oldsize = priv->rx_buffer_size;
1309         int frame_size = new_mtu + ETH_HLEN;
1310
1311         if (priv->vlan_enable)
1312                 frame_size += VLAN_HLEN;
1313
1314         if (gfar_uses_fcb(priv))
1315                 frame_size += GMAC_FCB_LEN;
1316
1317         frame_size += priv->padding;
1318
1319         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1320                 if (netif_msg_drv(priv))
1321                         printk(KERN_ERR "%s: Invalid MTU setting\n",
1322                                         dev->name);
1323                 return -EINVAL;
1324         }
1325
1326         tempsize =
1327             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1328             INCREMENTAL_BUFFER_SIZE;
1329
1330         /* Only stop and start the controller if it isn't already
1331          * stopped, and we changed something */
1332         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1333                 stop_gfar(dev);
1334
1335         priv->rx_buffer_size = tempsize;
1336
1337         dev->mtu = new_mtu;
1338
1339         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1340         gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1341
1342         /* If the mtu is larger than the max size for standard
1343          * ethernet frames (ie, a jumbo frame), then set maccfg2
1344          * to allow huge frames, and to check the length */
1345         tempval = gfar_read(&priv->regs->maccfg2);
1346
1347         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1348                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1349         else
1350                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1351
1352         gfar_write(&priv->regs->maccfg2, tempval);
1353
1354         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1355                 startup_gfar(dev);
1356
1357         return 0;
1358 }
1359
1360 /* gfar_timeout gets called when a packet has not been
1361  * transmitted after a set amount of time.
1362  * For now, assume that clearing out all the structures, and
1363  * starting over will fix the problem. */
1364 static void gfar_timeout(struct net_device *dev)
1365 {
1366         dev->stats.tx_errors++;
1367
1368         if (dev->flags & IFF_UP) {
1369                 stop_gfar(dev);
1370                 startup_gfar(dev);
1371         }
1372
1373         netif_schedule(dev);
1374 }
1375
1376 /* Interrupt Handler for Transmit complete */
1377 static int gfar_clean_tx_ring(struct net_device *dev)
1378 {
1379         struct txbd8 *bdp;
1380         struct gfar_private *priv = netdev_priv(dev);
1381         int howmany = 0;
1382
1383         bdp = priv->dirty_tx;
1384         while ((bdp->status & TXBD_READY) == 0) {
1385                 /* If dirty_tx and cur_tx are the same, then either the */
1386                 /* ring is empty or full now (it could only be full in the beginning, */
1387                 /* obviously).  If it is empty, we are done. */
1388                 if ((bdp == priv->cur_tx) && (netif_queue_stopped(dev) == 0))
1389                         break;
1390
1391                 howmany++;
1392
1393                 /* Deferred means some collisions occurred during transmit, */
1394                 /* but we eventually sent the packet. */
1395                 if (bdp->status & TXBD_DEF)
1396                         dev->stats.collisions++;
1397
1398                 /* Free the sk buffer associated with this TxBD */
1399                 dev_kfree_skb_irq(priv->tx_skbuff[priv->skb_dirtytx]);
1400
1401                 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
1402                 priv->skb_dirtytx =
1403                     (priv->skb_dirtytx +
1404                      1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1405
1406                 /* Clean BD length for empty detection */
1407                 bdp->length = 0;
1408
1409                 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1410                 if (bdp->status & TXBD_WRAP)
1411                         bdp = priv->tx_bd_base;
1412                 else
1413                         bdp++;
1414
1415                 /* Move dirty_tx to be the next bd */
1416                 priv->dirty_tx = bdp;
1417
1418                 /* We freed a buffer, so now we can restart transmission */
1419                 if (netif_queue_stopped(dev))
1420                         netif_wake_queue(dev);
1421         } /* while ((bdp->status & TXBD_READY) == 0) */
1422
1423         dev->stats.tx_packets += howmany;
1424
1425         return howmany;
1426 }
1427
1428 /* Interrupt Handler for Transmit complete */
1429 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1430 {
1431         struct net_device *dev = (struct net_device *) dev_id;
1432         struct gfar_private *priv = netdev_priv(dev);
1433
1434         /* Clear IEVENT */
1435         gfar_write(&priv->regs->ievent, IEVENT_TX_MASK);
1436
1437         /* Lock priv */
1438         spin_lock(&priv->txlock);
1439
1440         gfar_clean_tx_ring(dev);
1441
1442         /* If we are coalescing the interrupts, reset the timer */
1443         /* Otherwise, clear it */
1444         if (likely(priv->txcoalescing)) {
1445                 gfar_write(&priv->regs->txic, 0);
1446                 gfar_write(&priv->regs->txic,
1447                            mk_ic_value(priv->txcount, priv->txtime));
1448         }
1449
1450         spin_unlock(&priv->txlock);
1451
1452         return IRQ_HANDLED;
1453 }
1454
1455 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1456                 struct sk_buff *skb)
1457 {
1458         struct gfar_private *priv = netdev_priv(dev);
1459         u32 * status_len = (u32 *)bdp;
1460         u16 flags;
1461
1462         bdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1463                         priv->rx_buffer_size, DMA_FROM_DEVICE);
1464
1465         flags = RXBD_EMPTY | RXBD_INTERRUPT;
1466
1467         if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1468                 flags |= RXBD_WRAP;
1469
1470         eieio();
1471
1472         *status_len = (u32)flags << 16;
1473 }
1474
1475
1476 struct sk_buff * gfar_new_skb(struct net_device *dev)
1477 {
1478         unsigned int alignamount;
1479         struct gfar_private *priv = netdev_priv(dev);
1480         struct sk_buff *skb = NULL;
1481
1482         /* We have to allocate the skb, so keep trying till we succeed */
1483         skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
1484
1485         if (!skb)
1486                 return NULL;
1487
1488         alignamount = RXBUF_ALIGNMENT -
1489                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1490
1491         /* We need the data buffer to be aligned properly.  We will reserve
1492          * as many bytes as needed to align the data properly
1493          */
1494         skb_reserve(skb, alignamount);
1495
1496         return skb;
1497 }
1498
1499 static inline void count_errors(unsigned short status, struct net_device *dev)
1500 {
1501         struct gfar_private *priv = netdev_priv(dev);
1502         struct net_device_stats *stats = &dev->stats;
1503         struct gfar_extra_stats *estats = &priv->extra_stats;
1504
1505         /* If the packet was truncated, none of the other errors
1506          * matter */
1507         if (status & RXBD_TRUNCATED) {
1508                 stats->rx_length_errors++;
1509
1510                 estats->rx_trunc++;
1511
1512                 return;
1513         }
1514         /* Count the errors, if there were any */
1515         if (status & (RXBD_LARGE | RXBD_SHORT)) {
1516                 stats->rx_length_errors++;
1517
1518                 if (status & RXBD_LARGE)
1519                         estats->rx_large++;
1520                 else
1521                         estats->rx_short++;
1522         }
1523         if (status & RXBD_NONOCTET) {
1524                 stats->rx_frame_errors++;
1525                 estats->rx_nonoctet++;
1526         }
1527         if (status & RXBD_CRCERR) {
1528                 estats->rx_crcerr++;
1529                 stats->rx_crc_errors++;
1530         }
1531         if (status & RXBD_OVERRUN) {
1532                 estats->rx_overrun++;
1533                 stats->rx_crc_errors++;
1534         }
1535 }
1536
1537 irqreturn_t gfar_receive(int irq, void *dev_id)
1538 {
1539         struct net_device *dev = (struct net_device *) dev_id;
1540         struct gfar_private *priv = netdev_priv(dev);
1541 #ifdef CONFIG_GFAR_NAPI
1542         u32 tempval;
1543 #else
1544         unsigned long flags;
1545 #endif
1546
1547         /* support NAPI */
1548 #ifdef CONFIG_GFAR_NAPI
1549         /* Clear IEVENT, so interrupts aren't called again
1550          * because of the packets that have already arrived */
1551         gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1552
1553         if (netif_rx_schedule_prep(dev, &priv->napi)) {
1554                 tempval = gfar_read(&priv->regs->imask);
1555                 tempval &= IMASK_RTX_DISABLED;
1556                 gfar_write(&priv->regs->imask, tempval);
1557
1558                 __netif_rx_schedule(dev, &priv->napi);
1559         } else {
1560                 if (netif_msg_rx_err(priv))
1561                         printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n",
1562                                 dev->name, gfar_read(&priv->regs->ievent),
1563                                 gfar_read(&priv->regs->imask));
1564         }
1565 #else
1566         /* Clear IEVENT, so rx interrupt isn't called again
1567          * because of this interrupt */
1568         gfar_write(&priv->regs->ievent, IEVENT_RX_MASK);
1569
1570         spin_lock_irqsave(&priv->rxlock, flags);
1571         gfar_clean_rx_ring(dev, priv->rx_ring_size);
1572
1573         /* If we are coalescing interrupts, update the timer */
1574         /* Otherwise, clear it */
1575         if (likely(priv->rxcoalescing)) {
1576                 gfar_write(&priv->regs->rxic, 0);
1577                 gfar_write(&priv->regs->rxic,
1578                            mk_ic_value(priv->rxcount, priv->rxtime));
1579         }
1580
1581         spin_unlock_irqrestore(&priv->rxlock, flags);
1582 #endif
1583
1584         return IRQ_HANDLED;
1585 }
1586
1587 static inline int gfar_rx_vlan(struct sk_buff *skb,
1588                 struct vlan_group *vlgrp, unsigned short vlctl)
1589 {
1590 #ifdef CONFIG_GFAR_NAPI
1591         return vlan_hwaccel_receive_skb(skb, vlgrp, vlctl);
1592 #else
1593         return vlan_hwaccel_rx(skb, vlgrp, vlctl);
1594 #endif
1595 }
1596
1597 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1598 {
1599         /* If valid headers were found, and valid sums
1600          * were verified, then we tell the kernel that no
1601          * checksumming is necessary.  Otherwise, it is */
1602         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1603                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1604         else
1605                 skb->ip_summed = CHECKSUM_NONE;
1606 }
1607
1608
1609 static inline struct rxfcb *gfar_get_fcb(struct sk_buff *skb)
1610 {
1611         struct rxfcb *fcb = (struct rxfcb *)skb->data;
1612
1613         /* Remove the FCB from the skb */
1614         skb_pull(skb, GMAC_FCB_LEN);
1615
1616         return fcb;
1617 }
1618
1619 /* gfar_process_frame() -- handle one incoming packet if skb
1620  * isn't NULL.  */
1621 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1622                 int length)
1623 {
1624         struct gfar_private *priv = netdev_priv(dev);
1625         struct rxfcb *fcb = NULL;
1626
1627         if (NULL == skb) {
1628                 if (netif_msg_rx_err(priv))
1629                         printk(KERN_WARNING "%s: Missing skb!!.\n", dev->name);
1630                 dev->stats.rx_dropped++;
1631                 priv->extra_stats.rx_skbmissing++;
1632         } else {
1633                 int ret;
1634
1635                 /* Prep the skb for the packet */
1636                 skb_put(skb, length);
1637
1638                 /* Grab the FCB if there is one */
1639                 if (gfar_uses_fcb(priv))
1640                         fcb = gfar_get_fcb(skb);
1641
1642                 /* Remove the padded bytes, if there are any */
1643                 if (priv->padding)
1644                         skb_pull(skb, priv->padding);
1645
1646                 if (priv->rx_csum_enable)
1647                         gfar_rx_checksum(skb, fcb);
1648
1649                 /* Tell the skb what kind of packet this is */
1650                 skb->protocol = eth_type_trans(skb, dev);
1651
1652                 /* Send the packet up the stack */
1653                 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1654                         ret = gfar_rx_vlan(skb, priv->vlgrp, fcb->vlctl);
1655                 else
1656                         ret = RECEIVE(skb);
1657
1658                 if (NET_RX_DROP == ret)
1659                         priv->extra_stats.kernel_dropped++;
1660         }
1661
1662         return 0;
1663 }
1664
1665 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1666  *   until the budget/quota has been reached. Returns the number
1667  *   of frames handled
1668  */
1669 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1670 {
1671         struct rxbd8 *bdp;
1672         struct sk_buff *skb;
1673         u16 pkt_len;
1674         int howmany = 0;
1675         struct gfar_private *priv = netdev_priv(dev);
1676
1677         /* Get the first full descriptor */
1678         bdp = priv->cur_rx;
1679
1680         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1681                 struct sk_buff *newskb;
1682                 rmb();
1683
1684                 /* Add another skb for the future */
1685                 newskb = gfar_new_skb(dev);
1686
1687                 skb = priv->rx_skbuff[priv->skb_currx];
1688
1689                 /* We drop the frame if we failed to allocate a new buffer */
1690                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1691                                  bdp->status & RXBD_ERR)) {
1692                         count_errors(bdp->status, dev);
1693
1694                         if (unlikely(!newskb))
1695                                 newskb = skb;
1696
1697                         if (skb) {
1698                                 dma_unmap_single(&priv->dev->dev,
1699                                                 bdp->bufPtr,
1700                                                 priv->rx_buffer_size,
1701                                                 DMA_FROM_DEVICE);
1702
1703                                 dev_kfree_skb_any(skb);
1704                         }
1705                 } else {
1706                         /* Increment the number of packets */
1707                         dev->stats.rx_packets++;
1708                         howmany++;
1709
1710                         /* Remove the FCS from the packet length */
1711                         pkt_len = bdp->length - 4;
1712
1713                         gfar_process_frame(dev, skb, pkt_len);
1714
1715                         dev->stats.rx_bytes += pkt_len;
1716                 }
1717
1718                 dev->last_rx = jiffies;
1719
1720                 priv->rx_skbuff[priv->skb_currx] = newskb;
1721
1722                 /* Setup the new bdp */
1723                 gfar_new_rxbdp(dev, bdp, newskb);
1724
1725                 /* Update to the next pointer */
1726                 if (bdp->status & RXBD_WRAP)
1727                         bdp = priv->rx_bd_base;
1728                 else
1729                         bdp++;
1730
1731                 /* update to point at the next skb */
1732                 priv->skb_currx =
1733                     (priv->skb_currx + 1) &
1734                     RX_RING_MOD_MASK(priv->rx_ring_size);
1735         }
1736
1737         /* Update the current rxbd pointer to be the next one */
1738         priv->cur_rx = bdp;
1739
1740         return howmany;
1741 }
1742
1743 #ifdef CONFIG_GFAR_NAPI
1744 static int gfar_poll(struct napi_struct *napi, int budget)
1745 {
1746         struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1747         struct net_device *dev = priv->dev;
1748         int howmany;
1749         unsigned long flags;
1750
1751         /* If we fail to get the lock, don't bother with the TX BDs */
1752         if (spin_trylock_irqsave(&priv->txlock, flags)) {
1753                 gfar_clean_tx_ring(dev);
1754                 spin_unlock_irqrestore(&priv->txlock, flags);
1755         }
1756
1757         howmany = gfar_clean_rx_ring(dev, budget);
1758
1759         if (howmany < budget) {
1760                 netif_rx_complete(dev, napi);
1761
1762                 /* Clear the halt bit in RSTAT */
1763                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1764
1765                 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1766
1767                 /* If we are coalescing interrupts, update the timer */
1768                 /* Otherwise, clear it */
1769                 if (likely(priv->rxcoalescing)) {
1770                         gfar_write(&priv->regs->rxic, 0);
1771                         gfar_write(&priv->regs->rxic,
1772                                    mk_ic_value(priv->rxcount, priv->rxtime));
1773                 }
1774         }
1775
1776         return howmany;
1777 }
1778 #endif
1779
1780 #ifdef CONFIG_NET_POLL_CONTROLLER
1781 /*
1782  * Polling 'interrupt' - used by things like netconsole to send skbs
1783  * without having to re-enable interrupts. It's not called while
1784  * the interrupt routine is executing.
1785  */
1786 static void gfar_netpoll(struct net_device *dev)
1787 {
1788         struct gfar_private *priv = netdev_priv(dev);
1789
1790         /* If the device has multiple interrupts, run tx/rx */
1791         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1792                 disable_irq(priv->interruptTransmit);
1793                 disable_irq(priv->interruptReceive);
1794                 disable_irq(priv->interruptError);
1795                 gfar_interrupt(priv->interruptTransmit, dev);
1796                 enable_irq(priv->interruptError);
1797                 enable_irq(priv->interruptReceive);
1798                 enable_irq(priv->interruptTransmit);
1799         } else {
1800                 disable_irq(priv->interruptTransmit);
1801                 gfar_interrupt(priv->interruptTransmit, dev);
1802                 enable_irq(priv->interruptTransmit);
1803         }
1804 }
1805 #endif
1806
1807 /* The interrupt handler for devices with one interrupt */
1808 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1809 {
1810         struct net_device *dev = dev_id;
1811         struct gfar_private *priv = netdev_priv(dev);
1812
1813         /* Save ievent for future reference */
1814         u32 events = gfar_read(&priv->regs->ievent);
1815
1816         /* Check for reception */
1817         if (events & IEVENT_RX_MASK)
1818                 gfar_receive(irq, dev_id);
1819
1820         /* Check for transmit completion */
1821         if (events & IEVENT_TX_MASK)
1822                 gfar_transmit(irq, dev_id);
1823
1824         /* Check for errors */
1825         if (events & IEVENT_ERR_MASK)
1826                 gfar_error(irq, dev_id);
1827
1828         return IRQ_HANDLED;
1829 }
1830
1831 /* Called every time the controller might need to be made
1832  * aware of new link state.  The PHY code conveys this
1833  * information through variables in the phydev structure, and this
1834  * function converts those variables into the appropriate
1835  * register values, and can bring down the device if needed.
1836  */
1837 static void adjust_link(struct net_device *dev)
1838 {
1839         struct gfar_private *priv = netdev_priv(dev);
1840         struct gfar __iomem *regs = priv->regs;
1841         unsigned long flags;
1842         struct phy_device *phydev = priv->phydev;
1843         int new_state = 0;
1844
1845         spin_lock_irqsave(&priv->txlock, flags);
1846         if (phydev->link) {
1847                 u32 tempval = gfar_read(&regs->maccfg2);
1848                 u32 ecntrl = gfar_read(&regs->ecntrl);
1849
1850                 /* Now we make sure that we can be in full duplex mode.
1851                  * If not, we operate in half-duplex mode. */
1852                 if (phydev->duplex != priv->oldduplex) {
1853                         new_state = 1;
1854                         if (!(phydev->duplex))
1855                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
1856                         else
1857                                 tempval |= MACCFG2_FULL_DUPLEX;
1858
1859                         priv->oldduplex = phydev->duplex;
1860                 }
1861
1862                 if (phydev->speed != priv->oldspeed) {
1863                         new_state = 1;
1864                         switch (phydev->speed) {
1865                         case 1000:
1866                                 tempval =
1867                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1868                                 break;
1869                         case 100:
1870                         case 10:
1871                                 tempval =
1872                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1873
1874                                 /* Reduced mode distinguishes
1875                                  * between 10 and 100 */
1876                                 if (phydev->speed == SPEED_100)
1877                                         ecntrl |= ECNTRL_R100;
1878                                 else
1879                                         ecntrl &= ~(ECNTRL_R100);
1880                                 break;
1881                         default:
1882                                 if (netif_msg_link(priv))
1883                                         printk(KERN_WARNING
1884                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
1885                                                 dev->name, phydev->speed);
1886                                 break;
1887                         }
1888
1889                         priv->oldspeed = phydev->speed;
1890                 }
1891
1892                 gfar_write(&regs->maccfg2, tempval);
1893                 gfar_write(&regs->ecntrl, ecntrl);
1894
1895                 if (!priv->oldlink) {
1896                         new_state = 1;
1897                         priv->oldlink = 1;
1898                         netif_schedule(dev);
1899                 }
1900         } else if (priv->oldlink) {
1901                 new_state = 1;
1902                 priv->oldlink = 0;
1903                 priv->oldspeed = 0;
1904                 priv->oldduplex = -1;
1905         }
1906
1907         if (new_state && netif_msg_link(priv))
1908                 phy_print_status(phydev);
1909
1910         spin_unlock_irqrestore(&priv->txlock, flags);
1911 }
1912
1913 /* Update the hash table based on the current list of multicast
1914  * addresses we subscribe to.  Also, change the promiscuity of
1915  * the device based on the flags (this function is called
1916  * whenever dev->flags is changed */
1917 static void gfar_set_multi(struct net_device *dev)
1918 {
1919         struct dev_mc_list *mc_ptr;
1920         struct gfar_private *priv = netdev_priv(dev);
1921         struct gfar __iomem *regs = priv->regs;
1922         u32 tempval;
1923
1924         if(dev->flags & IFF_PROMISC) {
1925                 /* Set RCTRL to PROM */
1926                 tempval = gfar_read(&regs->rctrl);
1927                 tempval |= RCTRL_PROM;
1928                 gfar_write(&regs->rctrl, tempval);
1929         } else {
1930                 /* Set RCTRL to not PROM */
1931                 tempval = gfar_read(&regs->rctrl);
1932                 tempval &= ~(RCTRL_PROM);
1933                 gfar_write(&regs->rctrl, tempval);
1934         }
1935
1936         if(dev->flags & IFF_ALLMULTI) {
1937                 /* Set the hash to rx all multicast frames */
1938                 gfar_write(&regs->igaddr0, 0xffffffff);
1939                 gfar_write(&regs->igaddr1, 0xffffffff);
1940                 gfar_write(&regs->igaddr2, 0xffffffff);
1941                 gfar_write(&regs->igaddr3, 0xffffffff);
1942                 gfar_write(&regs->igaddr4, 0xffffffff);
1943                 gfar_write(&regs->igaddr5, 0xffffffff);
1944                 gfar_write(&regs->igaddr6, 0xffffffff);
1945                 gfar_write(&regs->igaddr7, 0xffffffff);
1946                 gfar_write(&regs->gaddr0, 0xffffffff);
1947                 gfar_write(&regs->gaddr1, 0xffffffff);
1948                 gfar_write(&regs->gaddr2, 0xffffffff);
1949                 gfar_write(&regs->gaddr3, 0xffffffff);
1950                 gfar_write(&regs->gaddr4, 0xffffffff);
1951                 gfar_write(&regs->gaddr5, 0xffffffff);
1952                 gfar_write(&regs->gaddr6, 0xffffffff);
1953                 gfar_write(&regs->gaddr7, 0xffffffff);
1954         } else {
1955                 int em_num;
1956                 int idx;
1957
1958                 /* zero out the hash */
1959                 gfar_write(&regs->igaddr0, 0x0);
1960                 gfar_write(&regs->igaddr1, 0x0);
1961                 gfar_write(&regs->igaddr2, 0x0);
1962                 gfar_write(&regs->igaddr3, 0x0);
1963                 gfar_write(&regs->igaddr4, 0x0);
1964                 gfar_write(&regs->igaddr5, 0x0);
1965                 gfar_write(&regs->igaddr6, 0x0);
1966                 gfar_write(&regs->igaddr7, 0x0);
1967                 gfar_write(&regs->gaddr0, 0x0);
1968                 gfar_write(&regs->gaddr1, 0x0);
1969                 gfar_write(&regs->gaddr2, 0x0);
1970                 gfar_write(&regs->gaddr3, 0x0);
1971                 gfar_write(&regs->gaddr4, 0x0);
1972                 gfar_write(&regs->gaddr5, 0x0);
1973                 gfar_write(&regs->gaddr6, 0x0);
1974                 gfar_write(&regs->gaddr7, 0x0);
1975
1976                 /* If we have extended hash tables, we need to
1977                  * clear the exact match registers to prepare for
1978                  * setting them */
1979                 if (priv->extended_hash) {
1980                         em_num = GFAR_EM_NUM + 1;
1981                         gfar_clear_exact_match(dev);
1982                         idx = 1;
1983                 } else {
1984                         idx = 0;
1985                         em_num = 0;
1986                 }
1987
1988                 if(dev->mc_count == 0)
1989                         return;
1990
1991                 /* Parse the list, and set the appropriate bits */
1992                 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
1993                         if (idx < em_num) {
1994                                 gfar_set_mac_for_addr(dev, idx,
1995                                                 mc_ptr->dmi_addr);
1996                                 idx++;
1997                         } else
1998                                 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
1999                 }
2000         }
2001
2002         return;
2003 }
2004
2005
2006 /* Clears each of the exact match registers to zero, so they
2007  * don't interfere with normal reception */
2008 static void gfar_clear_exact_match(struct net_device *dev)
2009 {
2010         int idx;
2011         u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
2012
2013         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
2014                 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
2015 }
2016
2017 /* Set the appropriate hash bit for the given addr */
2018 /* The algorithm works like so:
2019  * 1) Take the Destination Address (ie the multicast address), and
2020  * do a CRC on it (little endian), and reverse the bits of the
2021  * result.
2022  * 2) Use the 8 most significant bits as a hash into a 256-entry
2023  * table.  The table is controlled through 8 32-bit registers:
2024  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
2025  * gaddr7.  This means that the 3 most significant bits in the
2026  * hash index which gaddr register to use, and the 5 other bits
2027  * indicate which bit (assuming an IBM numbering scheme, which
2028  * for PowerPC (tm) is usually the case) in the register holds
2029  * the entry. */
2030 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2031 {
2032         u32 tempval;
2033         struct gfar_private *priv = netdev_priv(dev);
2034         u32 result = ether_crc(MAC_ADDR_LEN, addr);
2035         int width = priv->hash_width;
2036         u8 whichbit = (result >> (32 - width)) & 0x1f;
2037         u8 whichreg = result >> (32 - width + 5);
2038         u32 value = (1 << (31-whichbit));
2039
2040         tempval = gfar_read(priv->hash_regs[whichreg]);
2041         tempval |= value;
2042         gfar_write(priv->hash_regs[whichreg], tempval);
2043
2044         return;
2045 }
2046
2047
2048 /* There are multiple MAC Address register pairs on some controllers
2049  * This function sets the numth pair to a given address
2050  */
2051 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2052 {
2053         struct gfar_private *priv = netdev_priv(dev);
2054         int idx;
2055         char tmpbuf[MAC_ADDR_LEN];
2056         u32 tempval;
2057         u32 __iomem *macptr = &priv->regs->macstnaddr1;
2058
2059         macptr += num*2;
2060
2061         /* Now copy it into the mac registers backwards, cuz */
2062         /* little endian is silly */
2063         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2064                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2065
2066         gfar_write(macptr, *((u32 *) (tmpbuf)));
2067
2068         tempval = *((u32 *) (tmpbuf + 4));
2069
2070         gfar_write(macptr+1, tempval);
2071 }
2072
2073 /* GFAR error interrupt handler */
2074 static irqreturn_t gfar_error(int irq, void *dev_id)
2075 {
2076         struct net_device *dev = dev_id;
2077         struct gfar_private *priv = netdev_priv(dev);
2078
2079         /* Save ievent for future reference */
2080         u32 events = gfar_read(&priv->regs->ievent);
2081
2082         /* Clear IEVENT */
2083         gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2084
2085         /* Magic Packet is not an error. */
2086         if ((priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2087             (events & IEVENT_MAG))
2088                 events &= ~IEVENT_MAG;
2089
2090         /* Hmm... */
2091         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2092                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2093                        dev->name, events, gfar_read(&priv->regs->imask));
2094
2095         /* Update the error counters */
2096         if (events & IEVENT_TXE) {
2097                 dev->stats.tx_errors++;
2098
2099                 if (events & IEVENT_LC)
2100                         dev->stats.tx_window_errors++;
2101                 if (events & IEVENT_CRL)
2102                         dev->stats.tx_aborted_errors++;
2103                 if (events & IEVENT_XFUN) {
2104                         if (netif_msg_tx_err(priv))
2105                                 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2106                                        "packet dropped.\n", dev->name);
2107                         dev->stats.tx_dropped++;
2108                         priv->extra_stats.tx_underrun++;
2109
2110                         /* Reactivate the Tx Queues */
2111                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2112                 }
2113                 if (netif_msg_tx_err(priv))
2114                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2115         }
2116         if (events & IEVENT_BSY) {
2117                 dev->stats.rx_errors++;
2118                 priv->extra_stats.rx_bsy++;
2119
2120                 gfar_receive(irq, dev_id);
2121
2122 #ifndef CONFIG_GFAR_NAPI
2123                 /* Clear the halt bit in RSTAT */
2124                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
2125 #endif
2126
2127                 if (netif_msg_rx_err(priv))
2128                         printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2129                                dev->name, gfar_read(&priv->regs->rstat));
2130         }
2131         if (events & IEVENT_BABR) {
2132                 dev->stats.rx_errors++;
2133                 priv->extra_stats.rx_babr++;
2134
2135                 if (netif_msg_rx_err(priv))
2136                         printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2137         }
2138         if (events & IEVENT_EBERR) {
2139                 priv->extra_stats.eberr++;
2140                 if (netif_msg_rx_err(priv))
2141                         printk(KERN_DEBUG "%s: bus error\n", dev->name);
2142         }
2143         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2144                 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2145
2146         if (events & IEVENT_BABT) {
2147                 priv->extra_stats.tx_babt++;
2148                 if (netif_msg_tx_err(priv))
2149                         printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2150         }
2151         return IRQ_HANDLED;
2152 }
2153
2154 /* work with hotplug and coldplug */
2155 MODULE_ALIAS("platform:fsl-gianfar");
2156
2157 /* Structure for a device driver */
2158 static struct platform_driver gfar_driver = {
2159         .probe = gfar_probe,
2160         .remove = gfar_remove,
2161         .suspend = gfar_suspend,
2162         .resume = gfar_resume,
2163         .driver = {
2164                 .name = "fsl-gianfar",
2165                 .owner = THIS_MODULE,
2166         },
2167 };
2168
2169 static int __init gfar_init(void)
2170 {
2171         int err = gfar_mdio_init();
2172
2173         if (err)
2174                 return err;
2175
2176         err = platform_driver_register(&gfar_driver);
2177
2178         if (err)
2179                 gfar_mdio_exit();
2180
2181         return err;
2182 }
2183
2184 static void __exit gfar_exit(void)
2185 {
2186         platform_driver_unregister(&gfar_driver);
2187         gfar_mdio_exit();
2188 }
2189
2190 module_init(gfar_init);
2191 module_exit(gfar_exit);
2192