Merge git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi-rc-fixes-2.6
[linux-2.6] / drivers / i2c / busses / i2c-pxa.c
1 /*
2  *  i2c_adap_pxa.c
3  *
4  *  I2C adapter for the PXA I2C bus access.
5  *
6  *  Copyright (C) 2002 Intrinsyc Software Inc.
7  *  Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
8  *
9  *  This program is free software; you can redistribute it and/or modify
10  *  it under the terms of the GNU General Public License version 2 as
11  *  published by the Free Software Foundation.
12  *
13  *  History:
14  *    Apr 2002: Initial version [CS]
15  *    Jun 2002: Properly seperated algo/adap [FB]
16  *    Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
17  *    Jan 2003: added limited signal handling [Kai-Uwe Bloem]
18  *    Sep 2004: Major rework to ensure efficient bus handling [RMK]
19  *    Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
20  *    Feb 2005: Rework slave mode handling [RMK]
21  */
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/i2c.h>
25 #include <linux/i2c-id.h>
26 #include <linux/init.h>
27 #include <linux/time.h>
28 #include <linux/sched.h>
29 #include <linux/delay.h>
30 #include <linux/errno.h>
31 #include <linux/interrupt.h>
32 #include <linux/i2c-pxa.h>
33 #include <linux/platform_device.h>
34 #include <linux/err.h>
35 #include <linux/clk.h>
36
37 #include <asm/hardware.h>
38 #include <asm/irq.h>
39 #include <asm/io.h>
40 #include <asm/arch/i2c.h>
41 #include <asm/arch/pxa-regs.h>
42
43 struct pxa_i2c {
44         spinlock_t              lock;
45         wait_queue_head_t       wait;
46         struct i2c_msg          *msg;
47         unsigned int            msg_num;
48         unsigned int            msg_idx;
49         unsigned int            msg_ptr;
50         unsigned int            slave_addr;
51
52         struct i2c_adapter      adap;
53         struct clk              *clk;
54 #ifdef CONFIG_I2C_PXA_SLAVE
55         struct i2c_slave_client *slave;
56 #endif
57
58         unsigned int            irqlogidx;
59         u32                     isrlog[32];
60         u32                     icrlog[32];
61
62         void __iomem            *reg_base;
63
64         unsigned long           iobase;
65         unsigned long           iosize;
66
67         int                     irq;
68         int                     use_pio;
69 };
70
71 #define _IBMR(i2c)      ((i2c)->reg_base + 0)
72 #define _IDBR(i2c)      ((i2c)->reg_base + 8)
73 #define _ICR(i2c)       ((i2c)->reg_base + 0x10)
74 #define _ISR(i2c)       ((i2c)->reg_base + 0x18)
75 #define _ISAR(i2c)      ((i2c)->reg_base + 0x20)
76
77 /*
78  * I2C Slave mode address
79  */
80 #define I2C_PXA_SLAVE_ADDR      0x1
81
82 #ifdef DEBUG
83
84 struct bits {
85         u32     mask;
86         const char *set;
87         const char *unset;
88 };
89 #define PXA_BIT(m, s, u)        { .mask = m, .set = s, .unset = u }
90
91 static inline void
92 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
93 {
94         printk("%s %08x: ", prefix, val);
95         while (num--) {
96                 const char *str = val & bits->mask ? bits->set : bits->unset;
97                 if (str)
98                         printk("%s ", str);
99                 bits++;
100         }
101 }
102
103 static const struct bits isr_bits[] = {
104         PXA_BIT(ISR_RWM,        "RX",           "TX"),
105         PXA_BIT(ISR_ACKNAK,     "NAK",          "ACK"),
106         PXA_BIT(ISR_UB,         "Bsy",          "Rdy"),
107         PXA_BIT(ISR_IBB,        "BusBsy",       "BusRdy"),
108         PXA_BIT(ISR_SSD,        "SlaveStop",    NULL),
109         PXA_BIT(ISR_ALD,        "ALD",          NULL),
110         PXA_BIT(ISR_ITE,        "TxEmpty",      NULL),
111         PXA_BIT(ISR_IRF,        "RxFull",       NULL),
112         PXA_BIT(ISR_GCAD,       "GenCall",      NULL),
113         PXA_BIT(ISR_SAD,        "SlaveAddr",    NULL),
114         PXA_BIT(ISR_BED,        "BusErr",       NULL),
115 };
116
117 static void decode_ISR(unsigned int val)
118 {
119         decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
120         printk("\n");
121 }
122
123 static const struct bits icr_bits[] = {
124         PXA_BIT(ICR_START,  "START",    NULL),
125         PXA_BIT(ICR_STOP,   "STOP",     NULL),
126         PXA_BIT(ICR_ACKNAK, "ACKNAK",   NULL),
127         PXA_BIT(ICR_TB,     "TB",       NULL),
128         PXA_BIT(ICR_MA,     "MA",       NULL),
129         PXA_BIT(ICR_SCLE,   "SCLE",     "scle"),
130         PXA_BIT(ICR_IUE,    "IUE",      "iue"),
131         PXA_BIT(ICR_GCD,    "GCD",      NULL),
132         PXA_BIT(ICR_ITEIE,  "ITEIE",    NULL),
133         PXA_BIT(ICR_IRFIE,  "IRFIE",    NULL),
134         PXA_BIT(ICR_BEIE,   "BEIE",     NULL),
135         PXA_BIT(ICR_SSDIE,  "SSDIE",    NULL),
136         PXA_BIT(ICR_ALDIE,  "ALDIE",    NULL),
137         PXA_BIT(ICR_SADIE,  "SADIE",    NULL),
138         PXA_BIT(ICR_UR,     "UR",               "ur"),
139 };
140
141 #ifdef CONFIG_I2C_PXA_SLAVE
142 static void decode_ICR(unsigned int val)
143 {
144         decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
145         printk("\n");
146 }
147 #endif
148
149 static unsigned int i2c_debug = DEBUG;
150
151 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
152 {
153         dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno,
154                 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
155 }
156
157 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __FUNCTION__)
158 #else
159 #define i2c_debug       0
160
161 #define show_state(i2c) do { } while (0)
162 #define decode_ISR(val) do { } while (0)
163 #define decode_ICR(val) do { } while (0)
164 #endif
165
166 #define eedbg(lvl, x...) do { if ((lvl) < 1) { printk(KERN_DEBUG "" x); } } while(0)
167
168 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
169 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id);
170
171 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
172 {
173         unsigned int i;
174         printk("i2c: error: %s\n", why);
175         printk("i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n",
176                 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
177         printk("i2c: ICR: %08x ISR: %08x\n"
178                "i2c: log: ", readl(_ICR(i2c)), readl(_ISR(i2c)));
179         for (i = 0; i < i2c->irqlogidx; i++)
180                 printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
181         printk("\n");
182 }
183
184 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
185 {
186         return !(readl(_ICR(i2c)) & ICR_SCLE);
187 }
188
189 static void i2c_pxa_abort(struct pxa_i2c *i2c)
190 {
191         unsigned long timeout = jiffies + HZ/4;
192
193         if (i2c_pxa_is_slavemode(i2c)) {
194                 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
195                 return;
196         }
197
198         while (time_before(jiffies, timeout) && (readl(_IBMR(i2c)) & 0x1) == 0) {
199                 unsigned long icr = readl(_ICR(i2c));
200
201                 icr &= ~ICR_START;
202                 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
203
204                 writel(icr, _ICR(i2c));
205
206                 show_state(i2c);
207
208                 msleep(1);
209         }
210
211         writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
212                _ICR(i2c));
213 }
214
215 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
216 {
217         int timeout = DEF_TIMEOUT;
218
219         while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
220                 if ((readl(_ISR(i2c)) & ISR_SAD) != 0)
221                         timeout += 4;
222
223                 msleep(2);
224                 show_state(i2c);
225         }
226
227         if (timeout <= 0)
228                 show_state(i2c);
229
230         return timeout <= 0 ? I2C_RETRY : 0;
231 }
232
233 static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
234 {
235         unsigned long timeout = jiffies + HZ*4;
236
237         while (time_before(jiffies, timeout)) {
238                 if (i2c_debug > 1)
239                         dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
240                                 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
241
242                 if (readl(_ISR(i2c)) & ISR_SAD) {
243                         if (i2c_debug > 0)
244                                 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
245                         goto out;
246                 }
247
248                 /* wait for unit and bus being not busy, and we also do a
249                  * quick check of the i2c lines themselves to ensure they've
250                  * gone high...
251                  */
252                 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) {
253                         if (i2c_debug > 0)
254                                 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
255                         return 1;
256                 }
257
258                 msleep(1);
259         }
260
261         if (i2c_debug > 0)
262                 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
263  out:
264         return 0;
265 }
266
267 static int i2c_pxa_set_master(struct pxa_i2c *i2c)
268 {
269         if (i2c_debug)
270                 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
271
272         if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) {
273                 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
274                 if (!i2c_pxa_wait_master(i2c)) {
275                         dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
276                         return I2C_RETRY;
277                 }
278         }
279
280         writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
281         return 0;
282 }
283
284 #ifdef CONFIG_I2C_PXA_SLAVE
285 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
286 {
287         unsigned long timeout = jiffies + HZ*1;
288
289         /* wait for stop */
290
291         show_state(i2c);
292
293         while (time_before(jiffies, timeout)) {
294                 if (i2c_debug > 1)
295                         dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
296                                 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
297
298                 if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 ||
299                     (readl(_ISR(i2c)) & ISR_SAD) != 0 ||
300                     (readl(_ICR(i2c)) & ICR_SCLE) == 0) {
301                         if (i2c_debug > 1)
302                                 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
303                         return 1;
304                 }
305
306                 msleep(1);
307         }
308
309         if (i2c_debug > 0)
310                 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
311         return 0;
312 }
313
314 /*
315  * clear the hold on the bus, and take of anything else
316  * that has been configured
317  */
318 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
319 {
320         show_state(i2c);
321
322         if (errcode < 0) {
323                 udelay(100);   /* simple delay */
324         } else {
325                 /* we need to wait for the stop condition to end */
326
327                 /* if we where in stop, then clear... */
328                 if (readl(_ICR(i2c)) & ICR_STOP) {
329                         udelay(100);
330                         writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
331                 }
332
333                 if (!i2c_pxa_wait_slave(i2c)) {
334                         dev_err(&i2c->adap.dev, "%s: wait timedout\n",
335                                 __func__);
336                         return;
337                 }
338         }
339
340         writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
341         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
342
343         if (i2c_debug) {
344                 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c)));
345                 decode_ICR(readl(_ICR(i2c)));
346         }
347 }
348 #else
349 #define i2c_pxa_set_slave(i2c, err)     do { } while (0)
350 #endif
351
352 static void i2c_pxa_reset(struct pxa_i2c *i2c)
353 {
354         pr_debug("Resetting I2C Controller Unit\n");
355
356         /* abort any transfer currently under way */
357         i2c_pxa_abort(i2c);
358
359         /* reset according to 9.8 */
360         writel(ICR_UR, _ICR(i2c));
361         writel(I2C_ISR_INIT, _ISR(i2c));
362         writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
363
364         writel(i2c->slave_addr, _ISAR(i2c));
365
366         /* set control register values */
367         writel(I2C_ICR_INIT, _ICR(i2c));
368
369 #ifdef CONFIG_I2C_PXA_SLAVE
370         dev_info(&i2c->adap.dev, "Enabling slave mode\n");
371         writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
372 #endif
373
374         i2c_pxa_set_slave(i2c, 0);
375
376         /* enable unit */
377         writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
378         udelay(100);
379 }
380
381
382 #ifdef CONFIG_I2C_PXA_SLAVE
383 /*
384  * PXA I2C Slave mode
385  */
386
387 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
388 {
389         if (isr & ISR_BED) {
390                 /* what should we do here? */
391         } else {
392                 int ret = 0;
393
394                 if (i2c->slave != NULL)
395                         ret = i2c->slave->read(i2c->slave->data);
396
397                 writel(ret, _IDBR(i2c));
398                 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));   /* allow next byte */
399         }
400 }
401
402 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
403 {
404         unsigned int byte = readl(_IDBR(i2c));
405
406         if (i2c->slave != NULL)
407                 i2c->slave->write(i2c->slave->data, byte);
408
409         writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
410 }
411
412 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
413 {
414         int timeout;
415
416         if (i2c_debug > 0)
417                 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
418                        (isr & ISR_RWM) ? 'r' : 't');
419
420         if (i2c->slave != NULL)
421                 i2c->slave->event(i2c->slave->data,
422                                  (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE);
423
424         /*
425          * slave could interrupt in the middle of us generating a
426          * start condition... if this happens, we'd better back off
427          * and stop holding the poor thing up
428          */
429         writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
430         writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
431
432         timeout = 0x10000;
433
434         while (1) {
435                 if ((readl(_IBMR(i2c)) & 2) == 2)
436                         break;
437
438                 timeout--;
439
440                 if (timeout <= 0) {
441                         dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
442                         break;
443                 }
444         }
445
446         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
447 }
448
449 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
450 {
451         if (i2c_debug > 2)
452                 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
453
454         if (i2c->slave != NULL)
455                 i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP);
456
457         if (i2c_debug > 2)
458                 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
459
460         /*
461          * If we have a master-mode message waiting,
462          * kick it off now that the slave has completed.
463          */
464         if (i2c->msg)
465                 i2c_pxa_master_complete(i2c, I2C_RETRY);
466 }
467 #else
468 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
469 {
470         if (isr & ISR_BED) {
471                 /* what should we do here? */
472         } else {
473                 writel(0, _IDBR(i2c));
474                 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
475         }
476 }
477
478 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
479 {
480         writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
481 }
482
483 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
484 {
485         int timeout;
486
487         /*
488          * slave could interrupt in the middle of us generating a
489          * start condition... if this happens, we'd better back off
490          * and stop holding the poor thing up
491          */
492         writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
493         writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
494
495         timeout = 0x10000;
496
497         while (1) {
498                 if ((readl(_IBMR(i2c)) & 2) == 2)
499                         break;
500
501                 timeout--;
502
503                 if (timeout <= 0) {
504                         dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
505                         break;
506                 }
507         }
508
509         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
510 }
511
512 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
513 {
514         if (i2c->msg)
515                 i2c_pxa_master_complete(i2c, I2C_RETRY);
516 }
517 #endif
518
519 /*
520  * PXA I2C Master mode
521  */
522
523 static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg)
524 {
525         unsigned int addr = (msg->addr & 0x7f) << 1;
526
527         if (msg->flags & I2C_M_RD)
528                 addr |= 1;
529
530         return addr;
531 }
532
533 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
534 {
535         u32 icr;
536
537         /*
538          * Step 1: target slave address into IDBR
539          */
540         writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
541
542         /*
543          * Step 2: initiate the write.
544          */
545         icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
546         writel(icr | ICR_START | ICR_TB, _ICR(i2c));
547 }
548
549 static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c)
550 {
551         u32 icr;
552
553         /*
554          * Clear the STOP and ACK flags
555          */
556         icr = readl(_ICR(i2c));
557         icr &= ~(ICR_STOP | ICR_ACKNAK);
558         writel(icr, _ICR(i2c));
559 }
560
561 static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
562 {
563         /* make timeout the same as for interrupt based functions */
564         long timeout = 2 * DEF_TIMEOUT;
565
566         /*
567          * Wait for the bus to become free.
568          */
569         while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
570                 udelay(1000);
571                 show_state(i2c);
572         }
573
574         if (timeout <= 0) {
575                 show_state(i2c);
576                 dev_err(&i2c->adap.dev,
577                         "i2c_pxa: timeout waiting for bus free\n");
578                 return I2C_RETRY;
579         }
580
581         /*
582          * Set master mode.
583          */
584         writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
585
586         return 0;
587 }
588
589 static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
590                                struct i2c_msg *msg, int num)
591 {
592         unsigned long timeout = 500000; /* 5 seconds */
593         int ret = 0;
594
595         ret = i2c_pxa_pio_set_master(i2c);
596         if (ret)
597                 goto out;
598
599         i2c->msg = msg;
600         i2c->msg_num = num;
601         i2c->msg_idx = 0;
602         i2c->msg_ptr = 0;
603         i2c->irqlogidx = 0;
604
605         i2c_pxa_start_message(i2c);
606
607         while (timeout-- && i2c->msg_num > 0) {
608                 i2c_pxa_handler(0, i2c);
609                 udelay(10);
610         }
611
612         i2c_pxa_stop_message(i2c);
613
614         /*
615          * We place the return code in i2c->msg_idx.
616          */
617         ret = i2c->msg_idx;
618
619 out:
620         if (timeout == 0)
621                 i2c_pxa_scream_blue_murder(i2c, "timeout");
622
623         return ret;
624 }
625
626 /*
627  * We are protected by the adapter bus mutex.
628  */
629 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
630 {
631         long timeout;
632         int ret;
633
634         /*
635          * Wait for the bus to become free.
636          */
637         ret = i2c_pxa_wait_bus_not_busy(i2c);
638         if (ret) {
639                 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
640                 goto out;
641         }
642
643         /*
644          * Set master mode.
645          */
646         ret = i2c_pxa_set_master(i2c);
647         if (ret) {
648                 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
649                 goto out;
650         }
651
652         spin_lock_irq(&i2c->lock);
653
654         i2c->msg = msg;
655         i2c->msg_num = num;
656         i2c->msg_idx = 0;
657         i2c->msg_ptr = 0;
658         i2c->irqlogidx = 0;
659
660         i2c_pxa_start_message(i2c);
661
662         spin_unlock_irq(&i2c->lock);
663
664         /*
665          * The rest of the processing occurs in the interrupt handler.
666          */
667         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
668         i2c_pxa_stop_message(i2c);
669
670         /*
671          * We place the return code in i2c->msg_idx.
672          */
673         ret = i2c->msg_idx;
674
675         if (timeout == 0)
676                 i2c_pxa_scream_blue_murder(i2c, "timeout");
677
678  out:
679         return ret;
680 }
681
682 static int i2c_pxa_pio_xfer(struct i2c_adapter *adap,
683                             struct i2c_msg msgs[], int num)
684 {
685         struct pxa_i2c *i2c = adap->algo_data;
686         int ret, i;
687
688         /* If the I2C controller is disabled we need to reset it
689           (probably due to a suspend/resume destroying state). We do
690           this here as we can then avoid worrying about resuming the
691           controller before its users. */
692         if (!(readl(_ICR(i2c)) & ICR_IUE))
693                 i2c_pxa_reset(i2c);
694
695         for (i = adap->retries; i >= 0; i--) {
696                 ret = i2c_pxa_do_pio_xfer(i2c, msgs, num);
697                 if (ret != I2C_RETRY)
698                         goto out;
699
700                 if (i2c_debug)
701                         dev_dbg(&adap->dev, "Retrying transmission\n");
702                 udelay(100);
703         }
704         i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
705         ret = -EREMOTEIO;
706  out:
707         i2c_pxa_set_slave(i2c, ret);
708         return ret;
709 }
710
711 /*
712  * i2c_pxa_master_complete - complete the message and wake up.
713  */
714 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
715 {
716         i2c->msg_ptr = 0;
717         i2c->msg = NULL;
718         i2c->msg_idx ++;
719         i2c->msg_num = 0;
720         if (ret)
721                 i2c->msg_idx = ret;
722         if (!i2c->use_pio)
723                 wake_up(&i2c->wait);
724 }
725
726 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
727 {
728         u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
729
730  again:
731         /*
732          * If ISR_ALD is set, we lost arbitration.
733          */
734         if (isr & ISR_ALD) {
735                 /*
736                  * Do we need to do anything here?  The PXA docs
737                  * are vague about what happens.
738                  */
739                 i2c_pxa_scream_blue_murder(i2c, "ALD set");
740
741                 /*
742                  * We ignore this error.  We seem to see spurious ALDs
743                  * for seemingly no reason.  If we handle them as I think
744                  * they should, we end up causing an I2C error, which
745                  * is painful for some systems.
746                  */
747                 return; /* ignore */
748         }
749
750         if (isr & ISR_BED) {
751                 int ret = BUS_ERROR;
752
753                 /*
754                  * I2C bus error - either the device NAK'd us, or
755                  * something more serious happened.  If we were NAK'd
756                  * on the initial address phase, we can retry.
757                  */
758                 if (isr & ISR_ACKNAK) {
759                         if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
760                                 ret = I2C_RETRY;
761                         else
762                                 ret = XFER_NAKED;
763                 }
764                 i2c_pxa_master_complete(i2c, ret);
765         } else if (isr & ISR_RWM) {
766                 /*
767                  * Read mode.  We have just sent the address byte, and
768                  * now we must initiate the transfer.
769                  */
770                 if (i2c->msg_ptr == i2c->msg->len - 1 &&
771                     i2c->msg_idx == i2c->msg_num - 1)
772                         icr |= ICR_STOP | ICR_ACKNAK;
773
774                 icr |= ICR_ALDIE | ICR_TB;
775         } else if (i2c->msg_ptr < i2c->msg->len) {
776                 /*
777                  * Write mode.  Write the next data byte.
778                  */
779                 writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));
780
781                 icr |= ICR_ALDIE | ICR_TB;
782
783                 /*
784                  * If this is the last byte of the last message, send
785                  * a STOP.
786                  */
787                 if (i2c->msg_ptr == i2c->msg->len &&
788                     i2c->msg_idx == i2c->msg_num - 1)
789                         icr |= ICR_STOP;
790         } else if (i2c->msg_idx < i2c->msg_num - 1) {
791                 /*
792                  * Next segment of the message.
793                  */
794                 i2c->msg_ptr = 0;
795                 i2c->msg_idx ++;
796                 i2c->msg++;
797
798                 /*
799                  * If we aren't doing a repeated start and address,
800                  * go back and try to send the next byte.  Note that
801                  * we do not support switching the R/W direction here.
802                  */
803                 if (i2c->msg->flags & I2C_M_NOSTART)
804                         goto again;
805
806                 /*
807                  * Write the next address.
808                  */
809                 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
810
811                 /*
812                  * And trigger a repeated start, and send the byte.
813                  */
814                 icr &= ~ICR_ALDIE;
815                 icr |= ICR_START | ICR_TB;
816         } else {
817                 if (i2c->msg->len == 0) {
818                         /*
819                          * Device probes have a message length of zero
820                          * and need the bus to be reset before it can
821                          * be used again.
822                          */
823                         i2c_pxa_reset(i2c);
824                 }
825                 i2c_pxa_master_complete(i2c, 0);
826         }
827
828         i2c->icrlog[i2c->irqlogidx-1] = icr;
829
830         writel(icr, _ICR(i2c));
831         show_state(i2c);
832 }
833
834 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
835 {
836         u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
837
838         /*
839          * Read the byte.
840          */
841         i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c));
842
843         if (i2c->msg_ptr < i2c->msg->len) {
844                 /*
845                  * If this is the last byte of the last
846                  * message, send a STOP.
847                  */
848                 if (i2c->msg_ptr == i2c->msg->len - 1)
849                         icr |= ICR_STOP | ICR_ACKNAK;
850
851                 icr |= ICR_ALDIE | ICR_TB;
852         } else {
853                 i2c_pxa_master_complete(i2c, 0);
854         }
855
856         i2c->icrlog[i2c->irqlogidx-1] = icr;
857
858         writel(icr, _ICR(i2c));
859 }
860
861 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
862 {
863         struct pxa_i2c *i2c = dev_id;
864         u32 isr = readl(_ISR(i2c));
865
866         if (i2c_debug > 2 && 0) {
867                 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
868                         __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));
869                 decode_ISR(isr);
870         }
871
872         if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
873                 i2c->isrlog[i2c->irqlogidx++] = isr;
874
875         show_state(i2c);
876
877         /*
878          * Always clear all pending IRQs.
879          */
880         writel(isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED), _ISR(i2c));
881
882         if (isr & ISR_SAD)
883                 i2c_pxa_slave_start(i2c, isr);
884         if (isr & ISR_SSD)
885                 i2c_pxa_slave_stop(i2c);
886
887         if (i2c_pxa_is_slavemode(i2c)) {
888                 if (isr & ISR_ITE)
889                         i2c_pxa_slave_txempty(i2c, isr);
890                 if (isr & ISR_IRF)
891                         i2c_pxa_slave_rxfull(i2c, isr);
892         } else if (i2c->msg) {
893                 if (isr & ISR_ITE)
894                         i2c_pxa_irq_txempty(i2c, isr);
895                 if (isr & ISR_IRF)
896                         i2c_pxa_irq_rxfull(i2c, isr);
897         } else {
898                 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
899         }
900
901         return IRQ_HANDLED;
902 }
903
904
905 static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
906 {
907         struct pxa_i2c *i2c = adap->algo_data;
908         int ret, i;
909
910         /* If the I2C controller is disabled we need to reset it (probably due
911            to a suspend/resume destroying state). We do this here as we can then
912            avoid worrying about resuming the controller before its users. */
913         if (!(readl(_ICR(i2c)) & ICR_IUE))
914                 i2c_pxa_reset(i2c);
915
916         for (i = adap->retries; i >= 0; i--) {
917                 ret = i2c_pxa_do_xfer(i2c, msgs, num);
918                 if (ret != I2C_RETRY)
919                         goto out;
920
921                 if (i2c_debug)
922                         dev_dbg(&adap->dev, "Retrying transmission\n");
923                 udelay(100);
924         }
925         i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
926         ret = -EREMOTEIO;
927  out:
928         i2c_pxa_set_slave(i2c, ret);
929         return ret;
930 }
931
932 static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
933 {
934         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
935 }
936
937 static const struct i2c_algorithm i2c_pxa_algorithm = {
938         .master_xfer    = i2c_pxa_xfer,
939         .functionality  = i2c_pxa_functionality,
940 };
941
942 static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
943         .master_xfer    = i2c_pxa_pio_xfer,
944         .functionality  = i2c_pxa_functionality,
945 };
946
947 static void i2c_pxa_enable(struct platform_device *dev)
948 {
949         if (cpu_is_pxa27x()) {
950                 switch (dev->id) {
951                 case 0:
952                         pxa_gpio_mode(GPIO117_I2CSCL_MD);
953                         pxa_gpio_mode(GPIO118_I2CSDA_MD);
954                         break;
955                 case 1:
956                         local_irq_disable();
957                         PCFR |= PCFR_PI2CEN;
958                         local_irq_enable();
959                         break;
960                 }
961         }
962 }
963
964 static void i2c_pxa_disable(struct platform_device *dev)
965 {
966         if (cpu_is_pxa27x() && dev->id == 1) {
967                 local_irq_disable();
968                 PCFR &= ~PCFR_PI2CEN;
969                 local_irq_enable();
970         }
971 }
972
973 #define res_len(r)              ((r)->end - (r)->start + 1)
974 static int i2c_pxa_probe(struct platform_device *dev)
975 {
976         struct pxa_i2c *i2c;
977         struct resource *res;
978         struct i2c_pxa_platform_data *plat = dev->dev.platform_data;
979         int ret;
980         int irq;
981
982         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
983         irq = platform_get_irq(dev, 0);
984         if (res == NULL || irq < 0)
985                 return -ENODEV;
986
987         if (!request_mem_region(res->start, res_len(res), res->name))
988                 return -ENOMEM;
989
990         i2c = kzalloc(sizeof(struct pxa_i2c), GFP_KERNEL);
991         if (!i2c) {
992                 ret = -ENOMEM;
993                 goto emalloc;
994         }
995
996         i2c->adap.owner   = THIS_MODULE;
997         i2c->adap.retries = 5;
998
999         spin_lock_init(&i2c->lock);
1000         init_waitqueue_head(&i2c->wait);
1001
1002         sprintf(i2c->adap.name, "pxa_i2c-i2c.%u", dev->id);
1003
1004         i2c->clk = clk_get(&dev->dev, "I2CCLK");
1005         if (IS_ERR(i2c->clk)) {
1006                 ret = PTR_ERR(i2c->clk);
1007                 goto eclk;
1008         }
1009
1010         i2c->reg_base = ioremap(res->start, res_len(res));
1011         if (!i2c->reg_base) {
1012                 ret = -EIO;
1013                 goto eremap;
1014         }
1015
1016         i2c->iobase = res->start;
1017         i2c->iosize = res_len(res);
1018
1019         i2c->irq = irq;
1020
1021         i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
1022
1023 #ifdef CONFIG_I2C_PXA_SLAVE
1024         if (plat) {
1025                 i2c->slave_addr = plat->slave_addr;
1026                 i2c->slave = plat->slave;
1027         }
1028 #endif
1029
1030         clk_enable(i2c->clk);
1031         i2c_pxa_enable(dev);
1032
1033         if (plat) {
1034                 i2c->adap.class = plat->class;
1035                 i2c->use_pio = plat->use_pio;
1036         }
1037
1038         if (i2c->use_pio) {
1039                 i2c->adap.algo = &i2c_pxa_pio_algorithm;
1040         } else {
1041                 i2c->adap.algo = &i2c_pxa_algorithm;
1042                 ret = request_irq(irq, i2c_pxa_handler, IRQF_DISABLED,
1043                                   i2c->adap.name, i2c);
1044                 if (ret)
1045                         goto ereqirq;
1046         }
1047
1048         i2c_pxa_reset(i2c);
1049
1050         i2c->adap.algo_data = i2c;
1051         i2c->adap.dev.parent = &dev->dev;
1052
1053         /*
1054          * If "dev->id" is negative we consider it as zero.
1055          * The reason to do so is to avoid sysfs names that only make
1056          * sense when there are multiple adapters.
1057          */
1058         i2c->adap.nr = dev->id != -1 ? dev->id : 0;
1059
1060         ret = i2c_add_numbered_adapter(&i2c->adap);
1061         if (ret < 0) {
1062                 printk(KERN_INFO "I2C: Failed to add bus\n");
1063                 goto eadapt;
1064         }
1065
1066         platform_set_drvdata(dev, i2c);
1067
1068 #ifdef CONFIG_I2C_PXA_SLAVE
1069         printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n",
1070                i2c->adap.dev.bus_id, i2c->slave_addr);
1071 #else
1072         printk(KERN_INFO "I2C: %s: PXA I2C adapter\n",
1073                i2c->adap.dev.bus_id);
1074 #endif
1075         return 0;
1076
1077 eadapt:
1078         if (!i2c->use_pio)
1079                 free_irq(irq, i2c);
1080 ereqirq:
1081         clk_disable(i2c->clk);
1082         i2c_pxa_disable(dev);
1083 eremap:
1084         clk_put(i2c->clk);
1085 eclk:
1086         kfree(i2c);
1087 emalloc:
1088         release_mem_region(res->start, res_len(res));
1089         return ret;
1090 }
1091
1092 static int i2c_pxa_remove(struct platform_device *dev)
1093 {
1094         struct pxa_i2c *i2c = platform_get_drvdata(dev);
1095
1096         platform_set_drvdata(dev, NULL);
1097
1098         i2c_del_adapter(&i2c->adap);
1099         if (!i2c->use_pio)
1100                 free_irq(i2c->irq, i2c);
1101
1102         clk_disable(i2c->clk);
1103         clk_put(i2c->clk);
1104         i2c_pxa_disable(dev);
1105
1106         release_mem_region(i2c->iobase, i2c->iosize);
1107         kfree(i2c);
1108
1109         return 0;
1110 }
1111
1112 static struct platform_driver i2c_pxa_driver = {
1113         .probe          = i2c_pxa_probe,
1114         .remove         = i2c_pxa_remove,
1115         .driver         = {
1116                 .name   = "pxa2xx-i2c",
1117         },
1118 };
1119
1120 static int __init i2c_adap_pxa_init(void)
1121 {
1122         return platform_driver_register(&i2c_pxa_driver);
1123 }
1124
1125 static void i2c_adap_pxa_exit(void)
1126 {
1127         platform_driver_unregister(&i2c_pxa_driver);
1128 }
1129
1130 MODULE_LICENSE("GPL");
1131
1132 module_init(i2c_adap_pxa_init);
1133 module_exit(i2c_adap_pxa_exit);