git.oblomov.eu Git - linux-2.6/blob - drivers/scsi/advansys.c

   1 #define DRV_NAME "advansys"
   2 #define ASC_VERSION "3.4"       /* AdvanSys Driver Version */
   3
   4 /*
   5  * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
   6  *
   7  * Copyright (c) 1995-2000 Advanced System Products, Inc.
   8  * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
   9  * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
  10  * All Rights Reserved.
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  */
  17
  18 /*
  19  * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
  20  * changed its name to ConnectCom Solutions, Inc.
  21  * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/string.h>
  26 #include <linux/kernel.h>
  27 #include <linux/types.h>
  28 #include <linux/ioport.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/delay.h>
  31 #include <linux/slab.h>
  32 #include <linux/mm.h>
  33 #include <linux/proc_fs.h>
  34 #include <linux/init.h>
  35 #include <linux/blkdev.h>
  36 #include <linux/isa.h>
  37 #include <linux/eisa.h>
  38 #include <linux/pci.h>
  39 #include <linux/spinlock.h>
  40 #include <linux/dma-mapping.h>
  41
  42 #include <asm/io.h>
  43 #include <asm/system.h>
  44 #include <asm/dma.h>
  45
  46 #include <scsi/scsi_cmnd.h>
  47 #include <scsi/scsi_device.h>
  48 #include <scsi/scsi_tcq.h>
  49 #include <scsi/scsi.h>
  50 #include <scsi/scsi_host.h>
  51
  52 /* FIXME:
  53  *
  54  *  1. Although all of the necessary command mapping places have the
  55  *     appropriate dma_map.. APIs, the driver still processes its internal
  56  *     queue using bus_to_virt() and virt_to_bus() which are illegal under
  57  *     the API.  The entire queue processing structure will need to be
  58  *     altered to fix this.
  59  *  2. Need to add memory mapping workaround. Test the memory mapping.
  60  *     If it doesn't work revert to I/O port access. Can a test be done
  61  *     safely?
  62  *  3. Handle an interrupt not working. Keep an interrupt counter in
  63  *     the interrupt handler. In the timeout function if the interrupt
  64  *     has not occurred then print a message and run in polled mode.
  65  *  4. Need to add support for target mode commands, cf. CAM XPT.
  66  *  5. check DMA mapping functions for failure
  67  *  6. Use scsi_transport_spi
  68  *  7. advansys_info is not safe against multiple simultaneous callers
  69  *  8. Add module_param to override ISA/VLB ioport array
  70  */
  71 #warning this driver is still not properly converted to the DMA API
  72
  73 /* Enable driver /proc statistics. */
  74 #define ADVANSYS_STATS
  75
  76 /* Enable driver tracing. */
  77 #undef ADVANSYS_DEBUG
  78
  79 /*
  80  * Portable Data Types
  81  *
  82  * Any instance where a 32-bit long or pointer type is assumed
  83  * for precision or HW defined structures, the following define
  84  * types must be used. In Linux the char, short, and int types
  85  * are all consistent at 8, 16, and 32 bits respectively. Pointers
  86  * and long types are 64 bits on Alpha and UltraSPARC.
  87  */
  88 #define ASC_PADDR __u32         /* Physical/Bus address data type. */
  89 #define ASC_VADDR __u32         /* Virtual address data type. */
  90 #define ASC_DCNT  __u32         /* Unsigned Data count type. */
  91 #define ASC_SDCNT __s32         /* Signed Data count type. */
  92
  93 typedef unsigned char uchar;
  94
  95 #ifndef TRUE
  96 #define TRUE     (1)
  97 #endif
  98 #ifndef FALSE
  99 #define FALSE    (0)
 100 #endif
 101
 102 #define ERR      (-1)
 103 #define UW_ERR   (uint)(0xFFFF)
 104 #define isodd_word(val)   ((((uint)val) & (uint)0x0001) != 0)
 105
 106 #define PCI_VENDOR_ID_ASP               0x10cd
 107 #define PCI_DEVICE_ID_ASP_1200A         0x1100
 108 #define PCI_DEVICE_ID_ASP_ABP940        0x1200
 109 #define PCI_DEVICE_ID_ASP_ABP940U       0x1300
 110 #define PCI_DEVICE_ID_ASP_ABP940UW      0x2300
 111 #define PCI_DEVICE_ID_38C0800_REV1      0x2500
 112 #define PCI_DEVICE_ID_38C1600_REV1      0x2700
 113
 114 /*
 115  * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists.
 116  * The SRB structure will have to be changed and the ASC_SRB2SCSIQ()
 117  * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the
 118  * SRB structure.
 119  */
 120 #define CC_VERY_LONG_SG_LIST 0
 121 #define ASC_SRB2SCSIQ(srb_ptr)  (srb_ptr)
 122
 123 #define PortAddr                 unsigned short /* port address size  */
 124 #define inp(port)                inb(port)
 125 #define outp(port, byte)         outb((byte), (port))
 126
 127 #define inpw(port)               inw(port)
 128 #define outpw(port, word)        outw((word), (port))
 129
 130 #define ASC_MAX_SG_QUEUE    7
 131 #define ASC_MAX_SG_LIST     255
 132
 133 #define ASC_CS_TYPE  unsigned short
 134
 135 #define ASC_IS_ISA          (0x0001)
 136 #define ASC_IS_ISAPNP       (0x0081)
 137 #define ASC_IS_EISA         (0x0002)
 138 #define ASC_IS_PCI          (0x0004)
 139 #define ASC_IS_PCI_ULTRA    (0x0104)
 140 #define ASC_IS_PCMCIA       (0x0008)
 141 #define ASC_IS_MCA          (0x0020)
 142 #define ASC_IS_VL           (0x0040)
 143 #define ASC_IS_WIDESCSI_16  (0x0100)
 144 #define ASC_IS_WIDESCSI_32  (0x0200)
 145 #define ASC_IS_BIG_ENDIAN   (0x8000)
 146
 147 #define ASC_CHIP_MIN_VER_VL      (0x01)
 148 #define ASC_CHIP_MAX_VER_VL      (0x07)
 149 #define ASC_CHIP_MIN_VER_PCI     (0x09)
 150 #define ASC_CHIP_MAX_VER_PCI     (0x0F)
 151 #define ASC_CHIP_VER_PCI_BIT     (0x08)
 152 #define ASC_CHIP_MIN_VER_ISA     (0x11)
 153 #define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
 154 #define ASC_CHIP_MAX_VER_ISA     (0x27)
 155 #define ASC_CHIP_VER_ISA_BIT     (0x30)
 156 #define ASC_CHIP_VER_ISAPNP_BIT  (0x20)
 157 #define ASC_CHIP_VER_ASYN_BUG    (0x21)
 158 #define ASC_CHIP_VER_PCI             0x08
 159 #define ASC_CHIP_VER_PCI_ULTRA_3150  (ASC_CHIP_VER_PCI | 0x02)
 160 #define ASC_CHIP_VER_PCI_ULTRA_3050  (ASC_CHIP_VER_PCI | 0x03)
 161 #define ASC_CHIP_MIN_VER_EISA (0x41)
 162 #define ASC_CHIP_MAX_VER_EISA (0x47)
 163 #define ASC_CHIP_VER_EISA_BIT (0x40)
 164 #define ASC_CHIP_LATEST_VER_EISA   ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
 165 #define ASC_MAX_VL_DMA_COUNT    (0x07FFFFFFL)
 166 #define ASC_MAX_PCI_DMA_COUNT   (0xFFFFFFFFL)
 167 #define ASC_MAX_ISA_DMA_COUNT   (0x00FFFFFFL)
 168
 169 #define ASC_SCSI_ID_BITS  3
 170 #define ASC_SCSI_TIX_TYPE     uchar
 171 #define ASC_ALL_DEVICE_BIT_SET  0xFF
 172 #define ASC_SCSI_BIT_ID_TYPE  uchar
 173 #define ASC_MAX_TID       7
 174 #define ASC_MAX_LUN       7
 175 #define ASC_SCSI_WIDTH_BIT_SET  0xFF
 176 #define ASC_MAX_SENSE_LEN   32
 177 #define ASC_MIN_SENSE_LEN   14
 178 #define ASC_SCSI_RESET_HOLD_TIME_US  60
 179
 180 /*
 181  * Narrow boards only support 12-byte commands, while wide boards
 182  * extend to 16-byte commands.
 183  */
 184 #define ASC_MAX_CDB_LEN     12
 185 #define ADV_MAX_CDB_LEN     16
 186
 187 #define MS_SDTR_LEN    0x03
 188 #define MS_WDTR_LEN    0x02
 189
 190 #define ASC_SG_LIST_PER_Q   7
 191 #define QS_FREE        0x00
 192 #define QS_READY       0x01
 193 #define QS_DISC1       0x02
 194 #define QS_DISC2       0x04
 195 #define QS_BUSY        0x08
 196 #define QS_ABORTED     0x40
 197 #define QS_DONE        0x80
 198 #define QC_NO_CALLBACK   0x01
 199 #define QC_SG_SWAP_QUEUE 0x02
 200 #define QC_SG_HEAD       0x04
 201 #define QC_DATA_IN       0x08
 202 #define QC_DATA_OUT      0x10
 203 #define QC_URGENT        0x20
 204 #define QC_MSG_OUT       0x40
 205 #define QC_REQ_SENSE     0x80
 206 #define QCSG_SG_XFER_LIST  0x02
 207 #define QCSG_SG_XFER_MORE  0x04
 208 #define QCSG_SG_XFER_END   0x08
 209 #define QD_IN_PROGRESS       0x00
 210 #define QD_NO_ERROR          0x01
 211 #define QD_ABORTED_BY_HOST   0x02
 212 #define QD_WITH_ERROR        0x04
 213 #define QD_INVALID_REQUEST   0x80
 214 #define QD_INVALID_HOST_NUM  0x81
 215 #define QD_INVALID_DEVICE    0x82
 216 #define QD_ERR_INTERNAL      0xFF
 217 #define QHSTA_NO_ERROR               0x00
 218 #define QHSTA_M_SEL_TIMEOUT          0x11
 219 #define QHSTA_M_DATA_OVER_RUN        0x12
 220 #define QHSTA_M_DATA_UNDER_RUN       0x12
 221 #define QHSTA_M_UNEXPECTED_BUS_FREE  0x13
 222 #define QHSTA_M_BAD_BUS_PHASE_SEQ    0x14
 223 #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
 224 #define QHSTA_D_ASC_DVC_ERROR_CODE_SET  0x22
 225 #define QHSTA_D_HOST_ABORT_FAILED       0x23
 226 #define QHSTA_D_EXE_SCSI_Q_FAILED       0x24
 227 #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
 228 #define QHSTA_D_ASPI_NO_BUF_POOL        0x26
 229 #define QHSTA_M_WTM_TIMEOUT         0x41
 230 #define QHSTA_M_BAD_CMPL_STATUS_IN  0x42
 231 #define QHSTA_M_NO_AUTO_REQ_SENSE   0x43
 232 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
 233 #define QHSTA_M_TARGET_STATUS_BUSY  0x45
 234 #define QHSTA_M_BAD_TAG_CODE        0x46
 235 #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY  0x47
 236 #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
 237 #define QHSTA_D_LRAM_CMP_ERROR        0x81
 238 #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
 239 #define ASC_FLAG_SCSIQ_REQ        0x01
 240 #define ASC_FLAG_BIOS_SCSIQ_REQ   0x02
 241 #define ASC_FLAG_BIOS_ASYNC_IO    0x04
 242 #define ASC_FLAG_SRB_LINEAR_ADDR  0x08
 243 #define ASC_FLAG_WIN16            0x10
 244 #define ASC_FLAG_WIN32            0x20
 245 #define ASC_FLAG_ISA_OVER_16MB    0x40
 246 #define ASC_FLAG_DOS_VM_CALLBACK  0x80
 247 #define ASC_TAG_FLAG_EXTRA_BYTES               0x10
 248 #define ASC_TAG_FLAG_DISABLE_DISCONNECT        0x04
 249 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX  0x08
 250 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
 251 #define ASC_SCSIQ_CPY_BEG              4
 252 #define ASC_SCSIQ_SGHD_CPY_BEG         2
 253 #define ASC_SCSIQ_B_FWD                0
 254 #define ASC_SCSIQ_B_BWD                1
 255 #define ASC_SCSIQ_B_STATUS             2
 256 #define ASC_SCSIQ_B_QNO                3
 257 #define ASC_SCSIQ_B_CNTL               4
 258 #define ASC_SCSIQ_B_SG_QUEUE_CNT       5
 259 #define ASC_SCSIQ_D_DATA_ADDR          8
 260 #define ASC_SCSIQ_D_DATA_CNT          12
 261 #define ASC_SCSIQ_B_SENSE_LEN         20
 262 #define ASC_SCSIQ_DONE_INFO_BEG       22
 263 #define ASC_SCSIQ_D_SRBPTR            22
 264 #define ASC_SCSIQ_B_TARGET_IX         26
 265 #define ASC_SCSIQ_B_CDB_LEN           28
 266 #define ASC_SCSIQ_B_TAG_CODE          29
 267 #define ASC_SCSIQ_W_VM_ID             30
 268 #define ASC_SCSIQ_DONE_STATUS         32
 269 #define ASC_SCSIQ_HOST_STATUS         33
 270 #define ASC_SCSIQ_SCSI_STATUS         34
 271 #define ASC_SCSIQ_CDB_BEG             36
 272 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
 273 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT  60
 274 #define ASC_SCSIQ_B_FIRST_SG_WK_QP    48
 275 #define ASC_SCSIQ_B_SG_WK_QP          49
 276 #define ASC_SCSIQ_B_SG_WK_IX          50
 277 #define ASC_SCSIQ_W_ALT_DC1           52
 278 #define ASC_SCSIQ_B_LIST_CNT          6
 279 #define ASC_SCSIQ_B_CUR_LIST_CNT      7
 280 #define ASC_SGQ_B_SG_CNTL             4
 281 #define ASC_SGQ_B_SG_HEAD_QP          5
 282 #define ASC_SGQ_B_SG_LIST_CNT         6
 283 #define ASC_SGQ_B_SG_CUR_LIST_CNT     7
 284 #define ASC_SGQ_LIST_BEG              8
 285 #define ASC_DEF_SCSI1_QNG    4
 286 #define ASC_MAX_SCSI1_QNG    4
 287 #define ASC_DEF_SCSI2_QNG    16
 288 #define ASC_MAX_SCSI2_QNG    32
 289 #define ASC_TAG_CODE_MASK    0x23
 290 #define ASC_STOP_REQ_RISC_STOP      0x01
 291 #define ASC_STOP_ACK_RISC_STOP      0x03
 292 #define ASC_STOP_CLEAN_UP_BUSY_Q    0x10
 293 #define ASC_STOP_CLEAN_UP_DISC_Q    0x20
 294 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40
 295 #define ASC_TIDLUN_TO_IX(tid, lun)  (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
 296 #define ASC_TID_TO_TARGET_ID(tid)   (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
 297 #define ASC_TIX_TO_TARGET_ID(tix)   (0x01 << ((tix) & ASC_MAX_TID))
 298 #define ASC_TIX_TO_TID(tix)         ((tix) & ASC_MAX_TID)
 299 #define ASC_TID_TO_TIX(tid)         ((tid) & ASC_MAX_TID)
 300 #define ASC_TIX_TO_LUN(tix)         (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
 301 #define ASC_QNO_TO_QADDR(q_no)      ((ASC_QADR_BEG)+((int)(q_no) << 6))
 302
 303 typedef struct asc_scsiq_1 {
 304         uchar status;
 305         uchar q_no;
 306         uchar cntl;
 307         uchar sg_queue_cnt;
 308         uchar target_id;
 309         uchar target_lun;
 310         ASC_PADDR data_addr;
 311         ASC_DCNT data_cnt;
 312         ASC_PADDR sense_addr;
 313         uchar sense_len;
 314         uchar extra_bytes;
 315 } ASC_SCSIQ_1;
 316
 317 typedef struct asc_scsiq_2 {
 318         ASC_VADDR srb_ptr;
 319         uchar target_ix;
 320         uchar flag;
 321         uchar cdb_len;
 322         uchar tag_code;
 323         ushort vm_id;
 324 } ASC_SCSIQ_2;
 325
 326 typedef struct asc_scsiq_3 {
 327         uchar done_stat;
 328         uchar host_stat;
 329         uchar scsi_stat;
 330         uchar scsi_msg;
 331 } ASC_SCSIQ_3;
 332
 333 typedef struct asc_scsiq_4 {
 334         uchar cdb[ASC_MAX_CDB_LEN];
 335         uchar y_first_sg_list_qp;
 336         uchar y_working_sg_qp;
 337         uchar y_working_sg_ix;
 338         uchar y_res;
 339         ushort x_req_count;
 340         ushort x_reconnect_rtn;
 341         ASC_PADDR x_saved_data_addr;
 342         ASC_DCNT x_saved_data_cnt;
 343 } ASC_SCSIQ_4;
 344
 345 typedef struct asc_q_done_info {
 346         ASC_SCSIQ_2 d2;
 347         ASC_SCSIQ_3 d3;
 348         uchar q_status;
 349         uchar q_no;
 350         uchar cntl;
 351         uchar sense_len;
 352         uchar extra_bytes;
 353         uchar res;
 354         ASC_DCNT remain_bytes;
 355 } ASC_QDONE_INFO;
 356
 357 typedef struct asc_sg_list {
 358         ASC_PADDR addr;
 359         ASC_DCNT bytes;
 360 } ASC_SG_LIST;
 361
 362 typedef struct asc_sg_head {
 363         ushort entry_cnt;
 364         ushort queue_cnt;
 365         ushort entry_to_copy;
 366         ushort res;
 367         ASC_SG_LIST sg_list[0];
 368 } ASC_SG_HEAD;
 369
 370 typedef struct asc_scsi_q {
 371         ASC_SCSIQ_1 q1;
 372         ASC_SCSIQ_2 q2;
 373         uchar *cdbptr;
 374         ASC_SG_HEAD *sg_head;
 375         ushort remain_sg_entry_cnt;
 376         ushort next_sg_index;
 377 } ASC_SCSI_Q;
 378
 379 typedef struct asc_scsi_req_q {
 380         ASC_SCSIQ_1 r1;
 381         ASC_SCSIQ_2 r2;
 382         uchar *cdbptr;
 383         ASC_SG_HEAD *sg_head;
 384         uchar *sense_ptr;
 385         ASC_SCSIQ_3 r3;
 386         uchar cdb[ASC_MAX_CDB_LEN];
 387         uchar sense[ASC_MIN_SENSE_LEN];
 388 } ASC_SCSI_REQ_Q;
 389
 390 typedef struct asc_scsi_bios_req_q {
 391         ASC_SCSIQ_1 r1;
 392         ASC_SCSIQ_2 r2;
 393         uchar *cdbptr;
 394         ASC_SG_HEAD *sg_head;
 395         uchar *sense_ptr;
 396         ASC_SCSIQ_3 r3;
 397         uchar cdb[ASC_MAX_CDB_LEN];
 398         uchar sense[ASC_MIN_SENSE_LEN];
 399 } ASC_SCSI_BIOS_REQ_Q;
 400
 401 typedef struct asc_risc_q {
 402         uchar fwd;
 403         uchar bwd;
 404         ASC_SCSIQ_1 i1;
 405         ASC_SCSIQ_2 i2;
 406         ASC_SCSIQ_3 i3;
 407         ASC_SCSIQ_4 i4;
 408 } ASC_RISC_Q;
 409
 410 typedef struct asc_sg_list_q {
 411         uchar seq_no;
 412         uchar q_no;
 413         uchar cntl;
 414         uchar sg_head_qp;
 415         uchar sg_list_cnt;
 416         uchar sg_cur_list_cnt;
 417 } ASC_SG_LIST_Q;
 418
 419 typedef struct asc_risc_sg_list_q {
 420         uchar fwd;
 421         uchar bwd;
 422         ASC_SG_LIST_Q sg;
 423         ASC_SG_LIST sg_list[7];
 424 } ASC_RISC_SG_LIST_Q;
 425
 426 #define ASCQ_ERR_Q_STATUS             0x0D
 427 #define ASCQ_ERR_CUR_QNG              0x17
 428 #define ASCQ_ERR_SG_Q_LINKS           0x18
 429 #define ASCQ_ERR_ISR_RE_ENTRY         0x1A
 430 #define ASCQ_ERR_CRITICAL_RE_ENTRY    0x1B
 431 #define ASCQ_ERR_ISR_ON_CRITICAL      0x1C
 432
 433 /*
 434  * Warning code values are set in ASC_DVC_VAR  'warn_code'.
 435  */
 436 #define ASC_WARN_NO_ERROR             0x0000
 437 #define ASC_WARN_IO_PORT_ROTATE       0x0001
 438 #define ASC_WARN_EEPROM_CHKSUM        0x0002
 439 #define ASC_WARN_IRQ_MODIFIED         0x0004
 440 #define ASC_WARN_AUTO_CONFIG          0x0008
 441 #define ASC_WARN_CMD_QNG_CONFLICT     0x0010
 442 #define ASC_WARN_EEPROM_RECOVER       0x0020
 443 #define ASC_WARN_CFG_MSW_RECOVER      0x0040
 444
 445 /*
 446  * Error code values are set in {ASC/ADV}_DVC_VAR  'err_code'.
 447  */
 448 #define ASC_IERR_NO_CARRIER             0x0001  /* No more carrier memory */
 449 #define ASC_IERR_MCODE_CHKSUM           0x0002  /* micro code check sum error */
 450 #define ASC_IERR_SET_PC_ADDR            0x0004
 451 #define ASC_IERR_START_STOP_CHIP        0x0008  /* start/stop chip failed */
 452 #define ASC_IERR_ILLEGAL_CONNECTION     0x0010  /* Illegal cable connection */
 453 #define ASC_IERR_SINGLE_END_DEVICE      0x0020  /* SE device on DIFF bus */
 454 #define ASC_IERR_REVERSED_CABLE         0x0040  /* Narrow flat cable reversed */
 455 #define ASC_IERR_SET_SCSI_ID            0x0080  /* set SCSI ID failed */
 456 #define ASC_IERR_HVD_DEVICE             0x0100  /* HVD device on LVD port */
 457 #define ASC_IERR_BAD_SIGNATURE          0x0200  /* signature not found */
 458 #define ASC_IERR_NO_BUS_TYPE            0x0400
 459 #define ASC_IERR_BIST_PRE_TEST          0x0800  /* BIST pre-test error */
 460 #define ASC_IERR_BIST_RAM_TEST          0x1000  /* BIST RAM test error */
 461 #define ASC_IERR_BAD_CHIPTYPE           0x2000  /* Invalid chip_type setting */
 462
 463 #define ASC_DEF_MAX_TOTAL_QNG   (0xF0)
 464 #define ASC_MIN_TAG_Q_PER_DVC   (0x04)
 465 #define ASC_MIN_FREE_Q        (0x02)
 466 #define ASC_MIN_TOTAL_QNG     ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
 467 #define ASC_MAX_TOTAL_QNG 240
 468 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
 469 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG   8
 470 #define ASC_MAX_PCI_INRAM_TOTAL_QNG  20
 471 #define ASC_MAX_INRAM_TAG_QNG   16
 472 #define ASC_IOADR_GAP   0x10
 473 #define ASC_SYN_MAX_OFFSET         0x0F
 474 #define ASC_DEF_SDTR_OFFSET        0x0F
 475 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX  0x02
 476 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
 477
 478 /* The narrow chip only supports a limited selection of transfer rates.
 479  * These are encoded in the range 0..7 or 0..15 depending whether the chip
 480  * is Ultra-capable or not.  These tables let us convert from one to the other.
 481  */
 482 static const unsigned char asc_syn_xfer_period[8] = {
 483         25, 30, 35, 40, 50, 60, 70, 85
 484 };
 485
 486 static const unsigned char asc_syn_ultra_xfer_period[16] = {
 487         12, 19, 25, 32, 38, 44, 50, 57, 63, 69, 75, 82, 88, 94, 100, 107
 488 };
 489
 490 typedef struct ext_msg {
 491         uchar msg_type;
 492         uchar msg_len;
 493         uchar msg_req;
 494         union {
 495                 struct {
 496                         uchar sdtr_xfer_period;
 497                         uchar sdtr_req_ack_offset;
 498                 } sdtr;
 499                 struct {
 500                         uchar wdtr_width;
 501                 } wdtr;
 502                 struct {
 503                         uchar mdp_b3;
 504                         uchar mdp_b2;
 505                         uchar mdp_b1;
 506                         uchar mdp_b0;
 507                 } mdp;
 508         } u_ext_msg;
 509         uchar res;
 510 } EXT_MSG;
 511
 512 #define xfer_period     u_ext_msg.sdtr.sdtr_xfer_period
 513 #define req_ack_offset  u_ext_msg.sdtr.sdtr_req_ack_offset
 514 #define wdtr_width      u_ext_msg.wdtr.wdtr_width
 515 #define mdp_b3          u_ext_msg.mdp_b3
 516 #define mdp_b2          u_ext_msg.mdp_b2
 517 #define mdp_b1          u_ext_msg.mdp_b1
 518 #define mdp_b0          u_ext_msg.mdp_b0
 519
 520 typedef struct asc_dvc_cfg {
 521         ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
 522         ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
 523         ASC_SCSI_BIT_ID_TYPE disc_enable;
 524         ASC_SCSI_BIT_ID_TYPE sdtr_enable;
 525         uchar chip_scsi_id;
 526         uchar isa_dma_speed;
 527         uchar isa_dma_channel;
 528         uchar chip_version;
 529         ushort mcode_date;
 530         ushort mcode_version;
 531         uchar max_tag_qng[ASC_MAX_TID + 1];
 532         uchar *overrun_buf;
 533         uchar sdtr_period_offset[ASC_MAX_TID + 1];
 534         uchar adapter_info[6];
 535 } ASC_DVC_CFG;
 536
 537 #define ASC_DEF_DVC_CNTL       0xFFFF
 538 #define ASC_DEF_CHIP_SCSI_ID   7
 539 #define ASC_DEF_ISA_DMA_SPEED  4
 540 #define ASC_INIT_STATE_BEG_GET_CFG   0x0001
 541 #define ASC_INIT_STATE_END_GET_CFG   0x0002
 542 #define ASC_INIT_STATE_BEG_SET_CFG   0x0004
 543 #define ASC_INIT_STATE_END_SET_CFG   0x0008
 544 #define ASC_INIT_STATE_BEG_LOAD_MC   0x0010
 545 #define ASC_INIT_STATE_END_LOAD_MC   0x0020
 546 #define ASC_INIT_STATE_BEG_INQUIRY   0x0040
 547 #define ASC_INIT_STATE_END_INQUIRY   0x0080
 548 #define ASC_INIT_RESET_SCSI_DONE     0x0100
 549 #define ASC_INIT_STATE_WITHOUT_EEP   0x8000
 550 #define ASC_BUG_FIX_IF_NOT_DWB       0x0001
 551 #define ASC_BUG_FIX_ASYN_USE_SYN     0x0002
 552 #define ASC_MIN_TAGGED_CMD  7
 553 #define ASC_MAX_SCSI_RESET_WAIT      30
 554
 555 struct asc_dvc_var;             /* Forward Declaration. */
 556
 557 typedef struct asc_dvc_var {
 558         PortAddr iop_base;
 559         ushort err_code;
 560         ushort dvc_cntl;
 561         ushort bug_fix_cntl;
 562         ushort bus_type;
 563         ASC_SCSI_BIT_ID_TYPE init_sdtr;
 564         ASC_SCSI_BIT_ID_TYPE sdtr_done;
 565         ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
 566         ASC_SCSI_BIT_ID_TYPE unit_not_ready;
 567         ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
 568         ASC_SCSI_BIT_ID_TYPE start_motor;
 569         uchar scsi_reset_wait;
 570         uchar chip_no;
 571         char is_in_int;
 572         uchar max_total_qng;
 573         uchar cur_total_qng;
 574         uchar in_critical_cnt;
 575         uchar last_q_shortage;
 576         ushort init_state;
 577         uchar cur_dvc_qng[ASC_MAX_TID + 1];
 578         uchar max_dvc_qng[ASC_MAX_TID + 1];
 579         ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
 580         ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
 581         const uchar *sdtr_period_tbl;
 582         ASC_DVC_CFG *cfg;
 583         ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
 584         char redo_scam;
 585         ushort res2;
 586         uchar dos_int13_table[ASC_MAX_TID + 1];
 587         ASC_DCNT max_dma_count;
 588         ASC_SCSI_BIT_ID_TYPE no_scam;
 589         ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
 590         uchar min_sdtr_index;
 591         uchar max_sdtr_index;
 592         struct asc_board *drv_ptr;
 593         int ptr_map_count;
 594         void **ptr_map;
 595         ASC_DCNT uc_break;
 596 } ASC_DVC_VAR;
 597
 598 typedef struct asc_dvc_inq_info {
 599         uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
 600 } ASC_DVC_INQ_INFO;
 601
 602 typedef struct asc_cap_info {
 603         ASC_DCNT lba;
 604         ASC_DCNT blk_size;
 605 } ASC_CAP_INFO;
 606
 607 typedef struct asc_cap_info_array {
 608         ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
 609 } ASC_CAP_INFO_ARRAY;
 610
 611 #define ASC_MCNTL_NO_SEL_TIMEOUT  (ushort)0x0001
 612 #define ASC_MCNTL_NULL_TARGET     (ushort)0x0002
 613 #define ASC_CNTL_INITIATOR         (ushort)0x0001
 614 #define ASC_CNTL_BIOS_GT_1GB       (ushort)0x0002
 615 #define ASC_CNTL_BIOS_GT_2_DISK    (ushort)0x0004
 616 #define ASC_CNTL_BIOS_REMOVABLE    (ushort)0x0008
 617 #define ASC_CNTL_NO_SCAM           (ushort)0x0010
 618 #define ASC_CNTL_INT_MULTI_Q       (ushort)0x0080
 619 #define ASC_CNTL_NO_LUN_SUPPORT    (ushort)0x0040
 620 #define ASC_CNTL_NO_VERIFY_COPY    (ushort)0x0100
 621 #define ASC_CNTL_RESET_SCSI        (ushort)0x0200
 622 #define ASC_CNTL_INIT_INQUIRY      (ushort)0x0400
 623 #define ASC_CNTL_INIT_VERBOSE      (ushort)0x0800
 624 #define ASC_CNTL_SCSI_PARITY       (ushort)0x1000
 625 #define ASC_CNTL_BURST_MODE        (ushort)0x2000
 626 #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
 627 #define ASC_EEP_DVC_CFG_BEG_VL    2
 628 #define ASC_EEP_MAX_DVC_ADDR_VL   15
 629 #define ASC_EEP_DVC_CFG_BEG      32
 630 #define ASC_EEP_MAX_DVC_ADDR     45
 631 #define ASC_EEP_MAX_RETRY        20
 632
 633 /*
 634  * These macros keep the chip SCSI id and ISA DMA speed
 635  * bitfields in board order. C bitfields aren't portable
 636  * between big and little-endian platforms so they are
 637  * not used.
 638  */
 639
 640 #define ASC_EEP_GET_CHIP_ID(cfg)    ((cfg)->id_speed & 0x0f)
 641 #define ASC_EEP_GET_DMA_SPD(cfg)    (((cfg)->id_speed & 0xf0) >> 4)
 642 #define ASC_EEP_SET_CHIP_ID(cfg, sid) \
 643    ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
 644 #define ASC_EEP_SET_DMA_SPD(cfg, spd) \
 645    ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
 646
 647 typedef struct asceep_config {
 648         ushort cfg_lsw;
 649         ushort cfg_msw;
 650         uchar init_sdtr;
 651         uchar disc_enable;
 652         uchar use_cmd_qng;
 653         uchar start_motor;
 654         uchar max_total_qng;
 655         uchar max_tag_qng;
 656         uchar bios_scan;
 657         uchar power_up_wait;
 658         uchar no_scam;
 659         uchar id_speed;         /* low order 4 bits is chip scsi id */
 660         /* high order 4 bits is isa dma speed */
 661         uchar dos_int13_table[ASC_MAX_TID + 1];
 662         uchar adapter_info[6];
 663         ushort cntl;
 664         ushort chksum;
 665 } ASCEEP_CONFIG;
 666
 667 #define ASC_EEP_CMD_READ          0x80
 668 #define ASC_EEP_CMD_WRITE         0x40
 669 #define ASC_EEP_CMD_WRITE_ABLE    0x30
 670 #define ASC_EEP_CMD_WRITE_DISABLE 0x00
 671 #define ASC_OVERRUN_BSIZE  0x00000048UL
 672 #define ASCV_MSGOUT_BEG         0x0000
 673 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
 674 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
 675 #define ASCV_BREAK_SAVED_CODE   (ushort)0x0006
 676 #define ASCV_MSGIN_BEG          (ASCV_MSGOUT_BEG+8)
 677 #define ASCV_MSGIN_SDTR_PERIOD  (ASCV_MSGIN_BEG+3)
 678 #define ASCV_MSGIN_SDTR_OFFSET  (ASCV_MSGIN_BEG+4)
 679 #define ASCV_SDTR_DATA_BEG      (ASCV_MSGIN_BEG+8)
 680 #define ASCV_SDTR_DONE_BEG      (ASCV_SDTR_DATA_BEG+8)
 681 #define ASCV_MAX_DVC_QNG_BEG    (ushort)0x0020
 682 #define ASCV_BREAK_ADDR           (ushort)0x0028
 683 #define ASCV_BREAK_NOTIFY_COUNT   (ushort)0x002A
 684 #define ASCV_BREAK_CONTROL        (ushort)0x002C
 685 #define ASCV_BREAK_HIT_COUNT      (ushort)0x002E
 686
 687 #define ASCV_ASCDVC_ERR_CODE_W  (ushort)0x0030
 688 #define ASCV_MCODE_CHKSUM_W   (ushort)0x0032
 689 #define ASCV_MCODE_SIZE_W     (ushort)0x0034
 690 #define ASCV_STOP_CODE_B      (ushort)0x0036
 691 #define ASCV_DVC_ERR_CODE_B   (ushort)0x0037
 692 #define ASCV_OVERRUN_PADDR_D  (ushort)0x0038
 693 #define ASCV_OVERRUN_BSIZE_D  (ushort)0x003C
 694 #define ASCV_HALTCODE_W       (ushort)0x0040
 695 #define ASCV_CHKSUM_W         (ushort)0x0042
 696 #define ASCV_MC_DATE_W        (ushort)0x0044
 697 #define ASCV_MC_VER_W         (ushort)0x0046
 698 #define ASCV_NEXTRDY_B        (ushort)0x0048
 699 #define ASCV_DONENEXT_B       (ushort)0x0049
 700 #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
 701 #define ASCV_SCSIBUSY_B       (ushort)0x004B
 702 #define ASCV_Q_DONE_IN_PROGRESS_B  (ushort)0x004C
 703 #define ASCV_CURCDB_B         (ushort)0x004D
 704 #define ASCV_RCLUN_B          (ushort)0x004E
 705 #define ASCV_BUSY_QHEAD_B     (ushort)0x004F
 706 #define ASCV_DISC1_QHEAD_B    (ushort)0x0050
 707 #define ASCV_DISC_ENABLE_B    (ushort)0x0052
 708 #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
 709 #define ASCV_HOSTSCSI_ID_B    (ushort)0x0055
 710 #define ASCV_MCODE_CNTL_B     (ushort)0x0056
 711 #define ASCV_NULL_TARGET_B    (ushort)0x0057
 712 #define ASCV_FREE_Q_HEAD_W    (ushort)0x0058
 713 #define ASCV_DONE_Q_TAIL_W    (ushort)0x005A
 714 #define ASCV_FREE_Q_HEAD_B    (ushort)(ASCV_FREE_Q_HEAD_W+1)
 715 #define ASCV_DONE_Q_TAIL_B    (ushort)(ASCV_DONE_Q_TAIL_W+1)
 716 #define ASCV_HOST_FLAG_B      (ushort)0x005D
 717 #define ASCV_TOTAL_READY_Q_B  (ushort)0x0064
 718 #define ASCV_VER_SERIAL_B     (ushort)0x0065
 719 #define ASCV_HALTCODE_SAVED_W (ushort)0x0066
 720 #define ASCV_WTM_FLAG_B       (ushort)0x0068
 721 #define ASCV_RISC_FLAG_B      (ushort)0x006A
 722 #define ASCV_REQ_SG_LIST_QP   (ushort)0x006B
 723 #define ASC_HOST_FLAG_IN_ISR        0x01
 724 #define ASC_HOST_FLAG_ACK_INT       0x02
 725 #define ASC_RISC_FLAG_GEN_INT      0x01
 726 #define ASC_RISC_FLAG_REQ_SG_LIST  0x02
 727 #define IOP_CTRL         (0x0F)
 728 #define IOP_STATUS       (0x0E)
 729 #define IOP_INT_ACK      IOP_STATUS
 730 #define IOP_REG_IFC      (0x0D)
 731 #define IOP_SYN_OFFSET    (0x0B)
 732 #define IOP_EXTRA_CONTROL (0x0D)
 733 #define IOP_REG_PC        (0x0C)
 734 #define IOP_RAM_ADDR      (0x0A)
 735 #define IOP_RAM_DATA      (0x08)
 736 #define IOP_EEP_DATA      (0x06)
 737 #define IOP_EEP_CMD       (0x07)
 738 #define IOP_VERSION       (0x03)
 739 #define IOP_CONFIG_HIGH   (0x04)
 740 #define IOP_CONFIG_LOW    (0x02)
 741 #define IOP_SIG_BYTE      (0x01)
 742 #define IOP_SIG_WORD      (0x00)
 743 #define IOP_REG_DC1      (0x0E)
 744 #define IOP_REG_DC0      (0x0C)
 745 #define IOP_REG_SB       (0x0B)
 746 #define IOP_REG_DA1      (0x0A)
 747 #define IOP_REG_DA0      (0x08)
 748 #define IOP_REG_SC       (0x09)
 749 #define IOP_DMA_SPEED    (0x07)
 750 #define IOP_REG_FLAG     (0x07)
 751 #define IOP_FIFO_H       (0x06)
 752 #define IOP_FIFO_L       (0x04)
 753 #define IOP_REG_ID       (0x05)
 754 #define IOP_REG_QP       (0x03)
 755 #define IOP_REG_IH       (0x02)
 756 #define IOP_REG_IX       (0x01)
 757 #define IOP_REG_AX       (0x00)
 758 #define IFC_REG_LOCK      (0x00)
 759 #define IFC_REG_UNLOCK    (0x09)
 760 #define IFC_WR_EN_FILTER  (0x10)
 761 #define IFC_RD_NO_EEPROM  (0x10)
 762 #define IFC_SLEW_RATE     (0x20)
 763 #define IFC_ACT_NEG       (0x40)
 764 #define IFC_INP_FILTER    (0x80)
 765 #define IFC_INIT_DEFAULT  (IFC_ACT_NEG | IFC_REG_UNLOCK)
 766 #define SC_SEL   (uchar)(0x80)
 767 #define SC_BSY   (uchar)(0x40)
 768 #define SC_ACK   (uchar)(0x20)
 769 #define SC_REQ   (uchar)(0x10)
 770 #define SC_ATN   (uchar)(0x08)
 771 #define SC_IO    (uchar)(0x04)
 772 #define SC_CD    (uchar)(0x02)
 773 #define SC_MSG   (uchar)(0x01)
 774 #define SEC_SCSI_CTL         (uchar)(0x80)
 775 #define SEC_ACTIVE_NEGATE    (uchar)(0x40)
 776 #define SEC_SLEW_RATE        (uchar)(0x20)
 777 #define SEC_ENABLE_FILTER    (uchar)(0x10)
 778 #define ASC_HALT_EXTMSG_IN     (ushort)0x8000
 779 #define ASC_HALT_CHK_CONDITION (ushort)0x8100
 780 #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
 781 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX  (ushort)0x8300
 782 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX   (ushort)0x8400
 783 #define ASC_HALT_SDTR_REJECTED (ushort)0x4000
 784 #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
 785 #define ASC_MAX_QNO        0xF8
 786 #define ASC_DATA_SEC_BEG   (ushort)0x0080
 787 #define ASC_DATA_SEC_END   (ushort)0x0080
 788 #define ASC_CODE_SEC_BEG   (ushort)0x0080
 789 #define ASC_CODE_SEC_END   (ushort)0x0080
 790 #define ASC_QADR_BEG       (0x4000)
 791 #define ASC_QADR_USED      (ushort)(ASC_MAX_QNO * 64)
 792 #define ASC_QADR_END       (ushort)0x7FFF
 793 #define ASC_QLAST_ADR      (ushort)0x7FC0
 794 #define ASC_QBLK_SIZE      0x40
 795 #define ASC_BIOS_DATA_QBEG 0xF8
 796 #define ASC_MIN_ACTIVE_QNO 0x01
 797 #define ASC_QLINK_END      0xFF
 798 #define ASC_EEPROM_WORDS   0x10
 799 #define ASC_MAX_MGS_LEN    0x10
 800 #define ASC_BIOS_ADDR_DEF  0xDC00
 801 #define ASC_BIOS_SIZE      0x3800
 802 #define ASC_BIOS_RAM_OFF   0x3800
 803 #define ASC_BIOS_RAM_SIZE  0x800
 804 #define ASC_BIOS_MIN_ADDR  0xC000
 805 #define ASC_BIOS_MAX_ADDR  0xEC00
 806 #define ASC_BIOS_BANK_SIZE 0x0400
 807 #define ASC_MCODE_START_ADDR  0x0080
 808 #define ASC_CFG0_HOST_INT_ON    0x0020
 809 #define ASC_CFG0_BIOS_ON        0x0040
 810 #define ASC_CFG0_VERA_BURST_ON  0x0080
 811 #define ASC_CFG0_SCSI_PARITY_ON 0x0800
 812 #define ASC_CFG1_SCSI_TARGET_ON 0x0080
 813 #define ASC_CFG1_LRAM_8BITS_ON  0x0800
 814 #define ASC_CFG_MSW_CLR_MASK    0x3080
 815 #define CSW_TEST1             (ASC_CS_TYPE)0x8000
 816 #define CSW_AUTO_CONFIG       (ASC_CS_TYPE)0x4000
 817 #define CSW_RESERVED1         (ASC_CS_TYPE)0x2000
 818 #define CSW_IRQ_WRITTEN       (ASC_CS_TYPE)0x1000
 819 #define CSW_33MHZ_SELECTED    (ASC_CS_TYPE)0x0800
 820 #define CSW_TEST2             (ASC_CS_TYPE)0x0400
 821 #define CSW_TEST3             (ASC_CS_TYPE)0x0200
 822 #define CSW_RESERVED2         (ASC_CS_TYPE)0x0100
 823 #define CSW_DMA_DONE          (ASC_CS_TYPE)0x0080
 824 #define CSW_FIFO_RDY          (ASC_CS_TYPE)0x0040
 825 #define CSW_EEP_READ_DONE     (ASC_CS_TYPE)0x0020
 826 #define CSW_HALTED            (ASC_CS_TYPE)0x0010
 827 #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
 828 #define CSW_PARITY_ERR        (ASC_CS_TYPE)0x0004
 829 #define CSW_SCSI_RESET_LATCH  (ASC_CS_TYPE)0x0002
 830 #define CSW_INT_PENDING       (ASC_CS_TYPE)0x0001
 831 #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
 832 #define CIW_INT_ACK      (ASC_CS_TYPE)0x0100
 833 #define CIW_TEST1        (ASC_CS_TYPE)0x0200
 834 #define CIW_TEST2        (ASC_CS_TYPE)0x0400
 835 #define CIW_SEL_33MHZ    (ASC_CS_TYPE)0x0800
 836 #define CIW_IRQ_ACT      (ASC_CS_TYPE)0x1000
 837 #define CC_CHIP_RESET   (uchar)0x80
 838 #define CC_SCSI_RESET   (uchar)0x40
 839 #define CC_HALT         (uchar)0x20
 840 #define CC_SINGLE_STEP  (uchar)0x10
 841 #define CC_DMA_ABLE     (uchar)0x08
 842 #define CC_TEST         (uchar)0x04
 843 #define CC_BANK_ONE     (uchar)0x02
 844 #define CC_DIAG         (uchar)0x01
 845 #define ASC_1000_ID0W      0x04C1
 846 #define ASC_1000_ID0W_FIX  0x00C1
 847 #define ASC_1000_ID1B      0x25
 848 #define ASC_EISA_REV_IOP_MASK  (0x0C83)
 849 #define ASC_EISA_CFG_IOP_MASK  (0x0C86)
 850 #define ASC_GET_EISA_SLOT(iop)  (PortAddr)((iop) & 0xF000)
 851 #define INS_HALTINT        (ushort)0x6281
 852 #define INS_HALT           (ushort)0x6280
 853 #define INS_SINT           (ushort)0x6200
 854 #define INS_RFLAG_WTM      (ushort)0x7380
 855 #define ASC_MC_SAVE_CODE_WSIZE  0x500
 856 #define ASC_MC_SAVE_DATA_WSIZE  0x40
 857
 858 typedef struct asc_mc_saved {
 859         ushort data[ASC_MC_SAVE_DATA_WSIZE];
 860         ushort code[ASC_MC_SAVE_CODE_WSIZE];
 861 } ASC_MC_SAVED;
 862
 863 #define AscGetQDoneInProgress(port)         AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
 864 #define AscPutQDoneInProgress(port, val)    AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
 865 #define AscGetVarFreeQHead(port)            AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
 866 #define AscGetVarDoneQTail(port)            AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
 867 #define AscPutVarFreeQHead(port, val)       AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
 868 #define AscPutVarDoneQTail(port, val)       AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
 869 #define AscGetRiscVarFreeQHead(port)        AscReadLramByte((port), ASCV_NEXTRDY_B)
 870 #define AscGetRiscVarDoneQTail(port)        AscReadLramByte((port), ASCV_DONENEXT_B)
 871 #define AscPutRiscVarFreeQHead(port, val)   AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
 872 #define AscPutRiscVarDoneQTail(port, val)   AscWriteLramByte((port), ASCV_DONENEXT_B, val)
 873 #define AscPutMCodeSDTRDoneAtID(port, id, data)  AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
 874 #define AscGetMCodeSDTRDoneAtID(port, id)        AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
 875 #define AscPutMCodeInitSDTRAtID(port, id, data)  AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
 876 #define AscGetMCodeInitSDTRAtID(port, id)        AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
 877 #define AscGetChipSignatureByte(port)     (uchar)inp((port)+IOP_SIG_BYTE)
 878 #define AscGetChipSignatureWord(port)     (ushort)inpw((port)+IOP_SIG_WORD)
 879 #define AscGetChipVerNo(port)             (uchar)inp((port)+IOP_VERSION)
 880 #define AscGetChipCfgLsw(port)            (ushort)inpw((port)+IOP_CONFIG_LOW)
 881 #define AscGetChipCfgMsw(port)            (ushort)inpw((port)+IOP_CONFIG_HIGH)
 882 #define AscSetChipCfgLsw(port, data)      outpw((port)+IOP_CONFIG_LOW, data)
 883 #define AscSetChipCfgMsw(port, data)      outpw((port)+IOP_CONFIG_HIGH, data)
 884 #define AscGetChipEEPCmd(port)            (uchar)inp((port)+IOP_EEP_CMD)
 885 #define AscSetChipEEPCmd(port, data)      outp((port)+IOP_EEP_CMD, data)
 886 #define AscGetChipEEPData(port)           (ushort)inpw((port)+IOP_EEP_DATA)
 887 #define AscSetChipEEPData(port, data)     outpw((port)+IOP_EEP_DATA, data)
 888 #define AscGetChipLramAddr(port)          (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
 889 #define AscSetChipLramAddr(port, addr)    outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
 890 #define AscGetChipLramData(port)          (ushort)inpw((port)+IOP_RAM_DATA)
 891 #define AscSetChipLramData(port, data)    outpw((port)+IOP_RAM_DATA, data)
 892 #define AscGetChipIFC(port)               (uchar)inp((port)+IOP_REG_IFC)
 893 #define AscSetChipIFC(port, data)          outp((port)+IOP_REG_IFC, data)
 894 #define AscGetChipStatus(port)            (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
 895 #define AscSetChipStatus(port, cs_val)    outpw((port)+IOP_STATUS, cs_val)
 896 #define AscGetChipControl(port)           (uchar)inp((port)+IOP_CTRL)
 897 #define AscSetChipControl(port, cc_val)   outp((port)+IOP_CTRL, cc_val)
 898 #define AscGetChipSyn(port)               (uchar)inp((port)+IOP_SYN_OFFSET)
 899 #define AscSetChipSyn(port, data)         outp((port)+IOP_SYN_OFFSET, data)
 900 #define AscSetPCAddr(port, data)          outpw((port)+IOP_REG_PC, data)
 901 #define AscGetPCAddr(port)                (ushort)inpw((port)+IOP_REG_PC)
 902 #define AscIsIntPending(port)             (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
 903 #define AscGetChipScsiID(port)            ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
 904 #define AscGetExtraControl(port)          (uchar)inp((port)+IOP_EXTRA_CONTROL)
 905 #define AscSetExtraControl(port, data)    outp((port)+IOP_EXTRA_CONTROL, data)
 906 #define AscReadChipAX(port)               (ushort)inpw((port)+IOP_REG_AX)
 907 #define AscWriteChipAX(port, data)        outpw((port)+IOP_REG_AX, data)
 908 #define AscReadChipIX(port)               (uchar)inp((port)+IOP_REG_IX)
 909 #define AscWriteChipIX(port, data)        outp((port)+IOP_REG_IX, data)
 910 #define AscReadChipIH(port)               (ushort)inpw((port)+IOP_REG_IH)
 911 #define AscWriteChipIH(port, data)        outpw((port)+IOP_REG_IH, data)
 912 #define AscReadChipQP(port)               (uchar)inp((port)+IOP_REG_QP)
 913 #define AscWriteChipQP(port, data)        outp((port)+IOP_REG_QP, data)
 914 #define AscReadChipFIFO_L(port)           (ushort)inpw((port)+IOP_REG_FIFO_L)
 915 #define AscWriteChipFIFO_L(port, data)    outpw((port)+IOP_REG_FIFO_L, data)
 916 #define AscReadChipFIFO_H(port)           (ushort)inpw((port)+IOP_REG_FIFO_H)
 917 #define AscWriteChipFIFO_H(port, data)    outpw((port)+IOP_REG_FIFO_H, data)
 918 #define AscReadChipDmaSpeed(port)         (uchar)inp((port)+IOP_DMA_SPEED)
 919 #define AscWriteChipDmaSpeed(port, data)  outp((port)+IOP_DMA_SPEED, data)
 920 #define AscReadChipDA0(port)              (ushort)inpw((port)+IOP_REG_DA0)
 921 #define AscWriteChipDA0(port)             outpw((port)+IOP_REG_DA0, data)
 922 #define AscReadChipDA1(port)              (ushort)inpw((port)+IOP_REG_DA1)
 923 #define AscWriteChipDA1(port)             outpw((port)+IOP_REG_DA1, data)
 924 #define AscReadChipDC0(port)              (ushort)inpw((port)+IOP_REG_DC0)
 925 #define AscWriteChipDC0(port)             outpw((port)+IOP_REG_DC0, data)
 926 #define AscReadChipDC1(port)              (ushort)inpw((port)+IOP_REG_DC1)
 927 #define AscWriteChipDC1(port)             outpw((port)+IOP_REG_DC1, data)
 928 #define AscReadChipDvcID(port)            (uchar)inp((port)+IOP_REG_ID)
 929 #define AscWriteChipDvcID(port, data)     outp((port)+IOP_REG_ID, data)
 930
 931 /*
 932  * Portable Data Types
 933  *
 934  * Any instance where a 32-bit long or pointer type is assumed
 935  * for precision or HW defined structures, the following define
 936  * types must be used. In Linux the char, short, and int types
 937  * are all consistent at 8, 16, and 32 bits respectively. Pointers
 938  * and long types are 64 bits on Alpha and UltraSPARC.
 939  */
 940 #define ADV_PADDR __u32         /* Physical address data type. */
 941 #define ADV_VADDR __u32         /* Virtual address data type. */
 942 #define ADV_DCNT  __u32         /* Unsigned Data count type. */
 943 #define ADV_SDCNT __s32         /* Signed Data count type. */
 944
 945 /*
 946  * These macros are used to convert a virtual address to a
 947  * 32-bit value. This currently can be used on Linux Alpha
 948  * which uses 64-bit virtual address but a 32-bit bus address.
 949  * This is likely to break in the future, but doing this now
 950  * will give us time to change the HW and FW to handle 64-bit
 951  * addresses.
 952  */
 953 #define ADV_VADDR_TO_U32   virt_to_bus
 954 #define ADV_U32_TO_VADDR   bus_to_virt
 955
 956 #define AdvPortAddr  void __iomem *     /* Virtual memory address size */
 957
 958 /*
 959  * Define Adv Library required memory access macros.
 960  */
 961 #define ADV_MEM_READB(addr) readb(addr)
 962 #define ADV_MEM_READW(addr) readw(addr)
 963 #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
 964 #define ADV_MEM_WRITEW(addr, word) writew(word, addr)
 965 #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
 966
 967 #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 15)
 968
 969 /*
 970  * Define total number of simultaneous maximum element scatter-gather
 971  * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
 972  * maximum number of outstanding commands per wide host adapter. Each
 973  * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
 974  * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
 975  * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
 976  * structures or 255 scatter-gather elements.
 977  */
 978 #define ADV_TOT_SG_BLOCK        ASC_DEF_MAX_HOST_QNG
 979
 980 /*
 981  * Define maximum number of scatter-gather elements per request.
 982  */
 983 #define ADV_MAX_SG_LIST         255
 984 #define NO_OF_SG_PER_BLOCK              15
 985
 986 #define ADV_EEP_DVC_CFG_BEGIN           (0x00)
 987 #define ADV_EEP_DVC_CFG_END             (0x15)
 988 #define ADV_EEP_DVC_CTL_BEGIN           (0x16)  /* location of OEM name */
 989 #define ADV_EEP_MAX_WORD_ADDR           (0x1E)
 990
 991 #define ADV_EEP_DELAY_MS                100
 992
 993 #define ADV_EEPROM_BIG_ENDIAN          0x8000   /* EEPROM Bit 15 */
 994 #define ADV_EEPROM_BIOS_ENABLE         0x4000   /* EEPROM Bit 14 */
 995 /*
 996  * For the ASC3550 Bit 13 is Termination Polarity control bit.
 997  * For later ICs Bit 13 controls whether the CIS (Card Information
 998  * Service Section) is loaded from EEPROM.
 999  */
1000 #define ADV_EEPROM_TERM_POL            0x2000   /* EEPROM Bit 13 */
1001 #define ADV_EEPROM_CIS_LD              0x2000   /* EEPROM Bit 13 */
1002 /*
1003  * ASC38C1600 Bit 11
1004  *
1005  * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
1006  * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
1007  * Function 0 will specify INT B.
1008  *
1009  * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
1010  * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
1011  * Function 1 will specify INT A.
1012  */
1013 #define ADV_EEPROM_INTAB               0x0800   /* EEPROM Bit 11 */
1014
1015 typedef struct adveep_3550_config {
1016         /* Word Offset, Description */
1017
1018         ushort cfg_lsw;         /* 00 power up initialization */
1019         /*  bit 13 set - Term Polarity Control */
1020         /*  bit 14 set - BIOS Enable */
1021         /*  bit 15 set - Big Endian Mode */
1022         ushort cfg_msw;         /* 01 unused      */
1023         ushort disc_enable;     /* 02 disconnect enable */
1024         ushort wdtr_able;       /* 03 Wide DTR able */
1025         ushort sdtr_able;       /* 04 Synchronous DTR able */
1026         ushort start_motor;     /* 05 send start up motor */
1027         ushort tagqng_able;     /* 06 tag queuing able */
1028         ushort bios_scan;       /* 07 BIOS device control */
1029         ushort scam_tolerant;   /* 08 no scam */
1030
1031         uchar adapter_scsi_id;  /* 09 Host Adapter ID */
1032         uchar bios_boot_delay;  /*    power up wait */
1033
1034         uchar scsi_reset_delay; /* 10 reset delay */
1035         uchar bios_id_lun;      /*    first boot device scsi id & lun */
1036         /*    high nibble is lun */
1037         /*    low nibble is scsi id */
1038
1039         uchar termination;      /* 11 0 - automatic */
1040         /*    1 - low off / high off */
1041         /*    2 - low off / high on */
1042         /*    3 - low on  / high on */
1043         /*    There is no low on  / high off */
1044
1045         uchar reserved1;        /*    reserved byte (not used) */
1046
1047         ushort bios_ctrl;       /* 12 BIOS control bits */
1048         /*  bit 0  BIOS don't act as initiator. */
1049         /*  bit 1  BIOS > 1 GB support */
1050         /*  bit 2  BIOS > 2 Disk Support */
1051         /*  bit 3  BIOS don't support removables */
1052         /*  bit 4  BIOS support bootable CD */
1053         /*  bit 5  BIOS scan enabled */
1054         /*  bit 6  BIOS support multiple LUNs */
1055         /*  bit 7  BIOS display of message */
1056         /*  bit 8  SCAM disabled */
1057         /*  bit 9  Reset SCSI bus during init. */
1058         /*  bit 10 */
1059         /*  bit 11 No verbose initialization. */
1060         /*  bit 12 SCSI parity enabled */
1061         /*  bit 13 */
1062         /*  bit 14 */
1063         /*  bit 15 */
1064         ushort ultra_able;      /* 13 ULTRA speed able */
1065         ushort reserved2;       /* 14 reserved */
1066         uchar max_host_qng;     /* 15 maximum host queuing */
1067         uchar max_dvc_qng;      /*    maximum per device queuing */
1068         ushort dvc_cntl;        /* 16 control bit for driver */
1069         ushort bug_fix;         /* 17 control bit for bug fix */
1070         ushort serial_number_word1;     /* 18 Board serial number word 1 */
1071         ushort serial_number_word2;     /* 19 Board serial number word 2 */
1072         ushort serial_number_word3;     /* 20 Board serial number word 3 */
1073         ushort check_sum;       /* 21 EEP check sum */
1074         uchar oem_name[16];     /* 22 OEM name */
1075         ushort dvc_err_code;    /* 30 last device driver error code */
1076         ushort adv_err_code;    /* 31 last uc and Adv Lib error code */
1077         ushort adv_err_addr;    /* 32 last uc error address */
1078         ushort saved_dvc_err_code;      /* 33 saved last dev. driver error code   */
1079         ushort saved_adv_err_code;      /* 34 saved last uc and Adv Lib error code */
1080         ushort saved_adv_err_addr;      /* 35 saved last uc error address         */
1081         ushort num_of_err;      /* 36 number of error */
1082 } ADVEEP_3550_CONFIG;
1083
1084 typedef struct adveep_38C0800_config {
1085         /* Word Offset, Description */
1086
1087         ushort cfg_lsw;         /* 00 power up initialization */
1088         /*  bit 13 set - Load CIS */
1089         /*  bit 14 set - BIOS Enable */
1090         /*  bit 15 set - Big Endian Mode */
1091         ushort cfg_msw;         /* 01 unused      */
1092         ushort disc_enable;     /* 02 disconnect enable */
1093         ushort wdtr_able;       /* 03 Wide DTR able */
1094         ushort sdtr_speed1;     /* 04 SDTR Speed TID 0-3 */
1095         ushort start_motor;     /* 05 send start up motor */
1096         ushort tagqng_able;     /* 06 tag queuing able */
1097         ushort bios_scan;       /* 07 BIOS device control */
1098         ushort scam_tolerant;   /* 08 no scam */
1099
1100         uchar adapter_scsi_id;  /* 09 Host Adapter ID */
1101         uchar bios_boot_delay;  /*    power up wait */
1102
1103         uchar scsi_reset_delay; /* 10 reset delay */
1104         uchar bios_id_lun;      /*    first boot device scsi id & lun */
1105         /*    high nibble is lun */
1106         /*    low nibble is scsi id */
1107
1108         uchar termination_se;   /* 11 0 - automatic */
1109         /*    1 - low off / high off */
1110         /*    2 - low off / high on */
1111         /*    3 - low on  / high on */
1112         /*    There is no low on  / high off */
1113
1114         uchar termination_lvd;  /* 11 0 - automatic */
1115         /*    1 - low off / high off */
1116         /*    2 - low off / high on */
1117         /*    3 - low on  / high on */
1118         /*    There is no low on  / high off */
1119
1120         ushort bios_ctrl;       /* 12 BIOS control bits */
1121         /*  bit 0  BIOS don't act as initiator. */
1122         /*  bit 1  BIOS > 1 GB support */
1123         /*  bit 2  BIOS > 2 Disk Support */
1124         /*  bit 3  BIOS don't support removables */
1125         /*  bit 4  BIOS support bootable CD */
1126         /*  bit 5  BIOS scan enabled */
1127         /*  bit 6  BIOS support multiple LUNs */
1128         /*  bit 7  BIOS display of message */
1129         /*  bit 8  SCAM disabled */
1130         /*  bit 9  Reset SCSI bus during init. */
1131         /*  bit 10 */
1132         /*  bit 11 No verbose initialization. */
1133         /*  bit 12 SCSI parity enabled */
1134         /*  bit 13 */
1135         /*  bit 14 */
1136         /*  bit 15 */
1137         ushort sdtr_speed2;     /* 13 SDTR speed TID 4-7 */
1138         ushort sdtr_speed3;     /* 14 SDTR speed TID 8-11 */
1139         uchar max_host_qng;     /* 15 maximum host queueing */
1140         uchar max_dvc_qng;      /*    maximum per device queuing */
1141         ushort dvc_cntl;        /* 16 control bit for driver */
1142         ushort sdtr_speed4;     /* 17 SDTR speed 4 TID 12-15 */
1143         ushort serial_number_word1;     /* 18 Board serial number word 1 */
1144         ushort serial_number_word2;     /* 19 Board serial number word 2 */
1145         ushort serial_number_word3;     /* 20 Board serial number word 3 */
1146         ushort check_sum;       /* 21 EEP check sum */
1147         uchar oem_name[16];     /* 22 OEM name */
1148         ushort dvc_err_code;    /* 30 last device driver error code */
1149         ushort adv_err_code;    /* 31 last uc and Adv Lib error code */
1150         ushort adv_err_addr;    /* 32 last uc error address */
1151         ushort saved_dvc_err_code;      /* 33 saved last dev. driver error code   */
1152         ushort saved_adv_err_code;      /* 34 saved last uc and Adv Lib error code */
1153         ushort saved_adv_err_addr;      /* 35 saved last uc error address         */
1154         ushort reserved36;      /* 36 reserved */
1155         ushort reserved37;      /* 37 reserved */
1156         ushort reserved38;      /* 38 reserved */
1157         ushort reserved39;      /* 39 reserved */
1158         ushort reserved40;      /* 40 reserved */
1159         ushort reserved41;      /* 41 reserved */
1160         ushort reserved42;      /* 42 reserved */
1161         ushort reserved43;      /* 43 reserved */
1162         ushort reserved44;      /* 44 reserved */
1163         ushort reserved45;      /* 45 reserved */
1164         ushort reserved46;      /* 46 reserved */
1165         ushort reserved47;      /* 47 reserved */
1166         ushort reserved48;      /* 48 reserved */
1167         ushort reserved49;      /* 49 reserved */
1168         ushort reserved50;      /* 50 reserved */
1169         ushort reserved51;      /* 51 reserved */
1170         ushort reserved52;      /* 52 reserved */
1171         ushort reserved53;      /* 53 reserved */
1172         ushort reserved54;      /* 54 reserved */
1173         ushort reserved55;      /* 55 reserved */
1174         ushort cisptr_lsw;      /* 56 CIS PTR LSW */
1175         ushort cisprt_msw;      /* 57 CIS PTR MSW */
1176         ushort subsysvid;       /* 58 SubSystem Vendor ID */
1177         ushort subsysid;        /* 59 SubSystem ID */
1178         ushort reserved60;      /* 60 reserved */
1179         ushort reserved61;      /* 61 reserved */
1180         ushort reserved62;      /* 62 reserved */
1181         ushort reserved63;      /* 63 reserved */
1182 } ADVEEP_38C0800_CONFIG;
1183
1184 typedef struct adveep_38C1600_config {
1185         /* Word Offset, Description */
1186
1187         ushort cfg_lsw;         /* 00 power up initialization */
1188         /*  bit 11 set - Func. 0 INTB, Func. 1 INTA */
1189         /*       clear - Func. 0 INTA, Func. 1 INTB */
1190         /*  bit 13 set - Load CIS */
1191         /*  bit 14 set - BIOS Enable */
1192         /*  bit 15 set - Big Endian Mode */
1193         ushort cfg_msw;         /* 01 unused */
1194         ushort disc_enable;     /* 02 disconnect enable */
1195         ushort wdtr_able;       /* 03 Wide DTR able */
1196         ushort sdtr_speed1;     /* 04 SDTR Speed TID 0-3 */
1197         ushort start_motor;     /* 05 send start up motor */
1198         ushort tagqng_able;     /* 06 tag queuing able */
1199         ushort bios_scan;       /* 07 BIOS device control */
1200         ushort scam_tolerant;   /* 08 no scam */
1201
1202         uchar adapter_scsi_id;  /* 09 Host Adapter ID */
1203         uchar bios_boot_delay;  /*    power up wait */
1204
1205         uchar scsi_reset_delay; /* 10 reset delay */
1206         uchar bios_id_lun;      /*    first boot device scsi id & lun */
1207         /*    high nibble is lun */
1208         /*    low nibble is scsi id */
1209
1210         uchar termination_se;   /* 11 0 - automatic */
1211         /*    1 - low off / high off */
1212         /*    2 - low off / high on */
1213         /*    3 - low on  / high on */
1214         /*    There is no low on  / high off */
1215
1216         uchar termination_lvd;  /* 11 0 - automatic */
1217         /*    1 - low off / high off */
1218         /*    2 - low off / high on */
1219         /*    3 - low on  / high on */
1220         /*    There is no low on  / high off */
1221
1222         ushort bios_ctrl;       /* 12 BIOS control bits */
1223         /*  bit 0  BIOS don't act as initiator. */
1224         /*  bit 1  BIOS > 1 GB support */
1225         /*  bit 2  BIOS > 2 Disk Support */
1226         /*  bit 3  BIOS don't support removables */
1227         /*  bit 4  BIOS support bootable CD */
1228         /*  bit 5  BIOS scan enabled */
1229         /*  bit 6  BIOS support multiple LUNs */
1230         /*  bit 7  BIOS display of message */
1231         /*  bit 8  SCAM disabled */
1232         /*  bit 9  Reset SCSI bus during init. */
1233         /*  bit 10 Basic Integrity Checking disabled */
1234         /*  bit 11 No verbose initialization. */
1235         /*  bit 12 SCSI parity enabled */
1236         /*  bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
1237         /*  bit 14 */
1238         /*  bit 15 */
1239         ushort sdtr_speed2;     /* 13 SDTR speed TID 4-7 */
1240         ushort sdtr_speed3;     /* 14 SDTR speed TID 8-11 */
1241         uchar max_host_qng;     /* 15 maximum host queueing */
1242         uchar max_dvc_qng;      /*    maximum per device queuing */
1243         ushort dvc_cntl;        /* 16 control bit for driver */
1244         ushort sdtr_speed4;     /* 17 SDTR speed 4 TID 12-15 */
1245         ushort serial_number_word1;     /* 18 Board serial number word 1 */
1246         ushort serial_number_word2;     /* 19 Board serial number word 2 */
1247         ushort serial_number_word3;     /* 20 Board serial number word 3 */
1248         ushort check_sum;       /* 21 EEP check sum */
1249         uchar oem_name[16];     /* 22 OEM name */
1250         ushort dvc_err_code;    /* 30 last device driver error code */
1251         ushort adv_err_code;    /* 31 last uc and Adv Lib error code */
1252         ushort adv_err_addr;    /* 32 last uc error address */
1253         ushort saved_dvc_err_code;      /* 33 saved last dev. driver error code   */
1254         ushort saved_adv_err_code;      /* 34 saved last uc and Adv Lib error code */
1255         ushort saved_adv_err_addr;      /* 35 saved last uc error address         */
1256         ushort reserved36;      /* 36 reserved */
1257         ushort reserved37;      /* 37 reserved */
1258         ushort reserved38;      /* 38 reserved */
1259         ushort reserved39;      /* 39 reserved */
1260         ushort reserved40;      /* 40 reserved */
1261         ushort reserved41;      /* 41 reserved */
1262         ushort reserved42;      /* 42 reserved */
1263         ushort reserved43;      /* 43 reserved */
1264         ushort reserved44;      /* 44 reserved */
1265         ushort reserved45;      /* 45 reserved */
1266         ushort reserved46;      /* 46 reserved */
1267         ushort reserved47;      /* 47 reserved */
1268         ushort reserved48;      /* 48 reserved */
1269         ushort reserved49;      /* 49 reserved */
1270         ushort reserved50;      /* 50 reserved */
1271         ushort reserved51;      /* 51 reserved */
1272         ushort reserved52;      /* 52 reserved */
1273         ushort reserved53;      /* 53 reserved */
1274         ushort reserved54;      /* 54 reserved */
1275         ushort reserved55;      /* 55 reserved */
1276         ushort cisptr_lsw;      /* 56 CIS PTR LSW */
1277         ushort cisprt_msw;      /* 57 CIS PTR MSW */
1278         ushort subsysvid;       /* 58 SubSystem Vendor ID */
1279         ushort subsysid;        /* 59 SubSystem ID */
1280         ushort reserved60;      /* 60 reserved */
1281         ushort reserved61;      /* 61 reserved */
1282         ushort reserved62;      /* 62 reserved */
1283         ushort reserved63;      /* 63 reserved */
1284 } ADVEEP_38C1600_CONFIG;
1285
1286 /*
1287  * EEPROM Commands
1288  */
1289 #define ASC_EEP_CMD_DONE             0x0200
1290
1291 /* bios_ctrl */
1292 #define BIOS_CTRL_BIOS               0x0001
1293 #define BIOS_CTRL_EXTENDED_XLAT      0x0002
1294 #define BIOS_CTRL_GT_2_DISK          0x0004
1295 #define BIOS_CTRL_BIOS_REMOVABLE     0x0008
1296 #define BIOS_CTRL_BOOTABLE_CD        0x0010
1297 #define BIOS_CTRL_MULTIPLE_LUN       0x0040
1298 #define BIOS_CTRL_DISPLAY_MSG        0x0080
1299 #define BIOS_CTRL_NO_SCAM            0x0100
1300 #define BIOS_CTRL_RESET_SCSI_BUS     0x0200
1301 #define BIOS_CTRL_INIT_VERBOSE       0x0800
1302 #define BIOS_CTRL_SCSI_PARITY        0x1000
1303 #define BIOS_CTRL_AIPP_DIS           0x2000
1304
1305 #define ADV_3550_MEMSIZE   0x2000       /* 8 KB Internal Memory */
1306
1307 #define ADV_38C0800_MEMSIZE  0x4000     /* 16 KB Internal Memory */
1308
1309 /*
1310  * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
1311  * a special 16K Adv Library and Microcode version. After the issue is
1312  * resolved, should restore 32K support.
1313  *
1314  * #define ADV_38C1600_MEMSIZE  0x8000L   * 32 KB Internal Memory *
1315  */
1316 #define ADV_38C1600_MEMSIZE  0x4000     /* 16 KB Internal Memory */
1317
1318 /*
1319  * Byte I/O register address from base of 'iop_base'.
1320  */
1321 #define IOPB_INTR_STATUS_REG    0x00
1322 #define IOPB_CHIP_ID_1          0x01
1323 #define IOPB_INTR_ENABLES       0x02
1324 #define IOPB_CHIP_TYPE_REV      0x03
1325 #define IOPB_RES_ADDR_4         0x04
1326 #define IOPB_RES_ADDR_5         0x05
1327 #define IOPB_RAM_DATA           0x06
1328 #define IOPB_RES_ADDR_7         0x07
1329 #define IOPB_FLAG_REG           0x08
1330 #define IOPB_RES_ADDR_9         0x09
1331 #define IOPB_RISC_CSR           0x0A
1332 #define IOPB_RES_ADDR_B         0x0B
1333 #define IOPB_RES_ADDR_C         0x0C
1334 #define IOPB_RES_ADDR_D         0x0D
1335 #define IOPB_SOFT_OVER_WR       0x0E
1336 #define IOPB_RES_ADDR_F         0x0F
1337 #define IOPB_MEM_CFG            0x10
1338 #define IOPB_RES_ADDR_11        0x11
1339 #define IOPB_GPIO_DATA          0x12
1340 #define IOPB_RES_ADDR_13        0x13
1341 #define IOPB_FLASH_PAGE         0x14
1342 #define IOPB_RES_ADDR_15        0x15
1343 #define IOPB_GPIO_CNTL          0x16
1344 #define IOPB_RES_ADDR_17        0x17
1345 #define IOPB_FLASH_DATA         0x18
1346 #define IOPB_RES_ADDR_19        0x19
1347 #define IOPB_RES_ADDR_1A        0x1A
1348 #define IOPB_RES_ADDR_1B        0x1B
1349 #define IOPB_RES_ADDR_1C        0x1C
1350 #define IOPB_RES_ADDR_1D        0x1D
1351 #define IOPB_RES_ADDR_1E        0x1E
1352 #define IOPB_RES_ADDR_1F        0x1F
1353 #define IOPB_DMA_CFG0           0x20
1354 #define IOPB_DMA_CFG1           0x21
1355 #define IOPB_TICKLE             0x22
1356 #define IOPB_DMA_REG_WR         0x23
1357 #define IOPB_SDMA_STATUS        0x24
1358 #define IOPB_SCSI_BYTE_CNT      0x25
1359 #define IOPB_HOST_BYTE_CNT      0x26
1360 #define IOPB_BYTE_LEFT_TO_XFER  0x27
1361 #define IOPB_BYTE_TO_XFER_0     0x28
1362 #define IOPB_BYTE_TO_XFER_1     0x29
1363 #define IOPB_BYTE_TO_XFER_2     0x2A
1364 #define IOPB_BYTE_TO_XFER_3     0x2B
1365 #define IOPB_ACC_GRP            0x2C
1366 #define IOPB_RES_ADDR_2D        0x2D
1367 #define IOPB_DEV_ID             0x2E
1368 #define IOPB_RES_ADDR_2F        0x2F
1369 #define IOPB_SCSI_DATA          0x30
1370 #define IOPB_RES_ADDR_31        0x31
1371 #define IOPB_RES_ADDR_32        0x32
1372 #define IOPB_SCSI_DATA_HSHK     0x33
1373 #define IOPB_SCSI_CTRL          0x34
1374 #define IOPB_RES_ADDR_35        0x35
1375 #define IOPB_RES_ADDR_36        0x36
1376 #define IOPB_RES_ADDR_37        0x37
1377 #define IOPB_RAM_BIST           0x38
1378 #define IOPB_PLL_TEST           0x39
1379 #define IOPB_PCI_INT_CFG        0x3A
1380 #define IOPB_RES_ADDR_3B        0x3B
1381 #define IOPB_RFIFO_CNT          0x3C
1382 #define IOPB_RES_ADDR_3D        0x3D
1383 #define IOPB_RES_ADDR_3E        0x3E
1384 #define IOPB_RES_ADDR_3F        0x3F
1385
1386 /*
1387  * Word I/O register address from base of 'iop_base'.
1388  */
1389 #define IOPW_CHIP_ID_0          0x00    /* CID0  */
1390 #define IOPW_CTRL_REG           0x02    /* CC    */
1391 #define IOPW_RAM_ADDR           0x04    /* LA    */
1392 #define IOPW_RAM_DATA           0x06    /* LD    */
1393 #define IOPW_RES_ADDR_08        0x08
1394 #define IOPW_RISC_CSR           0x0A    /* CSR   */
1395 #define IOPW_SCSI_CFG0          0x0C    /* CFG0  */
1396 #define IOPW_SCSI_CFG1          0x0E    /* CFG1  */
1397 #define IOPW_RES_ADDR_10        0x10
1398 #define IOPW_SEL_MASK           0x12    /* SM    */
1399 #define IOPW_RES_ADDR_14        0x14
1400 #define IOPW_FLASH_ADDR         0x16    /* FA    */
1401 #define IOPW_RES_ADDR_18        0x18
1402 #define IOPW_EE_CMD             0x1A    /* EC    */
1403 #define IOPW_EE_DATA            0x1C    /* ED    */
1404 #define IOPW_SFIFO_CNT          0x1E    /* SFC   */
1405 #define IOPW_RES_ADDR_20        0x20
1406 #define IOPW_Q_BASE             0x22    /* QB    */
1407 #define IOPW_QP                 0x24    /* QP    */
1408 #define IOPW_IX                 0x26    /* IX    */
1409 #define IOPW_SP                 0x28    /* SP    */
1410 #define IOPW_PC                 0x2A    /* PC    */
1411 #define IOPW_RES_ADDR_2C        0x2C
1412 #define IOPW_RES_ADDR_2E        0x2E
1413 #define IOPW_SCSI_DATA          0x30    /* SD    */
1414 #define IOPW_SCSI_DATA_HSHK     0x32    /* SDH   */
1415 #define IOPW_SCSI_CTRL          0x34    /* SC    */
1416 #define IOPW_HSHK_CFG           0x36    /* HCFG  */
1417 #define IOPW_SXFR_STATUS        0x36    /* SXS   */
1418 #define IOPW_SXFR_CNTL          0x38    /* SXL   */
1419 #define IOPW_SXFR_CNTH          0x3A    /* SXH   */
1420 #define IOPW_RES_ADDR_3C        0x3C
1421 #define IOPW_RFIFO_DATA         0x3E    /* RFD   */
1422
1423 /*
1424  * Doubleword I/O register address from base of 'iop_base'.
1425  */
1426 #define IOPDW_RES_ADDR_0         0x00
1427 #define IOPDW_RAM_DATA           0x04
1428 #define IOPDW_RES_ADDR_8         0x08
1429 #define IOPDW_RES_ADDR_C         0x0C
1430 #define IOPDW_RES_ADDR_10        0x10
1431 #define IOPDW_COMMA              0x14
1432 #define IOPDW_COMMB              0x18
1433 #define IOPDW_RES_ADDR_1C        0x1C
1434 #define IOPDW_SDMA_ADDR0         0x20
1435 #define IOPDW_SDMA_ADDR1         0x24
1436 #define IOPDW_SDMA_COUNT         0x28
1437 #define IOPDW_SDMA_ERROR         0x2C
1438 #define IOPDW_RDMA_ADDR0         0x30
1439 #define IOPDW_RDMA_ADDR1         0x34
1440 #define IOPDW_RDMA_COUNT         0x38
1441 #define IOPDW_RDMA_ERROR         0x3C
1442
1443 #define ADV_CHIP_ID_BYTE         0x25
1444 #define ADV_CHIP_ID_WORD         0x04C1
1445
1446 #define ADV_INTR_ENABLE_HOST_INTR                   0x01
1447 #define ADV_INTR_ENABLE_SEL_INTR                    0x02
1448 #define ADV_INTR_ENABLE_DPR_INTR                    0x04
1449 #define ADV_INTR_ENABLE_RTA_INTR                    0x08
1450 #define ADV_INTR_ENABLE_RMA_INTR                    0x10
1451 #define ADV_INTR_ENABLE_RST_INTR                    0x20
1452 #define ADV_INTR_ENABLE_DPE_INTR                    0x40
1453 #define ADV_INTR_ENABLE_GLOBAL_INTR                 0x80
1454
1455 #define ADV_INTR_STATUS_INTRA            0x01
1456 #define ADV_INTR_STATUS_INTRB            0x02
1457 #define ADV_INTR_STATUS_INTRC            0x04
1458
1459 #define ADV_RISC_CSR_STOP           (0x0000)
1460 #define ADV_RISC_TEST_COND          (0x2000)
1461 #define ADV_RISC_CSR_RUN            (0x4000)
1462 #define ADV_RISC_CSR_SINGLE_STEP    (0x8000)
1463
1464 #define ADV_CTRL_REG_HOST_INTR      0x0100
1465 #define ADV_CTRL_REG_SEL_INTR       0x0200
1466 #define ADV_CTRL_REG_DPR_INTR       0x0400
1467 #define ADV_CTRL_REG_RTA_INTR       0x0800
1468 #define ADV_CTRL_REG_RMA_INTR       0x1000
1469 #define ADV_CTRL_REG_RES_BIT14      0x2000
1470 #define ADV_CTRL_REG_DPE_INTR       0x4000
1471 #define ADV_CTRL_REG_POWER_DONE     0x8000
1472 #define ADV_CTRL_REG_ANY_INTR       0xFF00
1473
1474 #define ADV_CTRL_REG_CMD_RESET             0x00C6
1475 #define ADV_CTRL_REG_CMD_WR_IO_REG         0x00C5
1476 #define ADV_CTRL_REG_CMD_RD_IO_REG         0x00C4
1477 #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE  0x00C3
1478 #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE  0x00C2
1479
1480 #define ADV_TICKLE_NOP                      0x00
1481 #define ADV_TICKLE_A                        0x01
1482 #define ADV_TICKLE_B                        0x02
1483 #define ADV_TICKLE_C                        0x03
1484
1485 #define AdvIsIntPending(port) \
1486     (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
1487
1488 /*
1489  * SCSI_CFG0 Register bit definitions
1490  */
1491 #define TIMER_MODEAB    0xC000  /* Watchdog, Second, and Select. Timer Ctrl. */
1492 #define PARITY_EN       0x2000  /* Enable SCSI Parity Error detection */
1493 #define EVEN_PARITY     0x1000  /* Select Even Parity */
1494 #define WD_LONG         0x0800  /* Watchdog Interval, 1: 57 min, 0: 13 sec */
1495 #define QUEUE_128       0x0400  /* Queue Size, 1: 128 byte, 0: 64 byte */
1496 #define PRIM_MODE       0x0100  /* Primitive SCSI mode */
1497 #define SCAM_EN         0x0080  /* Enable SCAM selection */
1498 #define SEL_TMO_LONG    0x0040  /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
1499 #define CFRM_ID         0x0020  /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
1500 #define OUR_ID_EN       0x0010  /* Enable OUR_ID bits */
1501 #define OUR_ID          0x000F  /* SCSI ID */
1502
1503 /*
1504  * SCSI_CFG1 Register bit definitions
1505  */
1506 #define BIG_ENDIAN      0x8000  /* Enable Big Endian Mode MIO:15, EEP:15 */
1507 #define TERM_POL        0x2000  /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
1508 #define SLEW_RATE       0x1000  /* SCSI output buffer slew rate */
1509 #define FILTER_SEL      0x0C00  /* Filter Period Selection */
1510 #define  FLTR_DISABLE    0x0000 /* Input Filtering Disabled */
1511 #define  FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
1512 #define  FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
1513 #define ACTIVE_DBL      0x0200  /* Disable Active Negation */
1514 #define DIFF_MODE       0x0100  /* SCSI differential Mode (Read-Only) */
1515 #define DIFF_SENSE      0x0080  /* 1: No SE cables, 0: SE cable (Read-Only) */
1516 #define TERM_CTL_SEL    0x0040  /* Enable TERM_CTL_H and TERM_CTL_L */
1517 #define TERM_CTL        0x0030  /* External SCSI Termination Bits */
1518 #define  TERM_CTL_H      0x0020 /* Enable External SCSI Upper Termination */
1519 #define  TERM_CTL_L      0x0010 /* Enable External SCSI Lower Termination */
1520 #define CABLE_DETECT    0x000F  /* External SCSI Cable Connection Status */
1521
1522 /*
1523  * Addendum for ASC-38C0800 Chip
1524  *
1525  * The ASC-38C1600 Chip uses the same definitions except that the
1526  * bus mode override bits [12:10] have been moved to byte register
1527  * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
1528  * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
1529  * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
1530  * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
1531  * and [1:0]. Bits [14], [7:6], [3:2] are unused.
1532  */
1533 #define DIS_TERM_DRV    0x4000  /* 1: Read c_det[3:0], 0: cannot read */
1534 #define HVD_LVD_SE      0x1C00  /* Device Detect Bits */
1535 #define  HVD             0x1000 /* HVD Device Detect */
1536 #define  LVD             0x0800 /* LVD Device Detect */
1537 #define  SE              0x0400 /* SE Device Detect */
1538 #define TERM_LVD        0x00C0  /* LVD Termination Bits */
1539 #define  TERM_LVD_HI     0x0080 /* Enable LVD Upper Termination */
1540 #define  TERM_LVD_LO     0x0040 /* Enable LVD Lower Termination */
1541 #define TERM_SE         0x0030  /* SE Termination Bits */
1542 #define  TERM_SE_HI      0x0020 /* Enable SE Upper Termination */
1543 #define  TERM_SE_LO      0x0010 /* Enable SE Lower Termination */
1544 #define C_DET_LVD       0x000C  /* LVD Cable Detect Bits */
1545 #define  C_DET3          0x0008 /* Cable Detect for LVD External Wide */
1546 #define  C_DET2          0x0004 /* Cable Detect for LVD Internal Wide */
1547 #define C_DET_SE        0x0003  /* SE Cable Detect Bits */
1548 #define  C_DET1          0x0002 /* Cable Detect for SE Internal Wide */
1549 #define  C_DET0          0x0001 /* Cable Detect for SE Internal Narrow */
1550
1551 #define CABLE_ILLEGAL_A 0x7
1552     /* x 0 0 0  | on  on | Illegal (all 3 connectors are used) */
1553
1554 #define CABLE_ILLEGAL_B 0xB
1555     /* 0 x 0 0  | on  on | Illegal (all 3 connectors are used) */
1556
1557 /*
1558  * MEM_CFG Register bit definitions
1559  */
1560 #define BIOS_EN         0x40    /* BIOS Enable MIO:14,EEP:14 */
1561 #define FAST_EE_CLK     0x20    /* Diagnostic Bit */
1562 #define RAM_SZ          0x1C    /* Specify size of RAM to RISC */
1563 #define  RAM_SZ_2KB      0x00   /* 2 KB */
1564 #define  RAM_SZ_4KB      0x04   /* 4 KB */
1565 #define  RAM_SZ_8KB      0x08   /* 8 KB */
1566 #define  RAM_SZ_16KB     0x0C   /* 16 KB */
1567 #define  RAM_SZ_32KB     0x10   /* 32 KB */
1568 #define  RAM_SZ_64KB     0x14   /* 64 KB */
1569
1570 /*
1571  * DMA_CFG0 Register bit definitions
1572  *
1573  * This register is only accessible to the host.
1574  */
1575 #define BC_THRESH_ENB   0x80    /* PCI DMA Start Conditions */
1576 #define FIFO_THRESH     0x70    /* PCI DMA FIFO Threshold */
1577 #define  FIFO_THRESH_16B  0x00  /* 16 bytes */
1578 #define  FIFO_THRESH_32B  0x20  /* 32 bytes */
1579 #define  FIFO_THRESH_48B  0x30  /* 48 bytes */
1580 #define  FIFO_THRESH_64B  0x40  /* 64 bytes */
1581 #define  FIFO_THRESH_80B  0x50  /* 80 bytes (default) */
1582 #define  FIFO_THRESH_96B  0x60  /* 96 bytes */
1583 #define  FIFO_THRESH_112B 0x70  /* 112 bytes */
1584 #define START_CTL       0x0C    /* DMA start conditions */
1585 #define  START_CTL_TH    0x00   /* Wait threshold level (default) */
1586 #define  START_CTL_ID    0x04   /* Wait SDMA/SBUS idle */
1587 #define  START_CTL_THID  0x08   /* Wait threshold and SDMA/SBUS idle */
1588 #define  START_CTL_EMFU  0x0C   /* Wait SDMA FIFO empty/full */
1589 #define READ_CMD        0x03    /* Memory Read Method */
1590 #define  READ_CMD_MR     0x00   /* Memory Read */
1591 #define  READ_CMD_MRL    0x02   /* Memory Read Long */
1592 #define  READ_CMD_MRM    0x03   /* Memory Read Multiple (default) */
1593
1594 /*
1595  * ASC-38C0800 RAM BIST Register bit definitions
1596  */
1597 #define RAM_TEST_MODE         0x80
1598 #define PRE_TEST_MODE         0x40
1599 #define NORMAL_MODE           0x00
1600 #define RAM_TEST_DONE         0x10
1601 #define RAM_TEST_STATUS       0x0F
1602 #define  RAM_TEST_HOST_ERROR   0x08
1603 #define  RAM_TEST_INTRAM_ERROR 0x04
1604 #define  RAM_TEST_RISC_ERROR   0x02
1605 #define  RAM_TEST_SCSI_ERROR   0x01
1606 #define  RAM_TEST_SUCCESS      0x00
1607 #define PRE_TEST_VALUE        0x05
1608 #define NORMAL_VALUE          0x00
1609
1610 /*
1611  * ASC38C1600 Definitions
1612  *
1613  * IOPB_PCI_INT_CFG Bit Field Definitions
1614  */
1615
1616 #define INTAB_LD        0x80    /* Value loaded from EEPROM Bit 11. */
1617
1618 /*
1619  * Bit 1 can be set to change the interrupt for the Function to operate in
1620  * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
1621  * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
1622  * mode, otherwise the operating mode is undefined.
1623  */
1624 #define TOTEMPOLE       0x02
1625
1626 /*
1627  * Bit 0 can be used to change the Int Pin for the Function. The value is
1628  * 0 by default for both Functions with Function 0 using INT A and Function
1629  * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
1630  * INT A is used.
1631  *
1632  * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
1633  * value specified in the PCI Configuration Space.
1634  */
1635 #define INTAB           0x01
1636
1637 /*
1638  * Adv Library Status Definitions
1639  */
1640 #define ADV_TRUE        1
1641 #define ADV_FALSE       0
1642 #define ADV_SUCCESS     1
1643 #define ADV_BUSY        0
1644 #define ADV_ERROR       (-1)
1645
1646 /*
1647  * ADV_DVC_VAR 'warn_code' values
1648  */
1649 #define ASC_WARN_BUSRESET_ERROR         0x0001  /* SCSI Bus Reset error */
1650 #define ASC_WARN_EEPROM_CHKSUM          0x0002  /* EEP check sum error */
1651 #define ASC_WARN_EEPROM_TERMINATION     0x0004  /* EEP termination bad field */
1652 #define ASC_WARN_ERROR                  0xFFFF  /* ADV_ERROR return */
1653
1654 #define ADV_MAX_TID                     15      /* max. target identifier */
1655 #define ADV_MAX_LUN                     7       /* max. logical unit number */
1656
1657 /*
1658  * Fixed locations of microcode operating variables.
1659  */
1660 #define ASC_MC_CODE_BEGIN_ADDR          0x0028  /* microcode start address */
1661 #define ASC_MC_CODE_END_ADDR            0x002A  /* microcode end address */
1662 #define ASC_MC_CODE_CHK_SUM             0x002C  /* microcode code checksum */
1663 #define ASC_MC_VERSION_DATE             0x0038  /* microcode version */
1664 #define ASC_MC_VERSION_NUM              0x003A  /* microcode number */
1665 #define ASC_MC_BIOSMEM                  0x0040  /* BIOS RISC Memory Start */
1666 #define ASC_MC_BIOSLEN                  0x0050  /* BIOS RISC Memory Length */
1667 #define ASC_MC_BIOS_SIGNATURE           0x0058  /* BIOS Signature 0x55AA */
1668 #define ASC_MC_BIOS_VERSION             0x005A  /* BIOS Version (2 bytes) */
1669 #define ASC_MC_SDTR_SPEED1              0x0090  /* SDTR Speed for TID 0-3 */
1670 #define ASC_MC_SDTR_SPEED2              0x0092  /* SDTR Speed for TID 4-7 */
1671 #define ASC_MC_SDTR_SPEED3              0x0094  /* SDTR Speed for TID 8-11 */
1672 #define ASC_MC_SDTR_SPEED4              0x0096  /* SDTR Speed for TID 12-15 */
1673 #define ASC_MC_CHIP_TYPE                0x009A
1674 #define ASC_MC_INTRB_CODE               0x009B
1675 #define ASC_MC_WDTR_ABLE                0x009C
1676 #define ASC_MC_SDTR_ABLE                0x009E
1677 #define ASC_MC_TAGQNG_ABLE              0x00A0
1678 #define ASC_MC_DISC_ENABLE              0x00A2
1679 #define ASC_MC_IDLE_CMD_STATUS          0x00A4
1680 #define ASC_MC_IDLE_CMD                 0x00A6
1681 #define ASC_MC_IDLE_CMD_PARAMETER       0x00A8
1682 #define ASC_MC_DEFAULT_SCSI_CFG0        0x00AC
1683 #define ASC_MC_DEFAULT_SCSI_CFG1        0x00AE
1684 #define ASC_MC_DEFAULT_MEM_CFG          0x00B0
1685 #define ASC_MC_DEFAULT_SEL_MASK         0x00B2
1686 #define ASC_MC_SDTR_DONE                0x00B6
1687 #define ASC_MC_NUMBER_OF_QUEUED_CMD     0x00C0
1688 #define ASC_MC_NUMBER_OF_MAX_CMD        0x00D0
1689 #define ASC_MC_DEVICE_HSHK_CFG_TABLE    0x0100
1690 #define ASC_MC_CONTROL_FLAG             0x0122  /* Microcode control flag. */
1691 #define ASC_MC_WDTR_DONE                0x0124
1692 #define ASC_MC_CAM_MODE_MASK            0x015E  /* CAM mode TID bitmask. */
1693 #define ASC_MC_ICQ                      0x0160
1694 #define ASC_MC_IRQ                      0x0164
1695 #define ASC_MC_PPR_ABLE                 0x017A
1696
1697 /*
1698  * BIOS LRAM variable absolute offsets.
1699  */
1700 #define BIOS_CODESEG    0x54
1701 #define BIOS_CODELEN    0x56
1702 #define BIOS_SIGNATURE  0x58
1703 #define BIOS_VERSION    0x5A
1704
1705 /*
1706  * Microcode Control Flags
1707  *
1708  * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
1709  * and handled by the microcode.
1710  */
1711 #define CONTROL_FLAG_IGNORE_PERR        0x0001  /* Ignore DMA Parity Errors */
1712 #define CONTROL_FLAG_ENABLE_AIPP        0x0002  /* Enabled AIPP checking. */
1713
1714 /*
1715  * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
1716  */
1717 #define HSHK_CFG_WIDE_XFR       0x8000
1718 #define HSHK_CFG_RATE           0x0F00
1719 #define HSHK_CFG_OFFSET         0x001F
1720
1721 #define ASC_DEF_MAX_HOST_QNG    0xFD    /* Max. number of host commands (253) */
1722 #define ASC_DEF_MIN_HOST_QNG    0x10    /* Min. number of host commands (16) */
1723 #define ASC_DEF_MAX_DVC_QNG     0x3F    /* Max. number commands per device (63) */
1724 #define ASC_DEF_MIN_DVC_QNG     0x04    /* Min. number commands per device (4) */
1725
1726 #define ASC_QC_DATA_CHECK  0x01 /* Require ASC_QC_DATA_OUT set or clear. */
1727 #define ASC_QC_DATA_OUT    0x02 /* Data out DMA transfer. */
1728 #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
1729 #define ASC_QC_NO_OVERRUN  0x08 /* Don't report overrun. */
1730 #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
1731
1732 #define ASC_QSC_NO_DISC     0x01        /* Don't allow disconnect for request. */
1733 #define ASC_QSC_NO_TAGMSG   0x02        /* Don't allow tag queuing for request. */
1734 #define ASC_QSC_NO_SYNC     0x04        /* Don't use Synch. transfer on request. */
1735 #define ASC_QSC_NO_WIDE     0x08        /* Don't use Wide transfer on request. */
1736 #define ASC_QSC_REDO_DTR    0x10        /* Renegotiate WDTR/SDTR before request. */
1737 /*
1738  * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
1739  * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
1740  */
1741 #define ASC_QSC_HEAD_TAG    0x40        /* Use Head Tag Message (0x21). */
1742 #define ASC_QSC_ORDERED_TAG 0x80        /* Use Ordered Tag Message (0x22). */
1743
1744 /*
1745  * All fields here are accessed by the board microcode and need to be
1746  * little-endian.
1747  */
1748 typedef struct adv_carr_t {
1749         ADV_VADDR carr_va;      /* Carrier Virtual Address */
1750         ADV_PADDR carr_pa;      /* Carrier Physical Address */
1751         ADV_VADDR areq_vpa;     /* ASC_SCSI_REQ_Q Virtual or Physical Address */
1752         /*
1753          * next_vpa [31:4]            Carrier Virtual or Physical Next Pointer
1754          *
1755          * next_vpa [3:1]             Reserved Bits
1756          * next_vpa [0]               Done Flag set in Response Queue.
1757          */
1758         ADV_VADDR next_vpa;
1759 } ADV_CARR_T;
1760
1761 /*
1762  * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
1763  */
1764 #define ASC_NEXT_VPA_MASK       0xFFFFFFF0
1765
1766 #define ASC_RQ_DONE             0x00000001
1767 #define ASC_RQ_GOOD             0x00000002
1768 #define ASC_CQ_STOPPER          0x00000000
1769
1770 #define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
1771
1772 #define ADV_CARRIER_NUM_PAGE_CROSSING \
1773     (((ADV_CARRIER_COUNT * sizeof(ADV_CARR_T)) + (PAGE_SIZE - 1))/PAGE_SIZE)
1774
1775 #define ADV_CARRIER_BUFSIZE \
1776     ((ADV_CARRIER_COUNT + ADV_CARRIER_NUM_PAGE_CROSSING) * sizeof(ADV_CARR_T))
1777
1778 /*
1779  * ASC_SCSI_REQ_Q 'a_flag' definitions
1780  *
1781  * The Adv Library should limit use to the lower nibble (4 bits) of
1782  * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
1783  */
1784 #define ADV_POLL_REQUEST                0x01    /* poll for request completion */
1785 #define ADV_SCSIQ_DONE                  0x02    /* request done */
1786 #define ADV_DONT_RETRY                  0x08    /* don't do retry */
1787
1788 #define ADV_CHIP_ASC3550          0x01  /* Ultra-Wide IC */
1789 #define ADV_CHIP_ASC38C0800       0x02  /* Ultra2-Wide/LVD IC */
1790 #define ADV_CHIP_ASC38C1600       0x03  /* Ultra3-Wide/LVD2 IC */
1791
1792 /*
1793  * Adapter temporary configuration structure
1794  *
1795  * This structure can be discarded after initialization. Don't add
1796  * fields here needed after initialization.
1797  *
1798  * Field naming convention:
1799  *
1800  *  *_enable indicates the field enables or disables a feature. The
1801  *  value of the field is never reset.
1802  */
1803 typedef struct adv_dvc_cfg {
1804         ushort disc_enable;     /* enable disconnection */
1805         uchar chip_version;     /* chip version */
1806         uchar termination;      /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
1807         ushort control_flag;    /* Microcode Control Flag */
1808         ushort mcode_date;      /* Microcode date */
1809         ushort mcode_version;   /* Microcode version */
1810         ushort serial1;         /* EEPROM serial number word 1 */
1811         ushort serial2;         /* EEPROM serial number word 2 */
1812         ushort serial3;         /* EEPROM serial number word 3 */
1813 } ADV_DVC_CFG;
1814
1815 struct adv_dvc_var;
1816 struct adv_scsi_req_q;
1817
1818 typedef struct asc_sg_block {
1819         uchar reserved1;
1820         uchar reserved2;
1821         uchar reserved3;
1822         uchar sg_cnt;           /* Valid entries in block. */
1823         ADV_PADDR sg_ptr;       /* Pointer to next sg block. */
1824         struct {
1825                 ADV_PADDR sg_addr;      /* SG element address. */
1826                 ADV_DCNT sg_count;      /* SG element count. */
1827         } sg_list[NO_OF_SG_PER_BLOCK];
1828 } ADV_SG_BLOCK;
1829
1830 /*
1831  * ADV_SCSI_REQ_Q - microcode request structure
1832  *
1833  * All fields in this structure up to byte 60 are used by the microcode.
1834  * The microcode makes assumptions about the size and ordering of fields
1835  * in this structure. Do not change the structure definition here without
1836  * coordinating the change with the microcode.
1837  *
1838  * All fields accessed by microcode must be maintained in little_endian
1839  * order.
1840  */
1841 typedef struct adv_scsi_req_q {
1842         uchar cntl;             /* Ucode flags and state (ASC_MC_QC_*). */
1843         uchar target_cmd;
1844         uchar target_id;        /* Device target identifier. */
1845         uchar target_lun;       /* Device target logical unit number. */
1846         ADV_PADDR data_addr;    /* Data buffer physical address. */
1847         ADV_DCNT data_cnt;      /* Data count. Ucode sets to residual. */
1848         ADV_PADDR sense_addr;
1849         ADV_PADDR carr_pa;
1850         uchar mflag;
1851         uchar sense_len;
1852         uchar cdb_len;          /* SCSI CDB length. Must <= 16 bytes. */
1853         uchar scsi_cntl;
1854         uchar done_status;      /* Completion status. */
1855         uchar scsi_status;      /* SCSI status byte. */
1856         uchar host_status;      /* Ucode host status. */
1857         uchar sg_working_ix;
1858         uchar cdb[12];          /* SCSI CDB bytes 0-11. */
1859         ADV_PADDR sg_real_addr; /* SG list physical address. */
1860         ADV_PADDR scsiq_rptr;
1861         uchar cdb16[4];         /* SCSI CDB bytes 12-15. */
1862         ADV_VADDR scsiq_ptr;
1863         ADV_VADDR carr_va;
1864         /*
1865          * End of microcode structure - 60 bytes. The rest of the structure
1866          * is used by the Adv Library and ignored by the microcode.
1867          */
1868         ADV_VADDR srb_ptr;
1869         ADV_SG_BLOCK *sg_list_ptr;      /* SG list virtual address. */
1870         char *vdata_addr;       /* Data buffer virtual address. */
1871         uchar a_flag;
1872         uchar pad[2];           /* Pad out to a word boundary. */
1873 } ADV_SCSI_REQ_Q;
1874
1875 /*
1876  * The following two structures are used to process Wide Board requests.
1877  *
1878  * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
1879  * and microcode with the ADV_SCSI_REQ_Q field 'srb_ptr' pointing to the
1880  * adv_req_t. The adv_req_t structure 'cmndp' field in turn points to the
1881  * Mid-Level SCSI request structure.
1882  *
1883  * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
1884  * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
1885  * up to 255 scatter-gather elements may be used per request or
1886  * ADV_SCSI_REQ_Q.
1887  *
1888  * Both structures must be 32 byte aligned.
1889  */
1890 typedef struct adv_sgblk {
1891         ADV_SG_BLOCK sg_block;  /* Sgblock structure. */
1892         uchar align[32];        /* Sgblock structure padding. */
1893         struct adv_sgblk *next_sgblkp;  /* Next scatter-gather structure. */
1894 } adv_sgblk_t;
1895
1896 typedef struct adv_req {
1897         ADV_SCSI_REQ_Q scsi_req_q;      /* Adv Library request structure. */
1898         uchar align[32];        /* Request structure padding. */
1899         struct scsi_cmnd *cmndp;        /* Mid-Level SCSI command pointer. */
1900         adv_sgblk_t *sgblkp;    /* Adv Library scatter-gather pointer. */
1901         struct adv_req *next_reqp;      /* Next Request Structure. */
1902 } adv_req_t;
1903
1904 /*
1905  * Adapter operation variable structure.
1906  *
1907  * One structure is required per host adapter.
1908  *
1909  * Field naming convention:
1910  *
1911  *  *_able indicates both whether a feature should be enabled or disabled
1912  *  and whether a device isi capable of the feature. At initialization
1913  *  this field may be set, but later if a device is found to be incapable
1914  *  of the feature, the field is cleared.
1915  */
1916 typedef struct adv_dvc_var {
1917         AdvPortAddr iop_base;   /* I/O port address */
1918         ushort err_code;        /* fatal error code */
1919         ushort bios_ctrl;       /* BIOS control word, EEPROM word 12 */
1920         ushort wdtr_able;       /* try WDTR for a device */
1921         ushort sdtr_able;       /* try SDTR for a device */
1922         ushort ultra_able;      /* try SDTR Ultra speed for a device */
1923         ushort sdtr_speed1;     /* EEPROM SDTR Speed for TID 0-3   */
1924         ushort sdtr_speed2;     /* EEPROM SDTR Speed for TID 4-7   */
1925         ushort sdtr_speed3;     /* EEPROM SDTR Speed for TID 8-11  */
1926         ushort sdtr_speed4;     /* EEPROM SDTR Speed for TID 12-15 */
1927         ushort tagqng_able;     /* try tagged queuing with a device */
1928         ushort ppr_able;        /* PPR message capable per TID bitmask. */
1929         uchar max_dvc_qng;      /* maximum number of tagged commands per device */
1930         ushort start_motor;     /* start motor command allowed */
1931         uchar scsi_reset_wait;  /* delay in seconds after scsi bus reset */
1932         uchar chip_no;          /* should be assigned by caller */
1933         uchar max_host_qng;     /* maximum number of Q'ed command allowed */
1934         ushort no_scam;         /* scam_tolerant of EEPROM */
1935         struct asc_board *drv_ptr;      /* driver pointer to private structure */
1936         uchar chip_scsi_id;     /* chip SCSI target ID */
1937         uchar chip_type;
1938         uchar bist_err_code;
1939         ADV_CARR_T *carrier_buf;
1940         ADV_CARR_T *carr_freelist;      /* Carrier free list. */
1941         ADV_CARR_T *icq_sp;     /* Initiator command queue stopper pointer. */
1942         ADV_CARR_T *irq_sp;     /* Initiator response queue stopper pointer. */
1943         ushort carr_pending_cnt;        /* Count of pending carriers. */
1944         struct adv_req *orig_reqp;      /* adv_req_t memory block. */
1945         /*
1946          * Note: The following fields will not be used after initialization. The
1947          * driver may discard the buffer after initialization is done.
1948          */
1949         ADV_DVC_CFG *cfg;       /* temporary configuration structure  */
1950 } ADV_DVC_VAR;
1951
1952 /*
1953  * Microcode idle loop commands
1954  */
1955 #define IDLE_CMD_COMPLETED           0
1956 #define IDLE_CMD_STOP_CHIP           0x0001
1957 #define IDLE_CMD_STOP_CHIP_SEND_INT  0x0002
1958 #define IDLE_CMD_SEND_INT            0x0004
1959 #define IDLE_CMD_ABORT               0x0008
1960 #define IDLE_CMD_DEVICE_RESET        0x0010
1961 #define IDLE_CMD_SCSI_RESET_START    0x0020     /* Assert SCSI Bus Reset */
1962 #define IDLE_CMD_SCSI_RESET_END      0x0040     /* Deassert SCSI Bus Reset */
1963 #define IDLE_CMD_SCSIREQ             0x0080
1964
1965 #define IDLE_CMD_STATUS_SUCCESS      0x0001
1966 #define IDLE_CMD_STATUS_FAILURE      0x0002
1967
1968 /*
1969  * AdvSendIdleCmd() flag definitions.
1970  */
1971 #define ADV_NOWAIT     0x01
1972
1973 /*
1974  * Wait loop time out values.
1975  */
1976 #define SCSI_WAIT_100_MSEC           100UL      /* 100 milliseconds */
1977 #define SCSI_US_PER_MSEC             1000       /* microseconds per millisecond */
1978 #define SCSI_MAX_RETRY               10 /* retry count */
1979
1980 #define ADV_ASYNC_RDMA_FAILURE          0x01    /* Fatal RDMA failure. */
1981 #define ADV_ASYNC_SCSI_BUS_RESET_DET    0x02    /* Detected SCSI Bus Reset. */
1982 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03    /* Carrier Ready failure. */
1983 #define ADV_RDMA_IN_CARR_AND_Q_INVALID  0x04    /* RDMAed-in data invalid. */
1984
1985 #define ADV_HOST_SCSI_BUS_RESET      0x80       /* Host Initiated SCSI Bus Reset. */
1986
1987 /* Read byte from a register. */
1988 #define AdvReadByteRegister(iop_base, reg_off) \
1989      (ADV_MEM_READB((iop_base) + (reg_off)))
1990
1991 /* Write byte to a register. */
1992 #define AdvWriteByteRegister(iop_base, reg_off, byte) \
1993      (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
1994
1995 /* Read word (2 bytes) from a register. */
1996 #define AdvReadWordRegister(iop_base, reg_off) \
1997      (ADV_MEM_READW((iop_base) + (reg_off)))
1998
1999 /* Write word (2 bytes) to a register. */
2000 #define AdvWriteWordRegister(iop_base, reg_off, word) \
2001      (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
2002
2003 /* Write dword (4 bytes) to a register. */
2004 #define AdvWriteDWordRegister(iop_base, reg_off, dword) \
2005      (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
2006
2007 /* Read byte from LRAM. */
2008 #define AdvReadByteLram(iop_base, addr, byte) \
2009 do { \
2010     ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2011     (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
2012 } while (0)
2013
2014 /* Write byte to LRAM. */
2015 #define AdvWriteByteLram(iop_base, addr, byte) \
2016     (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2017      ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
2018
2019 /* Read word (2 bytes) from LRAM. */
2020 #define AdvReadWordLram(iop_base, addr, word) \
2021 do { \
2022     ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2023     (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
2024 } while (0)
2025
2026 /* Write word (2 bytes) to LRAM. */
2027 #define AdvWriteWordLram(iop_base, addr, word) \
2028     (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2029      ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2030
2031 /* Write little-endian double word (4 bytes) to LRAM */
2032 /* Because of unspecified C language ordering don't use auto-increment. */
2033 #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
2034     ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2035       ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2036                      cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
2037      (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
2038       ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2039                      cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
2040
2041 /* Read word (2 bytes) from LRAM assuming that the address is already set. */
2042 #define AdvReadWordAutoIncLram(iop_base) \
2043      (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
2044
2045 /* Write word (2 bytes) to LRAM assuming that the address is already set. */
2046 #define AdvWriteWordAutoIncLram(iop_base, word) \
2047      (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2048
2049 /*
2050  * Define macro to check for Condor signature.
2051  *
2052  * Evaluate to ADV_TRUE if a Condor chip is found the specified port
2053  * address 'iop_base'. Otherwise evalue to ADV_FALSE.
2054  */
2055 #define AdvFindSignature(iop_base) \
2056     (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
2057     ADV_CHIP_ID_BYTE) && \
2058      (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
2059     ADV_CHIP_ID_WORD)) ?  ADV_TRUE : ADV_FALSE)
2060
2061 /*
2062  * Define macro to Return the version number of the chip at 'iop_base'.
2063  *
2064  * The second parameter 'bus_type' is currently unused.
2065  */
2066 #define AdvGetChipVersion(iop_base, bus_type) \
2067     AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
2068
2069 /*
2070  * Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must
2071  * match the ASC_SCSI_REQ_Q 'srb_ptr' field.
2072  *
2073  * If the request has not yet been sent to the device it will simply be
2074  * aborted from RISC memory. If the request is disconnected it will be
2075  * aborted on reselection by sending an Abort Message to the target ID.
2076  *
2077  * Return value:
2078  *      ADV_TRUE(1) - Queue was successfully aborted.
2079  *      ADV_FALSE(0) - Queue was not found on the active queue list.
2080  */
2081 #define AdvAbortQueue(asc_dvc, scsiq) \
2082         AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
2083                        (ADV_DCNT) (scsiq))
2084
2085 /*
2086  * Send a Bus Device Reset Message to the specified target ID.
2087  *
2088  * All outstanding commands will be purged if sending the
2089  * Bus Device Reset Message is successful.
2090  *
2091  * Return Value:
2092  *      ADV_TRUE(1) - All requests on the target are purged.
2093  *      ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
2094  *                     are not purged.
2095  */
2096 #define AdvResetDevice(asc_dvc, target_id) \
2097         AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
2098                     (ADV_DCNT) (target_id))
2099
2100 /*
2101  * SCSI Wide Type definition.
2102  */
2103 #define ADV_SCSI_BIT_ID_TYPE   ushort
2104
2105 /*
2106  * AdvInitScsiTarget() 'cntl_flag' options.
2107  */
2108 #define ADV_SCAN_LUN           0x01
2109 #define ADV_CAPINFO_NOLUN      0x02
2110
2111 /*
2112  * Convert target id to target id bit mask.
2113  */
2114 #define ADV_TID_TO_TIDMASK(tid)   (0x01 << ((tid) & ADV_MAX_TID))
2115
2116 /*
2117  * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values.
2118  */
2119
2120 #define QD_NO_STATUS         0x00       /* Request not completed yet. */
2121 #define QD_NO_ERROR          0x01
2122 #define QD_ABORTED_BY_HOST   0x02
2123 #define QD_WITH_ERROR        0x04
2124
2125 #define QHSTA_NO_ERROR              0x00
2126 #define QHSTA_M_SEL_TIMEOUT         0x11
2127 #define QHSTA_M_DATA_OVER_RUN       0x12
2128 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
2129 #define QHSTA_M_QUEUE_ABORTED       0x15
2130 #define QHSTA_M_SXFR_SDMA_ERR       0x16        /* SXFR_STATUS SCSI DMA Error */
2131 #define QHSTA_M_SXFR_SXFR_PERR      0x17        /* SXFR_STATUS SCSI Bus Parity Error */
2132 #define QHSTA_M_RDMA_PERR           0x18        /* RISC PCI DMA parity error */
2133 #define QHSTA_M_SXFR_OFF_UFLW       0x19        /* SXFR_STATUS Offset Underflow */
2134 #define QHSTA_M_SXFR_OFF_OFLW       0x20        /* SXFR_STATUS Offset Overflow */
2135 #define QHSTA_M_SXFR_WD_TMO         0x21        /* SXFR_STATUS Watchdog Timeout */
2136 #define QHSTA_M_SXFR_DESELECTED     0x22        /* SXFR_STATUS Deselected */
2137 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
2138 #define QHSTA_M_SXFR_XFR_OFLW       0x12        /* SXFR_STATUS Transfer Overflow */
2139 #define QHSTA_M_SXFR_XFR_PH_ERR     0x24        /* SXFR_STATUS Transfer Phase Error */
2140 #define QHSTA_M_SXFR_UNKNOWN_ERROR  0x25        /* SXFR_STATUS Unknown Error */
2141 #define QHSTA_M_SCSI_BUS_RESET      0x30        /* Request aborted from SBR */
2142 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31       /* Request aborted from unsol. SBR */
2143 #define QHSTA_M_BUS_DEVICE_RESET    0x32        /* Request aborted from BDR */
2144 #define QHSTA_M_DIRECTION_ERR       0x35        /* Data Phase mismatch */
2145 #define QHSTA_M_DIRECTION_ERR_HUNG  0x36        /* Data Phase mismatch and bus hang */
2146 #define QHSTA_M_WTM_TIMEOUT         0x41
2147 #define QHSTA_M_BAD_CMPL_STATUS_IN  0x42
2148 #define QHSTA_M_NO_AUTO_REQ_SENSE   0x43
2149 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
2150 #define QHSTA_M_INVALID_DEVICE      0x45        /* Bad target ID */
2151 #define QHSTA_M_FROZEN_TIDQ         0x46        /* TID Queue frozen. */
2152 #define QHSTA_M_SGBACKUP_ERROR      0x47        /* Scatter-Gather backup error */
2153
2154 /* Return the address that is aligned at the next doubleword >= to 'addr'. */
2155 #define ADV_8BALIGN(addr)      (((ulong) (addr) + 0x7) & ~0x7)
2156 #define ADV_16BALIGN(addr)     (((ulong) (addr) + 0xF) & ~0xF)
2157 #define ADV_32BALIGN(addr)     (((ulong) (addr) + 0x1F) & ~0x1F)
2158
2159 /*
2160  * Total contiguous memory needed for driver SG blocks.
2161  *
2162  * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
2163  * number of scatter-gather elements the driver supports in a
2164  * single request.
2165  */
2166
2167 #define ADV_SG_LIST_MAX_BYTE_SIZE \
2168          (sizeof(ADV_SG_BLOCK) * \
2169           ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
2170
2171 /* struct asc_board flags */
2172 #define ASC_IS_WIDE_BOARD       0x04    /* AdvanSys Wide Board */
2173
2174 #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
2175
2176 #define NO_ISA_DMA              0xff    /* No ISA DMA Channel Used */
2177
2178 #define ASC_INFO_SIZE           128     /* advansys_info() line size */
2179
2180 #ifdef CONFIG_PROC_FS
2181 /* /proc/scsi/advansys/[0...] related definitions */
2182 #define ASC_PRTBUF_SIZE         2048
2183 #define ASC_PRTLINE_SIZE        160
2184
2185 #define ASC_PRT_NEXT() \
2186     if (cp) { \
2187         totlen += len; \
2188         leftlen -= len; \
2189         if (leftlen == 0) { \
2190             return totlen; \
2191         } \
2192         cp += len; \
2193     }
2194 #endif /* CONFIG_PROC_FS */
2195
2196 /* Asc Library return codes */
2197 #define ASC_TRUE        1
2198 #define ASC_FALSE       0
2199 #define ASC_NOERROR     1
2200 #define ASC_BUSY        0
2201 #define ASC_ERROR       (-1)
2202
2203 /* struct scsi_cmnd function return codes */
2204 #define STATUS_BYTE(byte)   (byte)
2205 #define MSG_BYTE(byte)      ((byte) << 8)
2206 #define HOST_BYTE(byte)     ((byte) << 16)
2207 #define DRIVER_BYTE(byte)   ((byte) << 24)
2208
2209 #define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1)
2210 #ifndef ADVANSYS_STATS
2211 #define ASC_STATS_ADD(shost, counter, count)
2212 #else /* ADVANSYS_STATS */
2213 #define ASC_STATS_ADD(shost, counter, count) \
2214         (((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count))
2215 #endif /* ADVANSYS_STATS */
2216
2217 /* If the result wraps when calculating tenths, return 0. */
2218 #define ASC_TENTHS(num, den) \
2219     (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
2220     0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
2221
2222 /*
2223  * Display a message to the console.
2224  */
2225 #define ASC_PRINT(s) \
2226     { \
2227         printk("advansys: "); \
2228         printk(s); \
2229     }
2230
2231 #define ASC_PRINT1(s, a1) \
2232     { \
2233         printk("advansys: "); \
2234         printk((s), (a1)); \
2235     }
2236
2237 #define ASC_PRINT2(s, a1, a2) \
2238     { \
2239         printk("advansys: "); \
2240         printk((s), (a1), (a2)); \
2241     }
2242
2243 #define ASC_PRINT3(s, a1, a2, a3) \
2244     { \
2245         printk("advansys: "); \
2246         printk((s), (a1), (a2), (a3)); \
2247     }
2248
2249 #define ASC_PRINT4(s, a1, a2, a3, a4) \
2250     { \
2251         printk("advansys: "); \
2252         printk((s), (a1), (a2), (a3), (a4)); \
2253     }
2254
2255 #ifndef ADVANSYS_DEBUG
2256
2257 #define ASC_DBG(lvl, s...)
2258 #define ASC_DBG_PRT_SCSI_HOST(lvl, s)
2259 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
2260 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2261 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
2262 #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2263 #define ASC_DBG_PRT_HEX(lvl, name, start, length)
2264 #define ASC_DBG_PRT_CDB(lvl, cdb, len)
2265 #define ASC_DBG_PRT_SENSE(lvl, sense, len)
2266 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
2267
2268 #else /* ADVANSYS_DEBUG */
2269
2270 /*
2271  * Debugging Message Levels:
2272  * 0: Errors Only
2273  * 1: High-Level Tracing
2274  * 2-N: Verbose Tracing
2275  */
2276
2277 #define ASC_DBG(lvl, format, arg...) {                                  \
2278         if (asc_dbglvl >= (lvl))                                        \
2279                 printk(KERN_DEBUG "%s: %s: " format, DRV_NAME,          \
2280                         __FUNCTION__ , ## arg);                         \
2281 }
2282
2283 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
2284     { \
2285         if (asc_dbglvl >= (lvl)) { \
2286             asc_prt_scsi_host(s); \
2287         } \
2288     }
2289
2290 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
2291     { \
2292         if (asc_dbglvl >= (lvl)) { \
2293             asc_prt_asc_scsi_q(scsiqp); \
2294         } \
2295     }
2296
2297 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
2298     { \
2299         if (asc_dbglvl >= (lvl)) { \
2300             asc_prt_asc_qdone_info(qdone); \
2301         } \
2302     }
2303
2304 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
2305     { \
2306         if (asc_dbglvl >= (lvl)) { \
2307             asc_prt_adv_scsi_req_q(scsiqp); \
2308         } \
2309     }
2310
2311 #define ASC_DBG_PRT_HEX(lvl, name, start, length) \
2312     { \
2313         if (asc_dbglvl >= (lvl)) { \
2314             asc_prt_hex((name), (start), (length)); \
2315         } \
2316     }
2317
2318 #define ASC_DBG_PRT_CDB(lvl, cdb, len) \
2319         ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
2320
2321 #define ASC_DBG_PRT_SENSE(lvl, sense, len) \
2322         ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
2323
2324 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
2325         ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
2326 #endif /* ADVANSYS_DEBUG */
2327
2328 #ifdef ADVANSYS_STATS
2329
2330 /* Per board statistics structure */
2331 struct asc_stats {
2332         /* Driver Entrypoint Statistics */
2333         ADV_DCNT queuecommand;  /* # calls to advansys_queuecommand() */
2334         ADV_DCNT reset;         /* # calls to advansys_eh_bus_reset() */
2335         ADV_DCNT biosparam;     /* # calls to advansys_biosparam() */
2336         ADV_DCNT interrupt;     /* # advansys_interrupt() calls */
2337         ADV_DCNT callback;      /* # calls to asc/adv_isr_callback() */
2338         ADV_DCNT done;          /* # calls to request's scsi_done function */
2339         ADV_DCNT build_error;   /* # asc/adv_build_req() ASC_ERROR returns. */
2340         ADV_DCNT adv_build_noreq;       /* # adv_build_req() adv_req_t alloc. fail. */
2341         ADV_DCNT adv_build_nosg;        /* # adv_build_req() adv_sgblk_t alloc. fail. */
2342         /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
2343         ADV_DCNT exe_noerror;   /* # ASC_NOERROR returns. */
2344         ADV_DCNT exe_busy;      /* # ASC_BUSY returns. */
2345         ADV_DCNT exe_error;     /* # ASC_ERROR returns. */
2346         ADV_DCNT exe_unknown;   /* # unknown returns. */
2347         /* Data Transfer Statistics */
2348         ADV_DCNT xfer_cnt;      /* # I/O requests received */
2349         ADV_DCNT xfer_elem;     /* # scatter-gather elements */
2350         ADV_DCNT xfer_sect;     /* # 512-byte blocks */
2351 };
2352 #endif /* ADVANSYS_STATS */
2353
2354 /*
2355  * Structure allocated for each board.
2356  *
2357  * This structure is allocated by scsi_host_alloc() at the end
2358  * of the 'Scsi_Host' structure starting at the 'hostdata'
2359  * field. It is guaranteed to be allocated from DMA-able memory.
2360  */
2361 struct asc_board {
2362         struct device *dev;
2363         uint flags;             /* Board flags */
2364         unsigned int irq;
2365         union {
2366                 ASC_DVC_VAR asc_dvc_var;        /* Narrow board */
2367                 ADV_DVC_VAR adv_dvc_var;        /* Wide board */
2368         } dvc_var;
2369         union {
2370                 ASC_DVC_CFG asc_dvc_cfg;        /* Narrow board */
2371                 ADV_DVC_CFG adv_dvc_cfg;        /* Wide board */
2372         } dvc_cfg;
2373         ushort asc_n_io_port;   /* Number I/O ports. */
2374         ADV_SCSI_BIT_ID_TYPE init_tidmask;      /* Target init./valid mask */
2375         ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
2376         ADV_SCSI_BIT_ID_TYPE queue_full;        /* Queue full mask */
2377         ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
2378         union {
2379                 ASCEEP_CONFIG asc_eep;  /* Narrow EEPROM config. */
2380                 ADVEEP_3550_CONFIG adv_3550_eep;        /* 3550 EEPROM config. */
2381                 ADVEEP_38C0800_CONFIG adv_38C0800_eep;  /* 38C0800 EEPROM config. */
2382                 ADVEEP_38C1600_CONFIG adv_38C1600_eep;  /* 38C1600 EEPROM config. */
2383         } eep_config;
2384         ulong last_reset;       /* Saved last reset time */
2385         /* /proc/scsi/advansys/[0...] */
2386         char *prtbuf;           /* /proc print buffer */
2387 #ifdef ADVANSYS_STATS
2388         struct asc_stats asc_stats;     /* Board statistics */
2389 #endif                          /* ADVANSYS_STATS */
2390         /*
2391          * The following fields are used only for Narrow Boards.
2392          */
2393         uchar sdtr_data[ASC_MAX_TID + 1];       /* SDTR information */
2394         /*
2395          * The following fields are used only for Wide Boards.
2396          */
2397         void __iomem *ioremap_addr;     /* I/O Memory remap address. */
2398         ushort ioport;          /* I/O Port address. */
2399         adv_req_t *adv_reqp;    /* Request structures. */
2400         adv_sgblk_t *adv_sgblkp;        /* Scatter-gather structures. */
2401         ushort bios_signature;  /* BIOS Signature. */
2402         ushort bios_version;    /* BIOS Version. */
2403         ushort bios_codeseg;    /* BIOS Code Segment. */
2404         ushort bios_codelen;    /* BIOS Code Segment Length. */
2405 };
2406
2407 #define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
2408                                                         dvc_var.adv_dvc_var)
2409 #define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
2410
2411 /* Overrun buffer used by all narrow boards. */
2412 static uchar overrun_buf[ASC_OVERRUN_BSIZE] = { 0 };
2413
2414 #ifdef ADVANSYS_DEBUG
2415 static int asc_dbglvl = 3;
2416
2417 /*
2418  * asc_prt_asc_dvc_var()
2419  */
2420 static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
2421 {
2422         printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
2423
2424         printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
2425                "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
2426
2427         printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type,
2428                 (unsigned)h->init_sdtr);
2429
2430         printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
2431                "chip_no 0x%x,\n", (unsigned)h->sdtr_done,
2432                (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready,
2433                (unsigned)h->chip_no);
2434
2435         printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
2436                "%u,\n", (unsigned)h->queue_full_or_busy,
2437                (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2438
2439         printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
2440                "in_critical_cnt %u,\n", (unsigned)h->is_in_int,
2441                (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng,
2442                (unsigned)h->in_critical_cnt);
2443
2444         printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
2445                "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage,
2446                (unsigned)h->init_state, (unsigned)h->no_scam,
2447                (unsigned)h->pci_fix_asyn_xfer);
2448
2449         printk(" cfg 0x%lx\n", (ulong)h->cfg);
2450 }
2451
2452 /*
2453  * asc_prt_asc_dvc_cfg()
2454  */
2455 static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
2456 {
2457         printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
2458
2459         printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
2460                h->can_tagged_qng, h->cmd_qng_enabled);
2461         printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
2462                h->disc_enable, h->sdtr_enable);
2463
2464         printk(" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, "
2465                 "chip_version %d,\n", h->chip_scsi_id, h->isa_dma_speed,
2466                 h->isa_dma_channel, h->chip_version);
2467
2468         printk(" mcode_date 0x%x, mcode_version %d, overrun_buf 0x%p\n",
2469                 h->mcode_date, h->mcode_version, h->overrun_buf);
2470 }
2471
2472 /*
2473  * asc_prt_adv_dvc_var()
2474  *
2475  * Display an ADV_DVC_VAR structure.
2476  */
2477 static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
2478 {
2479         printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
2480
2481         printk("  iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
2482                (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
2483
2484         printk("  sdtr_able 0x%x, wdtr_able 0x%x\n",
2485                (unsigned)h->sdtr_able, (unsigned)h->wdtr_able);
2486
2487         printk("  start_motor 0x%x, scsi_reset_wait 0x%x\n",
2488                (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2489
2490         printk("  max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%lxn\n",
2491                (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
2492                (ulong)h->carr_freelist);
2493
2494         printk("  icq_sp 0x%lx, irq_sp 0x%lx\n",
2495                (ulong)h->icq_sp, (ulong)h->irq_sp);
2496
2497         printk("  no_scam 0x%x, tagqng_able 0x%x\n",
2498                (unsigned)h->no_scam, (unsigned)h->tagqng_able);
2499
2500         printk("  chip_scsi_id 0x%x, cfg 0x%lx\n",
2501                (unsigned)h->chip_scsi_id, (ulong)h->cfg);
2502 }
2503
2504 /*
2505  * asc_prt_adv_dvc_cfg()
2506  *
2507  * Display an ADV_DVC_CFG structure.
2508  */
2509 static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
2510 {
2511         printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
2512
2513         printk("  disc_enable 0x%x, termination 0x%x\n",
2514                h->disc_enable, h->termination);
2515
2516         printk("  chip_version 0x%x, mcode_date 0x%x\n",
2517                h->chip_version, h->mcode_date);
2518
2519         printk("  mcode_version 0x%x, control_flag 0x%x\n",
2520                h->mcode_version, h->control_flag);
2521 }
2522
2523 /*
2524  * asc_prt_scsi_host()
2525  */
2526 static void asc_prt_scsi_host(struct Scsi_Host *s)
2527 {
2528         struct asc_board *boardp = shost_priv(s);
2529
2530         printk("Scsi_Host at addr 0x%p, device %s\n", s, boardp->dev->bus_id);
2531         printk(" host_busy %u, host_no %d, last_reset %d,\n",
2532                s->host_busy, s->host_no, (unsigned)s->last_reset);
2533
2534         printk(" base 0x%lx, io_port 0x%lx, irq %d,\n",
2535                (ulong)s->base, (ulong)s->io_port, boardp->irq);
2536
2537         printk(" dma_channel %d, this_id %d, can_queue %d,\n",
2538                s->dma_channel, s->this_id, s->can_queue);
2539
2540         printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
2541                s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
2542
2543         if (ASC_NARROW_BOARD(boardp)) {
2544                 asc_prt_asc_dvc_var(&boardp->dvc_var.asc_dvc_var);
2545                 asc_prt_asc_dvc_cfg(&boardp->dvc_cfg.asc_dvc_cfg);
2546         } else {
2547                 asc_prt_adv_dvc_var(&boardp->dvc_var.adv_dvc_var);
2548                 asc_prt_adv_dvc_cfg(&boardp->dvc_cfg.adv_dvc_cfg);
2549         }
2550 }
2551
2552 /*
2553  * asc_prt_hex()
2554  *
2555  * Print hexadecimal output in 4 byte groupings 32 bytes
2556  * or 8 double-words per line.
2557  */
2558 static void asc_prt_hex(char *f, uchar *s, int l)
2559 {
2560         int i;
2561         int j;
2562         int k;
2563         int m;
2564
2565         printk("%s: (%d bytes)\n", f, l);
2566
2567         for (i = 0; i < l; i += 32) {
2568
2569                 /* Display a maximum of 8 double-words per line. */
2570                 if ((k = (l - i) / 4) >= 8) {
2571                         k = 8;
2572                         m = 0;
2573                 } else {
2574                         m = (l - i) % 4;
2575                 }
2576
2577                 for (j = 0; j < k; j++) {
2578                         printk(" %2.2X%2.2X%2.2X%2.2X",
2579                                (unsigned)s[i + (j * 4)],
2580                                (unsigned)s[i + (j * 4) + 1],
2581                                (unsigned)s[i + (j * 4) + 2],
2582                                (unsigned)s[i + (j * 4) + 3]);
2583                 }
2584
2585                 switch (m) {
2586                 case 0:
2587                 default:
2588                         break;
2589                 case 1:
2590                         printk(" %2.2X", (unsigned)s[i + (j * 4)]);
2591                         break;
2592                 case 2:
2593                         printk(" %2.2X%2.2X",
2594                                (unsigned)s[i + (j * 4)],
2595                                (unsigned)s[i + (j * 4) + 1]);
2596                         break;
2597                 case 3:
2598                         printk(" %2.2X%2.2X%2.2X",
2599                                (unsigned)s[i + (j * 4) + 1],
2600                                (unsigned)s[i + (j * 4) + 2],
2601                                (unsigned)s[i + (j * 4) + 3]);
2602                         break;
2603                 }
2604
2605                 printk("\n");
2606         }
2607 }
2608
2609 /*
2610  * asc_prt_asc_scsi_q()
2611  */
2612 static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
2613 {
2614         ASC_SG_HEAD *sgp;
2615         int i;
2616
2617         printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
2618
2619         printk
2620             (" target_ix 0x%x, target_lun %u, srb_ptr 0x%lx, tag_code 0x%x,\n",
2621              q->q2.target_ix, q->q1.target_lun, (ulong)q->q2.srb_ptr,
2622              q->q2.tag_code);
2623
2624         printk
2625             (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2626              (ulong)le32_to_cpu(q->q1.data_addr),
2627              (ulong)le32_to_cpu(q->q1.data_cnt),
2628              (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
2629
2630         printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
2631                (ulong)q->cdbptr, q->q2.cdb_len,
2632                (ulong)q->sg_head, q->q1.sg_queue_cnt);
2633
2634         if (q->sg_head) {
2635                 sgp = q->sg_head;
2636                 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
2637                 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
2638                        sgp->queue_cnt);
2639                 for (i = 0; i < sgp->entry_cnt; i++) {
2640                         printk(" [%u]: addr 0x%lx, bytes %lu\n",
2641                                i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
2642                                (ulong)le32_to_cpu(sgp->sg_list[i].bytes));
2643                 }
2644
2645         }
2646 }
2647
2648 /*
2649  * asc_prt_asc_qdone_info()
2650  */
2651 static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
2652 {
2653         printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
2654         printk(" srb_ptr 0x%lx, target_ix %u, cdb_len %u, tag_code %u,\n",
2655                (ulong)q->d2.srb_ptr, q->d2.target_ix, q->d2.cdb_len,
2656                q->d2.tag_code);
2657         printk
2658             (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
2659              q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
2660 }
2661
2662 /*
2663  * asc_prt_adv_sgblock()
2664  *
2665  * Display an ADV_SG_BLOCK structure.
2666  */
2667 static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
2668 {
2669         int i;
2670
2671         printk(" ASC_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
2672                (ulong)b, sgblockno);
2673         printk("  sg_cnt %u, sg_ptr 0x%lx\n",
2674                b->sg_cnt, (ulong)le32_to_cpu(b->sg_ptr));
2675         BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK);
2676         if (b->sg_ptr != 0)
2677                 BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK);
2678         for (i = 0; i < b->sg_cnt; i++) {
2679                 printk("  [%u]: sg_addr 0x%lx, sg_count 0x%lx\n",
2680                        i, (ulong)b->sg_list[i].sg_addr,
2681                        (ulong)b->sg_list[i].sg_count);
2682         }
2683 }
2684
2685 /*
2686  * asc_prt_adv_scsi_req_q()
2687  *
2688  * Display an ADV_SCSI_REQ_Q structure.
2689  */
2690 static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
2691 {
2692         int sg_blk_cnt;
2693         struct asc_sg_block *sg_ptr;
2694
2695         printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
2696
2697         printk("  target_id %u, target_lun %u, srb_ptr 0x%lx, a_flag 0x%x\n",
2698                q->target_id, q->target_lun, (ulong)q->srb_ptr, q->a_flag);
2699
2700         printk("  cntl 0x%x, data_addr 0x%lx, vdata_addr 0x%lx\n",
2701                q->cntl, (ulong)le32_to_cpu(q->data_addr), (ulong)q->vdata_addr);
2702
2703         printk("  data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2704                (ulong)le32_to_cpu(q->data_cnt),
2705                (ulong)le32_to_cpu(q->sense_addr), q->sense_len);
2706
2707         printk
2708             ("  cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
2709              q->cdb_len, q->done_status, q->host_status, q->scsi_status);
2710
2711         printk("  sg_working_ix 0x%x, target_cmd %u\n",
2712                q->sg_working_ix, q->target_cmd);
2713
2714         printk("  scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
2715                (ulong)le32_to_cpu(q->scsiq_rptr),
2716                (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
2717
2718         /* Display the request's ADV_SG_BLOCK structures. */
2719         if (q->sg_list_ptr != NULL) {
2720                 sg_blk_cnt = 0;
2721                 while (1) {
2722                         /*
2723                          * 'sg_ptr' is a physical address. Convert it to a virtual
2724                          * address by indexing 'sg_blk_cnt' into the virtual address
2725                          * array 'sg_list_ptr'.
2726                          *
2727                          * XXX - Assumes all SG physical blocks are virtually contiguous.
2728                          */
2729                         sg_ptr =
2730                             &(((ADV_SG_BLOCK *)(q->sg_list_ptr))[sg_blk_cnt]);
2731                         asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
2732                         if (sg_ptr->sg_ptr == 0) {
2733                                 break;
2734                         }
2735                         sg_blk_cnt++;
2736                 }
2737         }
2738 }
2739 #endif /* ADVANSYS_DEBUG */
2740
2741 /*
2742  * The advansys chip/microcode contains a 32-bit identifier for each command
2743  * known as the 'srb'.  I don't know what it stands for.  The driver used
2744  * to encode the scsi_cmnd pointer by calling virt_to_bus and retrieve it
2745  * with bus_to_virt.  Now the driver keeps a per-host map of integers to
2746  * pointers.  It auto-expands when full, unless it can't allocate memory.
2747  * Note that an srb of 0 is treated specially by the chip/firmware, hence
2748  * the return of i+1 in this routine, and the corresponding subtraction in
2749  * the inverse routine.
2750  */
2751 #define BAD_SRB 0
2752 static u32 advansys_ptr_to_srb(struct asc_dvc_var *asc_dvc, void *ptr)
2753 {
2754         int i;
2755         void **new_ptr;
2756
2757         for (i = 0; i < asc_dvc->ptr_map_count; i++) {
2758                 if (!asc_dvc->ptr_map[i])
2759                         goto out;
2760         }
2761
2762         if (asc_dvc->ptr_map_count == 0)
2763                 asc_dvc->ptr_map_count = 1;
2764         else
2765                 asc_dvc->ptr_map_count *= 2;
2766
2767         new_ptr = krealloc(asc_dvc->ptr_map,
2768                         asc_dvc->ptr_map_count * sizeof(void *), GFP_ATOMIC);
2769         if (!new_ptr)
2770                 return BAD_SRB;
2771         asc_dvc->ptr_map = new_ptr;
2772  out:
2773         ASC_DBG(3, "Putting ptr %p into array offset %d\n", ptr, i);
2774         asc_dvc->ptr_map[i] = ptr;
2775         return i + 1;
2776 }
2777
2778 static void * advansys_srb_to_ptr(struct asc_dvc_var *asc_dvc, u32 srb)
2779 {
2780         void *ptr;
2781
2782         srb--;
2783         if (srb >= asc_dvc->ptr_map_count) {
2784                 printk("advansys: bad SRB %u, max %u\n", srb,
2785                                                         asc_dvc->ptr_map_count);
2786                 return NULL;
2787         }
2788         ptr = asc_dvc->ptr_map[srb];
2789         asc_dvc->ptr_map[srb] = NULL;
2790         ASC_DBG(3, "Returning ptr %p from array offset %d\n", ptr, srb);
2791         return ptr;
2792 }
2793
2794 /*
2795  * advansys_info()
2796  *
2797  * Return suitable for printing on the console with the argument
2798  * adapter's configuration information.
2799  *
2800  * Note: The information line should not exceed ASC_INFO_SIZE bytes,
2801  * otherwise the static 'info' array will be overrun.
2802  */
2803 static const char *advansys_info(struct Scsi_Host *shost)
2804 {
2805         static char info[ASC_INFO_SIZE];
2806         struct asc_board *boardp = shost_priv(shost);
2807         ASC_DVC_VAR *asc_dvc_varp;
2808         ADV_DVC_VAR *adv_dvc_varp;
2809         char *busname;
2810         char *widename = NULL;
2811
2812         if (ASC_NARROW_BOARD(boardp)) {
2813                 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2814                 ASC_DBG(1, "begin\n");
2815                 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
2816                         if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) ==
2817                             ASC_IS_ISAPNP) {
2818                                 busname = "ISA PnP";
2819                         } else {
2820                                 busname = "ISA";
2821                         }
2822                         sprintf(info,
2823                                 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
2824                                 ASC_VERSION, busname,
2825                                 (ulong)shost->io_port,
2826                                 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2827                                 boardp->irq, shost->dma_channel);
2828                 } else {
2829                         if (asc_dvc_varp->bus_type & ASC_IS_VL) {
2830                                 busname = "VL";
2831                         } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
2832                                 busname = "EISA";
2833                         } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
2834                                 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
2835                                     == ASC_IS_PCI_ULTRA) {
2836                                         busname = "PCI Ultra";
2837                                 } else {
2838                                         busname = "PCI";
2839                                 }
2840                         } else {
2841                                 busname = "?";
2842                                 shost_printk(KERN_ERR, shost, "unknown bus "
2843                                         "type %d\n", asc_dvc_varp->bus_type);
2844                         }
2845                         sprintf(info,
2846                                 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
2847                                 ASC_VERSION, busname, (ulong)shost->io_port,
2848                                 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2849                                 boardp->irq);
2850                 }
2851         } else {
2852                 /*
2853                  * Wide Adapter Information
2854                  *
2855                  * Memory-mapped I/O is used instead of I/O space to access
2856                  * the adapter, but display the I/O Port range. The Memory
2857                  * I/O address is displayed through the driver /proc file.
2858                  */
2859                 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
2860                 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2861                         widename = "Ultra-Wide";
2862                 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2863                         widename = "Ultra2-Wide";
2864                 } else {
2865                         widename = "Ultra3-Wide";
2866                 }
2867                 sprintf(info,
2868                         "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
2869                         ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
2870                         (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, boardp->irq);
2871         }
2872         BUG_ON(strlen(info) >= ASC_INFO_SIZE);
2873         ASC_DBG(1, "end\n");
2874         return info;
2875 }
2876
2877 #ifdef CONFIG_PROC_FS
2878 /*
2879  * asc_prt_line()
2880  *
2881  * If 'cp' is NULL print to the console, otherwise print to a buffer.
2882  *
2883  * Return 0 if printing to the console, otherwise return the number of
2884  * bytes written to the buffer.
2885  *
2886  * Note: If any single line is greater than ASC_PRTLINE_SIZE bytes the stack
2887  * will be corrupted. 's[]' is defined to be ASC_PRTLINE_SIZE bytes.
2888  */
2889 static int asc_prt_line(char *buf, int buflen, char *fmt, ...)
2890 {
2891         va_list args;
2892         int ret;
2893         char s[ASC_PRTLINE_SIZE];
2894
2895         va_start(args, fmt);
2896         ret = vsprintf(s, fmt, args);
2897         BUG_ON(ret >= ASC_PRTLINE_SIZE);
2898         if (buf == NULL) {
2899                 (void)printk(s);
2900                 ret = 0;
2901         } else {
2902                 ret = min(buflen, ret);
2903                 memcpy(buf, s, ret);
2904         }
2905         va_end(args);
2906         return ret;
2907 }
2908
2909 /*
2910  * asc_prt_board_devices()
2911  *
2912  * Print driver information for devices attached to the board.
2913  *
2914  * Note: no single line should be greater than ASC_PRTLINE_SIZE,
2915  * cf. asc_prt_line().
2916  *
2917  * Return the number of characters copied into 'cp'. No more than
2918  * 'cplen' characters will be copied to 'cp'.
2919  */
2920 static int asc_prt_board_devices(struct Scsi_Host *shost, char *cp, int cplen)
2921 {
2922         struct asc_board *boardp = shost_priv(shost);
2923         int leftlen;
2924         int totlen;
2925         int len;
2926         int chip_scsi_id;
2927         int i;
2928
2929         leftlen = cplen;
2930         totlen = len = 0;
2931
2932         len = asc_prt_line(cp, leftlen,
2933                            "\nDevice Information for AdvanSys SCSI Host %d:\n",
2934                            shost->host_no);
2935         ASC_PRT_NEXT();
2936
2937         if (ASC_NARROW_BOARD(boardp)) {
2938                 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
2939         } else {
2940                 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
2941         }
2942
2943         len = asc_prt_line(cp, leftlen, "Target IDs Detected:");
2944         ASC_PRT_NEXT();
2945         for (i = 0; i <= ADV_MAX_TID; i++) {
2946                 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) {
2947                         len = asc_prt_line(cp, leftlen, " %X,", i);
2948                         ASC_PRT_NEXT();
2949                 }
2950         }
2951         len = asc_prt_line(cp, leftlen, " (%X=Host Adapter)\n", chip_scsi_id);
2952         ASC_PRT_NEXT();
2953
2954         return totlen;
2955 }
2956
2957 /*
2958  * Display Wide Board BIOS Information.
2959  */
2960 static int asc_prt_adv_bios(struct Scsi_Host *shost, char *cp, int cplen)
2961 {
2962         struct asc_board *boardp = shost_priv(shost);
2963         int leftlen;
2964         int totlen;
2965         int len;
2966         ushort major, minor, letter;
2967
2968         leftlen = cplen;
2969         totlen = len = 0;
2970
2971         len = asc_prt_line(cp, leftlen, "\nROM BIOS Version: ");
2972         ASC_PRT_NEXT();
2973
2974         /*
2975          * If the BIOS saved a valid signature, then fill in
2976          * the BIOS code segment base address.
2977          */
2978         if (boardp->bios_signature != 0x55AA) {
2979                 len = asc_prt_line(cp, leftlen, "Disabled or Pre-3.1\n");
2980                 ASC_PRT_NEXT();
2981                 len = asc_prt_line(cp, leftlen,
2982                                    "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n");
2983                 ASC_PRT_NEXT();
2984                 len = asc_prt_line(cp, leftlen,
2985                                    "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
2986                 ASC_PRT_NEXT();
2987         } else {
2988                 major = (boardp->bios_version >> 12) & 0xF;
2989                 minor = (boardp->bios_version >> 8) & 0xF;
2990                 letter = (boardp->bios_version & 0xFF);
2991
2992                 len = asc_prt_line(cp, leftlen, "%d.%d%c\n",
2993                                    major, minor,
2994                                    letter >= 26 ? '?' : letter + 'A');
2995                 ASC_PRT_NEXT();
2996
2997                 /*
2998                  * Current available ROM BIOS release is 3.1I for UW
2999                  * and 3.2I for U2W. This code doesn't differentiate
3000                  * UW and U2W boards.
3001                  */
3002                 if (major < 3 || (major <= 3 && minor < 1) ||
3003                     (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
3004                         len = asc_prt_line(cp, leftlen,
3005                                            "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n");
3006                         ASC_PRT_NEXT();
3007                         len = asc_prt_line(cp, leftlen,
3008                                            "ftp://ftp.connectcom.net/pub\n");
3009                         ASC_PRT_NEXT();
3010                 }
3011         }
3012
3013         return totlen;
3014 }
3015
3016 /*
3017  * Add serial number to information bar if signature AAh
3018  * is found in at bit 15-9 (7 bits) of word 1.
3019  *
3020  * Serial Number consists fo 12 alpha-numeric digits.
3021  *
3022  *       1 - Product type (A,B,C,D..)  Word0: 15-13 (3 bits)
3023  *       2 - MFG Location (A,B,C,D..)  Word0: 12-10 (3 bits)
3024  *     3-4 - Product ID (0-99)         Word0: 9-0 (10 bits)
3025  *       5 - Product revision (A-J)    Word0:  "         "
3026  *
3027  *           Signature                 Word1: 15-9 (7 bits)
3028  *       6 - Year (0-9)                Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
3029  *     7-8 - Week of the year (1-52)   Word1: 5-0 (6 bits)
3030  *
3031  *    9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
3032  *
3033  * Note 1: Only production cards will have a serial number.
3034  *
3035  * Note 2: Signature is most significant 7 bits (0xFE).
3036  *
3037  * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
3038  */
3039 static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
3040 {
3041         ushort w, num;
3042
3043         if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
3044                 return ASC_FALSE;
3045         } else {
3046                 /*
3047                  * First word - 6 digits.
3048                  */
3049                 w = serialnum[0];
3050
3051                 /* Product type - 1st digit. */
3052                 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
3053                         /* Product type is P=Prototype */
3054                         *cp += 0x8;
3055                 }
3056                 cp++;
3057
3058                 /* Manufacturing location - 2nd digit. */
3059                 *cp++ = 'A' + ((w & 0x1C00) >> 10);
3060
3061                 /* Product ID - 3rd, 4th digits. */
3062                 num = w & 0x3FF;
3063                 *cp++ = '0' + (num / 100);
3064                 num %= 100;
3065                 *cp++ = '0' + (num / 10);
3066
3067                 /* Product revision - 5th digit. */
3068                 *cp++ = 'A' + (num % 10);
3069
3070                 /*
3071                  * Second word
3072                  */
3073                 w = serialnum[1];
3074
3075                 /*
3076                  * Year - 6th digit.
3077                  *
3078                  * If bit 15 of third word is set, then the
3079                  * last digit of the year is greater than 7.
3080                  */
3081                 if (serialnum[2] & 0x8000) {
3082                         *cp++ = '8' + ((w & 0x1C0) >> 6);
3083                 } else {
3084                         *cp++ = '0' + ((w & 0x1C0) >> 6);
3085                 }
3086
3087                 /* Week of year - 7th, 8th digits. */
3088                 num = w & 0x003F;
3089                 *cp++ = '0' + num / 10;
3090                 num %= 10;
3091                 *cp++ = '0' + num;
3092
3093                 /*
3094                  * Third word
3095                  */
3096                 w = serialnum[2] & 0x7FFF;
3097
3098                 /* Serial number - 9th digit. */
3099                 *cp++ = 'A' + (w / 1000);
3100
3101                 /* 10th, 11th, 12th digits. */
3102                 num = w % 1000;
3103                 *cp++ = '0' + num / 100;
3104                 num %= 100;
3105                 *cp++ = '0' + num / 10;
3106                 num %= 10;
3107                 *cp++ = '0' + num;
3108
3109                 *cp = '\0';     /* Null Terminate the string. */
3110                 return ASC_TRUE;
3111         }
3112 }
3113
3114 /*
3115  * asc_prt_asc_board_eeprom()
3116  *
3117  * Print board EEPROM configuration.
3118  *
3119  * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3120  * cf. asc_prt_line().
3121  *
3122  * Return the number of characters copied into 'cp'. No more than
3123  * 'cplen' characters will be copied to 'cp'.
3124  */
3125 static int asc_prt_asc_board_eeprom(struct Scsi_Host *shost, char *cp, int cplen)
3126 {
3127         struct asc_board *boardp = shost_priv(shost);
3128         ASC_DVC_VAR *asc_dvc_varp;
3129         int leftlen;
3130         int totlen;
3131         int len;
3132         ASCEEP_CONFIG *ep;
3133         int i;
3134 #ifdef CONFIG_ISA
3135         int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
3136 #endif /* CONFIG_ISA */
3137         uchar serialstr[13];
3138
3139         asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
3140         ep = &boardp->eep_config.asc_eep;
3141
3142         leftlen = cplen;
3143         totlen = len = 0;
3144
3145         len = asc_prt_line(cp, leftlen,
3146                            "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3147                            shost->host_no);
3148         ASC_PRT_NEXT();
3149
3150         if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
3151             == ASC_TRUE) {
3152                 len =
3153                     asc_prt_line(cp, leftlen, " Serial Number: %s\n",
3154                                  serialstr);
3155                 ASC_PRT_NEXT();
3156         } else {
3157                 if (ep->adapter_info[5] == 0xBB) {
3158                         len = asc_prt_line(cp, leftlen,
3159                                            " Default Settings Used for EEPROM-less Adapter.\n");
3160                         ASC_PRT_NEXT();
3161                 } else {
3162                         len = asc_prt_line(cp, leftlen,
3163                                            " Serial Number Signature Not Present.\n");
3164                         ASC_PRT_NEXT();
3165                 }
3166         }
3167
3168         len = asc_prt_line(cp, leftlen,
3169                            " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3170                            ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
3171                            ep->max_tag_qng);
3172         ASC_PRT_NEXT();
3173
3174         len = asc_prt_line(cp, leftlen,
3175                            " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
3176         ASC_PRT_NEXT();
3177
3178         len = asc_prt_line(cp, leftlen, " Target ID:           ");
3179         ASC_PRT_NEXT();
3180         for (i = 0; i <= ASC_MAX_TID; i++) {
3181                 len = asc_prt_line(cp, leftlen, " %d", i);
3182                 ASC_PRT_NEXT();
3183         }
3184         len = asc_prt_line(cp, leftlen, "\n");
3185         ASC_PRT_NEXT();
3186
3187         len = asc_prt_line(cp, leftlen, " Disconnects:         ");
3188         ASC_PRT_NEXT();
3189         for (i = 0; i <= ASC_MAX_TID; i++) {
3190                 len = asc_prt_line(cp, leftlen, " %c",
3191                                    (ep->
3192                                     disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3193                                    'N');
3194                 ASC_PRT_NEXT();
3195         }
3196         len = asc_prt_line(cp, leftlen, "\n");
3197         ASC_PRT_NEXT();
3198
3199         len = asc_prt_line(cp, leftlen, " Command Queuing:     ");
3200         ASC_PRT_NEXT();
3201         for (i = 0; i <= ASC_MAX_TID; i++) {
3202                 len = asc_prt_line(cp, leftlen, " %c",
3203                                    (ep->
3204                                     use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3205                                    'N');
3206                 ASC_PRT_NEXT();
3207         }
3208         len = asc_prt_line(cp, leftlen, "\n");
3209         ASC_PRT_NEXT();
3210
3211         len = asc_prt_line(cp, leftlen, " Start Motor:         ");
3212         ASC_PRT_NEXT();
3213         for (i = 0; i <= ASC_MAX_TID; i++) {
3214                 len = asc_prt_line(cp, leftlen, " %c",
3215                                    (ep->
3216                                     start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3217                                    'N');
3218                 ASC_PRT_NEXT();
3219         }
3220         len = asc_prt_line(cp, leftlen, "\n");
3221         ASC_PRT_NEXT();
3222
3223         len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
3224         ASC_PRT_NEXT();
3225         for (i = 0; i <= ASC_MAX_TID; i++) {
3226                 len = asc_prt_line(cp, leftlen, " %c",
3227                                    (ep->
3228                                     init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3229                                    'N');
3230                 ASC_PRT_NEXT();
3231         }
3232         len = asc_prt_line(cp, leftlen, "\n");
3233         ASC_PRT_NEXT();
3234
3235 #ifdef CONFIG_ISA
3236         if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
3237                 len = asc_prt_line(cp, leftlen,
3238                                    " Host ISA DMA speed:   %d MB/S\n",
3239                                    isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
3240                 ASC_PRT_NEXT();
3241         }
3242 #endif /* CONFIG_ISA */
3243
3244         return totlen;
3245 }
3246
3247 /*
3248  * asc_prt_adv_board_eeprom()
3249  *
3250  * Print board EEPROM configuration.
3251  *
3252  * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3253  * cf. asc_prt_line().
3254  *
3255  * Return the number of characters copied into 'cp'. No more than
3256  * 'cplen' characters will be copied to 'cp'.
3257  */
3258 static int asc_prt_adv_board_eeprom(struct Scsi_Host *shost, char *cp, int cplen)
3259 {
3260         struct asc_board *boardp = shost_priv(shost);
3261         ADV_DVC_VAR *adv_dvc_varp;
3262         int leftlen;
3263         int totlen;
3264         int len;
3265         int i;
3266         char *termstr;
3267         uchar serialstr[13];
3268         ADVEEP_3550_CONFIG *ep_3550 = NULL;
3269         ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
3270         ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
3271         ushort word;
3272         ushort *wordp;
3273         ushort sdtr_speed = 0;
3274
3275         adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
3276         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3277                 ep_3550 = &boardp->eep_config.adv_3550_eep;
3278         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3279                 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
3280         } else {
3281                 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
3282         }
3283
3284         leftlen = cplen;
3285         totlen = len = 0;
3286
3287         len = asc_prt_line(cp, leftlen,
3288                            "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3289                            shost->host_no);
3290         ASC_PRT_NEXT();
3291
3292         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3293                 wordp = &ep_3550->serial_number_word1;
3294         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3295                 wordp = &ep_38C0800->serial_number_word1;
3296         } else {
3297                 wordp = &ep_38C1600->serial_number_word1;
3298         }
3299
3300         if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE) {
3301                 len =
3302                     asc_prt_line(cp, leftlen, " Serial Number: %s\n",
3303                                  serialstr);
3304                 ASC_PRT_NEXT();
3305         } else {
3306                 len = asc_prt_line(cp, leftlen,
3307                                    " Serial Number Signature Not Present.\n");
3308                 ASC_PRT_NEXT();
3309         }
3310
3311         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3312                 len = asc_prt_line(cp, leftlen,
3313                                    " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3314                                    ep_3550->adapter_scsi_id,
3315                                    ep_3550->max_host_qng, ep_3550->max_dvc_qng);
3316                 ASC_PRT_NEXT();
3317         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3318                 len = asc_prt_line(cp, leftlen,
3319                                    " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3320                                    ep_38C0800->adapter_scsi_id,
3321                                    ep_38C0800->max_host_qng,
3322                                    ep_38C0800->max_dvc_qng);
3323                 ASC_PRT_NEXT();
3324         } else {
3325                 len = asc_prt_line(cp, leftlen,
3326                                    " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3327                                    ep_38C1600->adapter_scsi_id,
3328                                    ep_38C1600->max_host_qng,
3329                                    ep_38C1600->max_dvc_qng);
3330                 ASC_PRT_NEXT();
3331         }
3332         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3333                 word = ep_3550->termination;
3334         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3335                 word = ep_38C0800->termination_lvd;
3336         } else {
3337                 word = ep_38C1600->termination_lvd;
3338         }
3339         switch (word) {
3340         case 1:
3341                 termstr = "Low Off/High Off";
3342                 break;
3343         case 2:
3344                 termstr = "Low Off/High On";
3345                 break;
3346         case 3:
3347                 termstr = "Low On/High On";
3348                 break;
3349         default:
3350         case 0:
3351                 termstr = "Automatic";
3352                 break;
3353         }
3354
3355         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3356                 len = asc_prt_line(cp, leftlen,
3357                                    " termination: %u (%s), bios_ctrl: 0x%x\n",
3358                                    ep_3550->termination, termstr,
3359                                    ep_3550->bios_ctrl);
3360                 ASC_PRT_NEXT();
3361         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3362                 len = asc_prt_line(cp, leftlen,
3363                                    " termination: %u (%s), bios_ctrl: 0x%x\n",
3364                                    ep_38C0800->termination_lvd, termstr,
3365                                    ep_38C0800->bios_ctrl);
3366                 ASC_PRT_NEXT();
3367         } else {
3368                 len = asc_prt_line(cp, leftlen,
3369                                    " termination: %u (%s), bios_ctrl: 0x%x\n",
3370                                    ep_38C1600->termination_lvd, termstr,
3371                                    ep_38C1600->bios_ctrl);
3372                 ASC_PRT_NEXT();
3373         }
3374
3375         len = asc_prt_line(cp, leftlen, " Target ID:           ");
3376         ASC_PRT_NEXT();
3377         for (i = 0; i <= ADV_MAX_TID; i++) {
3378                 len = asc_prt_line(cp, leftlen, " %X", i);
3379                 ASC_PRT_NEXT();
3380         }
3381         len = asc_prt_line(cp, leftlen, "\n");
3382         ASC_PRT_NEXT();
3383
3384         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3385                 word = ep_3550->disc_enable;
3386         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3387                 word = ep_38C0800->disc_enable;
3388         } else {
3389                 word = ep_38C1600->disc_enable;
3390         }
3391         len = asc_prt_line(cp, leftlen, " Disconnects:         ");
3392         ASC_PRT_NEXT();
3393         for (i = 0; i <= ADV_MAX_TID; i++) {
3394                 len = asc_prt_line(cp, leftlen, " %c",
3395                                    (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3396                 ASC_PRT_NEXT();
3397         }
3398         len = asc_prt_line(cp, leftlen, "\n");
3399         ASC_PRT_NEXT();
3400
3401         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3402                 word = ep_3550->tagqng_able;
3403         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3404                 word = ep_38C0800->tagqng_able;
3405         } else {
3406                 word = ep_38C1600->tagqng_able;
3407         }
3408         len = asc_prt_line(cp, leftlen, " Command Queuing:     ");
3409         ASC_PRT_NEXT();
3410         for (i = 0; i <= ADV_MAX_TID; i++) {
3411                 len = asc_prt_line(cp, leftlen, " %c",
3412                                    (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3413                 ASC_PRT_NEXT();
3414         }
3415         len = asc_prt_line(cp, leftlen, "\n");
3416         ASC_PRT_NEXT();
3417
3418         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3419                 word = ep_3550->start_motor;
3420         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3421                 word = ep_38C0800->start_motor;
3422         } else {
3423                 word = ep_38C1600->start_motor;
3424         }
3425         len = asc_prt_line(cp, leftlen, " Start Motor:         ");
3426         ASC_PRT_NEXT();
3427         for (i = 0; i <= ADV_MAX_TID; i++) {
3428                 len = asc_prt_line(cp, leftlen, " %c",
3429                                    (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3430                 ASC_PRT_NEXT();
3431         }
3432         len = asc_prt_line(cp, leftlen, "\n");
3433         ASC_PRT_NEXT();
3434
3435         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3436                 len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
3437                 ASC_PRT_NEXT();
3438                 for (i = 0; i <= ADV_MAX_TID; i++) {
3439                         len = asc_prt_line(cp, leftlen, " %c",
3440                                            (ep_3550->
3441                                             sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
3442                                            'Y' : 'N');
3443                         ASC_PRT_NEXT();
3444                 }
3445                 len = asc_prt_line(cp, leftlen, "\n");
3446                 ASC_PRT_NEXT();
3447         }
3448
3449         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3450                 len = asc_prt_line(cp, leftlen, " Ultra Transfer:      ");
3451                 ASC_PRT_NEXT();
3452                 for (i = 0; i <= ADV_MAX_TID; i++) {
3453                         len = asc_prt_line(cp, leftlen, " %c",
3454                                            (ep_3550->
3455                                             ultra_able & ADV_TID_TO_TIDMASK(i))
3456                                            ? 'Y' : 'N');
3457                         ASC_PRT_NEXT();
3458                 }
3459                 len = asc_prt_line(cp, leftlen, "\n");
3460                 ASC_PRT_NEXT();
3461         }
3462
3463         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3464                 word = ep_3550->wdtr_able;
3465         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3466                 word = ep_38C0800->wdtr_able;
3467         } else {
3468                 word = ep_38C1600->wdtr_able;
3469         }
3470         len = asc_prt_line(cp, leftlen, " Wide Transfer:       ");
3471         ASC_PRT_NEXT();
3472         for (i = 0; i <= ADV_MAX_TID; i++) {
3473                 len = asc_prt_line(cp, leftlen, " %c",
3474                                    (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3475                 ASC_PRT_NEXT();
3476         }
3477         len = asc_prt_line(cp, leftlen, "\n");
3478         ASC_PRT_NEXT();
3479
3480         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
3481             adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
3482                 len = asc_prt_line(cp, leftlen,
3483                                    " Synchronous Transfer Speed (Mhz):\n  ");
3484                 ASC_PRT_NEXT();
3485                 for (i = 0; i <= ADV_MAX_TID; i++) {
3486                         char *speed_str;
3487
3488                         if (i == 0) {
3489                                 sdtr_speed = adv_dvc_varp->sdtr_speed1;
3490                         } else if (i == 4) {
3491                                 sdtr_speed = adv_dvc_varp->sdtr_speed2;
3492                         } else if (i == 8) {
3493                                 sdtr_speed = adv_dvc_varp->sdtr_speed3;
3494                         } else if (i == 12) {
3495                                 sdtr_speed = adv_dvc_varp->sdtr_speed4;
3496                         }
3497                         switch (sdtr_speed & ADV_MAX_TID) {
3498                         case 0:
3499                                 speed_str = "Off";
3500                                 break;
3501                         case 1:
3502                                 speed_str = "  5";
3503                                 break;
3504                         case 2:
3505                                 speed_str = " 10";
3506                                 break;
3507                         case 3:
3508                                 speed_str = " 20";
3509                                 break;
3510                         case 4:
3511                                 speed_str = " 40";
3512                                 break;
3513                         case 5:
3514                                 speed_str = " 80";
3515                                 break;
3516                         default:
3517                                 speed_str = "Unk";
3518                                 break;
3519                         }
3520                         len = asc_prt_line(cp, leftlen, "%X:%s ", i, speed_str);
3521                         ASC_PRT_NEXT();
3522                         if (i == 7) {
3523                                 len = asc_prt_line(cp, leftlen, "\n  ");
3524                                 ASC_PRT_NEXT();
3525                         }
3526                         sdtr_speed >>= 4;
3527                 }
3528                 len = asc_prt_line(cp, leftlen, "\n");
3529                 ASC_PRT_NEXT();
3530         }
3531
3532         return totlen;
3533 }
3534
3535 /*
3536  * asc_prt_driver_conf()
3537  *
3538  * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3539  * cf. asc_prt_line().
3540  *
3541  * Return the number of characters copied into 'cp'. No more than
3542  * 'cplen' characters will be copied to 'cp'.
3543  */
3544 static int asc_prt_driver_conf(struct Scsi_Host *shost, char *cp, int cplen)
3545 {
3546         struct asc_board *boardp = shost_priv(shost);
3547         int leftlen;
3548         int totlen;
3549         int len;
3550         int chip_scsi_id;
3551
3552         leftlen = cplen;
3553         totlen = len = 0;
3554
3555         len = asc_prt_line(cp, leftlen,
3556                            "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
3557                            shost->host_no);
3558         ASC_PRT_NEXT();
3559
3560         len = asc_prt_line(cp, leftlen,
3561                            " host_busy %u, last_reset %u, max_id %u, max_lun %u, max_channel %u\n",
3562                            shost->host_busy, shost->last_reset, shost->max_id,
3563                            shost->max_lun, shost->max_channel);
3564         ASC_PRT_NEXT();
3565
3566         len = asc_prt_line(cp, leftlen,
3567                            " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
3568                            shost->unique_id, shost->can_queue, shost->this_id,
3569                            shost->sg_tablesize, shost->cmd_per_lun);
3570         ASC_PRT_NEXT();
3571
3572         len = asc_prt_line(cp, leftlen,
3573                            " unchecked_isa_dma %d, use_clustering %d\n",
3574                            shost->unchecked_isa_dma, shost->use_clustering);
3575         ASC_PRT_NEXT();
3576
3577         len = asc_prt_line(cp, leftlen,
3578                            " flags 0x%x, last_reset 0x%x, jiffies 0x%x, asc_n_io_port 0x%x\n",
3579                            boardp->flags, boardp->last_reset, jiffies,
3580                            boardp->asc_n_io_port);
3581         ASC_PRT_NEXT();
3582
3583         len = asc_prt_line(cp, leftlen, " io_port 0x%x\n", shost->io_port);
3584         ASC_PRT_NEXT();
3585
3586         if (ASC_NARROW_BOARD(boardp)) {
3587                 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
3588         } else {
3589                 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
3590         }
3591
3592         return totlen;
3593 }
3594
3595 /*
3596  * asc_prt_asc_board_info()
3597  *
3598  * Print dynamic board configuration information.
3599  *
3600  * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3601  * cf. asc_prt_line().
3602  *
3603  * Return the number of characters copied into 'cp'. No more than
3604  * 'cplen' characters will be copied to 'cp'.
3605  */
3606 static int asc_prt_asc_board_info(struct Scsi_Host *shost, char *cp, int cplen)
3607 {
3608         struct asc_board *boardp = shost_priv(shost);
3609         int chip_scsi_id;
3610         int leftlen;
3611         int totlen;
3612         int len;
3613         ASC_DVC_VAR *v;
3614         ASC_DVC_CFG *c;
3615         int i;
3616         int renegotiate = 0;
3617
3618         v = &boardp->dvc_var.asc_dvc_var;
3619         c = &boardp->dvc_cfg.asc_dvc_cfg;
3620         chip_scsi_id = c->chip_scsi_id;
3621
3622         leftlen = cplen;
3623         totlen = len = 0;
3624
3625         len = asc_prt_line(cp, leftlen,
3626                            "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3627                            shost->host_no);
3628         ASC_PRT_NEXT();
3629
3630         len = asc_prt_line(cp, leftlen, " chip_version %u, mcode_date 0x%x, "
3631                            "mcode_version 0x%x, err_code %u\n",
3632                            c->chip_version, c->mcode_date, c->mcode_version,
3633                            v->err_code);
3634         ASC_PRT_NEXT();
3635
3636         /* Current number of commands waiting for the host. */
3637         len = asc_prt_line(cp, leftlen,
3638                            " Total Command Pending: %d\n", v->cur_total_qng);
3639         ASC_PRT_NEXT();
3640
3641         len = asc_prt_line(cp, leftlen, " Command Queuing:");
3642         ASC_PRT_NEXT();
3643         for (i = 0; i <= ASC_MAX_TID; i++) {
3644                 if ((chip_scsi_id == i) ||
3645                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3646                         continue;
3647                 }
3648                 len = asc_prt_line(cp, leftlen, " %X:%c",
3649                                    i,
3650                                    (v->
3651                                     use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ?
3652                                    'Y' : 'N');
3653                 ASC_PRT_NEXT();
3654         }
3655         len = asc_prt_line(cp, leftlen, "\n");
3656         ASC_PRT_NEXT();
3657
3658         /* Current number of commands waiting for a device. */
3659         len = asc_prt_line(cp, leftlen, " Command Queue Pending:");
3660         ASC_PRT_NEXT();
3661         for (i = 0; i <= ASC_MAX_TID; i++) {
3662                 if ((chip_scsi_id == i) ||
3663                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3664                         continue;
3665                 }
3666                 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->cur_dvc_qng[i]);
3667                 ASC_PRT_NEXT();
3668         }
3669         len = asc_prt_line(cp, leftlen, "\n");
3670         ASC_PRT_NEXT();
3671
3672         /* Current limit on number of commands that can be sent to a device. */
3673         len = asc_prt_line(cp, leftlen, " Command Queue Limit:");
3674         ASC_PRT_NEXT();
3675         for (i = 0; i <= ASC_MAX_TID; i++) {
3676                 if ((chip_scsi_id == i) ||
3677                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3678                         continue;
3679                 }
3680                 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->max_dvc_qng[i]);
3681                 ASC_PRT_NEXT();
3682         }
3683         len = asc_prt_line(cp, leftlen, "\n");
3684         ASC_PRT_NEXT();
3685
3686         /* Indicate whether the device has returned queue full status. */
3687         len = asc_prt_line(cp, leftlen, " Command Queue Full:");
3688         ASC_PRT_NEXT();
3689         for (i = 0; i <= ASC_MAX_TID; i++) {
3690                 if ((chip_scsi_id == i) ||
3691                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3692                         continue;
3693                 }
3694                 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i)) {
3695                         len = asc_prt_line(cp, leftlen, " %X:Y-%d",
3696                                            i, boardp->queue_full_cnt[i]);
3697                 } else {
3698                         len = asc_prt_line(cp, leftlen, " %X:N", i);
3699                 }
3700                 ASC_PRT_NEXT();
3701         }
3702         len = asc_prt_line(cp, leftlen, "\n");
3703         ASC_PRT_NEXT();
3704
3705         len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
3706         ASC_PRT_NEXT();
3707         for (i = 0; i <= ASC_MAX_TID; i++) {
3708                 if ((chip_scsi_id == i) ||
3709                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3710                         continue;
3711                 }
3712                 len = asc_prt_line(cp, leftlen, " %X:%c",
3713                                    i,
3714                                    (v->
3715                                     sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3716                                    'N');
3717                 ASC_PRT_NEXT();
3718         }
3719         len = asc_prt_line(cp, leftlen, "\n");
3720         ASC_PRT_NEXT();
3721
3722         for (i = 0; i <= ASC_MAX_TID; i++) {
3723                 uchar syn_period_ix;
3724
3725                 if ((chip_scsi_id == i) ||
3726                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3727                     ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
3728                         continue;
3729                 }
3730
3731                 len = asc_prt_line(cp, leftlen, "  %X:", i);
3732                 ASC_PRT_NEXT();
3733
3734                 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
3735                         len = asc_prt_line(cp, leftlen, " Asynchronous");
3736                         ASC_PRT_NEXT();
3737                 } else {
3738                         syn_period_ix =
3739                             (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
3740                                                            1);
3741
3742                         len = asc_prt_line(cp, leftlen,
3743                                            " Transfer Period Factor: %d (%d.%d Mhz),",
3744                                            v->sdtr_period_tbl[syn_period_ix],
3745                                            250 /
3746                                            v->sdtr_period_tbl[syn_period_ix],
3747                                            ASC_TENTHS(250,
3748                                                       v->
3749                                                       sdtr_period_tbl
3750                                                       [syn_period_ix]));
3751                         ASC_PRT_NEXT();
3752
3753                         len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
3754                                            boardp->
3755                                            sdtr_data[i] & ASC_SYN_MAX_OFFSET);
3756                         ASC_PRT_NEXT();
3757                 }
3758
3759                 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3760                         len = asc_prt_line(cp, leftlen, "*\n");
3761                         renegotiate = 1;
3762                 } else {
3763                         len = asc_prt_line(cp, leftlen, "\n");
3764                 }
3765                 ASC_PRT_NEXT();
3766         }
3767
3768         if (renegotiate) {
3769                 len = asc_prt_line(cp, leftlen,
3770                                    " * = Re-negotiation pending before next command.\n");
3771                 ASC_PRT_NEXT();
3772         }
3773
3774         return totlen;
3775 }
3776
3777 /*
3778  * asc_prt_adv_board_info()
3779  *
3780  * Print dynamic board configuration information.
3781  *
3782  * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3783  * cf. asc_prt_line().
3784  *
3785  * Return the number of characters copied into 'cp'. No more than
3786  * 'cplen' characters will be copied to 'cp'.
3787  */
3788 static int asc_prt_adv_board_info(struct Scsi_Host *shost, char *cp, int cplen)
3789 {
3790         struct asc_board *boardp = shost_priv(shost);
3791         int leftlen;
3792         int totlen;
3793         int len;
3794         int i;
3795         ADV_DVC_VAR *v;
3796         ADV_DVC_CFG *c;
3797         AdvPortAddr iop_base;
3798         ushort chip_scsi_id;
3799         ushort lramword;
3800         uchar lrambyte;
3801         ushort tagqng_able;
3802         ushort sdtr_able, wdtr_able;
3803         ushort wdtr_done, sdtr_done;
3804         ushort period = 0;
3805         int renegotiate = 0;
3806
3807         v = &boardp->dvc_var.adv_dvc_var;
3808         c = &boardp->dvc_cfg.adv_dvc_cfg;
3809         iop_base = v->iop_base;
3810         chip_scsi_id = v->chip_scsi_id;
3811
3812         leftlen = cplen;
3813         totlen = len = 0;
3814
3815         len = asc_prt_line(cp, leftlen,
3816                            "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3817                            shost->host_no);
3818         ASC_PRT_NEXT();
3819
3820         len = asc_prt_line(cp, leftlen,
3821                            " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
3822                            v->iop_base,
3823                            AdvReadWordRegister(iop_base,
3824                                                IOPW_SCSI_CFG1) & CABLE_DETECT,
3825                            v->err_code);
3826         ASC_PRT_NEXT();
3827
3828         len = asc_prt_line(cp, leftlen, " chip_version %u, mcode_date 0x%x, "
3829                            "mcode_version 0x%x\n", c->chip_version,
3830                            c->mcode_date, c->mcode_version);
3831         ASC_PRT_NEXT();
3832
3833         AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
3834         len = asc_prt_line(cp, leftlen, " Queuing Enabled:");
3835         ASC_PRT_NEXT();
3836         for (i = 0; i <= ADV_MAX_TID; i++) {
3837                 if ((chip_scsi_id == i) ||
3838                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3839                         continue;
3840                 }
3841
3842                 len = asc_prt_line(cp, leftlen, " %X:%c",
3843                                    i,
3844                                    (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3845                                    'N');
3846                 ASC_PRT_NEXT();
3847         }
3848         len = asc_prt_line(cp, leftlen, "\n");
3849         ASC_PRT_NEXT();
3850
3851         len = asc_prt_line(cp, leftlen, " Queue Limit:");
3852         ASC_PRT_NEXT();
3853         for (i = 0; i <= ADV_MAX_TID; i++) {
3854                 if ((chip_scsi_id == i) ||
3855                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3856                         continue;
3857                 }
3858
3859                 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
3860                                 lrambyte);
3861
3862                 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
3863                 ASC_PRT_NEXT();
3864         }
3865         len = asc_prt_line(cp, leftlen, "\n");
3866         ASC_PRT_NEXT();
3867
3868         len = asc_prt_line(cp, leftlen, " Command Pending:");
3869         ASC_PRT_NEXT();
3870         for (i = 0; i <= ADV_MAX_TID; i++) {
3871                 if ((chip_scsi_id == i) ||
3872                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3873                         continue;
3874                 }
3875
3876                 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
3877                                 lrambyte);
3878
3879                 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
3880                 ASC_PRT_NEXT();
3881         }
3882         len = asc_prt_line(cp, leftlen, "\n");
3883         ASC_PRT_NEXT();
3884
3885         AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
3886         len = asc_prt_line(cp, leftlen, " Wide Enabled:");
3887         ASC_PRT_NEXT();
3888         for (i = 0; i <= ADV_MAX_TID; i++) {
3889                 if ((chip_scsi_id == i) ||
3890                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3891                         continue;
3892                 }
3893
3894                 len = asc_prt_line(cp, leftlen, " %X:%c",
3895                                    i,
3896                                    (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3897                                    'N');
3898                 ASC_PRT_NEXT();
3899         }
3900         len = asc_prt_line(cp, leftlen, "\n");
3901         ASC_PRT_NEXT();
3902
3903         AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
3904         len = asc_prt_line(cp, leftlen, " Transfer Bit Width:");
3905         ASC_PRT_NEXT();
3906         for (i = 0; i <= ADV_MAX_TID; i++) {
3907                 if ((chip_scsi_id == i) ||
3908                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3909                         continue;
3910                 }
3911
3912                 AdvReadWordLram(iop_base,
3913                                 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3914                                 lramword);
3915
3916                 len = asc_prt_line(cp, leftlen, " %X:%d",
3917                                    i, (lramword & 0x8000) ? 16 : 8);
3918                 ASC_PRT_NEXT();
3919
3920                 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
3921                     (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3922                         len = asc_prt_line(cp, leftlen, "*");
3923                         ASC_PRT_NEXT();
3924                         renegotiate = 1;
3925                 }
3926         }
3927         len = asc_prt_line(cp, leftlen, "\n");
3928         ASC_PRT_NEXT();
3929
3930         AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
3931         len = asc_prt_line(cp, leftlen, " Synchronous Enabled:");
3932         ASC_PRT_NEXT();
3933         for (i = 0; i <= ADV_MAX_TID; i++) {
3934                 if ((chip_scsi_id == i) ||
3935                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3936                         continue;
3937                 }
3938
3939                 len = asc_prt_line(cp, leftlen, " %X:%c",
3940                                    i,
3941                                    (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3942                                    'N');
3943                 ASC_PRT_NEXT();
3944         }
3945         len = asc_prt_line(cp, leftlen, "\n");
3946         ASC_PRT_NEXT();
3947
3948         AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
3949         for (i = 0; i <= ADV_MAX_TID; i++) {
3950
3951                 AdvReadWordLram(iop_base,
3952                                 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3953                                 lramword);
3954                 lramword &= ~0x8000;
3955
3956                 if ((chip_scsi_id == i) ||
3957                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3958                     ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
3959                         continue;
3960                 }
3961
3962                 len = asc_prt_line(cp, leftlen, "  %X:", i);
3963                 ASC_PRT_NEXT();
3964
3965                 if ((lramword & 0x1F) == 0) {   /* Check for REQ/ACK Offset 0. */
3966                         len = asc_prt_line(cp, leftlen, " Asynchronous");
3967                         ASC_PRT_NEXT();
3968                 } else {
3969                         len =
3970                             asc_prt_line(cp, leftlen,
3971                                          " Transfer Period Factor: ");
3972                         ASC_PRT_NEXT();
3973
3974                         if ((lramword & 0x1F00) == 0x1100) {    /* 80 Mhz */
3975                                 len =
3976                                     asc_prt_line(cp, leftlen, "9 (80.0 Mhz),");
3977                                 ASC_PRT_NEXT();
3978                         } else if ((lramword & 0x1F00) == 0x1000) {     /* 40 Mhz */
3979                                 len =
3980                                     asc_prt_line(cp, leftlen, "10 (40.0 Mhz),");
3981                                 ASC_PRT_NEXT();
3982                         } else {        /* 20 Mhz or below. */
3983
3984                                 period = (((lramword >> 8) * 25) + 50) / 4;
3985
3986                                 if (period == 0) {      /* Should never happen. */
3987                                         len =
3988                                             asc_prt_line(cp, leftlen,
3989                                                          "%d (? Mhz), ");
3990                                         ASC_PRT_NEXT();
3991                                 } else {
3992                                         len = asc_prt_line(cp, leftlen,
3993                                                            "%d (%d.%d Mhz),",
3994                                                            period, 250 / period,
3995                                                            ASC_TENTHS(250,
3996                                                                       period));
3997                                         ASC_PRT_NEXT();
3998                                 }
3999                         }
4000
4001                         len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
4002                                            lramword & 0x1F);
4003                         ASC_PRT_NEXT();
4004                 }
4005
4006                 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
4007                         len = asc_prt_line(cp, leftlen, "*\n");
4008                         renegotiate = 1;
4009                 } else {
4010                         len = asc_prt_line(cp, leftlen, "\n");
4011                 }
4012                 ASC_PRT_NEXT();
4013         }
4014
4015         if (renegotiate) {
4016                 len = asc_prt_line(cp, leftlen,
4017                                    " * = Re-negotiation pending before next command.\n");
4018                 ASC_PRT_NEXT();
4019         }
4020
4021         return totlen;
4022 }
4023
4024 /*
4025  * asc_proc_copy()
4026  *
4027  * Copy proc information to a read buffer taking into account the current
4028  * read offset in the file and the remaining space in the read buffer.
4029  */
4030 static int
4031 asc_proc_copy(off_t advoffset, off_t offset, char *curbuf, int leftlen,
4032               char *cp, int cplen)
4033 {
4034         int cnt = 0;
4035
4036         ASC_DBG(2, "offset %d, advoffset %d, cplen %d\n",
4037                  (unsigned)offset, (unsigned)advoffset, cplen);
4038         if (offset <= advoffset) {
4039                 /* Read offset below current offset, copy everything. */
4040                 cnt = min(cplen, leftlen);
4041                 ASC_DBG(2, "curbuf 0x%lx, cp 0x%lx, cnt %d\n",
4042                          (ulong)curbuf, (ulong)cp, cnt);
4043                 memcpy(curbuf, cp, cnt);
4044         } else if (offset < advoffset + cplen) {
4045                 /* Read offset within current range, partial copy. */
4046                 cnt = (advoffset + cplen) - offset;
4047                 cp = (cp + cplen) - cnt;
4048                 cnt = min(cnt, leftlen);
4049                 ASC_DBG(2, "curbuf 0x%lx, cp 0x%lx, cnt %d\n",
4050                          (ulong)curbuf, (ulong)cp, cnt);
4051                 memcpy(curbuf, cp, cnt);
4052         }
4053         return cnt;
4054 }
4055
4056 #ifdef ADVANSYS_STATS
4057 /*
4058  * asc_prt_board_stats()
4059  *
4060  * Note: no single line should be greater than ASC_PRTLINE_SIZE,
4061  * cf. asc_prt_line().
4062  *
4063  * Return the number of characters copied into 'cp'. No more than
4064  * 'cplen' characters will be copied to 'cp'.
4065  */
4066 static int asc_prt_board_stats(struct Scsi_Host *shost, char *cp, int cplen)
4067 {
4068         struct asc_board *boardp = shost_priv(shost);
4069         struct asc_stats *s = &boardp->asc_stats;
4070
4071         int leftlen = cplen;
4072         int len, totlen = 0;
4073
4074         len = asc_prt_line(cp, leftlen,
4075                            "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
4076                            shost->host_no);
4077         ASC_PRT_NEXT();
4078
4079         len = asc_prt_line(cp, leftlen,
4080                            " queuecommand %lu, reset %lu, biosparam %lu, interrupt %lu\n",
4081                            s->queuecommand, s->reset, s->biosparam,
4082                            s->interrupt);
4083         ASC_PRT_NEXT();
4084
4085         len = asc_prt_line(cp, leftlen,
4086                            " callback %lu, done %lu, build_error %lu, build_noreq %lu, build_nosg %lu\n",
4087                            s->callback, s->done, s->build_error,
4088                            s->adv_build_noreq, s->adv_build_nosg);
4089         ASC_PRT_NEXT();
4090
4091         len = asc_prt_line(cp, leftlen,
4092                            " exe_noerror %lu, exe_busy %lu, exe_error %lu, exe_unknown %lu\n",
4093                            s->exe_noerror, s->exe_busy, s->exe_error,
4094                            s->exe_unknown);
4095         ASC_PRT_NEXT();
4096
4097         /*
4098          * Display data transfer statistics.
4099          */
4100         if (s->xfer_cnt > 0) {
4101                 len = asc_prt_line(cp, leftlen, " xfer_cnt %lu, xfer_elem %lu, ",
4102                                    s->xfer_cnt, s->xfer_elem);
4103                 ASC_PRT_NEXT();
4104
4105                 len = asc_prt_line(cp, leftlen, "xfer_bytes %lu.%01lu kb\n",
4106                                    s->xfer_sect / 2, ASC_TENTHS(s->xfer_sect, 2));
4107                 ASC_PRT_NEXT();
4108
4109                 /* Scatter gather transfer statistics */
4110                 len = asc_prt_line(cp, leftlen, " avg_num_elem %lu.%01lu, ",
4111                                    s->xfer_elem / s->xfer_cnt,
4112                                    ASC_TENTHS(s->xfer_elem, s->xfer_cnt));
4113                 ASC_PRT_NEXT();
4114
4115                 len = asc_prt_line(cp, leftlen, "avg_elem_size %lu.%01lu kb, ",
4116                                    (s->xfer_sect / 2) / s->xfer_elem,
4117                                    ASC_TENTHS((s->xfer_sect / 2), s->xfer_elem));
4118                 ASC_PRT_NEXT();
4119
4120                 len = asc_prt_line(cp, leftlen, "avg_xfer_size %lu.%01lu kb\n",
4121                                    (s->xfer_sect / 2) / s->xfer_cnt,
4122                                    ASC_TENTHS((s->xfer_sect / 2), s->xfer_cnt));
4123                 ASC_PRT_NEXT();
4124         }
4125
4126         return totlen;
4127 }
4128 #endif /* ADVANSYS_STATS */
4129
4130 /*
4131  * advansys_proc_info() - /proc/scsi/advansys/{0,1,2,3,...}
4132  *
4133  * *buffer: I/O buffer
4134  * **start: if inout == FALSE pointer into buffer where user read should start
4135  * offset: current offset into a /proc/scsi/advansys/[0...] file
4136  * length: length of buffer
4137  * hostno: Scsi_Host host_no
4138  * inout: TRUE - user is writing; FALSE - user is reading
4139  *
4140  * Return the number of bytes read from or written to a
4141  * /proc/scsi/advansys/[0...] file.
4142  *
4143  * Note: This function uses the per board buffer 'prtbuf' which is
4144  * allocated when the board is initialized in advansys_detect(). The
4145  * buffer is ASC_PRTBUF_SIZE bytes. The function asc_proc_copy() is
4146  * used to write to the buffer. The way asc_proc_copy() is written
4147  * if 'prtbuf' is too small it will not be overwritten. Instead the
4148  * user just won't get all the available statistics.
4149  */
4150 static int
4151 advansys_proc_info(struct Scsi_Host *shost, char *buffer, char **start,
4152                    off_t offset, int length, int inout)
4153 {
4154         struct asc_board *boardp = shost_priv(shost);
4155         char *cp;
4156         int cplen;
4157         int cnt;
4158         int totcnt;
4159         int leftlen;
4160         char *curbuf;
4161         off_t advoffset;
4162
4163         ASC_DBG(1, "begin\n");
4164
4165         /*
4166          * User write not supported.
4167          */
4168         if (inout == TRUE)
4169                 return -ENOSYS;
4170
4171         /*
4172          * User read of /proc/scsi/advansys/[0...] file.
4173          */
4174
4175         /* Copy read data starting at the beginning of the buffer. */
4176         *start = buffer;
4177         curbuf = buffer;
4178         advoffset = 0;
4179         totcnt = 0;
4180         leftlen = length;
4181
4182         /*
4183          * Get board configuration information.
4184          *
4185          * advansys_info() returns the board string from its own static buffer.
4186          */
4187         cp = (char *)advansys_info(shost);
4188         strcat(cp, "\n");
4189         cplen = strlen(cp);
4190         /* Copy board information. */
4191         cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4192         totcnt += cnt;
4193         leftlen -= cnt;
4194         if (leftlen == 0) {
4195                 ASC_DBG(1, "totcnt %d\n", totcnt);
4196                 return totcnt;
4197         }
4198         advoffset += cplen;
4199         curbuf += cnt;
4200
4201         /*
4202          * Display Wide Board BIOS Information.
4203          */
4204         if (!ASC_NARROW_BOARD(boardp)) {
4205                 cp = boardp->prtbuf;
4206                 cplen = asc_prt_adv_bios(shost, cp, ASC_PRTBUF_SIZE);
4207                 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4208                 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp,
4209                                   cplen);
4210                 totcnt += cnt;
4211                 leftlen -= cnt;
4212                 if (leftlen == 0) {
4213                         ASC_DBG(1, "totcnt %d\n", totcnt);
4214                         return totcnt;
4215                 }
4216                 advoffset += cplen;
4217                 curbuf += cnt;
4218         }
4219
4220         /*
4221          * Display driver information for each device attached to the board.
4222          */
4223         cp = boardp->prtbuf;
4224         cplen = asc_prt_board_devices(shost, cp, ASC_PRTBUF_SIZE);
4225         BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4226         cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4227         totcnt += cnt;
4228         leftlen -= cnt;
4229         if (leftlen == 0) {
4230                 ASC_DBG(1, "totcnt %d\n", totcnt);
4231                 return totcnt;
4232         }
4233         advoffset += cplen;
4234         curbuf += cnt;
4235
4236         /*
4237          * Display EEPROM configuration for the board.
4238          */
4239         cp = boardp->prtbuf;
4240         if (ASC_NARROW_BOARD(boardp)) {
4241                 cplen = asc_prt_asc_board_eeprom(shost, cp, ASC_PRTBUF_SIZE);
4242         } else {
4243                 cplen = asc_prt_adv_board_eeprom(shost, cp, ASC_PRTBUF_SIZE);
4244         }
4245         BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4246         cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4247         totcnt += cnt;
4248         leftlen -= cnt;
4249         if (leftlen == 0) {
4250                 ASC_DBG(1, "totcnt %d\n", totcnt);
4251                 return totcnt;
4252         }
4253         advoffset += cplen;
4254         curbuf += cnt;
4255
4256         /*
4257          * Display driver configuration and information for the board.
4258          */
4259         cp = boardp->prtbuf;
4260         cplen = asc_prt_driver_conf(shost, cp, ASC_PRTBUF_SIZE);
4261         BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4262         cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4263         totcnt += cnt;
4264         leftlen -= cnt;
4265         if (leftlen == 0) {
4266                 ASC_DBG(1, "totcnt %d\n", totcnt);
4267                 return totcnt;
4268         }
4269         advoffset += cplen;
4270         curbuf += cnt;
4271
4272 #ifdef ADVANSYS_STATS
4273         /*
4274          * Display driver statistics for the board.
4275          */
4276         cp = boardp->prtbuf;
4277         cplen = asc_prt_board_stats(shost, cp, ASC_PRTBUF_SIZE);
4278         BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4279         cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4280         totcnt += cnt;
4281         leftlen -= cnt;
4282         if (leftlen == 0) {
4283                 ASC_DBG(1, "totcnt %d\n", totcnt);
4284                 return totcnt;
4285         }
4286         advoffset += cplen;
4287         curbuf += cnt;
4288 #endif /* ADVANSYS_STATS */
4289
4290         /*
4291          * Display Asc Library dynamic configuration information
4292          * for the board.
4293          */
4294         cp = boardp->prtbuf;
4295         if (ASC_NARROW_BOARD(boardp)) {
4296                 cplen = asc_prt_asc_board_info(shost, cp, ASC_PRTBUF_SIZE);
4297         } else {
4298                 cplen = asc_prt_adv_board_info(shost, cp, ASC_PRTBUF_SIZE);
4299         }
4300         BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4301         cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4302         totcnt += cnt;
4303         leftlen -= cnt;
4304         if (leftlen == 0) {
4305                 ASC_DBG(1, "totcnt %d\n", totcnt);
4306                 return totcnt;
4307         }
4308         advoffset += cplen;
4309         curbuf += cnt;
4310
4311         ASC_DBG(1, "totcnt %d\n", totcnt);
4312
4313         return totcnt;
4314 }
4315 #endif /* CONFIG_PROC_FS */
4316
4317 static void asc_scsi_done(struct scsi_cmnd *scp)
4318 {
4319         scsi_dma_unmap(scp);
4320         ASC_STATS(scp->device->host, done);
4321         scp->scsi_done(scp);
4322 }
4323
4324 static void AscSetBank(PortAddr iop_base, uchar bank)
4325 {
4326         uchar val;
4327
4328         val = AscGetChipControl(iop_base) &
4329             (~
4330              (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET |
4331               CC_CHIP_RESET));
4332         if (bank == 1) {
4333                 val |= CC_BANK_ONE;
4334         } else if (bank == 2) {
4335                 val |= CC_DIAG | CC_BANK_ONE;
4336         } else {
4337                 val &= ~CC_BANK_ONE;
4338         }
4339         AscSetChipControl(iop_base, val);
4340 }
4341
4342 static void AscSetChipIH(PortAddr iop_base, ushort ins_code)
4343 {
4344         AscSetBank(iop_base, 1);
4345         AscWriteChipIH(iop_base, ins_code);
4346         AscSetBank(iop_base, 0);
4347 }
4348
4349 static int AscStartChip(PortAddr iop_base)
4350 {
4351         AscSetChipControl(iop_base, 0);
4352         if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
4353                 return (0);
4354         }
4355         return (1);
4356 }
4357
4358 static int AscStopChip(PortAddr iop_base)
4359 {
4360         uchar cc_val;
4361
4362         cc_val =
4363             AscGetChipControl(iop_base) &
4364             (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
4365         AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT));
4366         AscSetChipIH(iop_base, INS_HALT);
4367         AscSetChipIH(iop_base, INS_RFLAG_WTM);
4368         if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
4369                 return (0);
4370         }
4371         return (1);
4372 }
4373
4374 static int AscIsChipHalted(PortAddr iop_base)
4375 {
4376         if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
4377                 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
4378                         return (1);
4379                 }
4380         }
4381         return (0);
4382 }
4383
4384 static int AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc)
4385 {
4386         PortAddr iop_base;
4387         int i = 10;
4388
4389         iop_base = asc_dvc->iop_base;
4390         while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE)
4391                && (i-- > 0)) {
4392                 mdelay(100);
4393         }
4394         AscStopChip(iop_base);
4395         AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
4396         udelay(60);
4397         AscSetChipIH(iop_base, INS_RFLAG_WTM);
4398         AscSetChipIH(iop_base, INS_HALT);
4399         AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
4400         AscSetChipControl(iop_base, CC_HALT);
4401         mdelay(200);
4402         AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
4403         AscSetChipStatus(iop_base, 0);
4404         return (AscIsChipHalted(iop_base));
4405 }
4406
4407 static int AscFindSignature(PortAddr iop_base)
4408 {
4409         ushort sig_word;
4410
4411         ASC_DBG(1, "AscGetChipSignatureByte(0x%x) 0x%x\n",
4412                  iop_base, AscGetChipSignatureByte(iop_base));
4413         if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) {
4414                 ASC_DBG(1, "AscGetChipSignatureWord(0x%x) 0x%x\n",
4415                          iop_base, AscGetChipSignatureWord(iop_base));
4416                 sig_word = AscGetChipSignatureWord(iop_base);
4417                 if ((sig_word == (ushort)ASC_1000_ID0W) ||
4418                     (sig_word == (ushort)ASC_1000_ID0W_FIX)) {
4419                         return (1);
4420                 }
4421         }
4422         return (0);
4423 }
4424
4425 static void AscEnableInterrupt(PortAddr iop_base)
4426 {
4427         ushort cfg;
4428
4429         cfg = AscGetChipCfgLsw(iop_base);
4430         AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
4431 }
4432
4433 static void AscDisableInterrupt(PortAddr iop_base)
4434 {
4435         ushort cfg;
4436
4437         cfg = AscGetChipCfgLsw(iop_base);
4438         AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
4439 }
4440
4441 static uchar AscReadLramByte(PortAddr iop_base, ushort addr)
4442 {
4443         unsigned char byte_data;
4444         unsigned short word_data;
4445
4446         if (isodd_word(addr)) {
4447                 AscSetChipLramAddr(iop_base, addr - 1);
4448                 word_data = AscGetChipLramData(iop_base);
4449                 byte_data = (word_data >> 8) & 0xFF;
4450         } else {
4451                 AscSetChipLramAddr(iop_base, addr);
4452                 word_data = AscGetChipLramData(iop_base);
4453                 byte_data = word_data & 0xFF;
4454         }
4455         return byte_data;
4456 }
4457
4458 static ushort AscReadLramWord(PortAddr iop_base, ushort addr)
4459 {
4460         ushort word_data;
4461
4462         AscSetChipLramAddr(iop_base, addr);
4463         word_data = AscGetChipLramData(iop_base);
4464         return (word_data);
4465 }
4466
4467 #if CC_VERY_LONG_SG_LIST
4468 static ASC_DCNT AscReadLramDWord(PortAddr iop_base, ushort addr)
4469 {
4470         ushort val_low, val_high;
4471         ASC_DCNT dword_data;
4472
4473         AscSetChipLramAddr(iop_base, addr);
4474         val_low = AscGetChipLramData(iop_base);
4475         val_high = AscGetChipLramData(iop_base);
4476         dword_data = ((ASC_DCNT) val_high << 16) | (ASC_DCNT) val_low;
4477         return (dword_data);
4478 }
4479 #endif /* CC_VERY_LONG_SG_LIST */
4480
4481 static void
4482 AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words)
4483 {
4484         int i;
4485
4486         AscSetChipLramAddr(iop_base, s_addr);
4487         for (i = 0; i < words; i++) {
4488                 AscSetChipLramData(iop_base, set_wval);
4489         }
4490 }
4491
4492 static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val)
4493 {
4494         AscSetChipLramAddr(iop_base, addr);
4495         AscSetChipLramData(iop_base, word_val);
4496 }
4497
4498 static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val)
4499 {
4500         ushort word_data;
4501
4502         if (isodd_word(addr)) {
4503                 addr--;
4504                 word_data = AscReadLramWord(iop_base, addr);
4505                 word_data &= 0x00FF;
4506                 word_data |= (((ushort)byte_val << 8) & 0xFF00);
4507         } else {
4508                 word_data = AscReadLramWord(iop_base, addr);
4509                 word_data &= 0xFF00;
4510                 word_data |= ((ushort)byte_val & 0x00FF);
4511         }
4512         AscWriteLramWord(iop_base, addr, word_data);
4513 }
4514
4515 /*
4516  * Copy 2 bytes to LRAM.
4517  *
4518  * The source data is assumed to be in little-endian order in memory
4519  * and is maintained in little-endian order when written to LRAM.
4520  */
4521 static void
4522 AscMemWordCopyPtrToLram(PortAddr iop_base,
4523                         ushort s_addr, uchar *s_buffer, int words)
4524 {
4525         int i;
4526
4527         AscSetChipLramAddr(iop_base, s_addr);
4528         for (i = 0; i < 2 * words; i += 2) {
4529                 /*
4530                  * On a little-endian system the second argument below
4531                  * produces a little-endian ushort which is written to
4532                  * LRAM in little-endian order. On a big-endian system
4533                  * the second argument produces a big-endian ushort which
4534                  * is "transparently" byte-swapped by outpw() and written
4535                  * in little-endian order to LRAM.
4536                  */
4537                 outpw(iop_base + IOP_RAM_DATA,
4538                       ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);
4539         }
4540 }
4541
4542 /*
4543  * Copy 4 bytes to LRAM.
4544  *
4545  * The source data is assumed to be in little-endian order in memory
4546  * and is maintained in little-endian order when writen to LRAM.
4547  */
4548 static void
4549 AscMemDWordCopyPtrToLram(PortAddr iop_base,
4550                          ushort s_addr, uchar *s_buffer, int dwords)
4551 {
4552         int i;
4553
4554         AscSetChipLramAddr(iop_base, s_addr);
4555         for (i = 0; i < 4 * dwords; i += 4) {
4556                 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);   /* LSW */
4557                 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]);       /* MSW */
4558         }
4559 }
4560
4561 /*
4562  * Copy 2 bytes from LRAM.
4563  *
4564  * The source data is assumed to be in little-endian order in LRAM
4565  * and is maintained in little-endian order when written to memory.
4566  */
4567 static void
4568 AscMemWordCopyPtrFromLram(PortAddr iop_base,
4569                           ushort s_addr, uchar *d_buffer, int words)
4570 {
4571         int i;
4572         ushort word;
4573
4574         AscSetChipLramAddr(iop_base, s_addr);
4575         for (i = 0; i < 2 * words; i += 2) {
4576                 word = inpw(iop_base + IOP_RAM_DATA);
4577                 d_buffer[i] = word & 0xff;
4578                 d_buffer[i + 1] = (word >> 8) & 0xff;
4579         }
4580 }
4581
4582 static ASC_DCNT AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words)
4583 {
4584         ASC_DCNT sum;
4585         int i;
4586
4587         sum = 0L;
4588         for (i = 0; i < words; i++, s_addr += 2) {
4589                 sum += AscReadLramWord(iop_base, s_addr);
4590         }
4591         return (sum);
4592 }
4593
4594 static ushort AscInitLram(ASC_DVC_VAR *asc_dvc)
4595 {
4596         uchar i;
4597         ushort s_addr;
4598         PortAddr iop_base;
4599         ushort warn_code;
4600
4601         iop_base = asc_dvc->iop_base;
4602         warn_code = 0;
4603         AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
4604                           (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) *
4605                                     64) >> 1));
4606         i = ASC_MIN_ACTIVE_QNO;
4607         s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
4608         AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4609                          (uchar)(i + 1));
4610         AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4611                          (uchar)(asc_dvc->max_total_qng));
4612         AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4613                          (uchar)i);
4614         i++;
4615         s_addr += ASC_QBLK_SIZE;
4616         for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
4617                 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4618                                  (uchar)(i + 1));
4619                 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4620                                  (uchar)(i - 1));
4621                 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4622                                  (uchar)i);
4623         }
4624         AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4625                          (uchar)ASC_QLINK_END);
4626         AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4627                          (uchar)(asc_dvc->max_total_qng - 1));
4628         AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4629                          (uchar)asc_dvc->max_total_qng);
4630         i++;
4631         s_addr += ASC_QBLK_SIZE;
4632         for (; i <= (uchar)(asc_dvc->max_total_qng + 3);
4633              i++, s_addr += ASC_QBLK_SIZE) {
4634                 AscWriteLramByte(iop_base,
4635                                  (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i);
4636                 AscWriteLramByte(iop_base,
4637                                  (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i);
4638                 AscWriteLramByte(iop_base,
4639                                  (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i);
4640         }
4641         return warn_code;
4642 }
4643
4644 static ASC_DCNT
4645 AscLoadMicroCode(PortAddr iop_base,
4646                  ushort s_addr, uchar *mcode_buf, ushort mcode_size)
4647 {
4648         ASC_DCNT chksum;
4649         ushort mcode_word_size;
4650         ushort mcode_chksum;
4651
4652         /* Write the microcode buffer starting at LRAM address 0. */
4653         mcode_word_size = (ushort)(mcode_size >> 1);
4654         AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
4655         AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
4656
4657         chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
4658         ASC_DBG(1, "chksum 0x%lx\n", (ulong)chksum);
4659         mcode_chksum = (ushort)AscMemSumLramWord(iop_base,
4660                                                  (ushort)ASC_CODE_SEC_BEG,
4661                                                  (ushort)((mcode_size -
4662                                                            s_addr - (ushort)
4663                                                            ASC_CODE_SEC_BEG) /
4664                                                           2));
4665         ASC_DBG(1, "mcode_chksum 0x%lx\n", (ulong)mcode_chksum);
4666         AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
4667         AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
4668         return chksum;
4669 }
4670
4671 /* Microcode buffer is kept after initialization for error recovery. */
4672 static uchar _asc_mcode_buf[] = {
4673         0x01, 0x03, 0x01, 0x19, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4674         0x00, 0x00, 0x00, 0x00, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F,
4675         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4676         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4677         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4678         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC3, 0x12, 0x0D, 0x05,
4679         0x01, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4680         0xFF, 0x80, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4681         0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0xFF,
4682         0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00,
4683         0x00, 0x00, 0xE4, 0x88, 0x00, 0x00, 0x00, 0x00, 0x80, 0x73, 0x48, 0x04,
4684         0x36, 0x00, 0x00, 0xA2, 0xC2, 0x00, 0x80, 0x73, 0x03, 0x23, 0x36, 0x40,
4685         0xB6, 0x00, 0x36, 0x00, 0x05, 0xD6, 0x0C, 0xD2, 0x12, 0xDA, 0x00, 0xA2,
4686         0xC2, 0x00, 0x92, 0x80, 0x1E, 0x98, 0x50, 0x00, 0xF5, 0x00, 0x48, 0x98,
4687         0xDF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80, 0x4F, 0x00, 0xF5, 0x00,
4688         0x48, 0x98, 0xEF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80, 0x80, 0x62,
4689         0x92, 0x80, 0x00, 0x46, 0x15, 0xEE, 0x13, 0xEA, 0x02, 0x01, 0x09, 0xD8,
4690         0xCD, 0x04, 0x4D, 0x00, 0x00, 0xA3, 0xD6, 0x00, 0xA6, 0x97, 0x7F, 0x23,
4691         0x04, 0x61, 0x84, 0x01, 0xE6, 0x84, 0xD2, 0xC1, 0x80, 0x73, 0xCD, 0x04,
4692         0x4D, 0x00, 0x00, 0xA3, 0xDA, 0x01, 0xA6, 0x97, 0xC6, 0x81, 0xC2, 0x88,
4693         0x80, 0x73, 0x80, 0x77, 0x00, 0x01, 0x01, 0xA1, 0xFE, 0x00, 0x4F, 0x00,
4694         0x84, 0x97, 0x07, 0xA6, 0x08, 0x01, 0x00, 0x33, 0x03, 0x00, 0xC2, 0x88,
4695         0x03, 0x03, 0x01, 0xDE, 0xC2, 0x88, 0xCE, 0x00, 0x69, 0x60, 0xCE, 0x00,
4696         0x02, 0x03, 0x4A, 0x60, 0x00, 0xA2, 0x78, 0x01, 0x80, 0x63, 0x07, 0xA6,
4697         0x24, 0x01, 0x78, 0x81, 0x03, 0x03, 0x80, 0x63, 0xE2, 0x00, 0x07, 0xA6,
4698         0x34, 0x01, 0x00, 0x33, 0x04, 0x00, 0xC2, 0x88, 0x03, 0x07, 0x02, 0x01,
4699         0x04, 0xCA, 0x0D, 0x23, 0x68, 0x98, 0x4D, 0x04, 0x04, 0x85, 0x05, 0xD8,
4700         0x0D, 0x23, 0x68, 0x98, 0xCD, 0x04, 0x15, 0x23, 0xF8, 0x88, 0xFB, 0x23,
4701         0x02, 0x61, 0x82, 0x01, 0x80, 0x63, 0x02, 0x03, 0x06, 0xA3, 0x62, 0x01,
4702         0x00, 0x33, 0x0A, 0x00, 0xC2, 0x88, 0x4E, 0x00, 0x07, 0xA3, 0x6E, 0x01,
4703         0x00, 0x33, 0x0B, 0x00, 0xC2, 0x88, 0xCD, 0x04, 0x36, 0x2D, 0x00, 0x33,
4704         0x1A, 0x00, 0xC2, 0x88, 0x50, 0x04, 0x88, 0x81, 0x06, 0xAB, 0x82, 0x01,
4705         0x88, 0x81, 0x4E, 0x00, 0x07, 0xA3, 0x92, 0x01, 0x50, 0x00, 0x00, 0xA3,
4706         0x3C, 0x01, 0x00, 0x05, 0x7C, 0x81, 0x46, 0x97, 0x02, 0x01, 0x05, 0xC6,
4707         0x04, 0x23, 0xA0, 0x01, 0x15, 0x23, 0xA1, 0x01, 0xBE, 0x81, 0xFD, 0x23,
4708         0x02, 0x61, 0x82, 0x01, 0x0A, 0xDA, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA0,
4709         0xB4, 0x01, 0x80, 0x63, 0xCD, 0x04, 0x36, 0x2D, 0x00, 0x33, 0x1B, 0x00,
4710         0xC2, 0x88, 0x06, 0x23, 0x68, 0x98, 0xCD, 0x04, 0xE6, 0x84, 0x06, 0x01,
4711         0x00, 0xA2, 0xD4, 0x01, 0x57, 0x60, 0x00, 0xA0, 0xDA, 0x01, 0xE6, 0x84,
4712         0x80, 0x23, 0xA0, 0x01, 0xE6, 0x84, 0x80, 0x73, 0x4B, 0x00, 0x06, 0x61,
4713         0x00, 0xA2, 0x00, 0x02, 0x04, 0x01, 0x0C, 0xDE, 0x02, 0x01, 0x03, 0xCC,
4714         0x4F, 0x00, 0x84, 0x97, 0xFC, 0x81, 0x08, 0x23, 0x02, 0x41, 0x82, 0x01,
4715         0x4F, 0x00, 0x62, 0x97, 0x48, 0x04, 0x84, 0x80, 0xF0, 0x97, 0x00, 0x46,
4716         0x56, 0x00, 0x03, 0xC0, 0x01, 0x23, 0xE8, 0x00, 0x81, 0x73, 0x06, 0x29,
4717         0x03, 0x42, 0x06, 0xE2, 0x03, 0xEE, 0x6B, 0xEB, 0x11, 0x23, 0xF8, 0x88,
4718         0x04, 0x98, 0xF0, 0x80, 0x80, 0x73, 0x80, 0x77, 0x07, 0xA4, 0x2A, 0x02,
4719         0x7C, 0x95, 0x06, 0xA6, 0x34, 0x02, 0x03, 0xA6, 0x4C, 0x04, 0x46, 0x82,
4720         0x04, 0x01, 0x03, 0xD8, 0xB4, 0x98, 0x6A, 0x96, 0x46, 0x82, 0xFE, 0x95,
4721         0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0xB6, 0x2D, 0x02, 0xA6, 0x6C, 0x02,
4722         0x07, 0xA6, 0x5A, 0x02, 0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x62, 0x02,
4723         0xC2, 0x88, 0x7C, 0x95, 0x48, 0x82, 0x60, 0x96, 0x48, 0x82, 0x04, 0x23,
4724         0xA0, 0x01, 0x14, 0x23, 0xA1, 0x01, 0x3C, 0x84, 0x04, 0x01, 0x0C, 0xDC,
4725         0xE0, 0x23, 0x25, 0x61, 0xEF, 0x00, 0x14, 0x01, 0x4F, 0x04, 0xA8, 0x01,
4726         0x6F, 0x00, 0xA5, 0x01, 0x03, 0x23, 0xA4, 0x01, 0x06, 0x23, 0x9C, 0x01,
4727         0x24, 0x2B, 0x1C, 0x01, 0x02, 0xA6, 0xAA, 0x02, 0x07, 0xA6, 0x5A, 0x02,
4728         0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x20, 0x04, 0x01, 0xA6, 0xB4, 0x02,
4729         0x00, 0xA6, 0xB4, 0x02, 0x00, 0x33, 0x12, 0x00, 0xC2, 0x88, 0x00, 0x0E,
4730         0x80, 0x63, 0x00, 0x43, 0x00, 0xA0, 0x8C, 0x02, 0x4D, 0x04, 0x04, 0x01,
4731         0x0B, 0xDC, 0xE7, 0x23, 0x04, 0x61, 0x84, 0x01, 0x10, 0x31, 0x12, 0x35,
4732         0x14, 0x01, 0xEC, 0x00, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0xEA, 0x82,
4733         0x18, 0x23, 0x04, 0x61, 0x18, 0xA0, 0xE2, 0x02, 0x04, 0x01, 0xA2, 0xC8,
4734         0x00, 0x33, 0x1F, 0x00, 0xC2, 0x88, 0x08, 0x31, 0x0A, 0x35, 0x0C, 0x39,
4735         0x0E, 0x3D, 0x7E, 0x98, 0xB6, 0x2D, 0x01, 0xA6, 0x14, 0x03, 0x00, 0xA6,
4736         0x14, 0x03, 0x07, 0xA6, 0x0C, 0x03, 0x06, 0xA6, 0x10, 0x03, 0x03, 0xA6,
4737         0x20, 0x04, 0x02, 0xA6, 0x6C, 0x02, 0x00, 0x33, 0x33, 0x00, 0xC2, 0x88,
4738         0x7C, 0x95, 0xEE, 0x82, 0x60, 0x96, 0xEE, 0x82, 0x82, 0x98, 0x80, 0x42,
4739         0x7E, 0x98, 0x64, 0xE4, 0x04, 0x01, 0x2D, 0xC8, 0x31, 0x05, 0x07, 0x01,
4740         0x00, 0xA2, 0x54, 0x03, 0x00, 0x43, 0x87, 0x01, 0x05, 0x05, 0x86, 0x98,
4741         0x7E, 0x98, 0x00, 0xA6, 0x16, 0x03, 0x07, 0xA6, 0x4C, 0x03, 0x03, 0xA6,
4742         0x3C, 0x04, 0x06, 0xA6, 0x50, 0x03, 0x01, 0xA6, 0x16, 0x03, 0x00, 0x33,
4743         0x25, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x32, 0x83, 0x60, 0x96, 0x32, 0x83,
4744         0x04, 0x01, 0x10, 0xCE, 0x07, 0xC8, 0x05, 0x05, 0xEB, 0x04, 0x00, 0x33,
4745         0x00, 0x20, 0xC0, 0x20, 0x81, 0x62, 0x72, 0x83, 0x00, 0x01, 0x05, 0x05,
4746         0xFF, 0xA2, 0x7A, 0x03, 0xB1, 0x01, 0x08, 0x23, 0xB2, 0x01, 0x2E, 0x83,
4747         0x05, 0x05, 0x15, 0x01, 0x00, 0xA2, 0x9A, 0x03, 0xEC, 0x00, 0x6E, 0x00,
4748         0x95, 0x01, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0x01, 0xA6, 0x96, 0x03,
4749         0x00, 0xA6, 0x96, 0x03, 0x10, 0x84, 0x80, 0x42, 0x7E, 0x98, 0x01, 0xA6,
4750         0xA4, 0x03, 0x00, 0xA6, 0xBC, 0x03, 0x10, 0x84, 0xA8, 0x98, 0x80, 0x42,
4751         0x01, 0xA6, 0xA4, 0x03, 0x07, 0xA6, 0xB2, 0x03, 0xD4, 0x83, 0x7C, 0x95,
4752         0xA8, 0x83, 0x00, 0x33, 0x2F, 0x00, 0xC2, 0x88, 0xA8, 0x98, 0x80, 0x42,
4753         0x00, 0xA6, 0xBC, 0x03, 0x07, 0xA6, 0xCA, 0x03, 0xD4, 0x83, 0x7C, 0x95,
4754         0xC0, 0x83, 0x00, 0x33, 0x26, 0x00, 0xC2, 0x88, 0x38, 0x2B, 0x80, 0x32,
4755         0x80, 0x36, 0x04, 0x23, 0xA0, 0x01, 0x12, 0x23, 0xA1, 0x01, 0x10, 0x84,
4756         0x07, 0xF0, 0x06, 0xA4, 0xF4, 0x03, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23,
4757         0x83, 0x03, 0x80, 0x63, 0x03, 0xA6, 0x0E, 0x04, 0x07, 0xA6, 0x06, 0x04,
4758         0x06, 0xA6, 0x0A, 0x04, 0x00, 0x33, 0x17, 0x00, 0xC2, 0x88, 0x7C, 0x95,
4759         0xF4, 0x83, 0x60, 0x96, 0xF4, 0x83, 0x20, 0x84, 0x07, 0xF0, 0x06, 0xA4,
4760         0x20, 0x04, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23, 0x83, 0x03, 0x80, 0x63,
4761         0xB6, 0x2D, 0x03, 0xA6, 0x3C, 0x04, 0x07, 0xA6, 0x34, 0x04, 0x06, 0xA6,
4762         0x38, 0x04, 0x00, 0x33, 0x30, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x20, 0x84,
4763         0x60, 0x96, 0x20, 0x84, 0x1D, 0x01, 0x06, 0xCC, 0x00, 0x33, 0x00, 0x84,
4764         0xC0, 0x20, 0x00, 0x23, 0xEA, 0x00, 0x81, 0x62, 0xA2, 0x0D, 0x80, 0x63,
4765         0x07, 0xA6, 0x5A, 0x04, 0x00, 0x33, 0x18, 0x00, 0xC2, 0x88, 0x03, 0x03,
4766         0x80, 0x63, 0xA3, 0x01, 0x07, 0xA4, 0x64, 0x04, 0x23, 0x01, 0x00, 0xA2,
4767         0x86, 0x04, 0x0A, 0xA0, 0x76, 0x04, 0xE0, 0x00, 0x00, 0x33, 0x1D, 0x00,
4768         0xC2, 0x88, 0x0B, 0xA0, 0x82, 0x04, 0xE0, 0x00, 0x00, 0x33, 0x1E, 0x00,
4769         0xC2, 0x88, 0x42, 0x23, 0xF8, 0x88, 0x00, 0x23, 0x22, 0xA3, 0xE6, 0x04,
4770         0x08, 0x23, 0x22, 0xA3, 0xA2, 0x04, 0x28, 0x23, 0x22, 0xA3, 0xAE, 0x04,
4771         0x02, 0x23, 0x22, 0xA3, 0xC4, 0x04, 0x42, 0x23, 0xF8, 0x88, 0x4A, 0x00,
4772         0x06, 0x61, 0x00, 0xA0, 0xAE, 0x04, 0x45, 0x23, 0xF8, 0x88, 0x04, 0x98,
4773         0x00, 0xA2, 0xC0, 0x04, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x82, 0xC0, 0x20,
4774         0x81, 0x62, 0xE8, 0x81, 0x47, 0x23, 0xF8, 0x88, 0x04, 0x01, 0x0B, 0xDE,
4775         0x04, 0x98, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x81, 0xC0, 0x20, 0x81, 0x62,
4776         0x14, 0x01, 0x00, 0xA0, 0x00, 0x02, 0x43, 0x23, 0xF8, 0x88, 0x04, 0x23,
4777         0xA0, 0x01, 0x44, 0x23, 0xA1, 0x01, 0x80, 0x73, 0x4D, 0x00, 0x03, 0xA3,
4778         0xF4, 0x04, 0x00, 0x33, 0x27, 0x00, 0xC2, 0x88, 0x04, 0x01, 0x04, 0xDC,
4779         0x02, 0x23, 0xA2, 0x01, 0x04, 0x23, 0xA0, 0x01, 0x04, 0x98, 0x26, 0x95,
4780         0x4B, 0x00, 0xF6, 0x00, 0x4F, 0x04, 0x4F, 0x00, 0x00, 0xA3, 0x22, 0x05,
4781         0x00, 0x05, 0x76, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x1C, 0x05, 0x0A, 0x85,
4782         0x46, 0x97, 0xCD, 0x04, 0x24, 0x85, 0x48, 0x04, 0x84, 0x80, 0x02, 0x01,
4783         0x03, 0xDA, 0x80, 0x23, 0x82, 0x01, 0x34, 0x85, 0x02, 0x23, 0xA0, 0x01,
4784         0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x40, 0x05, 0x1D, 0x01, 0x04, 0xD6,
4785         0xFF, 0x23, 0x86, 0x41, 0x4B, 0x60, 0xCB, 0x00, 0xFF, 0x23, 0x80, 0x01,
4786         0x49, 0x00, 0x81, 0x01, 0x04, 0x01, 0x02, 0xC8, 0x30, 0x01, 0x80, 0x01,
4787         0xF7, 0x04, 0x03, 0x01, 0x49, 0x04, 0x80, 0x01, 0xC9, 0x00, 0x00, 0x05,
4788         0x00, 0x01, 0xFF, 0xA0, 0x60, 0x05, 0x77, 0x04, 0x01, 0x23, 0xEA, 0x00,
4789         0x5D, 0x00, 0xFE, 0xC7, 0x00, 0x62, 0x00, 0x23, 0xEA, 0x00, 0x00, 0x63,
4790         0x07, 0xA4, 0xF8, 0x05, 0x03, 0x03, 0x02, 0xA0, 0x8E, 0x05, 0xF4, 0x85,
4791         0x00, 0x33, 0x2D, 0x00, 0xC2, 0x88, 0x04, 0xA0, 0xB8, 0x05, 0x80, 0x63,
4792         0x00, 0x23, 0xDF, 0x00, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0xA4, 0x05,
4793         0x1D, 0x01, 0x06, 0xD6, 0x02, 0x23, 0x02, 0x41, 0x82, 0x01, 0x50, 0x00,
4794         0x62, 0x97, 0x04, 0x85, 0x04, 0x23, 0x02, 0x41, 0x82, 0x01, 0x04, 0x85,
4795         0x08, 0xA0, 0xBE, 0x05, 0xF4, 0x85, 0x03, 0xA0, 0xC4, 0x05, 0xF4, 0x85,
4796         0x01, 0xA0, 0xCE, 0x05, 0x88, 0x00, 0x80, 0x63, 0xCC, 0x86, 0x07, 0xA0,
4797         0xEE, 0x05, 0x5F, 0x00, 0x00, 0x2B, 0xDF, 0x08, 0x00, 0xA2, 0xE6, 0x05,
4798         0x80, 0x67, 0x80, 0x63, 0x01, 0xA2, 0x7A, 0x06, 0x7C, 0x85, 0x06, 0x23,
4799         0x68, 0x98, 0x48, 0x23, 0xF8, 0x88, 0x07, 0x23, 0x80, 0x00, 0x06, 0x87,
4800         0x80, 0x63, 0x7C, 0x85, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63, 0x4A, 0x00,
4801         0x06, 0x61, 0x00, 0xA2, 0x36, 0x06, 0x1D, 0x01, 0x16, 0xD4, 0xC0, 0x23,
4802         0x07, 0x41, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6, 0x1C, 0x06, 0x00, 0x33,
4803         0x37, 0x00, 0xC2, 0x88, 0x1D, 0x01, 0x01, 0xD6, 0x20, 0x23, 0x63, 0x60,
4804         0x83, 0x03, 0x80, 0x63, 0x02, 0x23, 0xDF, 0x00, 0x07, 0xA6, 0x7C, 0x05,
4805         0xEF, 0x04, 0x6F, 0x00, 0x00, 0x63, 0x4B, 0x00, 0x06, 0x41, 0xCB, 0x00,
4806         0x52, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x4E, 0x06, 0x1D, 0x01, 0x03, 0xCA,
4807         0xC0, 0x23, 0x07, 0x41, 0x00, 0x63, 0x1D, 0x01, 0x04, 0xCC, 0x00, 0x33,
4808         0x00, 0x83, 0xC0, 0x20, 0x81, 0x62, 0x80, 0x23, 0x07, 0x41, 0x00, 0x63,
4809         0x80, 0x67, 0x08, 0x23, 0x83, 0x03, 0x80, 0x63, 0x00, 0x63, 0x01, 0x23,
4810         0xDF, 0x00, 0x06, 0xA6, 0x84, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67,
4811         0x80, 0x63, 0x00, 0x33, 0x00, 0x40, 0xC0, 0x20, 0x81, 0x62, 0x00, 0x63,
4812         0x00, 0x00, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6, 0x94, 0x06,
4813         0x07, 0xA6, 0x7C, 0x05, 0x00, 0x00, 0x01, 0xA0, 0x14, 0x07, 0x00, 0x2B,
4814         0x40, 0x0E, 0x80, 0x63, 0x01, 0x00, 0x06, 0xA6, 0xAA, 0x06, 0x07, 0xA6,
4815         0x7C, 0x05, 0x40, 0x0E, 0x80, 0x63, 0x00, 0x43, 0x00, 0xA0, 0xA2, 0x06,
4816         0x06, 0xA6, 0xBC, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67, 0x40, 0x0E,
4817         0x80, 0x63, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63,
4818         0x07, 0xA6, 0xD6, 0x06, 0x00, 0x33, 0x2A, 0x00, 0xC2, 0x88, 0x03, 0x03,
4819         0x80, 0x63, 0x89, 0x00, 0x0A, 0x2B, 0x07, 0xA6, 0xE8, 0x06, 0x00, 0x33,
4820         0x29, 0x00, 0xC2, 0x88, 0x00, 0x43, 0x00, 0xA2, 0xF4, 0x06, 0xC0, 0x0E,
4821         0x80, 0x63, 0xDE, 0x86, 0xC0, 0x0E, 0x00, 0x33, 0x00, 0x80, 0xC0, 0x20,
4822         0x81, 0x62, 0x04, 0x01, 0x02, 0xDA, 0x80, 0x63, 0x7C, 0x85, 0x80, 0x7B,
4823         0x80, 0x63, 0x06, 0xA6, 0x8C, 0x06, 0x00, 0x33, 0x2C, 0x00, 0xC2, 0x88,
4824         0x0C, 0xA2, 0x2E, 0x07, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6,
4825         0x2C, 0x07, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x33, 0x3D, 0x00, 0xC2, 0x88,
4826         0x00, 0x00, 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0x0C, 0xA0, 0x44, 0x07,
4827         0x07, 0xA6, 0x7C, 0x05, 0xBF, 0x23, 0x04, 0x61, 0x84, 0x01, 0xE6, 0x84,
4828         0x00, 0x63, 0xF0, 0x04, 0x01, 0x01, 0xF1, 0x00, 0x00, 0x01, 0xF2, 0x00,
4829         0x01, 0x05, 0x80, 0x01, 0x72, 0x04, 0x71, 0x00, 0x81, 0x01, 0x70, 0x04,
4830         0x80, 0x05, 0x81, 0x05, 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04,
4831         0x01, 0x01, 0xF1, 0x00, 0x70, 0x00, 0x81, 0x01, 0x70, 0x04, 0x71, 0x00,
4832         0x81, 0x01, 0x72, 0x00, 0x80, 0x01, 0x71, 0x04, 0x70, 0x00, 0x80, 0x01,
4833         0x70, 0x04, 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04, 0x00, 0x01,
4834         0xF1, 0x00, 0x70, 0x00, 0x80, 0x01, 0x70, 0x04, 0x71, 0x00, 0x80, 0x01,
4835         0x72, 0x00, 0x81, 0x01, 0x71, 0x04, 0x70, 0x00, 0x81, 0x01, 0x70, 0x04,
4836         0x00, 0x63, 0x00, 0x23, 0xB3, 0x01, 0x83, 0x05, 0xA3, 0x01, 0xA2, 0x01,
4837         0xA1, 0x01, 0x01, 0x23, 0xA0, 0x01, 0x00, 0x01, 0xC8, 0x00, 0x03, 0xA1,
4838         0xC4, 0x07, 0x00, 0x33, 0x07, 0x00, 0xC2, 0x88, 0x80, 0x05, 0x81, 0x05,
4839         0x04, 0x01, 0x11, 0xC8, 0x48, 0x00, 0xB0, 0x01, 0xB1, 0x01, 0x08, 0x23,
4840         0xB2, 0x01, 0x05, 0x01, 0x48, 0x04, 0x00, 0x43, 0x00, 0xA2, 0xE4, 0x07,
4841         0x00, 0x05, 0xDA, 0x87, 0x00, 0x01, 0xC8, 0x00, 0xFF, 0x23, 0x80, 0x01,
4842         0x05, 0x05, 0x00, 0x63, 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04,
4843         0x00, 0x02, 0x80, 0x43, 0x76, 0x08, 0x80, 0x02, 0x77, 0x04, 0x00, 0x63,
4844         0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04, 0x00, 0x02, 0x00, 0xA0,
4845         0x14, 0x08, 0x16, 0x88, 0x00, 0x43, 0x76, 0x08, 0x80, 0x02, 0x77, 0x04,
4846         0x00, 0x63, 0xF3, 0x04, 0x00, 0x23, 0xF4, 0x00, 0x74, 0x00, 0x80, 0x43,
4847         0xF4, 0x00, 0xCF, 0x40, 0x00, 0xA2, 0x44, 0x08, 0x74, 0x04, 0x02, 0x01,
4848         0xF7, 0xC9, 0xF6, 0xD9, 0x00, 0x01, 0x01, 0xA1, 0x24, 0x08, 0x04, 0x98,
4849         0x26, 0x95, 0x24, 0x88, 0x73, 0x04, 0x00, 0x63, 0xF3, 0x04, 0x75, 0x04,
4850         0x5A, 0x88, 0x02, 0x01, 0x04, 0xD8, 0x46, 0x97, 0x04, 0x98, 0x26, 0x95,
4851         0x4A, 0x88, 0x75, 0x00, 0x00, 0xA3, 0x64, 0x08, 0x00, 0x05, 0x4E, 0x88,
4852         0x73, 0x04, 0x00, 0x63, 0x80, 0x7B, 0x80, 0x63, 0x06, 0xA6, 0x76, 0x08,
4853         0x00, 0x33, 0x3E, 0x00, 0xC2, 0x88, 0x80, 0x67, 0x83, 0x03, 0x80, 0x63,
4854         0x00, 0x63, 0x38, 0x2B, 0x9C, 0x88, 0x38, 0x2B, 0x92, 0x88, 0x32, 0x09,
4855         0x31, 0x05, 0x92, 0x98, 0x05, 0x05, 0xB2, 0x09, 0x00, 0x63, 0x00, 0x32,
4856         0x00, 0x36, 0x00, 0x3A, 0x00, 0x3E, 0x00, 0x63, 0x80, 0x32, 0x80, 0x36,
4857         0x80, 0x3A, 0x80, 0x3E, 0xB4, 0x3D, 0x00, 0x63, 0x38, 0x2B, 0x40, 0x32,
4858         0x40, 0x36, 0x40, 0x3A, 0x40, 0x3E, 0x00, 0x63, 0x5A, 0x20, 0xC9, 0x40,
4859         0x00, 0xA0, 0xB4, 0x08, 0x5D, 0x00, 0xFE, 0xC3, 0x00, 0x63, 0x80, 0x73,
4860         0xE6, 0x20, 0x02, 0x23, 0xE8, 0x00, 0x82, 0x73, 0xFF, 0xFD, 0x80, 0x73,
4861         0x13, 0x23, 0xF8, 0x88, 0x66, 0x20, 0xC0, 0x20, 0x04, 0x23, 0xA0, 0x01,
4862         0xA1, 0x23, 0xA1, 0x01, 0x81, 0x62, 0xE2, 0x88, 0x80, 0x73, 0x80, 0x77,
4863         0x68, 0x00, 0x00, 0xA2, 0x80, 0x00, 0x03, 0xC2, 0xF1, 0xC7, 0x41, 0x23,
4864         0xF8, 0x88, 0x11, 0x23, 0xA1, 0x01, 0x04, 0x23, 0xA0, 0x01, 0xE6, 0x84,
4865 };
4866
4867 static unsigned short _asc_mcode_size = sizeof(_asc_mcode_buf);
4868 static ADV_DCNT _asc_mcode_chksum = 0x012C453FUL;
4869
4870 /* Microcode buffer is kept after initialization for error recovery. */
4871 static unsigned char _adv_asc3550_buf[] = {
4872         0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0x16, 0x18, 0xe4, 0x00, 0xfc,
4873         0x01, 0x00, 0x48, 0xe4, 0xbe, 0x18, 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00,
4874         0x00, 0xfa, 0xff, 0xff, 0x28, 0x0e, 0x9e, 0xe7, 0xff, 0x00, 0x82, 0xe7,
4875         0x00, 0xea, 0x00, 0xf6, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0, 0x01, 0xf6,
4876         0x01, 0xfa, 0x08, 0x00, 0x03, 0x00, 0x04, 0x00, 0x18, 0xf4, 0x10, 0x00,
4877         0x00, 0xec, 0x85, 0xf0, 0xbc, 0x00, 0xd5, 0xf0, 0x8e, 0x0c, 0x38, 0x54,
4878         0x00, 0xe6, 0x1e, 0xf0, 0x86, 0xf0, 0xb4, 0x00, 0x98, 0x57, 0xd0, 0x01,
4879         0x0c, 0x1c, 0x3e, 0x1c, 0x0c, 0x00, 0xbb, 0x00, 0xaa, 0x18, 0x02, 0x80,
4880         0x32, 0xf0, 0x01, 0xfc, 0x88, 0x0c, 0xc6, 0x12, 0x02, 0x13, 0x18, 0x40,
4881         0x00, 0x57, 0x01, 0xea, 0x3c, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12,
4882         0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00, 0xc0, 0x00, 0x01, 0x01,
4883         0x3e, 0x01, 0xda, 0x0f, 0x22, 0x10, 0x08, 0x12, 0x02, 0x4a, 0xb9, 0x54,
4884         0x03, 0x58, 0x1b, 0x80, 0x30, 0xe4, 0x4b, 0xe4, 0x20, 0x00, 0x32, 0x00,
4885         0x3e, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01,
4886         0x70, 0x01, 0x72, 0x01, 0x74, 0x01, 0x76, 0x01, 0x78, 0x01, 0x62, 0x0a,
4887         0x92, 0x0c, 0x2c, 0x10, 0x2e, 0x10, 0x06, 0x13, 0x4c, 0x1c, 0xbb, 0x55,
4888         0x3c, 0x56, 0x04, 0x80, 0x4a, 0xe4, 0x02, 0xee, 0x5b, 0xf0, 0xb1, 0xf0,
4889         0x03, 0xf7, 0x06, 0xf7, 0x03, 0xfc, 0x0f, 0x00, 0x40, 0x00, 0xbe, 0x00,
4890         0x00, 0x01, 0xb0, 0x08, 0x30, 0x13, 0x64, 0x15, 0x32, 0x1c, 0x38, 0x1c,
4891         0x4e, 0x1c, 0x10, 0x44, 0x02, 0x48, 0x00, 0x4c, 0x04, 0xea, 0x5d, 0xf0,
4892         0x04, 0xf6, 0x02, 0xfc, 0x05, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00,
4893         0xcc, 0x00, 0x20, 0x01, 0x4e, 0x01, 0x4e, 0x0b, 0x1e, 0x0e, 0x0c, 0x10,
4894         0x0a, 0x12, 0x04, 0x13, 0x40, 0x13, 0x30, 0x1c, 0x00, 0x4e, 0xbd, 0x56,
4895         0x06, 0x83, 0x00, 0xdc, 0x05, 0xf0, 0x09, 0xf0, 0x59, 0xf0, 0xa7, 0xf0,
4896         0xb8, 0xf0, 0x0e, 0xf7, 0x06, 0x00, 0x19, 0x00, 0x33, 0x00, 0x9b, 0x00,
4897         0xa4, 0x00, 0xb5, 0x00, 0xba, 0x00, 0xd0, 0x00, 0xe1, 0x00, 0xe7, 0x00,
4898         0xde, 0x03, 0x56, 0x0a, 0x14, 0x0e, 0x02, 0x10, 0x04, 0x10, 0x0a, 0x10,
4899         0x36, 0x10, 0x0a, 0x13, 0x12, 0x13, 0x52, 0x13, 0x10, 0x15, 0x14, 0x15,
4900         0xac, 0x16, 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c, 0x08, 0x44, 0x38, 0x44,
4901         0x91, 0x44, 0x0a, 0x45, 0x48, 0x46, 0x01, 0x48, 0x68, 0x54, 0x83, 0x55,
4902         0xb0, 0x57, 0x01, 0x58, 0x83, 0x59, 0x05, 0xe6, 0x0b, 0xf0, 0x0c, 0xf0,
4903         0x5c, 0xf0, 0x4b, 0xf4, 0x04, 0xf8, 0x05, 0xf8, 0x02, 0xfa, 0x03, 0xfa,
4904         0x04, 0xfc, 0x05, 0xfc, 0x07, 0x00, 0x0a, 0x00, 0x0d, 0x00, 0x1c, 0x00,
4905         0x9e, 0x00, 0xa8, 0x00, 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00, 0x22, 0x01,
4906         0x26, 0x01, 0x79, 0x01, 0x7a, 0x01, 0xc0, 0x01, 0xc2, 0x01, 0x7c, 0x02,
4907         0x5a, 0x03, 0xea, 0x04, 0xe8, 0x07, 0x68, 0x08, 0x69, 0x08, 0xba, 0x08,
4908         0xe9, 0x09, 0x06, 0x0b, 0x3a, 0x0e, 0x00, 0x10, 0x1a, 0x10, 0xed, 0x10,
4909         0xf1, 0x10, 0x06, 0x12, 0x0c, 0x13, 0x16, 0x13, 0x1e, 0x13, 0x82, 0x13,
4910         0x42, 0x14, 0xd6, 0x14, 0x8a, 0x15, 0xc6, 0x17, 0xd2, 0x17, 0x6b, 0x18,
4911         0x12, 0x1c, 0x46, 0x1c, 0x9c, 0x32, 0x00, 0x40, 0x0e, 0x47, 0x48, 0x47,
4912         0x41, 0x48, 0x89, 0x48, 0x80, 0x4c, 0x00, 0x54, 0x44, 0x55, 0xe5, 0x55,
4913         0x14, 0x56, 0x77, 0x57, 0xbf, 0x57, 0x40, 0x5c, 0x06, 0x80, 0x08, 0x90,
4914         0x03, 0xa1, 0xfe, 0x9c, 0xf0, 0x29, 0x02, 0xfe, 0xb8, 0x0c, 0xff, 0x10,
4915         0x00, 0x00, 0xd0, 0xfe, 0xcc, 0x18, 0x00, 0xcf, 0xfe, 0x80, 0x01, 0xff,
4916         0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00,
4917         0x00, 0xfe, 0x57, 0x24, 0x00, 0xfe, 0x48, 0x00, 0x4f, 0xff, 0x04, 0x00,
4918         0x00, 0x10, 0xff, 0x09, 0x00, 0x00, 0xff, 0x08, 0x01, 0x01, 0xff, 0x08,
4919         0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10, 0xff, 0xff, 0xff, 0x0f,
4920         0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00,
4921         0xfe, 0x04, 0xf7, 0xcf, 0x2a, 0x67, 0x0b, 0x01, 0xfe, 0xce, 0x0e, 0xfe,
4922         0x04, 0xf7, 0xcf, 0x67, 0x0b, 0x3c, 0x2a, 0xfe, 0x3d, 0xf0, 0xfe, 0x02,
4923         0x02, 0xfe, 0x20, 0xf0, 0x9c, 0xfe, 0x91, 0xf0, 0xfe, 0xf0, 0x01, 0xfe,
4924         0x90, 0xf0, 0xfe, 0xf0, 0x01, 0xfe, 0x8f, 0xf0, 0x9c, 0x05, 0x51, 0x3b,
4925         0x02, 0xfe, 0xd4, 0x0c, 0x01, 0xfe, 0x44, 0x0d, 0xfe, 0xdd, 0x12, 0xfe,
4926         0xfc, 0x10, 0xfe, 0x28, 0x1c, 0x05, 0xfe, 0xa6, 0x00, 0xfe, 0xd3, 0x12,
4927         0x47, 0x18, 0xfe, 0xa6, 0x00, 0xb5, 0xfe, 0x48, 0xf0, 0xfe, 0x86, 0x02,
4928         0xfe, 0x49, 0xf0, 0xfe, 0xa0, 0x02, 0xfe, 0x4a, 0xf0, 0xfe, 0xbe, 0x02,
4929         0xfe, 0x46, 0xf0, 0xfe, 0x50, 0x02, 0xfe, 0x47, 0xf0, 0xfe, 0x56, 0x02,
4930         0xfe, 0x43, 0xf0, 0xfe, 0x44, 0x02, 0xfe, 0x44, 0xf0, 0xfe, 0x48, 0x02,
4931         0xfe, 0x45, 0xf0, 0xfe, 0x4c, 0x02, 0x17, 0x0b, 0xa0, 0x17, 0x06, 0x18,
4932         0x96, 0x02, 0x29, 0xfe, 0x00, 0x1c, 0xde, 0xfe, 0x02, 0x1c, 0xdd, 0xfe,
4933         0x1e, 0x1c, 0xfe, 0xe9, 0x10, 0x01, 0xfe, 0x20, 0x17, 0xfe, 0xe7, 0x10,
4934         0xfe, 0x06, 0xfc, 0xc7, 0x0a, 0x6b, 0x01, 0x9e, 0x02, 0x29, 0x14, 0x4d,
4935         0x37, 0x97, 0x01, 0xfe, 0x64, 0x0f, 0x0a, 0x6b, 0x01, 0x82, 0xfe, 0xbd,
4936         0x10, 0x0a, 0x6b, 0x01, 0x82, 0xfe, 0xad, 0x10, 0xfe, 0x16, 0x1c, 0xfe,
4937         0x58, 0x1c, 0x17, 0x06, 0x18, 0x96, 0x2a, 0x25, 0x29, 0xfe, 0x3d, 0xf0,
4938         0xfe, 0x02, 0x02, 0x21, 0xfe, 0x94, 0x02, 0xfe, 0x5a, 0x1c, 0xea, 0xfe,
4939         0x14, 0x1c, 0x14, 0xfe, 0x30, 0x00, 0x37, 0x97, 0x01, 0xfe, 0x54, 0x0f,
4940         0x17, 0x06, 0x18, 0x96, 0x02, 0xd0, 0x1e, 0x20, 0x07, 0x10, 0x34, 0xfe,
4941         0x69, 0x10, 0x17, 0x06, 0x18, 0x96, 0xfe, 0x04, 0xec, 0x20, 0x46, 0x3d,
4942         0x12, 0x20, 0xfe, 0x05, 0xf6, 0xc7, 0x01, 0xfe, 0x52, 0x16, 0x09, 0x4a,
4943         0x4c, 0x35, 0x11, 0x2d, 0x3c, 0x8a, 0x01, 0xe6, 0x02, 0x29, 0x0a, 0x40,
4944         0x01, 0x0e, 0x07, 0x00, 0x5d, 0x01, 0x6f, 0xfe, 0x18, 0x10, 0xfe, 0x41,
4945         0x58, 0x0a, 0x99, 0x01, 0x0e, 0xfe, 0xc8, 0x54, 0x64, 0xfe, 0x0c, 0x03,
4946         0x01, 0xe6, 0x02, 0x29, 0x2a, 0x46, 0xfe, 0x02, 0xe8, 0x27, 0xf8, 0xfe,
4947         0x9e, 0x43, 0xf7, 0xfe, 0x27, 0xf0, 0xfe, 0xdc, 0x01, 0xfe, 0x07, 0x4b,
4948         0xfe, 0x20, 0xf0, 0x9c, 0xfe, 0x40, 0x1c, 0x25, 0xd2, 0xfe, 0x26, 0xf0,
4949         0xfe, 0x56, 0x03, 0xfe, 0xa0, 0xf0, 0xfe, 0x44, 0x03, 0xfe, 0x11, 0xf0,
4950         0x9c, 0xfe, 0xef, 0x10, 0xfe, 0x9f, 0xf0, 0xfe, 0x64, 0x03, 0xeb, 0x0f,
4951         0xfe, 0x11, 0x00, 0x02, 0x5a, 0x2a, 0xfe, 0x48, 0x1c, 0xeb, 0x09, 0x04,
4952         0x1d, 0xfe, 0x18, 0x13, 0x23, 0x1e, 0x98, 0xac, 0x12, 0x98, 0x0a, 0x40,
4953         0x01, 0x0e, 0xac, 0x75, 0x01, 0xfe, 0xbc, 0x15, 0x11, 0xca, 0x25, 0xd2,
4954         0xfe, 0x01, 0xf0, 0xd2, 0xfe, 0x82, 0xf0, 0xfe, 0x92, 0x03, 0xec, 0x11,
4955         0xfe, 0xe4, 0x00, 0x65, 0xfe, 0xa4, 0x03, 0x25, 0x32, 0x1f, 0xfe, 0xb4,
4956         0x03, 0x01, 0x43, 0xfe, 0x06, 0xf0, 0xfe, 0xc4, 0x03, 0x8d, 0x81, 0xfe,
4957         0x0a, 0xf0, 0xfe, 0x7a, 0x06, 0x02, 0x22, 0x05, 0x6b, 0x28, 0x16, 0xfe,
4958         0xf6, 0x04, 0x14, 0x2c, 0x01, 0x33, 0x8f, 0xfe, 0x66, 0x02, 0x02, 0xd1,
4959         0xeb, 0x2a, 0x67, 0x1a, 0xfe, 0x67, 0x1b, 0xf8, 0xf7, 0xfe, 0x48, 0x1c,
4960         0x70, 0x01, 0x6e, 0x87, 0x0a, 0x40, 0x01, 0x0e, 0x07, 0x00, 0x16, 0xd3,
4961         0x0a, 0xca, 0x01, 0x0e, 0x74, 0x60, 0x59, 0x76, 0x27, 0x05, 0x6b, 0x28,
4962         0xfe, 0x10, 0x12, 0x14, 0x2c, 0x01, 0x33, 0x8f, 0xfe, 0x66, 0x02, 0x02,
4963         0xd1, 0xbc, 0x7d, 0xbd, 0x7f, 0x25, 0x22, 0x65, 0xfe, 0x3c, 0x04, 0x1f,
4964         0xfe, 0x38, 0x04, 0x68, 0xfe, 0xa0, 0x00, 0xfe, 0x9b, 0x57, 0xfe, 0x4e,
4965         0x12, 0x2b, 0xff, 0x02, 0x00, 0x10, 0x01, 0x08, 0x1f, 0xfe, 0xe0, 0x04,
4966         0x2b, 0x01, 0x08, 0x1f, 0x22, 0x30, 0x2e, 0xd5, 0xfe, 0x4c, 0x44, 0xfe,
4967         0x4c, 0x12, 0x60, 0xfe, 0x44, 0x48, 0x13, 0x2c, 0xfe, 0x4c, 0x54, 0x64,
4968         0xd3, 0x46, 0x76, 0x27, 0xfa, 0xef, 0xfe, 0x62, 0x13, 0x09, 0x04, 0x1d,
4969         0xfe, 0x2a, 0x13, 0x2f, 0x07, 0x7e, 0xa5, 0xfe, 0x20, 0x10, 0x13, 0x2c,
4970         0xfe, 0x4c, 0x54, 0x64, 0xd3, 0xfa, 0xef, 0x86, 0x09, 0x04, 0x1d, 0xfe,
4971         0x08, 0x13, 0x2f, 0x07, 0x7e, 0x6e, 0x09, 0x04, 0x1d, 0xfe, 0x1c, 0x12,
4972         0x14, 0x92, 0x09, 0x04, 0x06, 0x3b, 0x14, 0xc4, 0x01, 0x33, 0x8f, 0xfe,
4973         0x70, 0x0c, 0x02, 0x22, 0x2b, 0x11, 0xfe, 0xe6, 0x00, 0xfe, 0x1c, 0x90,
4974         0xf9, 0x03, 0x14, 0x92, 0x01, 0x33, 0x02, 0x29, 0xfe, 0x42, 0x5b, 0x67,
4975         0x1a, 0xfe, 0x46, 0x59, 0xf8, 0xf7, 0xfe, 0x87, 0x80, 0xfe, 0x31, 0xe4,
4976         0x4f, 0x09, 0x04, 0x0b, 0xfe, 0x78, 0x13, 0xfe, 0x20, 0x80, 0x07, 0x1a,
4977         0xfe, 0x70, 0x12, 0x49, 0x04, 0x06, 0xfe, 0x60, 0x13, 0x05, 0xfe, 0xa2,
4978         0x00, 0x28, 0x16, 0xfe, 0x80, 0x05, 0xfe, 0x31, 0xe4, 0x6a, 0x49, 0x04,
4979         0x0b, 0xfe, 0x4a, 0x13, 0x05, 0xfe, 0xa0, 0x00, 0x28, 0xfe, 0x42, 0x12,
4980         0x5e, 0x01, 0x08, 0x25, 0x32, 0xf1, 0x01, 0x08, 0x26, 0xfe, 0x98, 0x05,
4981         0x11, 0xfe, 0xe3, 0x00, 0x23, 0x49, 0xfe, 0x4a, 0xf0, 0xfe, 0x6a, 0x05,
4982         0xfe, 0x49, 0xf0, 0xfe, 0x64, 0x05, 0x83, 0x24, 0xfe, 0x21, 0x00, 0xa1,
4983         0x24, 0xfe, 0x22, 0x00, 0xa0, 0x24, 0x4c, 0xfe, 0x09, 0x48, 0x01, 0x08,
4984         0x26, 0xfe, 0x98, 0x05, 0xfe, 0xe2, 0x08, 0x49, 0x04, 0xc5, 0x3b, 0x01,
4985         0x86, 0x24, 0x06, 0x12, 0xcc, 0x37, 0xfe, 0x27, 0x01, 0x09, 0x04, 0x1d,
4986         0xfe, 0x22, 0x12, 0x47, 0x01, 0xa7, 0x14, 0x92, 0x09, 0x04, 0x06, 0x3b,
4987         0x14, 0xc4, 0x01, 0x33, 0x8f, 0xfe, 0x70, 0x0c, 0x02, 0x22, 0x05, 0xfe,
4988         0x9c, 0x00, 0x28, 0xfe, 0x3e, 0x12, 0x05, 0x50, 0x28, 0xfe, 0x36, 0x13,
4989         0x47, 0x01, 0xa7, 0x26, 0xfe, 0x08, 0x06, 0x0a, 0x06, 0x49, 0x04, 0x19,
4990         0xfe, 0x02, 0x12, 0x5f, 0x01, 0xfe, 0xaa, 0x14, 0x1f, 0xfe, 0xfe, 0x05,
4991         0x11, 0x9a, 0x01, 0x43, 0x11, 0xfe, 0xe5, 0x00, 0x05, 0x50, 0xb4, 0x0c,
4992         0x50, 0x05, 0xc6, 0x28, 0xfe, 0x62, 0x12, 0x05, 0x3f, 0x28, 0xfe, 0x5a,
4993         0x13, 0x01, 0xfe, 0x14, 0x18, 0x01, 0xfe, 0x66, 0x18, 0xfe, 0x43, 0x48,
4994         0xb7, 0x19, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0x1c, 0x3d,
4995         0x85, 0xb7, 0x69, 0x47, 0x01, 0xa7, 0x26, 0xfe, 0x72, 0x06, 0x49, 0x04,
4996         0x1b, 0xdf, 0x89, 0x0a, 0x4d, 0x01, 0xfe, 0xd8, 0x14, 0x1f, 0xfe, 0x68,
4997         0x06, 0x11, 0x9a, 0x01, 0x43, 0x11, 0xfe, 0xe5, 0x00, 0x05, 0x3f, 0xb4,
4998         0x0c, 0x3f, 0x17, 0x06, 0x01, 0xa7, 0xec, 0x72, 0x70, 0x01, 0x6e, 0x87,
4999         0x11, 0xfe, 0xe2, 0x00, 0x01, 0x08, 0x25, 0x32, 0xfe, 0x0a, 0xf0, 0xfe,
5000         0xa6, 0x06, 0x8c, 0xfe, 0x5c, 0x07, 0xfe, 0x06, 0xf0, 0xfe, 0x64, 0x07,
5001         0x8d, 0x81, 0x02, 0x22, 0x09, 0x04, 0x0b, 0xfe, 0x2e, 0x12, 0x15, 0x1a,
5002         0x01, 0x08, 0x15, 0x00, 0x01, 0x08, 0x15, 0x00, 0x01, 0x08, 0x15, 0x00,
5003         0x01, 0x08, 0xfe, 0x99, 0xa4, 0x01, 0x08, 0x15, 0x00, 0x02, 0xfe, 0x32,
5004         0x08, 0x61, 0x04, 0x1b, 0xfe, 0x38, 0x12, 0x09, 0x04, 0x1b, 0x6e, 0x15,
5005         0xfe, 0x1b, 0x00, 0x01, 0x08, 0x15, 0x00, 0x01, 0x08, 0x15, 0x00, 0x01,
5006         0x08, 0x15, 0x00, 0x01, 0x08, 0x15, 0x06, 0x01, 0x08, 0x15, 0x00, 0x02,
5007         0xd9, 0x66, 0x4c, 0xfe, 0x3a, 0x55, 0x5f, 0xfe, 0x9a, 0x81, 0x4b, 0x1d,
5008         0xba, 0xfe, 0x32, 0x07, 0x0a, 0x1d, 0xfe, 0x09, 0x6f, 0xaf, 0xfe, 0xca,
5009         0x45, 0xfe, 0x32, 0x12, 0x62, 0x2c, 0x85, 0x66, 0x7b, 0x01, 0x08, 0x25,
5010         0x32, 0xfe, 0x0a, 0xf0, 0xfe, 0x32, 0x07, 0x8d, 0x81, 0x8c, 0xfe, 0x5c,
5011         0x07, 0x02, 0x22, 0x01, 0x43, 0x02, 0xfe, 0x8a, 0x06, 0x15, 0x19, 0x02,
5012         0xfe, 0x8a, 0x06, 0xfe, 0x9c, 0xf7, 0xd4, 0xfe, 0x2c, 0x90, 0xfe, 0xae,
5013         0x90, 0x77, 0xfe, 0xca, 0x07, 0x0c, 0x54, 0x18, 0x55, 0x09, 0x4a, 0x6a,
5014         0x35, 0x1e, 0x20, 0x07, 0x10, 0xfe, 0x0e, 0x12, 0x74, 0xfe, 0x80, 0x80,
5015         0x37, 0x20, 0x63, 0x27, 0xfe, 0x06, 0x10, 0xfe, 0x83, 0xe7, 0xc4, 0xa1,
5016         0xfe, 0x03, 0x40, 0x09, 0x4a, 0x4f, 0x35, 0x01, 0xa8, 0xad, 0xfe, 0x1f,
5017         0x40, 0x12, 0x58, 0x01, 0xa5, 0xfe, 0x08, 0x50, 0xfe, 0x8a, 0x50, 0xfe,
5018         0x44, 0x51, 0xfe, 0xc6, 0x51, 0x83, 0xfb, 0xfe, 0x8a, 0x90, 0x0c, 0x52,
5019         0x18, 0x53, 0xfe, 0x0c, 0x90, 0xfe, 0x8e, 0x90, 0xfe, 0x40, 0x50, 0xfe,
5020         0xc2, 0x50, 0x0c, 0x39, 0x18, 0x3a, 0xfe, 0x4a, 0x10, 0x09, 0x04, 0x6a,
5021         0xfe, 0x2a, 0x12, 0xfe, 0x2c, 0x90, 0xfe, 0xae, 0x90, 0x0c, 0x54, 0x18,
5022         0x55, 0x09, 0x04, 0x4f, 0x85, 0x01, 0xa8, 0xfe, 0x1f, 0x80, 0x12, 0x58,
5023         0xfe, 0x44, 0x90, 0xfe, 0xc6, 0x90, 0x0c, 0x56, 0x18, 0x57, 0xfb, 0xfe,
5024         0x8a, 0x90, 0x0c, 0x52, 0x18, 0x53, 0xfe, 0x40, 0x90, 0xfe, 0xc2, 0x90,
5025         0x0c, 0x39, 0x18, 0x3a, 0x0c, 0x38, 0x18, 0x4e, 0x09, 0x4a, 0x19, 0x35,
5026         0x2a, 0x13, 0xfe, 0x4e, 0x11, 0x65, 0xfe, 0x48, 0x08, 0xfe, 0x9e, 0xf0,
5027         0xfe, 0x5c, 0x08, 0xb1, 0x16, 0x32, 0x2a, 0x73, 0xdd, 0xb8, 0xfe, 0x80,
5028         0x08, 0xb9, 0xfe, 0x9e, 0x08, 0x8c, 0xfe, 0x74, 0x08, 0xfe, 0x06, 0xf0,
5029         0xfe, 0x7a, 0x08, 0x8d, 0x81, 0x02, 0x22, 0x01, 0x43, 0xfe, 0xc9, 0x10,
5030         0x15, 0x19, 0xfe, 0xc9, 0x10, 0x61, 0x04, 0x06, 0xfe, 0x10, 0x12, 0x61,
5031         0x04, 0x0b, 0x45, 0x09, 0x04, 0x0b, 0xfe, 0x68, 0x12, 0xfe, 0x2e, 0x1c,
5032         0x02, 0xfe, 0x24, 0x0a, 0x61, 0x04, 0x06, 0x45, 0x61, 0x04, 0x0b, 0xfe,
5033         0x52, 0x12, 0xfe, 0x2c, 0x1c, 0xfe, 0xaa, 0xf0, 0xfe, 0x1e, 0x09, 0xfe,
5034         0xac, 0xf0, 0xfe, 0xbe, 0x08, 0xfe, 0x8a, 0x10, 0xaa, 0xfe, 0xf3, 0x10,
5035         0xfe, 0xad, 0xf0, 0xfe, 0xca, 0x08, 0x02, 0xfe, 0x24, 0x0a, 0xab, 0xfe,
5036         0xe7, 0x10, 0xfe, 0x2b, 0xf0, 0x9d, 0xe9, 0x1c, 0xfe, 0x00, 0xfe, 0xfe,
5037         0x1c, 0x12, 0xb5, 0xfe, 0xd2, 0xf0, 0x9d, 0xfe, 0x76, 0x18, 0x1c, 0x1a,
5038         0x16, 0x9d, 0x05, 0xcb, 0x1c, 0x06, 0x16, 0x9d, 0xb8, 0x6d, 0xb9, 0x6d,
5039         0xaa, 0xab, 0xfe, 0xb1, 0x10, 0x70, 0x5e, 0x2b, 0x14, 0x92, 0x01, 0x33,
5040         0x0f, 0xfe, 0x35, 0x00, 0xfe, 0x01, 0xf0, 0x5a, 0x0f, 0x7c, 0x02, 0x5a,
5041         0xfe, 0x74, 0x18, 0x1c, 0xfe, 0x00, 0xf8, 0x16, 0x6d, 0x67, 0x1b, 0x01,
5042         0xfe, 0x44, 0x0d, 0x3b, 0x01, 0xe6, 0x1e, 0x27, 0x74, 0x67, 0x1a, 0x02,
5043         0x6d, 0x09, 0x04, 0x0b, 0x21, 0xfe, 0x06, 0x0a, 0x09, 0x04, 0x6a, 0xfe,
5044         0x82, 0x12, 0x09, 0x04, 0x19, 0xfe, 0x66, 0x13, 0x1e, 0x58, 0xac, 0xfc,
5045         0xfe, 0x83, 0x80, 0xfe, 0xc8, 0x44, 0xfe, 0x2e, 0x13, 0xfe, 0x04, 0x91,
5046         0xfe, 0x86, 0x91, 0x63, 0x27, 0xfe, 0x40, 0x59, 0xfe, 0xc1, 0x59, 0x77,
5047         0xd7, 0x05, 0x54, 0x31, 0x55, 0x0c, 0x7b, 0x18, 0x7c, 0xbe, 0x54, 0xbf,
5048         0x55, 0x01, 0xa8, 0xad, 0x63, 0x27, 0x12, 0x58, 0xc0, 0x38, 0xc1, 0x4e,
5049         0x79, 0x56, 0x68, 0x57, 0xf4, 0xf5, 0xfe, 0x04, 0xfa, 0x38, 0xfe, 0x05,
5050         0xfa, 0x4e, 0x01, 0xa5, 0xa2, 0x23, 0x0c, 0x7b, 0x0c, 0x7c, 0x79, 0x56,
5051         0x68, 0x57, 0xfe, 0x12, 0x10, 0x09, 0x04, 0x19, 0x16, 0xd7, 0x79, 0x39,
5052         0x68, 0x3a, 0x09, 0x04, 0xfe, 0xf7, 0x00, 0x35, 0x05, 0x52, 0x31, 0x53,
5053         0xfe, 0x10, 0x58, 0xfe, 0x91, 0x58, 0xfe, 0x14, 0x59, 0xfe, 0x95, 0x59,
5054         0x02, 0x6d, 0x09, 0x04, 0x19, 0x16, 0xd7, 0x09, 0x04, 0xfe, 0xf7, 0x00,
5055         0x35, 0xfe, 0x3a, 0x55, 0xfe, 0x19, 0x81, 0x5f, 0xfe, 0x10, 0x90, 0xfe,
5056         0x92, 0x90, 0xfe, 0xd7, 0x10, 0x2f, 0x07, 0x9b, 0x16, 0xfe, 0xc6, 0x08,
5057         0x11, 0x9b, 0x09, 0x04, 0x0b, 0xfe, 0x14, 0x13, 0x05, 0x39, 0x31, 0x3a,
5058         0x77, 0xfe, 0xc6, 0x08, 0xfe, 0x0c, 0x58, 0xfe, 0x8d, 0x58, 0x02, 0x6d,
5059         0x23, 0x47, 0xfe, 0x19, 0x80, 0xde, 0x09, 0x04, 0x0b, 0xfe, 0x1a, 0x12,
5060         0xfe, 0x6c, 0x19, 0xfe, 0x19, 0x41, 0xe9, 0xb5, 0xfe, 0xd1, 0xf0, 0xd9,
5061         0x14, 0x7a, 0x01, 0x33, 0x0f, 0xfe, 0x44, 0x00, 0xfe, 0x8e, 0x10, 0xfe,
5062         0x6c, 0x19, 0xbe, 0x39, 0xfe, 0xed, 0x19, 0xbf, 0x3a, 0xfe, 0x0c, 0x51,
5063         0xfe, 0x8e, 0x51, 0xe9, 0x1c, 0xfe, 0x00, 0xff, 0x34, 0xfe, 0x74, 0x10,
5064         0xb5, 0xfe, 0xd2, 0xf0, 0xfe, 0xb2, 0x0a, 0xfe, 0x76, 0x18, 0x1c, 0x1a,
5065         0x84, 0x05, 0xcb, 0x1c, 0x06, 0xfe, 0x08, 0x13, 0x0f, 0xfe, 0x16, 0x00,
5066         0x02, 0x5a, 0xfe, 0xd1, 0xf0, 0xfe, 0xc4, 0x0a, 0x14, 0x7a, 0x01, 0x33,
5067         0x0f, 0xfe, 0x17, 0x00, 0xfe, 0x42, 0x10, 0xfe, 0xce, 0xf0, 0xfe, 0xca,
5068         0x0a, 0xfe, 0x3c, 0x10, 0xfe, 0xcd, 0xf0, 0xfe, 0xd6, 0x0a, 0x0f, 0xfe,
5069         0x22, 0x00, 0x02, 0x5a, 0xfe, 0xcb, 0xf0, 0xfe, 0xe2, 0x0a, 0x0f, 0xfe,
5070         0x24, 0x00, 0x02, 0x5a, 0xfe, 0xd0, 0xf0, 0xfe, 0xec, 0x0a, 0x0f, 0x93,
5071         0xdc, 0xfe, 0xcf, 0xf0, 0xfe, 0xf6, 0x0a, 0x0f, 0x4c, 0xfe, 0x10, 0x10,
5072         0xfe, 0xcc, 0xf0, 0xd9, 0x61, 0x04, 0x19, 0x3b, 0x0f, 0xfe, 0x12, 0x00,
5073         0x2a, 0x13, 0xfe, 0x4e, 0x11, 0x65, 0xfe, 0x0c, 0x0b, 0xfe, 0x9e, 0xf0,
5074         0xfe, 0x20, 0x0b, 0xb1, 0x16, 0x32, 0x2a, 0x73, 0xdd, 0xb8, 0x22, 0xb9,
5075         0x22, 0x2a, 0xec, 0x65, 0xfe, 0x2c, 0x0b, 0x25, 0x32, 0x8c, 0xfe, 0x48,
5076         0x0b, 0x8d, 0x81, 0xb8, 0xd4, 0xb9, 0xd4, 0x02, 0x22, 0x01, 0x43, 0xfe,
5077         0xdb, 0x10, 0x11, 0xfe, 0xe8, 0x00, 0xaa, 0xab, 0x70, 0xbc, 0x7d, 0xbd,
5078         0x7f, 0xfe, 0x89, 0xf0, 0x22, 0x30, 0x2e, 0xd8, 0xbc, 0x7d, 0xbd, 0x7f,
5079         0x01, 0x08, 0x1f, 0x22, 0x30, 0x2e, 0xd6, 0xb1, 0x45, 0x0f, 0xfe, 0x42,
5080         0x00, 0x02, 0x5a, 0x78, 0x06, 0xfe, 0x81, 0x49, 0x16, 0xfe, 0x38, 0x0c,
5081         0x09, 0x04, 0x0b, 0xfe, 0x44, 0x13, 0x0f, 0x00, 0x4b, 0x0b, 0xfe, 0x54,
5082         0x12, 0x4b, 0xfe, 0x28, 0x00, 0x21, 0xfe, 0xa6, 0x0c, 0x0a, 0x40, 0x01,
5083         0x0e, 0x07, 0x00, 0x5d, 0x3e, 0xfe, 0x28, 0x00, 0xfe, 0xe2, 0x10, 0x01,
5084         0xe7, 0x01, 0xe8, 0x0a, 0x99, 0x01, 0xfe, 0x32, 0x0e, 0x59, 0x11, 0x2d,
5085         0x01, 0x6f, 0x02, 0x29, 0x0f, 0xfe, 0x44, 0x00, 0x4b, 0x0b, 0xdf, 0x3e,
5086         0x0b, 0xfe, 0xb4, 0x10, 0x01, 0x86, 0x3e, 0x0b, 0xfe, 0xaa, 0x10, 0x01,
5087         0x86, 0xfe, 0x19, 0x82, 0xfe, 0x34, 0x46, 0xa3, 0x3e, 0x0b, 0x0f, 0xfe,
5088         0x43, 0x00, 0xfe, 0x96, 0x10, 0x09, 0x4a, 0x0b, 0x35, 0x01, 0xe7, 0x01,
5089         0xe8, 0x59, 0x11, 0x2d, 0x01, 0x6f, 0x67, 0x0b, 0x59, 0x3c, 0x8a, 0x02,
5090         0xfe, 0x2a, 0x03, 0x09, 0x04, 0x0b, 0x84, 0x3e, 0x0b, 0x0f, 0x00, 0xfe,
5091         0x5c, 0x10, 0x61, 0x04, 0x1b, 0xfe, 0x58, 0x12, 0x09, 0x04, 0x1b, 0xfe,
5092         0x50, 0x13, 0xfe, 0x1c, 0x1c, 0xfe, 0x9d, 0xf0, 0xfe, 0x5c, 0x0c, 0xfe,
5093         0x1c, 0x1c, 0xfe, 0x9d, 0xf0, 0xfe, 0x62, 0x0c, 0x09, 0x4a, 0x1b, 0x35,
5094         0xfe, 0xa9, 0x10, 0x0f, 0xfe, 0x15, 0x00, 0xfe, 0x04, 0xe6, 0x0b, 0x5f,
5095         0x5c, 0x0f, 0xfe, 0x13, 0x00, 0xfe, 0x10, 0x10, 0x0f, 0xfe, 0x47, 0x00,
5096         0xa1, 0x0f, 0xfe, 0x41, 0x00, 0xa0, 0x0f, 0xfe, 0x24, 0x00, 0x87, 0xaa,
5097         0xab, 0x70, 0x05, 0x6b, 0x28, 0x21, 0xd1, 0x5f, 0xfe, 0x04, 0xe6, 0x1b,
5098         0xfe, 0x9d, 0x41, 0xfe, 0x1c, 0x42, 0x59, 0x01, 0xda, 0x02, 0x29, 0xea,
5099         0x14, 0x0b, 0x37, 0x95, 0xa9, 0x14, 0xfe, 0x31, 0x00, 0x37, 0x97, 0x01,
5100         0xfe, 0x54, 0x0f, 0x02, 0xd0, 0x3c, 0xfe, 0x06, 0xec, 0xc9, 0xee, 0x3e,
5101         0x1d, 0xfe, 0xce, 0x45, 0x34, 0x3c, 0xfe, 0x06, 0xea, 0xc9, 0xfe, 0x47,
5102         0x4b, 0x89, 0xfe, 0x75, 0x57, 0x05, 0x51, 0xfe, 0x98, 0x56, 0xfe, 0x38,
5103         0x12, 0x0a, 0x42, 0x01, 0x0e, 0xfe, 0x44, 0x48, 0x46, 0x09, 0x04, 0x1d,
5104         0xfe, 0x1a, 0x13, 0x0a, 0x40, 0x01, 0x0e, 0x47, 0xfe, 0x41, 0x58, 0x0a,
5105         0x99, 0x01, 0x0e, 0xfe, 0x49, 0x54, 0x8e, 0xfe, 0x2a, 0x0d, 0x02, 0xfe,
5106         0x2a, 0x03, 0x0a, 0x51, 0xfe, 0xee, 0x14, 0xee, 0x3e, 0x1d, 0xfe, 0xce,
5107         0x45, 0x34, 0x3c, 0xfe, 0xce, 0x47, 0xfe, 0xad, 0x13, 0x02, 0x29, 0x1e,
5108         0x20, 0x07, 0x10, 0xfe, 0x9e, 0x12, 0x23, 0x12, 0x4d, 0x12, 0x94, 0x12,
5109         0xce, 0x1e, 0x2d, 0x47, 0x37, 0x2d, 0xb1, 0xe0, 0xfe, 0xbc, 0xf0, 0xfe,
5110         0xec, 0x0d, 0x13, 0x06, 0x12, 0x4d, 0x01, 0xfe, 0xe2, 0x15, 0x05, 0xfe,
5111         0x38, 0x01, 0x31, 0xfe, 0x3a, 0x01, 0x77, 0xfe, 0xf0, 0x0d, 0xfe, 0x02,
5112         0xec, 0xce, 0x62, 0x00, 0x5d, 0xfe, 0x04, 0xec, 0x20, 0x46, 0xfe, 0x05,
5113         0xf6, 0xfe, 0x34, 0x01, 0x01, 0xfe, 0x52, 0x16, 0xfb, 0xfe, 0x48, 0xf4,
5114         0x0d, 0xfe, 0x18, 0x13, 0xaf, 0xfe, 0x02, 0xea, 0xce, 0x62, 0x7a, 0xfe,
5115         0xc5, 0x13, 0x14, 0x1b, 0x37, 0x95, 0xa9, 0x5c, 0x05, 0xfe, 0x38, 0x01,
5116         0x1c, 0xfe, 0xf0, 0xff, 0x0c, 0xfe, 0x60, 0x01, 0x05, 0xfe, 0x3a, 0x01,
5117         0x0c, 0xfe, 0x62, 0x01, 0x3d, 0x12, 0x20, 0x24, 0x06, 0x12, 0x2d, 0x11,
5118         0x2d, 0x8a, 0x13, 0x06, 0x03, 0x23, 0x03, 0x1e, 0x4d, 0xfe, 0xf7, 0x12,
5119         0x1e, 0x94, 0xac, 0x12, 0x94, 0x07, 0x7a, 0xfe, 0x71, 0x13, 0xfe, 0x24,
5120         0x1c, 0x14, 0x1a, 0x37, 0x95, 0xa9, 0xfe, 0xd9, 0x10, 0xb6, 0xfe, 0x03,
5121         0xdc, 0xfe, 0x73, 0x57, 0xfe, 0x80, 0x5d, 0x03, 0xb6, 0xfe, 0x03, 0xdc,
5122         0xfe, 0x5b, 0x57, 0xfe, 0x80, 0x5d, 0x03, 0xfe, 0x03, 0x57, 0xb6, 0x23,
5123         0xfe, 0x00, 0xcc, 0x03, 0xfe, 0x03, 0x57, 0xb6, 0x75, 0x03, 0x09, 0x04,
5124         0x4c, 0xfe, 0x22, 0x13, 0xfe, 0x1c, 0x80, 0x07, 0x06, 0xfe, 0x1a, 0x13,
5125         0xfe, 0x1e, 0x80, 0xe1, 0xfe, 0x1d, 0x80, 0xa4, 0xfe, 0x0c, 0x90, 0xfe,
5126         0x0e, 0x13, 0xfe, 0x0e, 0x90, 0xa3, 0xfe, 0x3c, 0x90, 0xfe, 0x30, 0xf4,
5127         0x0b, 0xfe, 0x3c, 0x50, 0xa0, 0x01, 0xfe, 0x82, 0x16, 0x2f, 0x07, 0x2d,
5128         0xe0, 0x01, 0xfe, 0xbc, 0x15, 0x09, 0x04, 0x1d, 0x45, 0x01, 0xe7, 0x01,
5129         0xe8, 0x11, 0xfe, 0xe9, 0x00, 0x09, 0x04, 0x4c, 0xfe, 0x2c, 0x13, 0x01,
5130         0xfe, 0x14, 0x16, 0xfe, 0x1e, 0x1c, 0xfe, 0x14, 0x90, 0xfe, 0x96, 0x90,
5131         0x0c, 0xfe, 0x64, 0x01, 0x18, 0xfe, 0x66, 0x01, 0x09, 0x04, 0x4f, 0xfe,
5132         0x12, 0x12, 0xfe, 0x03, 0x80, 0x74, 0xfe, 0x01, 0xec, 0x20, 0xfe, 0x80,
5133         0x40, 0x12, 0x20, 0x63, 0x27, 0x11, 0xc8, 0x59, 0x1e, 0x20, 0xed, 0x76,
5134         0x20, 0x03, 0xfe, 0x08, 0x1c, 0x05, 0xfe, 0xac, 0x00, 0xfe, 0x06, 0x58,
5135         0x05, 0xfe, 0xae, 0x00, 0xfe, 0x07, 0x58, 0x05, 0xfe, 0xb0, 0x00, 0xfe,
5136         0x08, 0x58, 0x05, 0xfe, 0xb2, 0x00, 0xfe, 0x09, 0x58, 0xfe, 0x0a, 0x1c,
5137         0x24, 0x69, 0x12, 0xc9, 0x23, 0x0c, 0x50, 0x0c, 0x3f, 0x13, 0x40, 0x48,
5138         0x5f, 0x17, 0x1d, 0xfe, 0x90, 0x4d, 0xfe, 0x91, 0x54, 0x21, 0xfe, 0x08,
5139         0x0f, 0x3e, 0x10, 0x13, 0x42, 0x48, 0x17, 0x4c, 0xfe, 0x90, 0x4d, 0xfe,
5140         0x91, 0x54, 0x21, 0xfe, 0x1e, 0x0f, 0x24, 0x10, 0x12, 0x20, 0x78, 0x2c,
5141         0x46, 0x1e, 0x20, 0xed, 0x76, 0x20, 0x11, 0xc8, 0xf6, 0xfe, 0xd6, 0xf0,
5142         0xfe, 0x32, 0x0f, 0xea, 0x70, 0xfe, 0x14, 0x1c, 0xfe, 0x10, 0x1c, 0xfe,
5143         0x18, 0x1c, 0x03, 0x3c, 0xfe, 0x0c, 0x14, 0xee, 0xfe, 0x07, 0xe6, 0x1d,
5144         0xfe, 0xce, 0x47, 0xfe, 0xf5, 0x13, 0x03, 0x01, 0x86, 0x78, 0x2c, 0x46,
5145         0xfa, 0xef, 0xfe, 0x42, 0x13, 0x2f, 0x07, 0x2d, 0xfe, 0x34, 0x13, 0x0a,
5146         0x42, 0x01, 0x0e, 0xb0, 0xfe, 0x36, 0x12, 0xf0, 0xfe, 0x45, 0x48, 0x01,
5147         0xe3, 0xfe, 0x00, 0xcc, 0xb0, 0xfe, 0xf3, 0x13, 0x3d, 0x75, 0x07, 0x10,
5148         0xa3, 0x0a, 0x80, 0x01, 0x0e, 0xfe, 0x80, 0x5c, 0x01, 0x6f, 0xfe, 0x0e,
5149         0x10, 0x07, 0x7e, 0x45, 0xf6, 0xfe, 0xd6, 0xf0, 0xfe, 0x6c, 0x0f, 0x03,
5150         0xfe, 0x44, 0x58, 0x74, 0xfe, 0x01, 0xec, 0x97, 0xfe, 0x9e, 0x40, 0xfe,
5151         0x9d, 0xe7, 0x00, 0xfe, 0x9c, 0xe7, 0x1b, 0x76, 0x27, 0x01, 0xda, 0xfe,
5152         0xdd, 0x10, 0x2a, 0xbc, 0x7d, 0xbd, 0x7f, 0x30, 0x2e, 0xd5, 0x07, 0x1b,
5153         0xfe, 0x48, 0x12, 0x07, 0x0b, 0xfe, 0x56, 0x12, 0x07, 0x1a, 0xfe, 0x30,
5154         0x12, 0x07, 0xc2, 0x16, 0xfe, 0x3e, 0x11, 0x07, 0xfe, 0x23, 0x00, 0x16,
5155         0xfe, 0x4a, 0x11, 0x07, 0x06, 0x16, 0xfe, 0xa8, 0x11, 0x07, 0x19, 0xfe,
5156         0x12, 0x12, 0x07, 0x00, 0x16, 0x22, 0x14, 0xc2, 0x01, 0x33, 0x9f, 0x2b,
5157         0x01, 0x08, 0x8c, 0x43, 0x03, 0x2b, 0xfe, 0x62, 0x08, 0x0a, 0xca, 0x01,
5158         0xfe, 0x32, 0x0e, 0x11, 0x7e, 0x02, 0x29, 0x2b, 0x2f, 0x07, 0x9b, 0xfe,
5159         0xd9, 0x13, 0x79, 0x39, 0x68, 0x3a, 0x77, 0xfe, 0xfc, 0x10, 0x09, 0x04,
5160         0x6a, 0xfe, 0x72, 0x12, 0xc0, 0x38, 0xc1, 0x4e, 0xf4, 0xf5, 0x8e, 0xfe,
5161         0xc6, 0x10, 0x1e, 0x58, 0xfe, 0x26, 0x13, 0x05, 0x7b, 0x31, 0x7c, 0x77,
5162         0xfe, 0x82, 0x0c, 0x0c, 0x54, 0x18, 0x55, 0x23, 0x0c, 0x7b, 0x0c, 0x7c,
5163         0x01, 0xa8, 0x24, 0x69, 0x73, 0x12, 0x58, 0x01, 0xa5, 0xc0, 0x38, 0xc1,
5164         0x4e, 0xfe, 0x04, 0x55, 0xfe, 0xa5, 0x55, 0xfe, 0x04, 0xfa, 0x38, 0xfe,
5165         0x05, 0xfa, 0x4e, 0xfe, 0x91, 0x10, 0x05, 0x56, 0x31, 0x57, 0xfe, 0x40,
5166         0x56, 0xfe, 0xe1, 0x56, 0x0c, 0x56, 0x18, 0x57, 0x83, 0xc0, 0x38, 0xc1,
5167         0x4e, 0xf4, 0xf5, 0x05, 0x52, 0x31, 0x53, 0xfe, 0x00, 0x56, 0xfe, 0xa1,
5168         0x56, 0x0c, 0x52, 0x18, 0x53, 0x09, 0x04, 0x6a, 0xfe, 0x1e, 0x12, 0x1e,
5169         0x58, 0xfe, 0x1f, 0x40, 0x05, 0x54, 0x31, 0x55, 0xfe, 0x2c, 0x50, 0xfe,
5170         0xae, 0x50, 0x05, 0x56, 0x31, 0x57, 0xfe, 0x44, 0x50, 0xfe, 0xc6, 0x50,
5171         0x05, 0x52, 0x31, 0x53, 0xfe, 0x08, 0x50, 0xfe, 0x8a, 0x50, 0x05, 0x39,
5172         0x31, 0x3a, 0xfe, 0x40, 0x50, 0xfe, 0xc2, 0x50, 0x02, 0x5c, 0x24, 0x06,
5173         0x12, 0xcd, 0x02, 0x5b, 0x2b, 0x01, 0x08, 0x1f, 0x44, 0x30, 0x2e, 0xd5,
5174         0x07, 0x06, 0x21, 0x44, 0x2f, 0x07, 0x9b, 0x21, 0x5b, 0x01, 0x6e, 0x1c,
5175         0x3d, 0x16, 0x44, 0x09, 0x04, 0x0b, 0xe2, 0x79, 0x39, 0x68, 0x3a, 0xfe,
5176         0x0a, 0x55, 0x34, 0xfe, 0x8b, 0x55, 0xbe, 0x39, 0xbf, 0x3a, 0xfe, 0x0c,
5177         0x51, 0xfe, 0x8e, 0x51, 0x02, 0x5b, 0xfe, 0x19, 0x81, 0xaf, 0xfe, 0x19,
5178         0x41, 0x02, 0x5b, 0x2b, 0x01, 0x08, 0x25, 0x32, 0x1f, 0xa2, 0x30, 0x2e,
5179         0xd8, 0x4b, 0x1a, 0xfe, 0xa6, 0x12, 0x4b, 0x0b, 0x3b, 0x02, 0x44, 0x01,
5180         0x08, 0x25, 0x32, 0x1f, 0xa2, 0x30, 0x2e, 0xd6, 0x07, 0x1a, 0x21, 0x44,
5181         0x01, 0x08, 0x1f, 0xa2, 0x30, 0x2e, 0xfe, 0xe8, 0x09, 0xfe, 0xc2, 0x49,
5182         0x60, 0x05, 0xfe, 0x9c, 0x00, 0x28, 0x84, 0x49, 0x04, 0x19, 0x34, 0x9f,
5183         0xfe, 0xbb, 0x45, 0x4b, 0x00, 0x45, 0x3e, 0x06, 0x78, 0x3d, 0xfe, 0xda,
5184         0x14, 0x01, 0x6e, 0x87, 0xfe, 0x4b, 0x45, 0xe2, 0x2f, 0x07, 0x9a, 0xe1,
5185         0x05, 0xc6, 0x28, 0x84, 0x05, 0x3f, 0x28, 0x34, 0x5e, 0x02, 0x5b, 0xfe,
5186         0xc0, 0x5d, 0xfe, 0xf8, 0x14, 0xfe, 0x03, 0x17, 0x05, 0x50, 0xb4, 0x0c,
5187         0x50, 0x5e, 0x2b, 0x01, 0x08, 0x26, 0x5c, 0x01, 0xfe, 0xaa, 0x14, 0x02,
5188         0x5c, 0x01, 0x08, 0x25, 0x32, 0x1f, 0x44, 0x30, 0x2e, 0xd6, 0x07, 0x06,
5189         0x21, 0x44, 0x01, 0xfe, 0x8e, 0x13, 0xfe, 0x42, 0x58, 0xfe, 0x82, 0x14,
5190         0xfe, 0xa4, 0x14, 0x87, 0xfe, 0x4a, 0xf4, 0x0b, 0x16, 0x44, 0xfe, 0x4a,
5191         0xf4, 0x06, 0xfe, 0x0c, 0x12, 0x2f, 0x07, 0x9a, 0x85, 0x02, 0x5b, 0x05,
5192         0x3f, 0xb4, 0x0c, 0x3f, 0x5e, 0x2b, 0x01, 0x08, 0x26, 0x5c, 0x01, 0xfe,
5193         0xd8, 0x14, 0x02, 0x5c, 0x13, 0x06, 0x65, 0xfe, 0xca, 0x12, 0x26, 0xfe,
5194         0xe0, 0x12, 0x72, 0xf1, 0x01, 0x08, 0x23, 0x72, 0x03, 0x8f, 0xfe, 0xdc,
5195         0x12, 0x25, 0xfe, 0xdc, 0x12, 0x1f, 0xfe, 0xca, 0x12, 0x5e, 0x2b, 0x01,
5196         0x08, 0xfe, 0xd5, 0x10, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b,
5197         0x1c, 0xfe, 0xff, 0x7f, 0xfe, 0x30, 0x56, 0xfe, 0x00, 0x5c, 0x03, 0x13,
5198         0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0x1c, 0x3d, 0xfe, 0x30, 0x56,
5199         0xfe, 0x00, 0x5c, 0x03, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b,
5200         0x03, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0xfe, 0x0b, 0x58,
5201         0x03, 0x0a, 0x50, 0x01, 0x82, 0x0a, 0x3f, 0x01, 0x82, 0x03, 0xfc, 0x1c,
5202         0x10, 0xff, 0x03, 0x00, 0x54, 0xfe, 0x00, 0xf4, 0x19, 0x48, 0xfe, 0x00,
5203         0x7d, 0xfe, 0x01, 0x7d, 0xfe, 0x02, 0x7d, 0xfe, 0x03, 0x7c, 0x63, 0x27,
5204         0x0c, 0x52, 0x18, 0x53, 0xbe, 0x56, 0xbf, 0x57, 0x03, 0xfe, 0x62, 0x08,
5205         0xfe, 0x82, 0x4a, 0xfe, 0xe1, 0x1a, 0xfe, 0x83, 0x5a, 0x74, 0x03, 0x01,
5206         0xfe, 0x14, 0x18, 0xfe, 0x42, 0x48, 0x5f, 0x60, 0x89, 0x01, 0x08, 0x1f,
5207         0xfe, 0xa2, 0x14, 0x30, 0x2e, 0xd8, 0x01, 0x08, 0x1f, 0xfe, 0xa2, 0x14,
5208         0x30, 0x2e, 0xfe, 0xe8, 0x0a, 0xfe, 0xc1, 0x59, 0x05, 0xc6, 0x28, 0xfe,
5209         0xcc, 0x12, 0x49, 0x04, 0x1b, 0xfe, 0xc4, 0x13, 0x23, 0x62, 0x1b, 0xe2,
5210         0x4b, 0xc3, 0x64, 0xfe, 0xe8, 0x13, 0x3b, 0x13, 0x06, 0x17, 0xc3, 0x78,
5211         0xdb, 0xfe, 0x78, 0x10, 0xff, 0x02, 0x83, 0x55, 0xa1, 0xff, 0x02, 0x83,
5212         0x55, 0x62, 0x1a, 0xa4, 0xbb, 0xfe, 0x30, 0x00, 0x8e, 0xe4, 0x17, 0x2c,
5213         0x13, 0x06, 0xfe, 0x56, 0x10, 0x62, 0x0b, 0xe1, 0xbb, 0xfe, 0x64, 0x00,
5214         0x8e, 0xe4, 0x0a, 0xfe, 0x64, 0x00, 0x17, 0x93, 0x13, 0x06, 0xfe, 0x28,
5215         0x10, 0x62, 0x06, 0xfe, 0x60, 0x13, 0xbb, 0xfe, 0xc8, 0x00, 0x8e, 0xe4,
5216         0x0a, 0xfe, 0xc8, 0x00, 0x17, 0x4d, 0x13, 0x06, 0x83, 0xbb, 0xfe, 0x90,
5217         0x01, 0xba, 0xfe, 0x4e, 0x14, 0x89, 0xfe, 0x12, 0x10, 0xfe, 0x43, 0xf4,
5218         0x94, 0xfe, 0x56, 0xf0, 0xfe, 0x60, 0x14, 0xfe, 0x04, 0xf4, 0x6c, 0xfe,
5219         0x43, 0xf4, 0x93, 0xfe, 0xf3, 0x10, 0xf9, 0x01, 0xfe, 0x22, 0x13, 0x1c,
5220         0x3d, 0xfe, 0x10, 0x13, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4, 0x69, 0xba,
5221         0xfe, 0x9c, 0x14, 0xb7, 0x69, 0xfe, 0x1c, 0x10, 0xfe, 0x00, 0x17, 0xfe,
5222         0x4d, 0xe4, 0x19, 0xba, 0xfe, 0x9c, 0x14, 0xb7, 0x19, 0x83, 0x60, 0x23,
5223         0xfe, 0x4d, 0xf4, 0x00, 0xdf, 0x89, 0x13, 0x06, 0xfe, 0xb4, 0x56, 0xfe,
5224         0xc3, 0x58, 0x03, 0x60, 0x13, 0x0b, 0x03, 0x15, 0x06, 0x01, 0x08, 0x26,
5225         0xe5, 0x15, 0x0b, 0x01, 0x08, 0x26, 0xe5, 0x15, 0x1a, 0x01, 0x08, 0x26,
5226         0xe5, 0x72, 0xfe, 0x89, 0x49, 0x01, 0x08, 0x03, 0x15, 0x06, 0x01, 0x08,
5227         0x26, 0xa6, 0x15, 0x1a, 0x01, 0x08, 0x26, 0xa6, 0x15, 0x06, 0x01, 0x08,
5228         0x26, 0xa6, 0xfe, 0x89, 0x49, 0x01, 0x08, 0x26, 0xa6, 0x72, 0xfe, 0x89,
5229         0x4a, 0x01, 0x08, 0x03, 0x60, 0x03, 0x1e, 0xcc, 0x07, 0x06, 0xfe, 0x44,
5230         0x13, 0xad, 0x12, 0xcc, 0xfe, 0x49, 0xf4, 0x00, 0x3b, 0x72, 0x9f, 0x5e,
5231         0xfe, 0x01, 0xec, 0xfe, 0x27, 0x01, 0xf1, 0x01, 0x08, 0x2f, 0x07, 0xfe,
5232         0xe3, 0x00, 0xfe, 0x20, 0x13, 0x1f, 0xfe, 0x5a, 0x15, 0x23, 0x12, 0xcd,
5233         0x01, 0x43, 0x1e, 0xcd, 0x07, 0x06, 0x45, 0x09, 0x4a, 0x06, 0x35, 0x03,
5234         0x0a, 0x42, 0x01, 0x0e, 0xed, 0x88, 0x07, 0x10, 0xa4, 0x0a, 0x80, 0x01,
5235         0x0e, 0x88, 0x0a, 0x51, 0x01, 0x9e, 0x03, 0x0a, 0x80, 0x01, 0x0e, 0x88,
5236         0xfe, 0x80, 0xe7, 0x10, 0x07, 0x10, 0x84, 0xfe, 0x45, 0x58, 0x01, 0xe3,
5237         0x88, 0x03, 0x0a, 0x42, 0x01, 0x0e, 0x88, 0x0a, 0x51, 0x01, 0x9e, 0x03,
5238         0x0a, 0x42, 0x01, 0x0e, 0xfe, 0x80, 0x80, 0xf2, 0xfe, 0x49, 0xe4, 0x10,
5239         0xa4, 0x0a, 0x80, 0x01, 0x0e, 0xf2, 0x0a, 0x51, 0x01, 0x82, 0x03, 0x17,
5240         0x10, 0x71, 0x66, 0xfe, 0x60, 0x01, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde,
5241         0xfe, 0x24, 0x1c, 0xfe, 0x1d, 0xf7, 0x1d, 0x90, 0xfe, 0xf6, 0x15, 0x01,
5242         0xfe, 0xfc, 0x16, 0xe0, 0x91, 0x1d, 0x66, 0xfe, 0x2c, 0x01, 0xfe, 0x2f,
5243         0x19, 0x03, 0xae, 0x21, 0xfe, 0xe6, 0x15, 0xfe, 0xda, 0x10, 0x17, 0x10,
5244         0x71, 0x05, 0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x19, 0xfe, 0x18, 0x58,
5245         0x05, 0xfe, 0x66, 0x01, 0xfe, 0x19, 0x58, 0x91, 0x19, 0xfe, 0x3c, 0x90,
5246         0xfe, 0x30, 0xf4, 0x06, 0xfe, 0x3c, 0x50, 0x66, 0xfe, 0x38, 0x00, 0xfe,
5247         0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0x19, 0x90, 0xfe, 0x40, 0x16, 0xfe, 0xb6,
5248         0x14, 0x34, 0x03, 0xae, 0x21, 0xfe, 0x18, 0x16, 0xfe, 0x9c, 0x10, 0x17,
5249         0x10, 0x71, 0xfe, 0x83, 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe,
5250         0x1d, 0xf7, 0x38, 0x90, 0xfe, 0x62, 0x16, 0xfe, 0x94, 0x14, 0xfe, 0x10,
5251         0x13, 0x91, 0x38, 0x66, 0x1b, 0xfe, 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00,
5252         0x03, 0xae, 0x21, 0xfe, 0x56, 0x16, 0xfe, 0x6c, 0x10, 0x17, 0x10, 0x71,
5253         0xfe, 0x30, 0xbc, 0xfe, 0xb2, 0xbc, 0x91, 0xc5, 0x66, 0x1b, 0xfe, 0x0f,
5254         0x79, 0xfe, 0x1c, 0xf7, 0xc5, 0x90, 0xfe, 0x9a, 0x16, 0xfe, 0x5c, 0x14,
5255         0x34, 0x03, 0xae, 0x21, 0xfe, 0x86, 0x16, 0xfe, 0x42, 0x10, 0xfe, 0x02,
5256         0xf6, 0x10, 0x71, 0xfe, 0x18, 0xfe, 0x54, 0xfe, 0x19, 0xfe, 0x55, 0xfc,
5257         0xfe, 0x1d, 0xf7, 0x4f, 0x90, 0xfe, 0xc0, 0x16, 0xfe, 0x36, 0x14, 0xfe,
5258         0x1c, 0x13, 0x91, 0x4f, 0x47, 0xfe, 0x83, 0x58, 0xfe, 0xaf, 0x19, 0xfe,
5259         0x80, 0xe7, 0x10, 0xfe, 0x81, 0xe7, 0x10, 0x11, 0xfe, 0xdd, 0x00, 0x63,
5260         0x27, 0x03, 0x63, 0x27, 0xfe, 0x12, 0x45, 0x21, 0xfe, 0xb0, 0x16, 0x14,
5261         0x06, 0x37, 0x95, 0xa9, 0x02, 0x29, 0xfe, 0x39, 0xf0, 0xfe, 0x04, 0x17,
5262         0x23, 0x03, 0xfe, 0x7e, 0x18, 0x1c, 0x1a, 0x5d, 0x13, 0x0d, 0x03, 0x71,
5263         0x05, 0xcb, 0x1c, 0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10, 0x78, 0x2c,
5264         0x46, 0x2f, 0x07, 0x2d, 0xfe, 0x3c, 0x13, 0xfe, 0x82, 0x14, 0xfe, 0x42,
5265         0x13, 0x3c, 0x8a, 0x0a, 0x42, 0x01, 0x0e, 0xb0, 0xfe, 0x3e, 0x12, 0xf0,
5266         0xfe, 0x45, 0x48, 0x01, 0xe3, 0xfe, 0x00, 0xcc, 0xb0, 0xfe, 0xf3, 0x13,
5267         0x3d, 0x75, 0x07, 0x10, 0xa3, 0x0a, 0x80, 0x01, 0x0e, 0xf2, 0x01, 0x6f,
5268         0xfe, 0x16, 0x10, 0x07, 0x7e, 0x85, 0xfe, 0x40, 0x14, 0xfe, 0x24, 0x12,
5269         0xf6, 0xfe, 0xd6, 0xf0, 0xfe, 0x24, 0x17, 0x17, 0x0b, 0x03, 0xfe, 0x9c,
5270         0xe7, 0x0b, 0x0f, 0xfe, 0x15, 0x00, 0x59, 0x76, 0x27, 0x01, 0xda, 0x17,
5271         0x06, 0x03, 0x3c, 0x8a, 0x09, 0x4a, 0x1d, 0x35, 0x11, 0x2d, 0x01, 0x6f,
5272         0x17, 0x06, 0x03, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x79, 0xc7, 0x68,
5273         0xc8, 0xfe, 0x48, 0x55, 0x34, 0xfe, 0xc9, 0x55, 0x03, 0x1e, 0x98, 0x73,
5274         0x12, 0x98, 0x03, 0x0a, 0x99, 0x01, 0x0e, 0xf0, 0x0a, 0x40, 0x01, 0x0e,
5275         0xfe, 0x49, 0x44, 0x16, 0xfe, 0xf0, 0x17, 0x73, 0x75, 0x03, 0x0a, 0x42,
5276         0x01, 0x0e, 0x07, 0x10, 0x45, 0x0a, 0x51, 0x01, 0x9e, 0x0a, 0x40, 0x01,
5277         0x0e, 0x73, 0x75, 0x03, 0xfe, 0x4e, 0xe4, 0x1a, 0x64, 0xfe, 0x24, 0x18,
5278         0x05, 0xfe, 0x90, 0x00, 0xfe, 0x3a, 0x45, 0x5b, 0xfe, 0x4e, 0xe4, 0xc2,
5279         0x64, 0xfe, 0x36, 0x18, 0x05, 0xfe, 0x92, 0x00, 0xfe, 0x02, 0xe6, 0x1b,
5280         0xdc, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x64, 0xfe, 0x48, 0x18, 0x05,
5281         0xfe, 0x94, 0x00, 0xfe, 0x02, 0xe6, 0x19, 0xfe, 0x08, 0x10, 0x05, 0xfe,
5282         0x96, 0x00, 0xfe, 0x02, 0xe6, 0x2c, 0xfe, 0x4e, 0x45, 0xfe, 0x0c, 0x12,
5283         0xaf, 0xff, 0x04, 0x68, 0x54, 0xde, 0x1c, 0x69, 0x03, 0x07, 0x7a, 0xfe,
5284         0x5a, 0xf0, 0xfe, 0x74, 0x18, 0x24, 0xfe, 0x09, 0x00, 0xfe, 0x34, 0x10,
5285         0x07, 0x1b, 0xfe, 0x5a, 0xf0, 0xfe, 0x82, 0x18, 0x24, 0xc3, 0xfe, 0x26,
5286         0x10, 0x07, 0x1a, 0x5d, 0x24, 0x2c, 0xdc, 0x07, 0x0b, 0x5d, 0x24, 0x93,
5287         0xfe, 0x0e, 0x10, 0x07, 0x06, 0x5d, 0x24, 0x4d, 0x9f, 0xad, 0x03, 0x14,
5288         0xfe, 0x09, 0x00, 0x01, 0x33, 0xfe, 0x04, 0xfe, 0x7d, 0x05, 0x7f, 0xf9,
5289         0x03, 0x25, 0xfe, 0xca, 0x18, 0xfe, 0x14, 0xf0, 0x08, 0x65, 0xfe, 0xc6,
5290         0x18, 0x03, 0xff, 0x1a, 0x00, 0x00,
5291 };
5292
5293 static unsigned short _adv_asc3550_size = sizeof(_adv_asc3550_buf);     /* 0x13AD */
5294 static ADV_DCNT _adv_asc3550_chksum = 0x04D52DDDUL;     /* Expanded little-endian checksum. */
5295
5296 /* Microcode buffer is kept after initialization for error recovery. */
5297 static unsigned char _adv_asc38C0800_buf[] = {
5298         0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0xfc, 0x00, 0x16, 0x18, 0xe4,
5299         0x01, 0x00, 0x48, 0xe4, 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00, 0xce, 0x19,
5300         0x00, 0xfa, 0xff, 0xff, 0x1c, 0x0f, 0x00, 0xf6, 0x9e, 0xe7, 0xff, 0x00,
5301         0x82, 0xe7, 0x00, 0xea, 0x01, 0xfa, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0,
5302         0x01, 0xf6, 0x03, 0x00, 0x04, 0x00, 0x10, 0x00, 0x1e, 0xf0, 0x85, 0xf0,
5303         0x18, 0xf4, 0x08, 0x00, 0xbc, 0x00, 0x38, 0x54, 0x00, 0xec, 0xd5, 0xf0,
5304         0x82, 0x0d, 0x00, 0xe6, 0x86, 0xf0, 0xb1, 0xf0, 0x98, 0x57, 0x01, 0xfc,
5305         0xb4, 0x00, 0xd4, 0x01, 0x0c, 0x1c, 0x3e, 0x1c, 0x3c, 0x00, 0xbb, 0x00,
5306         0x00, 0x10, 0xba, 0x19, 0x02, 0x80, 0x32, 0xf0, 0x7c, 0x0d, 0x02, 0x13,
5307         0xba, 0x13, 0x18, 0x40, 0x00, 0x57, 0x01, 0xea, 0x02, 0xfc, 0x03, 0xfc,
5308         0x3e, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x74, 0x01, 0x76, 0x01, 0xb9, 0x54,
5309         0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00, 0xc0, 0x00, 0x01, 0x01,
5310         0x3e, 0x01, 0x7a, 0x01, 0xca, 0x08, 0xce, 0x10, 0x16, 0x11, 0x04, 0x12,
5311         0x08, 0x12, 0x02, 0x4a, 0xbb, 0x55, 0x3c, 0x56, 0x03, 0x58, 0x1b, 0x80,
5312         0x30, 0xe4, 0x4b, 0xe4, 0x5d, 0xf0, 0x02, 0xfa, 0x20, 0x00, 0x32, 0x00,
5313         0x40, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01,
5314         0x70, 0x01, 0x72, 0x01, 0x78, 0x01, 0x7c, 0x01, 0x62, 0x0a, 0x86, 0x0d,
5315         0x06, 0x13, 0x4c, 0x1c, 0x04, 0x80, 0x4a, 0xe4, 0x02, 0xee, 0x5b, 0xf0,
5316         0x03, 0xf7, 0x0c, 0x00, 0x0f, 0x00, 0x47, 0x00, 0xbe, 0x00, 0x00, 0x01,
5317         0x20, 0x11, 0x5c, 0x16, 0x32, 0x1c, 0x38, 0x1c, 0x4e, 0x1c, 0x10, 0x44,
5318         0x00, 0x4c, 0x04, 0xea, 0x5c, 0xf0, 0xa7, 0xf0, 0x04, 0xf6, 0x03, 0xfa,
5319         0x05, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00, 0xcc, 0x00, 0x20, 0x01,
5320         0x4e, 0x01, 0x4a, 0x0b, 0x42, 0x0c, 0x12, 0x0f, 0x0c, 0x10, 0x22, 0x11,
5321         0x0a, 0x12, 0x04, 0x13, 0x30, 0x1c, 0x02, 0x48, 0x00, 0x4e, 0x42, 0x54,
5322         0x44, 0x55, 0xbd, 0x56, 0x06, 0x83, 0x00, 0xdc, 0x05, 0xf0, 0x09, 0xf0,
5323         0x59, 0xf0, 0xb8, 0xf0, 0x4b, 0xf4, 0x06, 0xf7, 0x0e, 0xf7, 0x04, 0xfc,
5324         0x05, 0xfc, 0x06, 0x00, 0x19, 0x00, 0x33, 0x00, 0x9b, 0x00, 0xa4, 0x00,
5325         0xb5, 0x00, 0xba, 0x00, 0xd0, 0x00, 0xe1, 0x00, 0xe7, 0x00, 0xe2, 0x03,
5326         0x08, 0x0f, 0x02, 0x10, 0x04, 0x10, 0x0a, 0x10, 0x0a, 0x13, 0x0c, 0x13,
5327         0x12, 0x13, 0x24, 0x14, 0x34, 0x14, 0x04, 0x16, 0x08, 0x16, 0xa4, 0x17,
5328         0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c, 0x08, 0x44, 0x38, 0x44, 0x91, 0x44,
5329         0x0a, 0x45, 0x48, 0x46, 0x01, 0x48, 0x68, 0x54, 0x3a, 0x55, 0x83, 0x55,
5330         0xe5, 0x55, 0xb0, 0x57, 0x01, 0x58, 0x83, 0x59, 0x05, 0xe6, 0x0b, 0xf0,
5331         0x0c, 0xf0, 0x04, 0xf8, 0x05, 0xf8, 0x07, 0x00, 0x0a, 0x00, 0x1c, 0x00,
5332         0x1e, 0x00, 0x9e, 0x00, 0xa8, 0x00, 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00,
5333         0x22, 0x01, 0x26, 0x01, 0x79, 0x01, 0x7e, 0x01, 0xc4, 0x01, 0xc6, 0x01,
5334         0x80, 0x02, 0x5e, 0x03, 0xee, 0x04, 0x9a, 0x06, 0xf8, 0x07, 0x62, 0x08,
5335         0x68, 0x08, 0x69, 0x08, 0xd6, 0x08, 0xe9, 0x09, 0xfa, 0x0b, 0x2e, 0x0f,
5336         0x12, 0x10, 0x1a, 0x10, 0xed, 0x10, 0xf1, 0x10, 0x2a, 0x11, 0x06, 0x12,
5337         0x0c, 0x12, 0x3e, 0x12, 0x10, 0x13, 0x16, 0x13, 0x1e, 0x13, 0x46, 0x14,
5338         0x76, 0x14, 0x82, 0x14, 0x36, 0x15, 0xca, 0x15, 0x6b, 0x18, 0xbe, 0x18,
5339         0xca, 0x18, 0xe6, 0x19, 0x12, 0x1c, 0x46, 0x1c, 0x9c, 0x32, 0x00, 0x40,
5340         0x0e, 0x47, 0xfe, 0x9c, 0xf0, 0x2b, 0x02, 0xfe, 0xac, 0x0d, 0xff, 0x10,
5341         0x00, 0x00, 0xd7, 0xfe, 0xe8, 0x19, 0x00, 0xd6, 0xfe, 0x84, 0x01, 0xff,
5342         0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00,
5343         0x00, 0xfe, 0x57, 0x24, 0x00, 0xfe, 0x4c, 0x00, 0x5b, 0xff, 0x04, 0x00,
5344         0x00, 0x11, 0xff, 0x09, 0x00, 0x00, 0xff, 0x08, 0x01, 0x01, 0xff, 0x08,
5345         0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10, 0xff, 0xff, 0xff, 0x11,
5346         0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00,
5347         0xfe, 0x04, 0xf7, 0xd6, 0x2c, 0x99, 0x0a, 0x01, 0xfe, 0xc2, 0x0f, 0xfe,
5348         0x04, 0xf7, 0xd6, 0x99, 0x0a, 0x42, 0x2c, 0xfe, 0x3d, 0xf0, 0xfe, 0x06,
5349         0x02, 0xfe, 0x20, 0xf0, 0xa7, 0xfe, 0x91, 0xf0, 0xfe, 0xf4, 0x01, 0xfe,
5350         0x90, 0xf0, 0xfe, 0xf4, 0x01, 0xfe, 0x8f, 0xf0, 0xa7, 0x03, 0x5d, 0x4d,
5351         0x02, 0xfe, 0xc8, 0x0d, 0x01, 0xfe, 0x38, 0x0e, 0xfe, 0xdd, 0x12, 0xfe,
5352         0xfc, 0x10, 0xfe, 0x28, 0x1c, 0x03, 0xfe, 0xa6, 0x00, 0xfe, 0xd3, 0x12,
5353         0x41, 0x14, 0xfe, 0xa6, 0x00, 0xc2, 0xfe, 0x48, 0xf0, 0xfe, 0x8a, 0x02,
5354         0xfe, 0x49, 0xf0, 0xfe, 0xa4, 0x02, 0xfe, 0x4a, 0xf0, 0xfe, 0xc2, 0x02,
5355         0xfe, 0x46, 0xf0, 0xfe, 0x54, 0x02, 0xfe, 0x47, 0xf0, 0xfe, 0x5a, 0x02,
5356         0xfe, 0x43, 0xf0, 0xfe, 0x48, 0x02, 0xfe, 0x44, 0xf0, 0xfe, 0x4c, 0x02,
5357         0xfe, 0x45, 0xf0, 0xfe, 0x50, 0x02, 0x18, 0x0a, 0xaa, 0x18, 0x06, 0x14,
5358         0xa1, 0x02, 0x2b, 0xfe, 0x00, 0x1c, 0xe7, 0xfe, 0x02, 0x1c, 0xe6, 0xfe,
5359         0x1e, 0x1c, 0xfe, 0xe9, 0x10, 0x01, 0xfe, 0x18, 0x18, 0xfe, 0xe7, 0x10,
5360         0xfe, 0x06, 0xfc, 0xce, 0x09, 0x70, 0x01, 0xa8, 0x02, 0x2b, 0x15, 0x59,
5361         0x39, 0xa2, 0x01, 0xfe, 0x58, 0x10, 0x09, 0x70, 0x01, 0x87, 0xfe, 0xbd,
5362         0x10, 0x09, 0x70, 0x01, 0x87, 0xfe, 0xad, 0x10, 0xfe, 0x16, 0x1c, 0xfe,
5363         0x58, 0x1c, 0x18, 0x06, 0x14, 0xa1, 0x2c, 0x1c, 0x2b, 0xfe, 0x3d, 0xf0,
5364         0xfe, 0x06, 0x02, 0x23, 0xfe, 0x98, 0x02, 0xfe, 0x5a, 0x1c, 0xf8, 0xfe,
5365         0x14, 0x1c, 0x15, 0xfe, 0x30, 0x00, 0x39, 0xa2, 0x01, 0xfe, 0x48, 0x10,
5366         0x18, 0x06, 0x14, 0xa1, 0x02, 0xd7, 0x22, 0x20, 0x07, 0x11, 0x35, 0xfe,
5367         0x69, 0x10, 0x18, 0x06, 0x14, 0xa1, 0xfe, 0x04, 0xec, 0x20, 0x4f, 0x43,
5368         0x13, 0x20, 0xfe, 0x05, 0xf6, 0xce, 0x01, 0xfe, 0x4a, 0x17, 0x08, 0x54,
5369         0x58, 0x37, 0x12, 0x2f, 0x42, 0x92, 0x01, 0xfe, 0x82, 0x16, 0x02, 0x2b,
5370         0x09, 0x46, 0x01, 0x0e, 0x07, 0x00, 0x66, 0x01, 0x73, 0xfe, 0x18, 0x10,
5371         0xfe, 0x41, 0x58, 0x09, 0xa4, 0x01, 0x0e, 0xfe, 0xc8, 0x54, 0x6b, 0xfe,
5372         0x10, 0x03, 0x01, 0xfe, 0x82, 0x16, 0x02, 0x2b, 0x2c, 0x4f, 0xfe, 0x02,
5373         0xe8, 0x2a, 0xfe, 0xbf, 0x57, 0xfe, 0x9e, 0x43, 0xfe, 0x77, 0x57, 0xfe,
5374         0x27, 0xf0, 0xfe, 0xe0, 0x01, 0xfe, 0x07, 0x4b, 0xfe, 0x20, 0xf0, 0xa7,
5375         0xfe, 0x40, 0x1c, 0x1c, 0xd9, 0xfe, 0x26, 0xf0, 0xfe, 0x5a, 0x03, 0xfe,
5376         0xa0, 0xf0, 0xfe, 0x48, 0x03, 0xfe, 0x11, 0xf0, 0xa7, 0xfe, 0xef, 0x10,
5377         0xfe, 0x9f, 0xf0, 0xfe, 0x68, 0x03, 0xf9, 0x10, 0xfe, 0x11, 0x00, 0x02,
5378         0x65, 0x2c, 0xfe, 0x48, 0x1c, 0xf9, 0x08, 0x05, 0x1b, 0xfe, 0x18, 0x13,
5379         0x21, 0x22, 0xa3, 0xb7, 0x13, 0xa3, 0x09, 0x46, 0x01, 0x0e, 0xb7, 0x78,
5380         0x01, 0xfe, 0xb4, 0x16, 0x12, 0xd1, 0x1c, 0xd9, 0xfe, 0x01, 0xf0, 0xd9,
5381         0xfe, 0x82, 0xf0, 0xfe, 0x96, 0x03, 0xfa, 0x12, 0xfe, 0xe4, 0x00, 0x27,
5382         0xfe, 0xa8, 0x03, 0x1c, 0x34, 0x1d, 0xfe, 0xb8, 0x03, 0x01, 0x4b, 0xfe,
5383         0x06, 0xf0, 0xfe, 0xc8, 0x03, 0x95, 0x86, 0xfe, 0x0a, 0xf0, 0xfe, 0x8a,
5384         0x06, 0x02, 0x24, 0x03, 0x70, 0x28, 0x17, 0xfe, 0xfa, 0x04, 0x15, 0x6d,
5385         0x01, 0x36, 0x7b, 0xfe, 0x6a, 0x02, 0x02, 0xd8, 0xf9, 0x2c, 0x99, 0x19,
5386         0xfe, 0x67, 0x1b, 0xfe, 0xbf, 0x57, 0xfe, 0x77, 0x57, 0xfe, 0x48, 0x1c,
5387         0x74, 0x01, 0xaf, 0x8c, 0x09, 0x46, 0x01, 0x0e, 0x07, 0x00, 0x17, 0xda,
5388         0x09, 0xd1, 0x01, 0x0e, 0x8d, 0x51, 0x64, 0x79, 0x2a, 0x03, 0x70, 0x28,
5389         0xfe, 0x10, 0x12, 0x15, 0x6d, 0x01, 0x36, 0x7b, 0xfe, 0x6a, 0x02, 0x02,
5390         0xd8, 0xc7, 0x81, 0xc8, 0x83, 0x1c, 0x24, 0x27, 0xfe, 0x40, 0x04, 0x1d,
5391         0xfe, 0x3c, 0x04, 0x3b, 0xfe, 0xa0, 0x00, 0xfe, 0x9b, 0x57, 0xfe, 0x4e,
5392         0x12, 0x2d, 0xff, 0x02, 0x00, 0x10, 0x01, 0x0b, 0x1d, 0xfe, 0xe4, 0x04,
5393         0x2d, 0x01, 0x0b, 0x1d, 0x24, 0x33, 0x31, 0xde, 0xfe, 0x4c, 0x44, 0xfe,
5394         0x4c, 0x12, 0x51, 0xfe, 0x44, 0x48, 0x0f, 0x6f, 0xfe, 0x4c, 0x54, 0x6b,
5395         0xda, 0x4f, 0x79, 0x2a, 0xfe, 0x06, 0x80, 0xfe, 0x48, 0x47, 0xfe, 0x62,
5396         0x13, 0x08, 0x05, 0x1b, 0xfe, 0x2a, 0x13, 0x32, 0x07, 0x82, 0xfe, 0x52,
5397         0x13, 0xfe, 0x20, 0x10, 0x0f, 0x6f, 0xfe, 0x4c, 0x54, 0x6b, 0xda, 0xfe,
5398         0x06, 0x80, 0xfe, 0x48, 0x47, 0xfe, 0x40, 0x13, 0x08, 0x05, 0x1b, 0xfe,
5399         0x08, 0x13, 0x32, 0x07, 0x82, 0xfe, 0x30, 0x13, 0x08, 0x05, 0x1b, 0xfe,
5400         0x1c, 0x12, 0x15, 0x9d, 0x08, 0x05, 0x06, 0x4d, 0x15, 0xfe, 0x0d, 0x00,
5401         0x01, 0x36, 0x7b, 0xfe, 0x64, 0x0d, 0x02, 0x24, 0x2d, 0x12, 0xfe, 0xe6,
5402         0x00, 0xfe, 0x1c, 0x90, 0xfe, 0x40, 0x5c, 0x04, 0x15, 0x9d, 0x01, 0x36,
5403         0x02, 0x2b, 0xfe, 0x42, 0x5b, 0x99, 0x19, 0xfe, 0x46, 0x59, 0xfe, 0xbf,
5404         0x57, 0xfe, 0x77, 0x57, 0xfe, 0x87, 0x80, 0xfe, 0x31, 0xe4, 0x5b, 0x08,
5405         0x05, 0x0a, 0xfe, 0x84, 0x13, 0xfe, 0x20, 0x80, 0x07, 0x19, 0xfe, 0x7c,
5406         0x12, 0x53, 0x05, 0x06, 0xfe, 0x6c, 0x13, 0x03, 0xfe, 0xa2, 0x00, 0x28,
5407         0x17, 0xfe, 0x90, 0x05, 0xfe, 0x31, 0xe4, 0x5a, 0x53, 0x05, 0x0a, 0xfe,
5408         0x56, 0x13, 0x03, 0xfe, 0xa0, 0x00, 0x28, 0xfe, 0x4e, 0x12, 0x67, 0xff,
5409         0x02, 0x00, 0x10, 0x27, 0xfe, 0x48, 0x05, 0x1c, 0x34, 0xfe, 0x89, 0x48,
5410         0xff, 0x02, 0x00, 0x10, 0x27, 0xfe, 0x56, 0x05, 0x26, 0xfe, 0xa8, 0x05,
5411         0x12, 0xfe, 0xe3, 0x00, 0x21, 0x53, 0xfe, 0x4a, 0xf0, 0xfe, 0x76, 0x05,
5412         0xfe, 0x49, 0xf0, 0xfe, 0x70, 0x05, 0x88, 0x25, 0xfe, 0x21, 0x00, 0xab,
5413         0x25, 0xfe, 0x22, 0x00, 0xaa, 0x25, 0x58, 0xfe, 0x09, 0x48, 0xff, 0x02,
5414         0x00, 0x10, 0x27, 0xfe, 0x86, 0x05, 0x26, 0xfe, 0xa8, 0x05, 0xfe, 0xe2,
5415         0x08, 0x53, 0x05, 0xcb, 0x4d, 0x01, 0xb0, 0x25, 0x06, 0x13, 0xd3, 0x39,
5416         0xfe, 0x27, 0x01, 0x08, 0x05, 0x1b, 0xfe, 0x22, 0x12, 0x41, 0x01, 0xb2,
5417         0x15, 0x9d, 0x08, 0x05, 0x06, 0x4d, 0x15, 0xfe, 0x0d, 0x00, 0x01, 0x36,
5418         0x7b, 0xfe, 0x64, 0x0d, 0x02, 0x24, 0x03, 0xfe, 0x9c, 0x00, 0x28, 0xeb,
5419         0x03, 0x5c, 0x28, 0xfe, 0x36, 0x13, 0x41, 0x01, 0xb2, 0x26, 0xfe, 0x18,
5420         0x06, 0x09, 0x06, 0x53, 0x05, 0x1f, 0xfe, 0x02, 0x12, 0x50, 0x01, 0xfe,
5421         0x9e, 0x15, 0x1d, 0xfe, 0x0e, 0x06, 0x12, 0xa5, 0x01, 0x4b, 0x12, 0xfe,
5422         0xe5, 0x00, 0x03, 0x5c, 0xc1, 0x0c, 0x5c, 0x03, 0xcd, 0x28, 0xfe, 0x62,
5423         0x12, 0x03, 0x45, 0x28, 0xfe, 0x5a, 0x13, 0x01, 0xfe, 0x0c, 0x19, 0x01,
5424         0xfe, 0x76, 0x19, 0xfe, 0x43, 0x48, 0xc4, 0xcc, 0x0f, 0x71, 0xff, 0x02,
5425         0x00, 0x57, 0x52, 0x93, 0x1e, 0x43, 0x8b, 0xc4, 0x6e, 0x41, 0x01, 0xb2,
5426         0x26, 0xfe, 0x82, 0x06, 0x53, 0x05, 0x1a, 0xe9, 0x91, 0x09, 0x59, 0x01,
5427         0xfe, 0xcc, 0x15, 0x1d, 0xfe, 0x78, 0x06, 0x12, 0xa5, 0x01, 0x4b, 0x12,
5428         0xfe, 0xe5, 0x00, 0x03, 0x45, 0xc1, 0x0c, 0x45, 0x18, 0x06, 0x01, 0xb2,
5429         0xfa, 0x76, 0x74, 0x01, 0xaf, 0x8c, 0x12, 0xfe, 0xe2, 0x00, 0x27, 0xdb,
5430         0x1c, 0x34, 0xfe, 0x0a, 0xf0, 0xfe, 0xb6, 0x06, 0x94, 0xfe, 0x6c, 0x07,
5431         0xfe, 0x06, 0xf0, 0xfe, 0x74, 0x07, 0x95, 0x86, 0x02, 0x24, 0x08, 0x05,
5432         0x0a, 0xfe, 0x2e, 0x12, 0x16, 0x19, 0x01, 0x0b, 0x16, 0x00, 0x01, 0x0b,
5433         0x16, 0x00, 0x01, 0x0b, 0x16, 0x00, 0x01, 0x0b, 0xfe, 0x99, 0xa4, 0x01,
5434         0x0b, 0x16, 0x00, 0x02, 0xfe, 0x42, 0x08, 0x68, 0x05, 0x1a, 0xfe, 0x38,
5435         0x12, 0x08, 0x05, 0x1a, 0xfe, 0x30, 0x13, 0x16, 0xfe, 0x1b, 0x00, 0x01,
5436         0x0b, 0x16, 0x00, 0x01, 0x0b, 0x16, 0x00, 0x01, 0x0b, 0x16, 0x00, 0x01,
5437         0x0b, 0x16, 0x06, 0x01, 0x0b, 0x16, 0x00, 0x02, 0xe2, 0x6c, 0x58, 0xbe,
5438         0x50, 0xfe, 0x9a, 0x81, 0x55, 0x1b, 0x7a, 0xfe, 0x42, 0x07, 0x09, 0x1b,
5439         0xfe, 0x09, 0x6f, 0xba, 0xfe, 0xca, 0x45, 0xfe, 0x32, 0x12, 0x69, 0x6d,
5440         0x8b, 0x6c, 0x7f, 0x27, 0xfe, 0x54, 0x07, 0x1c, 0x34, 0xfe, 0x0a, 0xf0,
5441         0xfe, 0x42, 0x07, 0x95, 0x86, 0x94, 0xfe, 0x6c, 0x07, 0x02, 0x24, 0x01,
5442         0x4b, 0x02, 0xdb, 0x16, 0x1f, 0x02, 0xdb, 0xfe, 0x9c, 0xf7, 0xdc, 0xfe,
5443         0x2c, 0x90, 0xfe, 0xae, 0x90, 0x56, 0xfe, 0xda, 0x07, 0x0c, 0x60, 0x14,
5444         0x61, 0x08, 0x54, 0x5a, 0x37, 0x22, 0x20, 0x07, 0x11, 0xfe, 0x0e, 0x12,
5445         0x8d, 0xfe, 0x80, 0x80, 0x39, 0x20, 0x6a, 0x2a, 0xfe, 0x06, 0x10, 0xfe,
5446         0x83, 0xe7, 0xfe, 0x48, 0x00, 0xab, 0xfe, 0x03, 0x40, 0x08, 0x54, 0x5b,
5447         0x37, 0x01, 0xb3, 0xb8, 0xfe, 0x1f, 0x40, 0x13, 0x62, 0x01, 0xef, 0xfe,
5448         0x08, 0x50, 0xfe, 0x8a, 0x50, 0xfe, 0x44, 0x51, 0xfe, 0xc6, 0x51, 0x88,
5449         0xfe, 0x08, 0x90, 0xfe, 0x8a, 0x90, 0x0c, 0x5e, 0x14, 0x5f, 0xfe, 0x0c,
5450         0x90, 0xfe, 0x8e, 0x90, 0xfe, 0x40, 0x50, 0xfe, 0xc2, 0x50, 0x0c, 0x3d,
5451         0x14, 0x3e, 0xfe, 0x4a, 0x10, 0x08, 0x05, 0x5a, 0xfe, 0x2a, 0x12, 0xfe,
5452         0x2c, 0x90, 0xfe, 0xae, 0x90, 0x0c, 0x60, 0x14, 0x61, 0x08, 0x05, 0x5b,
5453         0x8b, 0x01, 0xb3, 0xfe, 0x1f, 0x80, 0x13, 0x62, 0xfe, 0x44, 0x90, 0xfe,
5454         0xc6, 0x90, 0x0c, 0x3f, 0x14, 0x40, 0xfe, 0x08, 0x90, 0xfe, 0x8a, 0x90,
5455         0x0c, 0x5e, 0x14, 0x5f, 0xfe, 0x40, 0x90, 0xfe, 0xc2, 0x90, 0x0c, 0x3d,
5456         0x14, 0x3e, 0x0c, 0x2e, 0x14, 0x3c, 0x21, 0x0c, 0x49, 0x0c, 0x63, 0x08,
5457         0x54, 0x1f, 0x37, 0x2c, 0x0f, 0xfe, 0x4e, 0x11, 0x27, 0xdd, 0xfe, 0x9e,
5458         0xf0, 0xfe, 0x76, 0x08, 0xbc, 0x17, 0x34, 0x2c, 0x77, 0xe6, 0xc5, 0xfe,
5459         0x9a, 0x08, 0xc6, 0xfe, 0xb8, 0x08, 0x94, 0xfe, 0x8e, 0x08, 0xfe, 0x06,
5460         0xf0, 0xfe, 0x94, 0x08, 0x95, 0x86, 0x02, 0x24, 0x01, 0x4b, 0xfe, 0xc9,
5461         0x10, 0x16, 0x1f, 0xfe, 0xc9, 0x10, 0x68, 0x05, 0x06, 0xfe, 0x10, 0x12,
5462         0x68, 0x05, 0x0a, 0x4e, 0x08, 0x05, 0x0a, 0xfe, 0x90, 0x12, 0xfe, 0x2e,
5463         0x1c, 0x02, 0xfe, 0x18, 0x0b, 0x68, 0x05, 0x06, 0x4e, 0x68, 0x05, 0x0a,
5464         0xfe, 0x7a, 0x12, 0xfe, 0x2c, 0x1c, 0xfe, 0xaa, 0xf0, 0xfe, 0xd2, 0x09,
5465         0xfe, 0xac, 0xf0, 0xfe, 0x00, 0x09, 0x02, 0xfe, 0xde, 0x09, 0xfe, 0xb7,
5466         0xf0, 0xfe, 0xfc, 0x08, 0xfe, 0x02, 0xf6, 0x1a, 0x50, 0xfe, 0x70, 0x18,
5467         0xfe, 0xf1, 0x18, 0xfe, 0x40, 0x55, 0xfe, 0xe1, 0x55, 0xfe, 0x10, 0x58,
5468         0xfe, 0x91, 0x58, 0xfe, 0x14, 0x59, 0xfe, 0x95, 0x59, 0x1c, 0x85, 0xfe,
5469         0x8c, 0xf0, 0xfe, 0xfc, 0x08, 0xfe, 0xac, 0xf0, 0xfe, 0xf0, 0x08, 0xb5,
5470         0xfe, 0xcb, 0x10, 0xfe, 0xad, 0xf0, 0xfe, 0x0c, 0x09, 0x02, 0xfe, 0x18,
5471         0x0b, 0xb6, 0xfe, 0xbf, 0x10, 0xfe, 0x2b, 0xf0, 0x85, 0xf4, 0x1e, 0xfe,
5472         0x00, 0xfe, 0xfe, 0x1c, 0x12, 0xc2, 0xfe, 0xd2, 0xf0, 0x85, 0xfe, 0x76,
5473         0x18, 0x1e, 0x19, 0x17, 0x85, 0x03, 0xd2, 0x1e, 0x06, 0x17, 0x85, 0xc5,
5474         0x4a, 0xc6, 0x4a, 0xb5, 0xb6, 0xfe, 0x89, 0x10, 0x74, 0x67, 0x2d, 0x15,
5475         0x9d, 0x01, 0x36, 0x10, 0xfe, 0x35, 0x00, 0xfe, 0x01, 0xf0, 0x65, 0x10,
5476         0x80, 0x02, 0x65, 0xfe, 0x98, 0x80, 0xfe, 0x19, 0xe4, 0x0a, 0xfe, 0x1a,
5477         0x12, 0x51, 0xfe, 0x19, 0x82, 0xfe, 0x6c, 0x18, 0xfe, 0x44, 0x54, 0xbe,
5478         0xfe, 0x19, 0x81, 0xfe, 0x74, 0x18, 0x8f, 0x90, 0x17, 0xfe, 0xce, 0x08,
5479         0x02, 0x4a, 0x08, 0x05, 0x5a, 0xec, 0x03, 0x2e, 0x29, 0x3c, 0x0c, 0x3f,
5480         0x14, 0x40, 0x9b, 0x2e, 0x9c, 0x3c, 0xfe, 0x6c, 0x18, 0xfe, 0xed, 0x18,
5481         0xfe, 0x44, 0x54, 0xfe, 0xe5, 0x54, 0x3a, 0x3f, 0x3b, 0x40, 0x03, 0x49,
5482         0x29, 0x63, 0x8f, 0xfe, 0xe3, 0x54, 0xfe, 0x74, 0x18, 0xfe, 0xf5, 0x18,
5483         0x8f, 0xfe, 0xe3, 0x54, 0x90, 0xc0, 0x56, 0xfe, 0xce, 0x08, 0x02, 0x4a,
5484         0xfe, 0x37, 0xf0, 0xfe, 0xda, 0x09, 0xfe, 0x8b, 0xf0, 0xfe, 0x60, 0x09,
5485         0x02, 0x4a, 0x08, 0x05, 0x0a, 0x23, 0xfe, 0xfa, 0x0a, 0x3a, 0x49, 0x3b,
5486         0x63, 0x56, 0xfe, 0x3e, 0x0a, 0x0f, 0xfe, 0xc0, 0x07, 0x41, 0x98, 0x00,
5487         0xad, 0xfe, 0x01, 0x59, 0xfe, 0x52, 0xf0, 0xfe, 0x0c, 0x0a, 0x8f, 0x7a,
5488         0xfe, 0x24, 0x0a, 0x3a, 0x49, 0x8f, 0xfe, 0xe3, 0x54, 0x57, 0x49, 0x7d,
5489         0x63, 0xfe, 0x14, 0x58, 0xfe, 0x95, 0x58, 0x02, 0x4a, 0x3a, 0x49, 0x3b,
5490         0x63, 0xfe, 0x14, 0x59, 0xfe, 0x95, 0x59, 0xbe, 0x57, 0x49, 0x57, 0x63,
5491         0x02, 0x4a, 0x08, 0x05, 0x5a, 0xfe, 0x82, 0x12, 0x08, 0x05, 0x1f, 0xfe,
5492         0x66, 0x13, 0x22, 0x62, 0xb7, 0xfe, 0x03, 0xa1, 0xfe, 0x83, 0x80, 0xfe,
5493         0xc8, 0x44, 0xfe, 0x2e, 0x13, 0xfe, 0x04, 0x91, 0xfe, 0x86, 0x91, 0x6a,
5494         0x2a, 0xfe, 0x40, 0x59, 0xfe, 0xc1, 0x59, 0x56, 0xe0, 0x03, 0x60, 0x29,
5495         0x61, 0x0c, 0x7f, 0x14, 0x80, 0x57, 0x60, 0x7d, 0x61, 0x01, 0xb3, 0xb8,
5496         0x6a, 0x2a, 0x13, 0x62, 0x9b, 0x2e, 0x9c, 0x3c, 0x3a, 0x3f, 0x3b, 0x40,
5497         0x90, 0xc0, 0xfe, 0x04, 0xfa, 0x2e, 0xfe, 0x05, 0xfa, 0x3c, 0x01, 0xef,
5498         0xfe, 0x36, 0x10, 0x21, 0x0c, 0x7f, 0x0c, 0x80, 0x3a, 0x3f, 0x3b, 0x40,
5499         0xe4, 0x08, 0x05, 0x1f, 0x17, 0xe0, 0x3a, 0x3d, 0x3b, 0x3e, 0x08, 0x05,
5500         0xfe, 0xf7, 0x00, 0x37, 0x03, 0x5e, 0x29, 0x5f, 0xfe, 0x10, 0x58, 0xfe,
5501         0x91, 0x58, 0x57, 0x49, 0x7d, 0x63, 0x02, 0xfe, 0xf4, 0x09, 0x08, 0x05,
5502         0x1f, 0x17, 0xe0, 0x08, 0x05, 0xfe, 0xf7, 0x00, 0x37, 0xbe, 0xfe, 0x19,
5503         0x81, 0x50, 0xfe, 0x10, 0x90, 0xfe, 0x92, 0x90, 0xfe, 0xd3, 0x10, 0x32,
5504         0x07, 0xa6, 0x17, 0xfe, 0x08, 0x09, 0x12, 0xa6, 0x08, 0x05, 0x0a, 0xfe,
5505         0x14, 0x13, 0x03, 0x3d, 0x29, 0x3e, 0x56, 0xfe, 0x08, 0x09, 0xfe, 0x0c,
5506         0x58, 0xfe, 0x8d, 0x58, 0x02, 0x4a, 0x21, 0x41, 0xfe, 0x19, 0x80, 0xe7,
5507         0x08, 0x05, 0x0a, 0xfe, 0x1a, 0x12, 0xfe, 0x6c, 0x19, 0xfe, 0x19, 0x41,
5508         0xf4, 0xc2, 0xfe, 0xd1, 0xf0, 0xe2, 0x15, 0x7e, 0x01, 0x36, 0x10, 0xfe,
5509         0x44, 0x00, 0xfe, 0x8e, 0x10, 0xfe, 0x6c, 0x19, 0x57, 0x3d, 0xfe, 0xed,
5510         0x19, 0x7d, 0x3e, 0xfe, 0x0c, 0x51, 0xfe, 0x8e, 0x51, 0xf4, 0x1e, 0xfe,
5511         0x00, 0xff, 0x35, 0xfe, 0x74, 0x10, 0xc2, 0xfe, 0xd2, 0xf0, 0xfe, 0xa6,
5512         0x0b, 0xfe, 0x76, 0x18, 0x1e, 0x19, 0x8a, 0x03, 0xd2, 0x1e, 0x06, 0xfe,
5513         0x08, 0x13, 0x10, 0xfe, 0x16, 0x00, 0x02, 0x65, 0xfe, 0xd1, 0xf0, 0xfe,
5514         0xb8, 0x0b, 0x15, 0x7e, 0x01, 0x36, 0x10, 0xfe, 0x17, 0x00, 0xfe, 0x42,
5515         0x10, 0xfe, 0xce, 0xf0, 0xfe, 0xbe, 0x0b, 0xfe, 0x3c, 0x10, 0xfe, 0xcd,
5516         0xf0, 0xfe, 0xca, 0x0b, 0x10, 0xfe, 0x22, 0x00, 0x02, 0x65, 0xfe, 0xcb,
5517         0xf0, 0xfe, 0xd6, 0x0b, 0x10, 0xfe, 0x24, 0x00, 0x02, 0x65, 0xfe, 0xd0,
5518         0xf0, 0xfe, 0xe0, 0x0b, 0x10, 0x9e, 0xe5, 0xfe, 0xcf, 0xf0, 0xfe, 0xea,
5519         0x0b, 0x10, 0x58, 0xfe, 0x10, 0x10, 0xfe, 0xcc, 0xf0, 0xe2, 0x68, 0x05,
5520         0x1f, 0x4d, 0x10, 0xfe, 0x12, 0x00, 0x2c, 0x0f, 0xfe, 0x4e, 0x11, 0x27,
5521         0xfe, 0x00, 0x0c, 0xfe, 0x9e, 0xf0, 0xfe, 0x14, 0x0c, 0xbc, 0x17, 0x34,
5522         0x2c, 0x77, 0xe6, 0xc5, 0x24, 0xc6, 0x24, 0x2c, 0xfa, 0x27, 0xfe, 0x20,
5523         0x0c, 0x1c, 0x34, 0x94, 0xfe, 0x3c, 0x0c, 0x95, 0x86, 0xc5, 0xdc, 0xc6,
5524         0xdc, 0x02, 0x24, 0x01, 0x4b, 0xfe, 0xdb, 0x10, 0x12, 0xfe, 0xe8, 0x00,
5525         0xb5, 0xb6, 0x74, 0xc7, 0x81, 0xc8, 0x83, 0xfe, 0x89, 0xf0, 0x24, 0x33,
5526         0x31, 0xe1, 0xc7, 0x81, 0xc8, 0x83, 0x27, 0xfe, 0x66, 0x0c, 0x1d, 0x24,
5527         0x33, 0x31, 0xdf, 0xbc, 0x4e, 0x10, 0xfe, 0x42, 0x00, 0x02, 0x65, 0x7c,
5528         0x06, 0xfe, 0x81, 0x49, 0x17, 0xfe, 0x2c, 0x0d, 0x08, 0x05, 0x0a, 0xfe,
5529         0x44, 0x13, 0x10, 0x00, 0x55, 0x0a, 0xfe, 0x54, 0x12, 0x55, 0xfe, 0x28,
5530         0x00, 0x23, 0xfe, 0x9a, 0x0d, 0x09, 0x46, 0x01, 0x0e, 0x07, 0x00, 0x66,
5531         0x44, 0xfe, 0x28, 0x00, 0xfe, 0xe2, 0x10, 0x01, 0xf5, 0x01, 0xf6, 0x09,
5532         0xa4, 0x01, 0xfe, 0x26, 0x0f, 0x64, 0x12, 0x2f, 0x01, 0x73, 0x02, 0x2b,
5533         0x10, 0xfe, 0x44, 0x00, 0x55, 0x0a, 0xe9, 0x44, 0x0a, 0xfe, 0xb4, 0x10,
5534         0x01, 0xb0, 0x44, 0x0a, 0xfe, 0xaa, 0x10, 0x01, 0xb0, 0xfe, 0x19, 0x82,
5535         0xfe, 0x34, 0x46, 0xac, 0x44, 0x0a, 0x10, 0xfe, 0x43, 0x00, 0xfe, 0x96,
5536         0x10, 0x08, 0x54, 0x0a, 0x37, 0x01, 0xf5, 0x01, 0xf6, 0x64, 0x12, 0x2f,
5537         0x01, 0x73, 0x99, 0x0a, 0x64, 0x42, 0x92, 0x02, 0xfe, 0x2e, 0x03, 0x08,
5538         0x05, 0x0a, 0x8a, 0x44, 0x0a, 0x10, 0x00, 0xfe, 0x5c, 0x10, 0x68, 0x05,
5539         0x1a, 0xfe, 0x58, 0x12, 0x08, 0x05, 0x1a, 0xfe, 0x50, 0x13, 0xfe, 0x1c,
5540         0x1c, 0xfe, 0x9d, 0xf0, 0xfe, 0x50, 0x0d, 0xfe, 0x1c, 0x1c, 0xfe, 0x9d,
5541         0xf0, 0xfe, 0x56, 0x0d, 0x08, 0x54, 0x1a, 0x37, 0xfe, 0xa9, 0x10, 0x10,
5542         0xfe, 0x15, 0x00, 0xfe, 0x04, 0xe6, 0x0a, 0x50, 0xfe, 0x2e, 0x10, 0x10,
5543         0xfe, 0x13, 0x00, 0xfe, 0x10, 0x10, 0x10, 0x6f, 0xab, 0x10, 0xfe, 0x41,
5544         0x00, 0xaa, 0x10, 0xfe, 0x24, 0x00, 0x8c, 0xb5, 0xb6, 0x74, 0x03, 0x70,
5545         0x28, 0x23, 0xd8, 0x50, 0xfe, 0x04, 0xe6, 0x1a, 0xfe, 0x9d, 0x41, 0xfe,
5546         0x1c, 0x42, 0x64, 0x01, 0xe3, 0x02, 0x2b, 0xf8, 0x15, 0x0a, 0x39, 0xa0,
5547         0xb4, 0x15, 0xfe, 0x31, 0x00, 0x39, 0xa2, 0x01, 0xfe, 0x48, 0x10, 0x02,
5548         0xd7, 0x42, 0xfe, 0x06, 0xec, 0xd0, 0xfc, 0x44, 0x1b, 0xfe, 0xce, 0x45,
5549         0x35, 0x42, 0xfe, 0x06, 0xea, 0xd0, 0xfe, 0x47, 0x4b, 0x91, 0xfe, 0x75,
5550         0x57, 0x03, 0x5d, 0xfe, 0x98, 0x56, 0xfe, 0x38, 0x12, 0x09, 0x48, 0x01,
5551         0x0e, 0xfe, 0x44, 0x48, 0x4f, 0x08, 0x05, 0x1b, 0xfe, 0x1a, 0x13, 0x09,
5552         0x46, 0x01, 0x0e, 0x41, 0xfe, 0x41, 0x58, 0x09, 0xa4, 0x01, 0x0e, 0xfe,
5553         0x49, 0x54, 0x96, 0xfe, 0x1e, 0x0e, 0x02, 0xfe, 0x2e, 0x03, 0x09, 0x5d,
5554         0xfe, 0xee, 0x14, 0xfc, 0x44, 0x1b, 0xfe, 0xce, 0x45, 0x35, 0x42, 0xfe,
5555         0xce, 0x47, 0xfe, 0xad, 0x13, 0x02, 0x2b, 0x22, 0x20, 0x07, 0x11, 0xfe,
5556         0x9e, 0x12, 0x21, 0x13, 0x59, 0x13, 0x9f, 0x13, 0xd5, 0x22, 0x2f, 0x41,
5557         0x39, 0x2f, 0xbc, 0xad, 0xfe, 0xbc, 0xf0, 0xfe, 0xe0, 0x0e, 0x0f, 0x06,
5558         0x13, 0x59, 0x01, 0xfe, 0xda, 0x16, 0x03, 0xfe, 0x38, 0x01, 0x29, 0xfe,
5559         0x3a, 0x01, 0x56, 0xfe, 0xe4, 0x0e, 0xfe, 0x02, 0xec, 0xd5, 0x69, 0x00,
5560         0x66, 0xfe, 0x04, 0xec, 0x20, 0x4f, 0xfe, 0x05, 0xf6, 0xfe, 0x34, 0x01,
5561         0x01, 0xfe, 0x4a, 0x17, 0xfe, 0x08, 0x90, 0xfe, 0x48, 0xf4, 0x0d, 0xfe,
5562         0x18, 0x13, 0xba, 0xfe, 0x02, 0xea, 0xd5, 0x69, 0x7e, 0xfe, 0xc5, 0x13,
5563         0x15, 0x1a, 0x39, 0xa0, 0xb4, 0xfe, 0x2e, 0x10, 0x03, 0xfe, 0x38, 0x01,
5564         0x1e, 0xfe, 0xf0, 0xff, 0x0c, 0xfe, 0x60, 0x01, 0x03, 0xfe, 0x3a, 0x01,
5565         0x0c, 0xfe, 0x62, 0x01, 0x43, 0x13, 0x20, 0x25, 0x06, 0x13, 0x2f, 0x12,
5566         0x2f, 0x92, 0x0f, 0x06, 0x04, 0x21, 0x04, 0x22, 0x59, 0xfe, 0xf7, 0x12,
5567         0x22, 0x9f, 0xb7, 0x13, 0x9f, 0x07, 0x7e, 0xfe, 0x71, 0x13, 0xfe, 0x24,
5568         0x1c, 0x15, 0x19, 0x39, 0xa0, 0xb4, 0xfe, 0xd9, 0x10, 0xc3, 0xfe, 0x03,
5569         0xdc, 0xfe, 0x73, 0x57, 0xfe, 0x80, 0x5d, 0x04, 0xc3, 0xfe, 0x03, 0xdc,
5570         0xfe, 0x5b, 0x57, 0xfe, 0x80, 0x5d, 0x04, 0xfe, 0x03, 0x57, 0xc3, 0x21,
5571         0xfe, 0x00, 0xcc, 0x04, 0xfe, 0x03, 0x57, 0xc3, 0x78, 0x04, 0x08, 0x05,
5572         0x58, 0xfe, 0x22, 0x13, 0xfe, 0x1c, 0x80, 0x07, 0x06, 0xfe, 0x1a, 0x13,
5573         0xfe, 0x1e, 0x80, 0xed, 0xfe, 0x1d, 0x80, 0xae, 0xfe, 0x0c, 0x90, 0xfe,
5574         0x0e, 0x13, 0xfe, 0x0e, 0x90, 0xac, 0xfe, 0x3c, 0x90, 0xfe, 0x30, 0xf4,
5575         0x0a, 0xfe, 0x3c, 0x50, 0xaa, 0x01, 0xfe, 0x7a, 0x17, 0x32, 0x07, 0x2f,
5576         0xad, 0x01, 0xfe, 0xb4, 0x16, 0x08, 0x05, 0x1b, 0x4e, 0x01, 0xf5, 0x01,
5577         0xf6, 0x12, 0xfe, 0xe9, 0x00, 0x08, 0x05, 0x58, 0xfe, 0x2c, 0x13, 0x01,
5578         0xfe, 0x0c, 0x17, 0xfe, 0x1e, 0x1c, 0xfe, 0x14, 0x90, 0xfe, 0x96, 0x90,
5579         0x0c, 0xfe, 0x64, 0x01, 0x14, 0xfe, 0x66, 0x01, 0x08, 0x05, 0x5b, 0xfe,
5580         0x12, 0x12, 0xfe, 0x03, 0x80, 0x8d, 0xfe, 0x01, 0xec, 0x20, 0xfe, 0x80,
5581         0x40, 0x13, 0x20, 0x6a, 0x2a, 0x12, 0xcf, 0x64, 0x22, 0x20, 0xfb, 0x79,
5582         0x20, 0x04, 0xfe, 0x08, 0x1c, 0x03, 0xfe, 0xac, 0x00, 0xfe, 0x06, 0x58,
5583         0x03, 0xfe, 0xae, 0x00, 0xfe, 0x07, 0x58, 0x03, 0xfe, 0xb0, 0x00, 0xfe,
5584         0x08, 0x58, 0x03, 0xfe, 0xb2, 0x00, 0xfe, 0x09, 0x58, 0xfe, 0x0a, 0x1c,
5585         0x25, 0x6e, 0x13, 0xd0, 0x21, 0x0c, 0x5c, 0x0c, 0x45, 0x0f, 0x46, 0x52,
5586         0x50, 0x18, 0x1b, 0xfe, 0x90, 0x4d, 0xfe, 0x91, 0x54, 0x23, 0xfe, 0xfc,
5587         0x0f, 0x44, 0x11, 0x0f, 0x48, 0x52, 0x18, 0x58, 0xfe, 0x90, 0x4d, 0xfe,
5588         0x91, 0x54, 0x23, 0xe4, 0x25, 0x11, 0x13, 0x20, 0x7c, 0x6f, 0x4f, 0x22,
5589         0x20, 0xfb, 0x79, 0x20, 0x12, 0xcf, 0xfe, 0x14, 0x56, 0xfe, 0xd6, 0xf0,
5590         0xfe, 0x26, 0x10, 0xf8, 0x74, 0xfe, 0x14, 0x1c, 0xfe, 0x10, 0x1c, 0xfe,
5591         0x18, 0x1c, 0x04, 0x42, 0xfe, 0x0c, 0x14, 0xfc, 0xfe, 0x07, 0xe6, 0x1b,
5592         0xfe, 0xce, 0x47, 0xfe, 0xf5, 0x13, 0x04, 0x01, 0xb0, 0x7c, 0x6f, 0x4f,
5593         0xfe, 0x06, 0x80, 0xfe, 0x48, 0x47, 0xfe, 0x42, 0x13, 0x32, 0x07, 0x2f,
5594         0xfe, 0x34, 0x13, 0x09, 0x48, 0x01, 0x0e, 0xbb, 0xfe, 0x36, 0x12, 0xfe,
5595         0x41, 0x48, 0xfe, 0x45, 0x48, 0x01, 0xf0, 0xfe, 0x00, 0xcc, 0xbb, 0xfe,
5596         0xf3, 0x13, 0x43, 0x78, 0x07, 0x11, 0xac, 0x09, 0x84, 0x01, 0x0e, 0xfe,
5597         0x80, 0x5c, 0x01, 0x73, 0xfe, 0x0e, 0x10, 0x07, 0x82, 0x4e, 0xfe, 0x14,
5598         0x56, 0xfe, 0xd6, 0xf0, 0xfe, 0x60, 0x10, 0x04, 0xfe, 0x44, 0x58, 0x8d,
5599         0xfe, 0x01, 0xec, 0xa2, 0xfe, 0x9e, 0x40, 0xfe, 0x9d, 0xe7, 0x00, 0xfe,
5600         0x9c, 0xe7, 0x1a, 0x79, 0x2a, 0x01, 0xe3, 0xfe, 0xdd, 0x10, 0x2c, 0xc7,
5601         0x81, 0xc8, 0x83, 0x33, 0x31, 0xde, 0x07, 0x1a, 0xfe, 0x48, 0x12, 0x07,
5602         0x0a, 0xfe, 0x56, 0x12, 0x07, 0x19, 0xfe, 0x30, 0x12, 0x07, 0xc9, 0x17,
5603         0xfe, 0x32, 0x12, 0x07, 0xfe, 0x23, 0x00, 0x17, 0xeb, 0x07, 0x06, 0x17,
5604         0xfe, 0x9c, 0x12, 0x07, 0x1f, 0xfe, 0x12, 0x12, 0x07, 0x00, 0x17, 0x24,
5605         0x15, 0xc9, 0x01, 0x36, 0xa9, 0x2d, 0x01, 0x0b, 0x94, 0x4b, 0x04, 0x2d,
5606         0xdd, 0x09, 0xd1, 0x01, 0xfe, 0x26, 0x0f, 0x12, 0x82, 0x02, 0x2b, 0x2d,
5607         0x32, 0x07, 0xa6, 0xfe, 0xd9, 0x13, 0x3a, 0x3d, 0x3b, 0x3e, 0x56, 0xfe,
5608         0xf0, 0x11, 0x08, 0x05, 0x5a, 0xfe, 0x72, 0x12, 0x9b, 0x2e, 0x9c, 0x3c,
5609         0x90, 0xc0, 0x96, 0xfe, 0xba, 0x11, 0x22, 0x62, 0xfe, 0x26, 0x13, 0x03,
5610         0x7f, 0x29, 0x80, 0x56, 0xfe, 0x76, 0x0d, 0x0c, 0x60, 0x14, 0x61, 0x21,
5611         0x0c, 0x7f, 0x0c, 0x80, 0x01, 0xb3, 0x25, 0x6e, 0x77, 0x13, 0x62, 0x01,
5612         0xef, 0x9b, 0x2e, 0x9c, 0x3c, 0xfe, 0x04, 0x55, 0xfe, 0xa5, 0x55, 0xfe,
5613         0x04, 0xfa, 0x2e, 0xfe, 0x05, 0xfa, 0x3c, 0xfe, 0x91, 0x10, 0x03, 0x3f,
5614         0x29, 0x40, 0xfe, 0x40, 0x56, 0xfe, 0xe1, 0x56, 0x0c, 0x3f, 0x14, 0x40,
5615         0x88, 0x9b, 0x2e, 0x9c, 0x3c, 0x90, 0xc0, 0x03, 0x5e, 0x29, 0x5f, 0xfe,
5616         0x00, 0x56, 0xfe, 0xa1, 0x56, 0x0c, 0x5e, 0x14, 0x5f, 0x08, 0x05, 0x5a,
5617         0xfe, 0x1e, 0x12, 0x22, 0x62, 0xfe, 0x1f, 0x40, 0x03, 0x60, 0x29, 0x61,
5618         0xfe, 0x2c, 0x50, 0xfe, 0xae, 0x50, 0x03, 0x3f, 0x29, 0x40, 0xfe, 0x44,
5619         0x50, 0xfe, 0xc6, 0x50, 0x03, 0x5e, 0x29, 0x5f, 0xfe, 0x08, 0x50, 0xfe,
5620         0x8a, 0x50, 0x03, 0x3d, 0x29, 0x3e, 0xfe, 0x40, 0x50, 0xfe, 0xc2, 0x50,
5621         0x02, 0x89, 0x25, 0x06, 0x13, 0xd4, 0x02, 0x72, 0x2d, 0x01, 0x0b, 0x1d,
5622         0x4c, 0x33, 0x31, 0xde, 0x07, 0x06, 0x23, 0x4c, 0x32, 0x07, 0xa6, 0x23,
5623         0x72, 0x01, 0xaf, 0x1e, 0x43, 0x17, 0x4c, 0x08, 0x05, 0x0a, 0xee, 0x3a,
5624         0x3d, 0x3b, 0x3e, 0xfe, 0x0a, 0x55, 0x35, 0xfe, 0x8b, 0x55, 0x57, 0x3d,
5625         0x7d, 0x3e, 0xfe, 0x0c, 0x51, 0xfe, 0x8e, 0x51, 0x02, 0x72, 0xfe, 0x19,
5626         0x81, 0xba, 0xfe, 0x19, 0x41, 0x02, 0x72, 0x2d, 0x01, 0x0b, 0x1c, 0x34,
5627         0x1d, 0xe8, 0x33, 0x31, 0xe1, 0x55, 0x19, 0xfe, 0xa6, 0x12, 0x55, 0x0a,
5628         0x4d, 0x02, 0x4c, 0x01, 0x0b, 0x1c, 0x34, 0x1d, 0xe8, 0x33, 0x31, 0xdf,
5629         0x07, 0x19, 0x23, 0x4c, 0x01, 0x0b, 0x1d, 0xe8, 0x33, 0x31, 0xfe, 0xe8,
5630         0x09, 0xfe, 0xc2, 0x49, 0x51, 0x03, 0xfe, 0x9c, 0x00, 0x28, 0x8a, 0x53,
5631         0x05, 0x1f, 0x35, 0xa9, 0xfe, 0xbb, 0x45, 0x55, 0x00, 0x4e, 0x44, 0x06,
5632         0x7c, 0x43, 0xfe, 0xda, 0x14, 0x01, 0xaf, 0x8c, 0xfe, 0x4b, 0x45, 0xee,
5633         0x32, 0x07, 0xa5, 0xed, 0x03, 0xcd, 0x28, 0x8a, 0x03, 0x45, 0x28, 0x35,
5634         0x67, 0x02, 0x72, 0xfe, 0xc0, 0x5d, 0xfe, 0xf8, 0x14, 0xfe, 0x03, 0x17,
5635         0x03, 0x5c, 0xc1, 0x0c, 0x5c, 0x67, 0x2d, 0x01, 0x0b, 0x26, 0x89, 0x01,
5636         0xfe, 0x9e, 0x15, 0x02, 0x89, 0x01, 0x0b, 0x1c, 0x34, 0x1d, 0x4c, 0x33,
5637         0x31, 0xdf, 0x07, 0x06, 0x23, 0x4c, 0x01, 0xf1, 0xfe, 0x42, 0x58, 0xf1,
5638         0xfe, 0xa4, 0x14, 0x8c, 0xfe, 0x4a, 0xf4, 0x0a, 0x17, 0x4c, 0xfe, 0x4a,
5639         0xf4, 0x06, 0xea, 0x32, 0x07, 0xa5, 0x8b, 0x02, 0x72, 0x03, 0x45, 0xc1,
5640         0x0c, 0x45, 0x67, 0x2d, 0x01, 0x0b, 0x26, 0x89, 0x01, 0xfe, 0xcc, 0x15,
5641         0x02, 0x89, 0x0f, 0x06, 0x27, 0xfe, 0xbe, 0x13, 0x26, 0xfe, 0xd4, 0x13,
5642         0x76, 0xfe, 0x89, 0x48, 0x01, 0x0b, 0x21, 0x76, 0x04, 0x7b, 0xfe, 0xd0,
5643         0x13, 0x1c, 0xfe, 0xd0, 0x13, 0x1d, 0xfe, 0xbe, 0x13, 0x67, 0x2d, 0x01,
5644         0x0b, 0xfe, 0xd5, 0x10, 0x0f, 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93,
5645         0x1e, 0xfe, 0xff, 0x7f, 0xfe, 0x30, 0x56, 0xfe, 0x00, 0x5c, 0x04, 0x0f,
5646         0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93, 0x1e, 0x43, 0xfe, 0x30, 0x56,
5647         0xfe, 0x00, 0x5c, 0x04, 0x0f, 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93,
5648         0x04, 0x0f, 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93, 0xfe, 0x0b, 0x58,
5649         0x04, 0x09, 0x5c, 0x01, 0x87, 0x09, 0x45, 0x01, 0x87, 0x04, 0xfe, 0x03,
5650         0xa1, 0x1e, 0x11, 0xff, 0x03, 0x00, 0x54, 0xfe, 0x00, 0xf4, 0x1f, 0x52,
5651         0xfe, 0x00, 0x7d, 0xfe, 0x01, 0x7d, 0xfe, 0x02, 0x7d, 0xfe, 0x03, 0x7c,
5652         0x6a, 0x2a, 0x0c, 0x5e, 0x14, 0x5f, 0x57, 0x3f, 0x7d, 0x40, 0x04, 0xdd,
5653         0xfe, 0x82, 0x4a, 0xfe, 0xe1, 0x1a, 0xfe, 0x83, 0x5a, 0x8d, 0x04, 0x01,
5654         0xfe, 0x0c, 0x19, 0xfe, 0x42, 0x48, 0x50, 0x51, 0x91, 0x01, 0x0b, 0x1d,
5655         0xfe, 0x96, 0x15, 0x33, 0x31, 0xe1, 0x01, 0x0b, 0x1d, 0xfe, 0x96, 0x15,
5656         0x33, 0x31, 0xfe, 0xe8, 0x0a, 0xfe, 0xc1, 0x59, 0x03, 0xcd, 0x28, 0xfe,
5657         0xcc, 0x12, 0x53, 0x05, 0x1a, 0xfe, 0xc4, 0x13, 0x21, 0x69, 0x1a, 0xee,
5658         0x55, 0xca, 0x6b, 0xfe, 0xdc, 0x14, 0x4d, 0x0f, 0x06, 0x18, 0xca, 0x7c,
5659         0x30, 0xfe, 0x78, 0x10, 0xff, 0x02, 0x83, 0x55, 0xab, 0xff, 0x02, 0x83,
5660         0x55, 0x69, 0x19, 0xae, 0x98, 0xfe, 0x30, 0x00, 0x96, 0xf2, 0x18, 0x6d,
5661         0x0f, 0x06, 0xfe, 0x56, 0x10, 0x69, 0x0a, 0xed, 0x98, 0xfe, 0x64, 0x00,
5662         0x96, 0xf2, 0x09, 0xfe, 0x64, 0x00, 0x18, 0x9e, 0x0f, 0x06, 0xfe, 0x28,
5663         0x10, 0x69, 0x06, 0xfe, 0x60, 0x13, 0x98, 0xfe, 0xc8, 0x00, 0x96, 0xf2,
5664         0x09, 0xfe, 0xc8, 0x00, 0x18, 0x59, 0x0f, 0x06, 0x88, 0x98, 0xfe, 0x90,
5665         0x01, 0x7a, 0xfe, 0x42, 0x15, 0x91, 0xe4, 0xfe, 0x43, 0xf4, 0x9f, 0xfe,
5666         0x56, 0xf0, 0xfe, 0x54, 0x15, 0xfe, 0x04, 0xf4, 0x71, 0xfe, 0x43, 0xf4,
5667         0x9e, 0xfe, 0xf3, 0x10, 0xfe, 0x40, 0x5c, 0x01, 0xfe, 0x16, 0x14, 0x1e,
5668         0x43, 0xec, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4, 0x6e, 0x7a, 0xfe, 0x90,
5669         0x15, 0xc4, 0x6e, 0xfe, 0x1c, 0x10, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4,
5670         0xcc, 0x7a, 0xfe, 0x90, 0x15, 0xc4, 0xcc, 0x88, 0x51, 0x21, 0xfe, 0x4d,
5671         0xf4, 0x00, 0xe9, 0x91, 0x0f, 0x06, 0xfe, 0xb4, 0x56, 0xfe, 0xc3, 0x58,
5672         0x04, 0x51, 0x0f, 0x0a, 0x04, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xf3, 0x16,
5673         0x0a, 0x01, 0x0b, 0x26, 0xf3, 0x16, 0x19, 0x01, 0x0b, 0x26, 0xf3, 0x76,
5674         0xfe, 0x89, 0x49, 0x01, 0x0b, 0x04, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xb1,
5675         0x16, 0x19, 0x01, 0x0b, 0x26, 0xb1, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xb1,
5676         0xfe, 0x89, 0x49, 0x01, 0x0b, 0x26, 0xb1, 0x76, 0xfe, 0x89, 0x4a, 0x01,
5677         0x0b, 0x04, 0x51, 0x04, 0x22, 0xd3, 0x07, 0x06, 0xfe, 0x48, 0x13, 0xb8,
5678         0x13, 0xd3, 0xfe, 0x49, 0xf4, 0x00, 0x4d, 0x76, 0xa9, 0x67, 0xfe, 0x01,
5679         0xec, 0xfe, 0x27, 0x01, 0xfe, 0x89, 0x48, 0xff, 0x02, 0x00, 0x10, 0x27,
5680         0xfe, 0x2e, 0x16, 0x32, 0x07, 0xfe, 0xe3, 0x00, 0xfe, 0x20, 0x13, 0x1d,
5681         0xfe, 0x52, 0x16, 0x21, 0x13, 0xd4, 0x01, 0x4b, 0x22, 0xd4, 0x07, 0x06,
5682         0x4e, 0x08, 0x54, 0x06, 0x37, 0x04, 0x09, 0x48, 0x01, 0x0e, 0xfb, 0x8e,
5683         0x07, 0x11, 0xae, 0x09, 0x84, 0x01, 0x0e, 0x8e, 0x09, 0x5d, 0x01, 0xa8,
5684         0x04, 0x09, 0x84, 0x01, 0x0e, 0x8e, 0xfe, 0x80, 0xe7, 0x11, 0x07, 0x11,
5685         0x8a, 0xfe, 0x45, 0x58, 0x01, 0xf0, 0x8e, 0x04, 0x09, 0x48, 0x01, 0x0e,
5686         0x8e, 0x09, 0x5d, 0x01, 0xa8, 0x04, 0x09, 0x48, 0x01, 0x0e, 0xfe, 0x80,
5687         0x80, 0xfe, 0x80, 0x4c, 0xfe, 0x49, 0xe4, 0x11, 0xae, 0x09, 0x84, 0x01,
5688         0x0e, 0xfe, 0x80, 0x4c, 0x09, 0x5d, 0x01, 0x87, 0x04, 0x18, 0x11, 0x75,
5689         0x6c, 0xfe, 0x60, 0x01, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x24,
5690         0x1c, 0xfe, 0x1d, 0xf7, 0x1b, 0x97, 0xfe, 0xee, 0x16, 0x01, 0xfe, 0xf4,
5691         0x17, 0xad, 0x9a, 0x1b, 0x6c, 0xfe, 0x2c, 0x01, 0xfe, 0x2f, 0x19, 0x04,
5692         0xb9, 0x23, 0xfe, 0xde, 0x16, 0xfe, 0xda, 0x10, 0x18, 0x11, 0x75, 0x03,
5693         0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x1f, 0xfe, 0x18, 0x58, 0x03, 0xfe,
5694         0x66, 0x01, 0xfe, 0x19, 0x58, 0x9a, 0x1f, 0xfe, 0x3c, 0x90, 0xfe, 0x30,
5695         0xf4, 0x06, 0xfe, 0x3c, 0x50, 0x6c, 0xfe, 0x38, 0x00, 0xfe, 0x0f, 0x79,
5696         0xfe, 0x1c, 0xf7, 0x1f, 0x97, 0xfe, 0x38, 0x17, 0xfe, 0xb6, 0x14, 0x35,
5697         0x04, 0xb9, 0x23, 0xfe, 0x10, 0x17, 0xfe, 0x9c, 0x10, 0x18, 0x11, 0x75,
5698         0xfe, 0x83, 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x1d, 0xf7,
5699         0x2e, 0x97, 0xfe, 0x5a, 0x17, 0xfe, 0x94, 0x14, 0xec, 0x9a, 0x2e, 0x6c,
5700         0x1a, 0xfe, 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00, 0x04, 0xb9, 0x23, 0xfe,
5701         0x4e, 0x17, 0xfe, 0x6c, 0x10, 0x18, 0x11, 0x75, 0xfe, 0x30, 0xbc, 0xfe,
5702         0xb2, 0xbc, 0x9a, 0xcb, 0x6c, 0x1a, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7,
5703         0xcb, 0x97, 0xfe, 0x92, 0x17, 0xfe, 0x5c, 0x14, 0x35, 0x04, 0xb9, 0x23,
5704         0xfe, 0x7e, 0x17, 0xfe, 0x42, 0x10, 0xfe, 0x02, 0xf6, 0x11, 0x75, 0xfe,
5705         0x18, 0xfe, 0x60, 0xfe, 0x19, 0xfe, 0x61, 0xfe, 0x03, 0xa1, 0xfe, 0x1d,
5706         0xf7, 0x5b, 0x97, 0xfe, 0xb8, 0x17, 0xfe, 0x36, 0x14, 0xfe, 0x1c, 0x13,
5707         0x9a, 0x5b, 0x41, 0xfe, 0x83, 0x58, 0xfe, 0xaf, 0x19, 0xfe, 0x80, 0xe7,
5708         0x11, 0xfe, 0x81, 0xe7, 0x11, 0x12, 0xfe, 0xdd, 0x00, 0x6a, 0x2a, 0x04,
5709         0x6a, 0x2a, 0xfe, 0x12, 0x45, 0x23, 0xfe, 0xa8, 0x17, 0x15, 0x06, 0x39,
5710         0xa0, 0xb4, 0x02, 0x2b, 0xfe, 0x39, 0xf0, 0xfe, 0xfc, 0x17, 0x21, 0x04,
5711         0xfe, 0x7e, 0x18, 0x1e, 0x19, 0x66, 0x0f, 0x0d, 0x04, 0x75, 0x03, 0xd2,
5712         0x1e, 0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10, 0x7c, 0x6f, 0x4f, 0x32,
5713         0x07, 0x2f, 0xfe, 0x3c, 0x13, 0xf1, 0xfe, 0x42, 0x13, 0x42, 0x92, 0x09,
5714         0x48, 0x01, 0x0e, 0xbb, 0xeb, 0xfe, 0x41, 0x48, 0xfe, 0x45, 0x48, 0x01,
5715         0xf0, 0xfe, 0x00, 0xcc, 0xbb, 0xfe, 0xf3, 0x13, 0x43, 0x78, 0x07, 0x11,
5716         0xac, 0x09, 0x84, 0x01, 0x0e, 0xfe, 0x80, 0x4c, 0x01, 0x73, 0xfe, 0x16,
5717         0x10, 0x07, 0x82, 0x8b, 0xfe, 0x40, 0x14, 0xfe, 0x24, 0x12, 0xfe, 0x14,
5718         0x56, 0xfe, 0xd6, 0xf0, 0xfe, 0x1c, 0x18, 0x18, 0x0a, 0x04, 0xfe, 0x9c,
5719         0xe7, 0x0a, 0x10, 0xfe, 0x15, 0x00, 0x64, 0x79, 0x2a, 0x01, 0xe3, 0x18,
5720         0x06, 0x04, 0x42, 0x92, 0x08, 0x54, 0x1b, 0x37, 0x12, 0x2f, 0x01, 0x73,
5721         0x18, 0x06, 0x04, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x3a, 0xce, 0x3b,
5722         0xcf, 0xfe, 0x48, 0x55, 0x35, 0xfe, 0xc9, 0x55, 0x04, 0x22, 0xa3, 0x77,
5723         0x13, 0xa3, 0x04, 0x09, 0xa4, 0x01, 0x0e, 0xfe, 0x41, 0x48, 0x09, 0x46,
5724         0x01, 0x0e, 0xfe, 0x49, 0x44, 0x17, 0xfe, 0xe8, 0x18, 0x77, 0x78, 0x04,
5725         0x09, 0x48, 0x01, 0x0e, 0x07, 0x11, 0x4e, 0x09, 0x5d, 0x01, 0xa8, 0x09,
5726         0x46, 0x01, 0x0e, 0x77, 0x78, 0x04, 0xfe, 0x4e, 0xe4, 0x19, 0x6b, 0xfe,
5727         0x1c, 0x19, 0x03, 0xfe, 0x90, 0x00, 0xfe, 0x3a, 0x45, 0xfe, 0x2c, 0x10,
5728         0xfe, 0x4e, 0xe4, 0xc9, 0x6b, 0xfe, 0x2e, 0x19, 0x03, 0xfe, 0x92, 0x00,
5729         0xfe, 0x02, 0xe6, 0x1a, 0xe5, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x6b,
5730         0xfe, 0x40, 0x19, 0x03, 0xfe, 0x94, 0x00, 0xfe, 0x02, 0xe6, 0x1f, 0xfe,
5731         0x08, 0x10, 0x03, 0xfe, 0x96, 0x00, 0xfe, 0x02, 0xe6, 0x6d, 0xfe, 0x4e,
5732         0x45, 0xea, 0xba, 0xff, 0x04, 0x68, 0x54, 0xe7, 0x1e, 0x6e, 0xfe, 0x08,
5733         0x1c, 0xfe, 0x67, 0x19, 0xfe, 0x0a, 0x1c, 0xfe, 0x1a, 0xf4, 0xfe, 0x00,
5734         0x04, 0xea, 0xfe, 0x48, 0xf4, 0x19, 0x7a, 0xfe, 0x74, 0x19, 0x0f, 0x19,
5735         0x04, 0x07, 0x7e, 0xfe, 0x5a, 0xf0, 0xfe, 0x84, 0x19, 0x25, 0xfe, 0x09,
5736         0x00, 0xfe, 0x34, 0x10, 0x07, 0x1a, 0xfe, 0x5a, 0xf0, 0xfe, 0x92, 0x19,
5737         0x25, 0xca, 0xfe, 0x26, 0x10, 0x07, 0x19, 0x66, 0x25, 0x6d, 0xe5, 0x07,
5738         0x0a, 0x66, 0x25, 0x9e, 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x66, 0x25, 0x59,
5739         0xa9, 0xb8, 0x04, 0x15, 0xfe, 0x09, 0x00, 0x01, 0x36, 0xfe, 0x04, 0xfe,
5740         0x81, 0x03, 0x83, 0xfe, 0x40, 0x5c, 0x04, 0x1c, 0xf7, 0xfe, 0x14, 0xf0,
5741         0x0b, 0x27, 0xfe, 0xd6, 0x19, 0x1c, 0xf7, 0x7b, 0xf7, 0xfe, 0x82, 0xf0,
5742         0xfe, 0xda, 0x19, 0x04, 0xff, 0xcc, 0x00, 0x00,
5743 };
5744
5745 static unsigned short _adv_asc38C0800_size = sizeof(_adv_asc38C0800_buf);       /* 0x14E1 */
5746 static ADV_DCNT _adv_asc38C0800_chksum = 0x050D3FD8UL;  /* Expanded little-endian checksum. */
5747
5748 /* Microcode buffer is kept after initialization for error recovery. */
5749 static unsigned char _adv_asc38C1600_buf[] = {
5750         0x00, 0x00, 0x00, 0xf2, 0x00, 0x16, 0x00, 0xfc, 0x00, 0x10, 0x00, 0xf0,
5751         0x18, 0xe4, 0x01, 0x00, 0x04, 0x1e, 0x48, 0xe4, 0x03, 0xf6, 0xf7, 0x13,
5752         0x2e, 0x1e, 0x02, 0x00, 0x07, 0x17, 0xc0, 0x5f, 0x00, 0xfa, 0xff, 0xff,
5753         0x04, 0x00, 0x00, 0xf6, 0x09, 0xe7, 0x82, 0xe7, 0x85, 0xf0, 0x86, 0xf0,
5754         0x4e, 0x10, 0x9e, 0xe7, 0xff, 0x00, 0x55, 0xf0, 0x01, 0xf6, 0x03, 0x00,
5755         0x98, 0x57, 0x01, 0xe6, 0x00, 0xea, 0x00, 0xec, 0x01, 0xfa, 0x18, 0xf4,
5756         0x08, 0x00, 0xf0, 0x1d, 0x38, 0x54, 0x32, 0xf0, 0x10, 0x00, 0xc2, 0x0e,
5757         0x1e, 0xf0, 0xd5, 0xf0, 0xbc, 0x00, 0x4b, 0xe4, 0x00, 0xe6, 0xb1, 0xf0,
5758         0xb4, 0x00, 0x02, 0x13, 0x3e, 0x1c, 0xc8, 0x47, 0x3e, 0x00, 0xd8, 0x01,
5759         0x06, 0x13, 0x0c, 0x1c, 0x5e, 0x1e, 0x00, 0x57, 0xc8, 0x57, 0x01, 0xfc,
5760         0xbc, 0x0e, 0xa2, 0x12, 0xb9, 0x54, 0x00, 0x80, 0x62, 0x0a, 0x5a, 0x12,
5761         0xc8, 0x15, 0x3e, 0x1e, 0x18, 0x40, 0xbd, 0x56, 0x03, 0xe6, 0x01, 0xea,
5762         0x5c, 0xf0, 0x0f, 0x00, 0x20, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12,
5763         0x04, 0x13, 0xbb, 0x55, 0x3c, 0x56, 0x3e, 0x57, 0x03, 0x58, 0x4a, 0xe4,
5764         0x40, 0x00, 0xb6, 0x00, 0xbb, 0x00, 0xc0, 0x00, 0x00, 0x01, 0x01, 0x01,
5765         0x3e, 0x01, 0x58, 0x0a, 0x44, 0x10, 0x0a, 0x12, 0x4c, 0x1c, 0x4e, 0x1c,
5766         0x02, 0x4a, 0x30, 0xe4, 0x05, 0xe6, 0x0c, 0x00, 0x3c, 0x00, 0x80, 0x00,
5767         0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01, 0x70, 0x01, 0x72, 0x01,
5768         0x74, 0x01, 0x76, 0x01, 0x78, 0x01, 0x7c, 0x01, 0xc6, 0x0e, 0x0c, 0x10,
5769         0xac, 0x12, 0xae, 0x12, 0x16, 0x1a, 0x32, 0x1c, 0x6e, 0x1e, 0x02, 0x48,
5770         0x3a, 0x55, 0xc9, 0x57, 0x02, 0xee, 0x5b, 0xf0, 0x03, 0xf7, 0x06, 0xf7,
5771         0x03, 0xfc, 0x06, 0x00, 0x1e, 0x00, 0xbe, 0x00, 0xe1, 0x00, 0x0c, 0x12,
5772         0x18, 0x1a, 0x70, 0x1a, 0x30, 0x1c, 0x38, 0x1c, 0x10, 0x44, 0x00, 0x4c,
5773         0xb0, 0x57, 0x40, 0x5c, 0x4d, 0xe4, 0x04, 0xea, 0x5d, 0xf0, 0xa7, 0xf0,
5774         0x04, 0xf6, 0x02, 0xfc, 0x05, 0x00, 0x09, 0x00, 0x19, 0x00, 0x32, 0x00,
5775         0x33, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00, 0x9e, 0x00, 0xcc, 0x00,
5776         0x20, 0x01, 0x4e, 0x01, 0x79, 0x01, 0x3c, 0x09, 0x68, 0x0d, 0x02, 0x10,
5777         0x04, 0x10, 0x3a, 0x10, 0x08, 0x12, 0x0a, 0x13, 0x40, 0x16, 0x50, 0x16,
5778         0x00, 0x17, 0x4a, 0x19, 0x00, 0x4e, 0x00, 0x54, 0x01, 0x58, 0x00, 0xdc,
5779         0x05, 0xf0, 0x09, 0xf0, 0x59, 0xf0, 0xb8, 0xf0, 0x48, 0xf4, 0x0e, 0xf7,
5780         0x0a, 0x00, 0x9b, 0x00, 0x9c, 0x00, 0xa4, 0x00, 0xb5, 0x00, 0xba, 0x00,
5781         0xd0, 0x00, 0xe7, 0x00, 0xf0, 0x03, 0x69, 0x08, 0xe9, 0x09, 0x5c, 0x0c,
5782         0xb6, 0x12, 0xbc, 0x19, 0xd8, 0x1b, 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c,
5783         0x42, 0x1d, 0x08, 0x44, 0x38, 0x44, 0x91, 0x44, 0x0a, 0x45, 0x48, 0x46,
5784         0x89, 0x48, 0x68, 0x54, 0x83, 0x55, 0x83, 0x59, 0x31, 0xe4, 0x02, 0xe6,
5785         0x07, 0xf0, 0x08, 0xf0, 0x0b, 0xf0, 0x0c, 0xf0, 0x4b, 0xf4, 0x04, 0xf8,
5786         0x05, 0xf8, 0x02, 0xfa, 0x03, 0xfa, 0x04, 0xfc, 0x05, 0xfc, 0x07, 0x00,
5787         0xa8, 0x00, 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00, 0xe5, 0x00, 0x22, 0x01,
5788         0x26, 0x01, 0x60, 0x01, 0x7a, 0x01, 0x82, 0x01, 0xc8, 0x01, 0xca, 0x01,
5789         0x86, 0x02, 0x6a, 0x03, 0x18, 0x05, 0xb2, 0x07, 0x68, 0x08, 0x10, 0x0d,
5790         0x06, 0x10, 0x0a, 0x10, 0x0e, 0x10, 0x12, 0x10, 0x60, 0x10, 0xed, 0x10,
5791         0xf3, 0x10, 0x06, 0x12, 0x10, 0x12, 0x1e, 0x12, 0x0c, 0x13, 0x0e, 0x13,
5792         0x10, 0x13, 0xfe, 0x9c, 0xf0, 0x35, 0x05, 0xfe, 0xec, 0x0e, 0xff, 0x10,
5793         0x00, 0x00, 0xe9, 0xfe, 0x34, 0x1f, 0x00, 0xe8, 0xfe, 0x88, 0x01, 0xff,
5794         0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00,
5795         0x00, 0xfe, 0x57, 0x24, 0x00, 0xfe, 0x4c, 0x00, 0x65, 0xff, 0x04, 0x00,
5796         0x00, 0x1a, 0xff, 0x09, 0x00, 0x00, 0xff, 0x08, 0x01, 0x01, 0xff, 0x08,
5797         0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10, 0xff, 0xff, 0xff, 0x13,
5798         0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00,
5799         0xfe, 0x04, 0xf7, 0xe8, 0x37, 0x7d, 0x0d, 0x01, 0xfe, 0x4a, 0x11, 0xfe,
5800         0x04, 0xf7, 0xe8, 0x7d, 0x0d, 0x51, 0x37, 0xfe, 0x3d, 0xf0, 0xfe, 0x0c,
5801         0x02, 0xfe, 0x20, 0xf0, 0xbc, 0xfe, 0x91, 0xf0, 0xfe, 0xf8, 0x01, 0xfe,
5802         0x90, 0xf0, 0xfe, 0xf8, 0x01, 0xfe, 0x8f, 0xf0, 0xbc, 0x03, 0x67, 0x4d,
5803         0x05, 0xfe, 0x08, 0x0f, 0x01, 0xfe, 0x78, 0x0f, 0xfe, 0xdd, 0x12, 0x05,
5804         0xfe, 0x0e, 0x03, 0xfe, 0x28, 0x1c, 0x03, 0xfe, 0xa6, 0x00, 0xfe, 0xd1,
5805         0x12, 0x3e, 0x22, 0xfe, 0xa6, 0x00, 0xac, 0xfe, 0x48, 0xf0, 0xfe, 0x90,
5806         0x02, 0xfe, 0x49, 0xf0, 0xfe, 0xaa, 0x02, 0xfe, 0x4a, 0xf0, 0xfe, 0xc8,
5807         0x02, 0xfe, 0x46, 0xf0, 0xfe, 0x5a, 0x02, 0xfe, 0x47, 0xf0, 0xfe, 0x60,
5808         0x02, 0xfe, 0x43, 0xf0, 0xfe, 0x4e, 0x02, 0xfe, 0x44, 0xf0, 0xfe, 0x52,
5809         0x02, 0xfe, 0x45, 0xf0, 0xfe, 0x56, 0x02, 0x1c, 0x0d, 0xa2, 0x1c, 0x07,
5810         0x22, 0xb7, 0x05, 0x35, 0xfe, 0x00, 0x1c, 0xfe, 0xf1, 0x10, 0xfe, 0x02,
5811         0x1c, 0xf5, 0xfe, 0x1e, 0x1c, 0xfe, 0xe9, 0x10, 0x01, 0x5f, 0xfe, 0xe7,
5812         0x10, 0xfe, 0x06, 0xfc, 0xde, 0x0a, 0x81, 0x01, 0xa3, 0x05, 0x35, 0x1f,
5813         0x95, 0x47, 0xb8, 0x01, 0xfe, 0xe4, 0x11, 0x0a, 0x81, 0x01, 0x5c, 0xfe,
5814         0xbd, 0x10, 0x0a, 0x81, 0x01, 0x5c, 0xfe, 0xad, 0x10, 0xfe, 0x16, 0x1c,
5815         0xfe, 0x58, 0x1c, 0x1c, 0x07, 0x22, 0xb7, 0x37, 0x2a, 0x35, 0xfe, 0x3d,
5816         0xf0, 0xfe, 0x0c, 0x02, 0x2b, 0xfe, 0x9e, 0x02, 0xfe, 0x5a, 0x1c, 0xfe,
5817         0x12, 0x1c, 0xfe, 0x14, 0x1c, 0x1f, 0xfe, 0x30, 0x00, 0x47, 0xb8, 0x01,
5818         0xfe, 0xd4, 0x11, 0x1c, 0x07, 0x22, 0xb7, 0x05, 0xe9, 0x21, 0x2c, 0x09,
5819         0x1a, 0x31, 0xfe, 0x69, 0x10, 0x1c, 0x07, 0x22, 0xb7, 0xfe, 0x04, 0xec,
5820         0x2c, 0x60, 0x01, 0xfe, 0x1e, 0x1e, 0x20, 0x2c, 0xfe, 0x05, 0xf6, 0xde,
5821         0x01, 0xfe, 0x62, 0x1b, 0x01, 0x0c, 0x61, 0x4a, 0x44, 0x15, 0x56, 0x51,
5822         0x01, 0xfe, 0x9e, 0x1e, 0x01, 0xfe, 0x96, 0x1a, 0x05, 0x35, 0x0a, 0x57,
5823         0x01, 0x18, 0x09, 0x00, 0x36, 0x01, 0x85, 0xfe, 0x18, 0x10, 0xfe, 0x41,
5824         0x58, 0x0a, 0xba, 0x01, 0x18, 0xfe, 0xc8, 0x54, 0x7b, 0xfe, 0x1c, 0x03,
5825         0x01, 0xfe, 0x96, 0x1a, 0x05, 0x35, 0x37, 0x60, 0xfe, 0x02, 0xe8, 0x30,
5826         0xfe, 0xbf, 0x57, 0xfe, 0x9e, 0x43, 0xfe, 0x77, 0x57, 0xfe, 0x27, 0xf0,
5827         0xfe, 0xe4, 0x01, 0xfe, 0x07, 0x4b, 0xfe, 0x20, 0xf0, 0xbc, 0xfe, 0x40,
5828         0x1c, 0x2a, 0xeb, 0xfe, 0x26, 0xf0, 0xfe, 0x66, 0x03, 0xfe, 0xa0, 0xf0,
5829         0xfe, 0x54, 0x03, 0xfe, 0x11, 0xf0, 0xbc, 0xfe, 0xef, 0x10, 0xfe, 0x9f,
5830         0xf0, 0xfe, 0x74, 0x03, 0xfe, 0x46, 0x1c, 0x19, 0xfe, 0x11, 0x00, 0x05,
5831         0x70, 0x37, 0xfe, 0x48, 0x1c, 0xfe, 0x46, 0x1c, 0x01, 0x0c, 0x06, 0x28,
5832         0xfe, 0x18, 0x13, 0x26, 0x21, 0xb9, 0xc7, 0x20, 0xb9, 0x0a, 0x57, 0x01,
5833         0x18, 0xc7, 0x89, 0x01, 0xfe, 0xc8, 0x1a, 0x15, 0xe1, 0x2a, 0xeb, 0xfe,
5834         0x01, 0xf0, 0xeb, 0xfe, 0x82, 0xf0, 0xfe, 0xa4, 0x03, 0xfe, 0x9c, 0x32,
5835         0x15, 0xfe, 0xe4, 0x00, 0x2f, 0xfe, 0xb6, 0x03, 0x2a, 0x3c, 0x16, 0xfe,
5836         0xc6, 0x03, 0x01, 0x41, 0xfe, 0x06, 0xf0, 0xfe, 0xd6, 0x03, 0xaf, 0xa0,
5837         0xfe, 0x0a, 0xf0, 0xfe, 0xa2, 0x07, 0x05, 0x29, 0x03, 0x81, 0x1e, 0x1b,
5838         0xfe, 0x24, 0x05, 0x1f, 0x63, 0x01, 0x42, 0x8f, 0xfe, 0x70, 0x02, 0x05,
5839         0xea, 0xfe, 0x46, 0x1c, 0x37, 0x7d, 0x1d, 0xfe, 0x67, 0x1b, 0xfe, 0xbf,
5840         0x57, 0xfe, 0x77, 0x57, 0xfe, 0x48, 0x1c, 0x75, 0x01, 0xa6, 0x86, 0x0a,
5841         0x57, 0x01, 0x18, 0x09, 0x00, 0x1b, 0xec, 0x0a, 0xe1, 0x01, 0x18, 0x77,
5842         0x50, 0x40, 0x8d, 0x30, 0x03, 0x81, 0x1e, 0xf8, 0x1f, 0x63, 0x01, 0x42,
5843         0x8f, 0xfe, 0x70, 0x02, 0x05, 0xea, 0xd7, 0x99, 0xd8, 0x9c, 0x2a, 0x29,
5844         0x2f, 0xfe, 0x4e, 0x04, 0x16, 0xfe, 0x4a, 0x04, 0x7e, 0xfe, 0xa0, 0x00,
5845         0xfe, 0x9b, 0x57, 0xfe, 0x54, 0x12, 0x32, 0xff, 0x02, 0x00, 0x10, 0x01,
5846         0x08, 0x16, 0xfe, 0x02, 0x05, 0x32, 0x01, 0x08, 0x16, 0x29, 0x27, 0x25,
5847         0xee, 0xfe, 0x4c, 0x44, 0xfe, 0x58, 0x12, 0x50, 0xfe, 0x44, 0x48, 0x13,
5848         0x34, 0xfe, 0x4c, 0x54, 0x7b, 0xec, 0x60, 0x8d, 0x30, 0x01, 0xfe, 0x4e,
5849         0x1e, 0xfe, 0x48, 0x47, 0xfe, 0x7c, 0x13, 0x01, 0x0c, 0x06, 0x28, 0xfe,
5850         0x32, 0x13, 0x01, 0x43, 0x09, 0x9b, 0xfe, 0x68, 0x13, 0xfe, 0x26, 0x10,
5851         0x13, 0x34, 0xfe, 0x4c, 0x54, 0x7b, 0xec, 0x01, 0xfe, 0x4e, 0x1e, 0xfe,
5852         0x48, 0x47, 0xfe, 0x54, 0x13, 0x01, 0x0c, 0x06, 0x28, 0xa5, 0x01, 0x43,
5853         0x09, 0x9b, 0xfe, 0x40, 0x13, 0x01, 0x0c, 0x06, 0x28, 0xf9, 0x1f, 0x7f,
5854         0x01, 0x0c, 0x06, 0x07, 0x4d, 0x1f, 0xfe, 0x0d, 0x00, 0x01, 0x42, 0x8f,
5855         0xfe, 0xa4, 0x0e, 0x05, 0x29, 0x32, 0x15, 0xfe, 0xe6, 0x00, 0x0f, 0xfe,
5856         0x1c, 0x90, 0x04, 0xfe, 0x9c, 0x93, 0x3a, 0x0b, 0x0e, 0x8b, 0x02, 0x1f,
5857         0x7f, 0x01, 0x42, 0x05, 0x35, 0xfe, 0x42, 0x5b, 0x7d, 0x1d, 0xfe, 0x46,
5858         0x59, 0xfe, 0xbf, 0x57, 0xfe, 0x77, 0x57, 0x0f, 0xfe, 0x87, 0x80, 0x04,
5859         0xfe, 0x87, 0x83, 0xfe, 0xc9, 0x47, 0x0b, 0x0e, 0xd0, 0x65, 0x01, 0x0c,
5860         0x06, 0x0d, 0xfe, 0x98, 0x13, 0x0f, 0xfe, 0x20, 0x80, 0x04, 0xfe, 0xa0,
5861         0x83, 0x33, 0x0b, 0x0e, 0x09, 0x1d, 0xfe, 0x84, 0x12, 0x01, 0x38, 0x06,
5862         0x07, 0xfe, 0x70, 0x13, 0x03, 0xfe, 0xa2, 0x00, 0x1e, 0x1b, 0xfe, 0xda,
5863         0x05, 0xd0, 0x54, 0x01, 0x38, 0x06, 0x0d, 0xfe, 0x58, 0x13, 0x03, 0xfe,
5864         0xa0, 0x00, 0x1e, 0xfe, 0x50, 0x12, 0x5e, 0xff, 0x02, 0x00, 0x10, 0x2f,
5865         0xfe, 0x90, 0x05, 0x2a, 0x3c, 0xcc, 0xff, 0x02, 0x00, 0x10, 0x2f, 0xfe,
5866         0x9e, 0x05, 0x17, 0xfe, 0xf4, 0x05, 0x15, 0xfe, 0xe3, 0x00, 0x26, 0x01,
5867         0x38, 0xfe, 0x4a, 0xf0, 0xfe, 0xc0, 0x05, 0xfe, 0x49, 0xf0, 0xfe, 0xba,
5868         0x05, 0x71, 0x2e, 0xfe, 0x21, 0x00, 0xf1, 0x2e, 0xfe, 0x22, 0x00, 0xa2,
5869         0x2e, 0x4a, 0xfe, 0x09, 0x48, 0xff, 0x02, 0x00, 0x10, 0x2f, 0xfe, 0xd0,
5870         0x05, 0x17, 0xfe, 0xf4, 0x05, 0xfe, 0xe2, 0x08, 0x01, 0x38, 0x06, 0xfe,
5871         0x1c, 0x00, 0x4d, 0x01, 0xa7, 0x2e, 0x07, 0x20, 0xe4, 0x47, 0xfe, 0x27,
5872         0x01, 0x01, 0x0c, 0x06, 0x28, 0xfe, 0x24, 0x12, 0x3e, 0x01, 0x84, 0x1f,
5873         0x7f, 0x01, 0x0c, 0x06, 0x07, 0x4d, 0x1f, 0xfe, 0x0d, 0x00, 0x01, 0x42,
5874         0x8f, 0xfe, 0xa4, 0x0e, 0x05, 0x29, 0x03, 0xe6, 0x1e, 0xfe, 0xca, 0x13,
5875         0x03, 0xb6, 0x1e, 0xfe, 0x40, 0x12, 0x03, 0x66, 0x1e, 0xfe, 0x38, 0x13,
5876         0x3e, 0x01, 0x84, 0x17, 0xfe, 0x72, 0x06, 0x0a, 0x07, 0x01, 0x38, 0x06,
5877         0x24, 0xfe, 0x02, 0x12, 0x4f, 0x01, 0xfe, 0x56, 0x19, 0x16, 0xfe, 0x68,
5878         0x06, 0x15, 0x82, 0x01, 0x41, 0x15, 0xe2, 0x03, 0x66, 0x8a, 0x10, 0x66,
5879         0x03, 0x9a, 0x1e, 0xfe, 0x70, 0x12, 0x03, 0x55, 0x1e, 0xfe, 0x68, 0x13,
5880         0x01, 0xc6, 0x09, 0x12, 0x48, 0xfe, 0x92, 0x06, 0x2e, 0x12, 0x01, 0xfe,
5881         0xac, 0x1d, 0xfe, 0x43, 0x48, 0x62, 0x80, 0x13, 0x58, 0xff, 0x02, 0x00,
5882         0x57, 0x52, 0xad, 0x23, 0x3f, 0x4e, 0x62, 0x49, 0x3e, 0x01, 0x84, 0x17,
5883         0xfe, 0xea, 0x06, 0x01, 0x38, 0x06, 0x12, 0xf7, 0x45, 0x0a, 0x95, 0x01,
5884         0xfe, 0x84, 0x19, 0x16, 0xfe, 0xe0, 0x06, 0x15, 0x82, 0x01, 0x41, 0x15,
5885         0xe2, 0x03, 0x55, 0x8a, 0x10, 0x55, 0x1c, 0x07, 0x01, 0x84, 0xfe, 0xae,
5886         0x10, 0x03, 0x6f, 0x1e, 0xfe, 0x9e, 0x13, 0x3e, 0x01, 0x84, 0x03, 0x9a,
5887         0x1e, 0xfe, 0x1a, 0x12, 0x01, 0x38, 0x06, 0x12, 0xfc, 0x01, 0xc6, 0x01,
5888         0xfe, 0xac, 0x1d, 0xfe, 0x43, 0x48, 0x62, 0x80, 0xf0, 0x45, 0x0a, 0x95,
5889         0x03, 0xb6, 0x1e, 0xf8, 0x01, 0x38, 0x06, 0x24, 0x36, 0xfe, 0x02, 0xf6,
5890         0x07, 0x71, 0x78, 0x8c, 0x00, 0x4d, 0x62, 0x49, 0x3e, 0x2d, 0x93, 0x4e,
5891         0xd0, 0x0d, 0x17, 0xfe, 0x9a, 0x07, 0x01, 0xfe, 0xc0, 0x19, 0x16, 0xfe,
5892         0x90, 0x07, 0x26, 0x20, 0x9e, 0x15, 0x82, 0x01, 0x41, 0x15, 0xe2, 0x21,
5893         0x9e, 0x09, 0x07, 0xfb, 0x03, 0xe6, 0xfe, 0x58, 0x57, 0x10, 0xe6, 0x05,
5894         0xfe, 0x2a, 0x06, 0x03, 0x6f, 0x8a, 0x10, 0x6f, 0x1c, 0x07, 0x01, 0x84,
5895         0xfe, 0x9c, 0x32, 0x5f, 0x75, 0x01, 0xa6, 0x86, 0x15, 0xfe, 0xe2, 0x00,
5896         0x2f, 0xed, 0x2a, 0x3c, 0xfe, 0x0a, 0xf0, 0xfe, 0xce, 0x07, 0xae, 0xfe,
5897         0x96, 0x08, 0xfe, 0x06, 0xf0, 0xfe, 0x9e, 0x08, 0xaf, 0xa0, 0x05, 0x29,
5898         0x01, 0x0c, 0x06, 0x0d, 0xfe, 0x2e, 0x12, 0x14, 0x1d, 0x01, 0x08, 0x14,
5899         0x00, 0x01, 0x08, 0x14, 0x00, 0x01, 0x08, 0x14, 0x00, 0x01, 0x08, 0xfe,
5900         0x99, 0xa4, 0x01, 0x08, 0x14, 0x00, 0x05, 0xfe, 0xc6, 0x09, 0x01, 0x76,
5901         0x06, 0x12, 0xfe, 0x3a, 0x12, 0x01, 0x0c, 0x06, 0x12, 0xfe, 0x30, 0x13,
5902         0x14, 0xfe, 0x1b, 0x00, 0x01, 0x08, 0x14, 0x00, 0x01, 0x08, 0x14, 0x00,
5903         0x01, 0x08, 0x14, 0x00, 0x01, 0x08, 0x14, 0x07, 0x01, 0x08, 0x14, 0x00,
5904         0x05, 0xef, 0x7c, 0x4a, 0x78, 0x4f, 0x0f, 0xfe, 0x9a, 0x81, 0x04, 0xfe,
5905         0x9a, 0x83, 0xfe, 0xcb, 0x47, 0x0b, 0x0e, 0x2d, 0x28, 0x48, 0xfe, 0x6c,
5906         0x08, 0x0a, 0x28, 0xfe, 0x09, 0x6f, 0xca, 0xfe, 0xca, 0x45, 0xfe, 0x32,
5907         0x12, 0x53, 0x63, 0x4e, 0x7c, 0x97, 0x2f, 0xfe, 0x7e, 0x08, 0x2a, 0x3c,
5908         0xfe, 0x0a, 0xf0, 0xfe, 0x6c, 0x08, 0xaf, 0xa0, 0xae, 0xfe, 0x96, 0x08,
5909         0x05, 0x29, 0x01, 0x41, 0x05, 0xed, 0x14, 0x24, 0x05, 0xed, 0xfe, 0x9c,
5910         0xf7, 0x9f, 0x01, 0xfe, 0xae, 0x1e, 0xfe, 0x18, 0x58, 0x01, 0xfe, 0xbe,
5911         0x1e, 0xfe, 0x99, 0x58, 0xfe, 0x78, 0x18, 0xfe, 0xf9, 0x18, 0x8e, 0xfe,
5912         0x16, 0x09, 0x10, 0x6a, 0x22, 0x6b, 0x01, 0x0c, 0x61, 0x54, 0x44, 0x21,
5913         0x2c, 0x09, 0x1a, 0xf8, 0x77, 0x01, 0xfe, 0x7e, 0x1e, 0x47, 0x2c, 0x7a,
5914         0x30, 0xf0, 0xfe, 0x83, 0xe7, 0xfe, 0x3f, 0x00, 0x71, 0xfe, 0x03, 0x40,
5915         0x01, 0x0c, 0x61, 0x65, 0x44, 0x01, 0xc2, 0xc8, 0xfe, 0x1f, 0x40, 0x20,
5916         0x6e, 0x01, 0xfe, 0x6a, 0x16, 0xfe, 0x08, 0x50, 0xfe, 0x8a, 0x50, 0xfe,
5917         0x44, 0x51, 0xfe, 0xc6, 0x51, 0xfe, 0x10, 0x10, 0x01, 0xfe, 0xce, 0x1e,
5918         0x01, 0xfe, 0xde, 0x1e, 0x10, 0x68, 0x22, 0x69, 0x01, 0xfe, 0xee, 0x1e,
5919         0x01, 0xfe, 0xfe, 0x1e, 0xfe, 0x40, 0x50, 0xfe, 0xc2, 0x50, 0x10, 0x4b,
5920         0x22, 0x4c, 0xfe, 0x8a, 0x10, 0x01, 0x0c, 0x06, 0x54, 0xfe, 0x50, 0x12,
5921         0x01, 0xfe, 0xae, 0x1e, 0x01, 0xfe, 0xbe, 0x1e, 0x10, 0x6a, 0x22, 0x6b,
5922         0x01, 0x0c, 0x06, 0x65, 0x4e, 0x01, 0xc2, 0x0f, 0xfe, 0x1f, 0x80, 0x04,
5923         0xfe, 0x9f, 0x83, 0x33, 0x0b, 0x0e, 0x20, 0x6e, 0x0f, 0xfe, 0x44, 0x90,
5924         0x04, 0xfe, 0xc4, 0x93, 0x3a, 0x0b, 0xfe, 0xc6, 0x90, 0x04, 0xfe, 0xc6,
5925         0x93, 0x79, 0x0b, 0x0e, 0x10, 0x6c, 0x22, 0x6d, 0x01, 0xfe, 0xce, 0x1e,
5926         0x01, 0xfe, 0xde, 0x1e, 0x10, 0x68, 0x22, 0x69, 0x0f, 0xfe, 0x40, 0x90,
5927         0x04, 0xfe, 0xc0, 0x93, 0x3a, 0x0b, 0xfe, 0xc2, 0x90, 0x04, 0xfe, 0xc2,
5928         0x93, 0x79, 0x0b, 0x0e, 0x10, 0x4b, 0x22, 0x4c, 0x10, 0x64, 0x22, 0x34,
5929         0x01, 0x0c, 0x61, 0x24, 0x44, 0x37, 0x13, 0xfe, 0x4e, 0x11, 0x2f, 0xfe,
5930         0xde, 0x09, 0xfe, 0x9e, 0xf0, 0xfe, 0xf2, 0x09, 0xfe, 0x01, 0x48, 0x1b,
5931         0x3c, 0x37, 0x88, 0xf5, 0xd4, 0xfe, 0x1e, 0x0a, 0xd5, 0xfe, 0x42, 0x0a,
5932         0xd2, 0xfe, 0x1e, 0x0a, 0xd3, 0xfe, 0x42, 0x0a, 0xae, 0xfe, 0x12, 0x0a,
5933         0xfe, 0x06, 0xf0, 0xfe, 0x18, 0x0a, 0xaf, 0xa0, 0x05, 0x29, 0x01, 0x41,
5934         0xfe, 0xc1, 0x10, 0x14, 0x24, 0xfe, 0xc1, 0x10, 0x01, 0x76, 0x06, 0x07,
5935         0xfe, 0x14, 0x12, 0x01, 0x76, 0x06, 0x0d, 0x5d, 0x01, 0x0c, 0x06, 0x0d,
5936         0xfe, 0x74, 0x12, 0xfe, 0x2e, 0x1c, 0x05, 0xfe, 0x1a, 0x0c, 0x01, 0x76,
5937         0x06, 0x07, 0x5d, 0x01, 0x76, 0x06, 0x0d, 0x41, 0xfe, 0x2c, 0x1c, 0xfe,
5938         0xaa, 0xf0, 0xfe, 0xce, 0x0a, 0xfe, 0xac, 0xf0, 0xfe, 0x66, 0x0a, 0xfe,
5939         0x92, 0x10, 0xc4, 0xf6, 0xfe, 0xad, 0xf0, 0xfe, 0x72, 0x0a, 0x05, 0xfe,
5940         0x1a, 0x0c, 0xc5, 0xfe, 0xe7, 0x10, 0xfe, 0x2b, 0xf0, 0xbf, 0xfe, 0x6b,
5941         0x18, 0x23, 0xfe, 0x00, 0xfe, 0xfe, 0x1c, 0x12, 0xac, 0xfe, 0xd2, 0xf0,
5942         0xbf, 0xfe, 0x76, 0x18, 0x23, 0x1d, 0x1b, 0xbf, 0x03, 0xe3, 0x23, 0x07,
5943         0x1b, 0xbf, 0xd4, 0x5b, 0xd5, 0x5b, 0xd2, 0x5b, 0xd3, 0x5b, 0xc4, 0xc5,
5944         0xfe, 0xa9, 0x10, 0x75, 0x5e, 0x32, 0x1f, 0x7f, 0x01, 0x42, 0x19, 0xfe,
5945         0x35, 0x00, 0xfe, 0x01, 0xf0, 0x70, 0x19, 0x98, 0x05, 0x70, 0xfe, 0x74,
5946         0x18, 0x23, 0xfe, 0x00, 0xf8, 0x1b, 0x5b, 0x7d, 0x12, 0x01, 0xfe, 0x78,
5947         0x0f, 0x4d, 0x01, 0xfe, 0x96, 0x1a, 0x21, 0x30, 0x77, 0x7d, 0x1d, 0x05,
5948         0x5b, 0x01, 0x0c, 0x06, 0x0d, 0x2b, 0xfe, 0xe2, 0x0b, 0x01, 0x0c, 0x06,
5949         0x54, 0xfe, 0xa6, 0x12, 0x01, 0x0c, 0x06, 0x24, 0xfe, 0x88, 0x13, 0x21,
5950         0x6e, 0xc7, 0x01, 0xfe, 0x1e, 0x1f, 0x0f, 0xfe, 0x83, 0x80, 0x04, 0xfe,
5951         0x83, 0x83, 0xfe, 0xc9, 0x47, 0x0b, 0x0e, 0xfe, 0xc8, 0x44, 0xfe, 0x42,
5952         0x13, 0x0f, 0xfe, 0x04, 0x91, 0x04, 0xfe, 0x84, 0x93, 0xfe, 0xca, 0x57,
5953         0x0b, 0xfe, 0x86, 0x91, 0x04, 0xfe, 0x86, 0x93, 0xfe, 0xcb, 0x57, 0x0b,
5954         0x0e, 0x7a, 0x30, 0xfe, 0x40, 0x59, 0xfe, 0xc1, 0x59, 0x8e, 0x40, 0x03,
5955         0x6a, 0x3b, 0x6b, 0x10, 0x97, 0x22, 0x98, 0xd9, 0x6a, 0xda, 0x6b, 0x01,
5956         0xc2, 0xc8, 0x7a, 0x30, 0x20, 0x6e, 0xdb, 0x64, 0xdc, 0x34, 0x91, 0x6c,
5957         0x7e, 0x6d, 0xfe, 0x44, 0x55, 0xfe, 0xe5, 0x55, 0xfe, 0x04, 0xfa, 0x64,
5958         0xfe, 0x05, 0xfa, 0x34, 0x01, 0xfe, 0x6a, 0x16, 0xa3, 0x26, 0x10, 0x97,
5959         0x10, 0x98, 0x91, 0x6c, 0x7e, 0x6d, 0xfe, 0x14, 0x10, 0x01, 0x0c, 0x06,
5960         0x24, 0x1b, 0x40, 0x91, 0x4b, 0x7e, 0x4c, 0x01, 0x0c, 0x06, 0xfe, 0xf7,
5961         0x00, 0x44, 0x03, 0x68, 0x3b, 0x69, 0xfe, 0x10, 0x58, 0xfe, 0x91, 0x58,
5962         0xfe, 0x14, 0x59, 0xfe, 0x95, 0x59, 0x05, 0x5b, 0x01, 0x0c, 0x06, 0x24,
5963         0x1b, 0x40, 0x01, 0x0c, 0x06, 0xfe, 0xf7, 0x00, 0x44, 0x78, 0x01, 0xfe,
5964         0x8e, 0x1e, 0x4f, 0x0f, 0xfe, 0x10, 0x90, 0x04, 0xfe, 0x90, 0x93, 0x3a,
5965         0x0b, 0xfe, 0x92, 0x90, 0x04, 0xfe, 0x92, 0x93, 0x79, 0x0b, 0x0e, 0xfe,
5966         0xbd, 0x10, 0x01, 0x43, 0x09, 0xbb, 0x1b, 0xfe, 0x6e, 0x0a, 0x15, 0xbb,
5967         0x01, 0x0c, 0x06, 0x0d, 0xfe, 0x14, 0x13, 0x03, 0x4b, 0x3b, 0x4c, 0x8e,
5968         0xfe, 0x6e, 0x0a, 0xfe, 0x0c, 0x58, 0xfe, 0x8d, 0x58, 0x05, 0x5b, 0x26,
5969         0x3e, 0x0f, 0xfe, 0x19, 0x80, 0x04, 0xfe, 0x99, 0x83, 0x33, 0x0b, 0x0e,
5970         0xfe, 0xe5, 0x10, 0x01, 0x0c, 0x06, 0x0d, 0xfe, 0x1a, 0x12, 0xfe, 0x6c,
5971         0x19, 0xfe, 0x19, 0x41, 0xfe, 0x6b, 0x18, 0xac, 0xfe, 0xd1, 0xf0, 0xef,
5972         0x1f, 0x92, 0x01, 0x42, 0x19, 0xfe, 0x44, 0x00, 0xfe, 0x90, 0x10, 0xfe,
5973         0x6c, 0x19, 0xd9, 0x4b, 0xfe, 0xed, 0x19, 0xda, 0x4c, 0xfe, 0x0c, 0x51,
5974         0xfe, 0x8e, 0x51, 0xfe, 0x6b, 0x18, 0x23, 0xfe, 0x00, 0xff, 0x31, 0xfe,
5975         0x76, 0x10, 0xac, 0xfe, 0xd2, 0xf0, 0xfe, 0xba, 0x0c, 0xfe, 0x76, 0x18,
5976         0x23, 0x1d, 0x5d, 0x03, 0xe3, 0x23, 0x07, 0xfe, 0x08, 0x13, 0x19, 0xfe,
5977         0x16, 0x00, 0x05, 0x70, 0xfe, 0xd1, 0xf0, 0xfe, 0xcc, 0x0c, 0x1f, 0x92,
5978         0x01, 0x42, 0x19, 0xfe, 0x17, 0x00, 0x5c, 0xfe, 0xce, 0xf0, 0xfe, 0xd2,
5979         0x0c, 0xfe, 0x3e, 0x10, 0xfe, 0xcd, 0xf0, 0xfe, 0xde, 0x0c, 0x19, 0xfe,
5980         0x22, 0x00, 0x05, 0x70, 0xfe, 0xcb, 0xf0, 0xfe, 0xea, 0x0c, 0x19, 0xfe,
5981         0x24, 0x00, 0x05, 0x70, 0xfe, 0xd0, 0xf0, 0xfe, 0xf4, 0x0c, 0x19, 0x94,
5982         0xfe, 0x1c, 0x10, 0xfe, 0xcf, 0xf0, 0xfe, 0xfe, 0x0c, 0x19, 0x4a, 0xf3,
5983         0xfe, 0xcc, 0xf0, 0xef, 0x01, 0x76, 0x06, 0x24, 0x4d, 0x19, 0xfe, 0x12,
5984         0x00, 0x37, 0x13, 0xfe, 0x4e, 0x11, 0x2f, 0xfe, 0x16, 0x0d, 0xfe, 0x9e,
5985         0xf0, 0xfe, 0x2a, 0x0d, 0xfe, 0x01, 0x48, 0x1b, 0x3c, 0x37, 0x88, 0xf5,
5986         0xd4, 0x29, 0xd5, 0x29, 0xd2, 0x29, 0xd3, 0x29, 0x37, 0xfe, 0x9c, 0x32,
5987         0x2f, 0xfe, 0x3e, 0x0d, 0x2a, 0x3c, 0xae, 0xfe, 0x62, 0x0d, 0xaf, 0xa0,
5988         0xd4, 0x9f, 0xd5, 0x9f, 0xd2, 0x9f, 0xd3, 0x9f, 0x05, 0x29, 0x01, 0x41,
5989         0xfe, 0xd3, 0x10, 0x15, 0xfe, 0xe8, 0x00, 0xc4, 0xc5, 0x75, 0xd7, 0x99,
5990         0xd8, 0x9c, 0xfe, 0x89, 0xf0, 0x29, 0x27, 0x25, 0xbe, 0xd7, 0x99, 0xd8,
5991         0x9c, 0x2f, 0xfe, 0x8c, 0x0d, 0x16, 0x29, 0x27, 0x25, 0xbd, 0xfe, 0x01,
5992         0x48, 0xa4, 0x19, 0xfe, 0x42, 0x00, 0x05, 0x70, 0x90, 0x07, 0xfe, 0x81,
5993         0x49, 0x1b, 0xfe, 0x64, 0x0e, 0x01, 0x0c, 0x06, 0x0d, 0xfe, 0x44, 0x13,
5994         0x19, 0x00, 0x2d, 0x0d, 0xfe, 0x54, 0x12, 0x2d, 0xfe, 0x28, 0x00, 0x2b,
5995         0xfe, 0xda, 0x0e, 0x0a, 0x57, 0x01, 0x18, 0x09, 0x00, 0x36, 0x46, 0xfe,
5996         0x28, 0x00, 0xfe, 0xfa, 0x10, 0x01, 0xfe, 0xf4, 0x1c, 0x01, 0xfe, 0x00,
5997         0x1d, 0x0a, 0xba, 0x01, 0xfe, 0x58, 0x10, 0x40, 0x15, 0x56, 0x01, 0x85,
5998         0x05, 0x35, 0x19, 0xfe, 0x44, 0x00, 0x2d, 0x0d, 0xf7, 0x46, 0x0d, 0xfe,
5999         0xcc, 0x10, 0x01, 0xa7, 0x46, 0x0d, 0xfe, 0xc2, 0x10, 0x01, 0xa7, 0x0f,
6000         0xfe, 0x19, 0x82, 0x04, 0xfe, 0x99, 0x83, 0xfe, 0xcc, 0x47, 0x0b, 0x0e,
6001         0xfe, 0x34, 0x46, 0xa5, 0x46, 0x0d, 0x19, 0xfe, 0x43, 0x00, 0xfe, 0xa2,
6002         0x10, 0x01, 0x0c, 0x61, 0x0d, 0x44, 0x01, 0xfe, 0xf4, 0x1c, 0x01, 0xfe,
6003         0x00, 0x1d, 0x40, 0x15, 0x56, 0x01, 0x85, 0x7d, 0x0d, 0x40, 0x51, 0x01,
6004         0xfe, 0x9e, 0x1e, 0x05, 0xfe, 0x3a, 0x03, 0x01, 0x0c, 0x06, 0x0d, 0x5d,
6005         0x46, 0x0d, 0x19, 0x00, 0xfe, 0x62, 0x10, 0x01, 0x76, 0x06, 0x12, 0xfe,
6006         0x5c, 0x12, 0x01, 0x0c, 0x06, 0x12, 0xfe, 0x52, 0x13, 0xfe, 0x1c, 0x1c,
6007         0xfe, 0x9d, 0xf0, 0xfe, 0x8e, 0x0e, 0xfe, 0x1c, 0x1c, 0xfe, 0x9d, 0xf0,
6008         0xfe, 0x94, 0x0e, 0x01, 0x0c, 0x61, 0x12, 0x44, 0xfe, 0x9f, 0x10, 0x19,
6009         0xfe, 0x15, 0x00, 0xfe, 0x04, 0xe6, 0x0d, 0x4f, 0xfe, 0x2e, 0x10, 0x19,
6010         0xfe, 0x13, 0x00, 0xfe, 0x10, 0x10, 0x19, 0xfe, 0x47, 0x00, 0xf1, 0x19,
6011         0xfe, 0x41, 0x00, 0xa2, 0x19, 0xfe, 0x24, 0x00, 0x86, 0xc4, 0xc5, 0x75,
6012         0x03, 0x81, 0x1e, 0x2b, 0xea, 0x4f, 0xfe, 0x04, 0xe6, 0x12, 0xfe, 0x9d,
6013         0x41, 0xfe, 0x1c, 0x42, 0x40, 0x01, 0xf4, 0x05, 0x35, 0xfe, 0x12, 0x1c,
6014         0x1f, 0x0d, 0x47, 0xb5, 0xc3, 0x1f, 0xfe, 0x31, 0x00, 0x47, 0xb8, 0x01,
6015         0xfe, 0xd4, 0x11, 0x05, 0xe9, 0x51, 0xfe, 0x06, 0xec, 0xe0, 0xfe, 0x0e,
6016         0x47, 0x46, 0x28, 0xfe, 0xce, 0x45, 0x31, 0x51, 0xfe, 0x06, 0xea, 0xe0,
6017         0xfe, 0x47, 0x4b, 0x45, 0xfe, 0x75, 0x57, 0x03, 0x67, 0xfe, 0x98, 0x56,
6018         0xfe, 0x38, 0x12, 0x0a, 0x5a, 0x01, 0x18, 0xfe, 0x44, 0x48, 0x60, 0x01,
6019         0x0c, 0x06, 0x28, 0xfe, 0x18, 0x13, 0x0a, 0x57, 0x01, 0x18, 0x3e, 0xfe,
6020         0x41, 0x58, 0x0a, 0xba, 0xfe, 0xfa, 0x14, 0xfe, 0x49, 0x54, 0xb0, 0xfe,
6021         0x5e, 0x0f, 0x05, 0xfe, 0x3a, 0x03, 0x0a, 0x67, 0xfe, 0xe0, 0x14, 0xfe,
6022         0x0e, 0x47, 0x46, 0x28, 0xfe, 0xce, 0x45, 0x31, 0x51, 0xfe, 0xce, 0x47,
6023         0xfe, 0xad, 0x13, 0x05, 0x35, 0x21, 0x2c, 0x09, 0x1a, 0xfe, 0x98, 0x12,
6024         0x26, 0x20, 0x96, 0x20, 0xe7, 0xfe, 0x08, 0x1c, 0xfe, 0x7c, 0x19, 0xfe,
6025         0xfd, 0x19, 0xfe, 0x0a, 0x1c, 0x03, 0xe5, 0xfe, 0x48, 0x55, 0xa5, 0x3b,
6026         0xfe, 0x62, 0x01, 0xfe, 0xc9, 0x55, 0x31, 0xfe, 0x74, 0x10, 0x01, 0xfe,
6027         0xf0, 0x1a, 0x03, 0xfe, 0x38, 0x01, 0x3b, 0xfe, 0x3a, 0x01, 0x8e, 0xfe,
6028         0x1e, 0x10, 0xfe, 0x02, 0xec, 0xe7, 0x53, 0x00, 0x36, 0xfe, 0x04, 0xec,
6029         0x2c, 0x60, 0xfe, 0x05, 0xf6, 0xfe, 0x34, 0x01, 0x01, 0xfe, 0x62, 0x1b,
6030         0x01, 0xfe, 0xce, 0x1e, 0xb2, 0x11, 0xfe, 0x18, 0x13, 0xca, 0xfe, 0x02,
6031         0xea, 0xe7, 0x53, 0x92, 0xfe, 0xc3, 0x13, 0x1f, 0x12, 0x47, 0xb5, 0xc3,
6032         0xfe, 0x2a, 0x10, 0x03, 0xfe, 0x38, 0x01, 0x23, 0xfe, 0xf0, 0xff, 0x10,
6033         0xe5, 0x03, 0xfe, 0x3a, 0x01, 0x10, 0xfe, 0x62, 0x01, 0x01, 0xfe, 0x1e,
6034         0x1e, 0x20, 0x2c, 0x15, 0x56, 0x01, 0xfe, 0x9e, 0x1e, 0x13, 0x07, 0x02,
6035         0x26, 0x02, 0x21, 0x96, 0xc7, 0x20, 0x96, 0x09, 0x92, 0xfe, 0x79, 0x13,
6036         0x1f, 0x1d, 0x47, 0xb5, 0xc3, 0xfe, 0xe1, 0x10, 0xcf, 0xfe, 0x03, 0xdc,
6037         0xfe, 0x73, 0x57, 0xfe, 0x80, 0x5d, 0x02, 0xcf, 0xfe, 0x03, 0xdc, 0xfe,
6038         0x5b, 0x57, 0xfe, 0x80, 0x5d, 0x02, 0xfe, 0x03, 0x57, 0xcf, 0x26, 0xfe,
6039         0x00, 0xcc, 0x02, 0xfe, 0x03, 0x57, 0xcf, 0x89, 0x02, 0x01, 0x0c, 0x06,
6040         0x4a, 0xfe, 0x4e, 0x13, 0x0f, 0xfe, 0x1c, 0x80, 0x04, 0xfe, 0x9c, 0x83,
6041         0x33, 0x0b, 0x0e, 0x09, 0x07, 0xfe, 0x3a, 0x13, 0x0f, 0xfe, 0x1e, 0x80,
6042         0x04, 0xfe, 0x9e, 0x83, 0x33, 0x0b, 0x0e, 0xfe, 0x2a, 0x13, 0x0f, 0xfe,
6043         0x1d, 0x80, 0x04, 0xfe, 0x9d, 0x83, 0xfe, 0xf9, 0x13, 0x0e, 0xfe, 0x1c,
6044         0x13, 0x01, 0xfe, 0xee, 0x1e, 0xac, 0xfe, 0x14, 0x13, 0x01, 0xfe, 0xfe,
6045         0x1e, 0xfe, 0x81, 0x58, 0xfa, 0x01, 0xfe, 0x0e, 0x1f, 0xfe, 0x30, 0xf4,
6046         0x0d, 0xfe, 0x3c, 0x50, 0xa2, 0x01, 0xfe, 0x92, 0x1b, 0x01, 0x43, 0x09,
6047         0x56, 0xfb, 0x01, 0xfe, 0xc8, 0x1a, 0x01, 0x0c, 0x06, 0x28, 0xa4, 0x01,
6048         0xfe, 0xf4, 0x1c, 0x01, 0xfe, 0x00, 0x1d, 0x15, 0xfe, 0xe9, 0x00, 0x01,
6049         0x0c, 0x06, 0x4a, 0xfe, 0x4e, 0x13, 0x01, 0xfe, 0x22, 0x1b, 0xfe, 0x1e,
6050         0x1c, 0x0f, 0xfe, 0x14, 0x90, 0x04, 0xfe, 0x94, 0x93, 0x3a, 0x0b, 0xfe,
6051         0x96, 0x90, 0x04, 0xfe, 0x96, 0x93, 0x79, 0x0b, 0x0e, 0x10, 0xfe, 0x64,
6052         0x01, 0x22, 0xfe, 0x66, 0x01, 0x01, 0x0c, 0x06, 0x65, 0xf9, 0x0f, 0xfe,
6053         0x03, 0x80, 0x04, 0xfe, 0x83, 0x83, 0x33, 0x0b, 0x0e, 0x77, 0xfe, 0x01,
6054         0xec, 0x2c, 0xfe, 0x80, 0x40, 0x20, 0x2c, 0x7a, 0x30, 0x15, 0xdf, 0x40,
6055         0x21, 0x2c, 0xfe, 0x00, 0x40, 0x8d, 0x2c, 0x02, 0xfe, 0x08, 0x1c, 0x03,
6056         0xfe, 0xac, 0x00, 0xfe, 0x06, 0x58, 0x03, 0xfe, 0xae, 0x00, 0xfe, 0x07,
6057         0x58, 0x03, 0xfe, 0xb0, 0x00, 0xfe, 0x08, 0x58, 0x03, 0xfe, 0xb2, 0x00,
6058         0xfe, 0x09, 0x58, 0xfe, 0x0a, 0x1c, 0x2e, 0x49, 0x20, 0xe0, 0x26, 0x10,
6059         0x66, 0x10, 0x55, 0x10, 0x6f, 0x13, 0x57, 0x52, 0x4f, 0x1c, 0x28, 0xfe,
6060         0x90, 0x4d, 0xfe, 0x91, 0x54, 0x2b, 0xfe, 0x88, 0x11, 0x46, 0x1a, 0x13,
6061         0x5a, 0x52, 0x1c, 0x4a, 0xfe, 0x90, 0x4d, 0xfe, 0x91, 0x54, 0x2b, 0xfe,
6062         0x9e, 0x11, 0x2e, 0x1a, 0x20, 0x2c, 0x90, 0x34, 0x60, 0x21, 0x2c, 0xfe,
6063         0x00, 0x40, 0x8d, 0x2c, 0x15, 0xdf, 0xfe, 0x14, 0x56, 0xfe, 0xd6, 0xf0,
6064         0xfe, 0xb2, 0x11, 0xfe, 0x12, 0x1c, 0x75, 0xfe, 0x14, 0x1c, 0xfe, 0x10,
6065         0x1c, 0xfe, 0x18, 0x1c, 0x02, 0x51, 0xfe, 0x0c, 0x14, 0xfe, 0x0e, 0x47,
6066         0xfe, 0x07, 0xe6, 0x28, 0xfe, 0xce, 0x47, 0xfe, 0xf5, 0x13, 0x02, 0x01,
6067         0xa7, 0x90, 0x34, 0x60, 0xfe, 0x06, 0x80, 0xfe, 0x48, 0x47, 0xfe, 0x42,
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6088         0x04, 0x55, 0xfe, 0xa5, 0x55, 0xfe, 0x04, 0xfa, 0x64, 0xfe, 0x05, 0xfa,
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6091         0x44, 0x55, 0xfe, 0xe5, 0x55, 0x03, 0x68, 0x3b, 0x69, 0xfe, 0x00, 0x56,
6092         0xfe, 0xa1, 0x56, 0x10, 0x68, 0x22, 0x69, 0x01, 0x0c, 0x06, 0x54, 0xf9,
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6096         0x4b, 0x3b, 0x4c, 0xfe, 0x40, 0x50, 0xfe, 0xc2, 0x50, 0x05, 0x73, 0x2e,
6097         0x07, 0x20, 0x9e, 0x05, 0x72, 0x32, 0x01, 0x08, 0x16, 0x3d, 0x27, 0x25,
6098         0xee, 0x09, 0x07, 0x2b, 0x3d, 0x01, 0x43, 0x09, 0xbb, 0x2b, 0x72, 0x01,
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6101         0x4b, 0xda, 0x4c, 0xfe, 0x0c, 0x51, 0xfe, 0x8e, 0x51, 0x05, 0x72, 0x01,
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6108         0x2d, 0x00, 0xa4, 0x46, 0x07, 0x90, 0x3f, 0x01, 0xfe, 0xf8, 0x15, 0x01,
6109         0xa6, 0x86, 0xfe, 0x4b, 0x45, 0xfe, 0x20, 0x13, 0x01, 0x43, 0x09, 0x82,
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6115         0xe8, 0x14, 0x01, 0xa6, 0x86, 0xfe, 0x4a, 0xf4, 0x0d, 0x1b, 0x3d, 0xfe,
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6158         0x0d, 0x02, 0x50, 0x3e, 0x78, 0x4f, 0x45, 0x01, 0x08, 0x16, 0xa9, 0x27,
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6163         0x08, 0x16, 0xa9, 0x27, 0x25, 0xfe, 0xe8, 0x08, 0x47, 0xfe, 0x81, 0x01,
6164         0x03, 0xb6, 0x1e, 0x83, 0x01, 0x38, 0x06, 0x24, 0x31, 0xa2, 0x78, 0xf2,
6165         0x53, 0x07, 0x36, 0xfe, 0x34, 0xf4, 0x3f, 0xa1, 0x78, 0x03, 0x9a, 0x1e,
6166         0x83, 0x01, 0x38, 0x06, 0x12, 0x31, 0xf0, 0x4f, 0x45, 0xfe, 0x90, 0x10,
6167         0xfe, 0x40, 0x5a, 0x23, 0x3f, 0xfb, 0x8c, 0x49, 0x48, 0xfe, 0xaa, 0x18,
6168         0x62, 0x49, 0x71, 0x8c, 0x80, 0x48, 0xfe, 0xaa, 0x18, 0x62, 0x80, 0xfe,
6169         0xb4, 0x56, 0xfe, 0x40, 0x5d, 0x01, 0xc6, 0x01, 0xfe, 0xac, 0x1d, 0xfe,
6170         0x02, 0x17, 0xfe, 0xc8, 0x45, 0xfe, 0x5a, 0xf0, 0xfe, 0xc0, 0x18, 0xfe,
6171         0x43, 0x48, 0x2d, 0x93, 0x36, 0xfe, 0x34, 0xf4, 0xfe, 0x00, 0x11, 0xfe,
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6173         0x2d, 0xfe, 0x0b, 0x00, 0x36, 0x46, 0x63, 0xfe, 0x28, 0x10, 0xfe, 0xc0,
6174         0x49, 0xff, 0x02, 0x00, 0x54, 0xb2, 0xfe, 0x90, 0x01, 0x48, 0xfe, 0xfa,
6175         0x18, 0x45, 0xfe, 0x1c, 0xf4, 0x3f, 0xf3, 0xfe, 0x40, 0xf4, 0x96, 0xfe,
6176         0x56, 0xf0, 0xfe, 0x0c, 0x19, 0xfe, 0x04, 0xf4, 0x58, 0xfe, 0x40, 0xf4,
6177         0x94, 0xf6, 0x3e, 0x2d, 0x93, 0x4e, 0xd0, 0x0d, 0x21, 0xfe, 0x7f, 0x01,
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6179         0x7e, 0x01, 0xfe, 0xc8, 0x45, 0xfe, 0x14, 0x13, 0x21, 0xfe, 0x80, 0x01,
6180         0xfe, 0x48, 0x45, 0xfa, 0x21, 0xfe, 0x81, 0x01, 0xfe, 0xc8, 0x44, 0x4e,
6181         0x26, 0x02, 0x13, 0x07, 0x02, 0x78, 0x45, 0x50, 0x13, 0x0d, 0x02, 0x14,
6182         0x07, 0x01, 0x08, 0x17, 0xfe, 0x82, 0x19, 0x14, 0x0d, 0x01, 0x08, 0x17,
6183         0xfe, 0x82, 0x19, 0x14, 0x1d, 0x01, 0x08, 0x17, 0xfe, 0x82, 0x19, 0x5f,
6184         0xfe, 0x89, 0x49, 0x01, 0x08, 0x02, 0x14, 0x07, 0x01, 0x08, 0x17, 0xc1,
6185         0x14, 0x1d, 0x01, 0x08, 0x17, 0xc1, 0x14, 0x07, 0x01, 0x08, 0x17, 0xc1,
6186         0xfe, 0x89, 0x49, 0x01, 0x08, 0x17, 0xc1, 0x5f, 0xfe, 0x89, 0x4a, 0x01,
6187         0x08, 0x02, 0x50, 0x02, 0x14, 0x07, 0x01, 0x08, 0x17, 0x74, 0x14, 0x7f,
6188         0x01, 0x08, 0x17, 0x74, 0x14, 0x12, 0x01, 0x08, 0x17, 0x74, 0xfe, 0x89,
6189         0x49, 0x01, 0x08, 0x17, 0x74, 0x14, 0x00, 0x01, 0x08, 0x17, 0x74, 0xfe,
6190         0x89, 0x4a, 0x01, 0x08, 0x17, 0x74, 0xfe, 0x09, 0x49, 0x01, 0x08, 0x17,
6191         0x74, 0x5f, 0xcc, 0x01, 0x08, 0x02, 0x21, 0xe4, 0x09, 0x07, 0xfe, 0x4c,
6192         0x13, 0xc8, 0x20, 0xe4, 0xfe, 0x49, 0xf4, 0x00, 0x4d, 0x5f, 0xa1, 0x5e,
6193         0xfe, 0x01, 0xec, 0xfe, 0x27, 0x01, 0xcc, 0xff, 0x02, 0x00, 0x10, 0x2f,
6194         0xfe, 0x3e, 0x1a, 0x01, 0x43, 0x09, 0xfe, 0xe3, 0x00, 0xfe, 0x22, 0x13,
6195         0x16, 0xfe, 0x64, 0x1a, 0x26, 0x20, 0x9e, 0x01, 0x41, 0x21, 0x9e, 0x09,
6196         0x07, 0x5d, 0x01, 0x0c, 0x61, 0x07, 0x44, 0x02, 0x0a, 0x5a, 0x01, 0x18,
6197         0xfe, 0x00, 0x40, 0xaa, 0x09, 0x1a, 0xfe, 0x12, 0x13, 0x0a, 0x9d, 0x01,
6198         0x18, 0xaa, 0x0a, 0x67, 0x01, 0xa3, 0x02, 0x0a, 0x9d, 0x01, 0x18, 0xaa,
6199         0xfe, 0x80, 0xe7, 0x1a, 0x09, 0x1a, 0x5d, 0xfe, 0x45, 0x58, 0x01, 0xfe,
6200         0xb2, 0x16, 0xaa, 0x02, 0x0a, 0x5a, 0x01, 0x18, 0xaa, 0x0a, 0x67, 0x01,
6201         0xa3, 0x02, 0x0a, 0x5a, 0x01, 0x18, 0x01, 0xfe, 0x7e, 0x1e, 0xfe, 0x80,
6202         0x4c, 0xfe, 0x49, 0xe4, 0x1a, 0xfe, 0x12, 0x13, 0x0a, 0x9d, 0x01, 0x18,
6203         0xfe, 0x80, 0x4c, 0x0a, 0x67, 0x01, 0x5c, 0x02, 0x1c, 0x1a, 0x87, 0x7c,
6204         0xe5, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x24, 0x1c, 0xfe, 0x1d,
6205         0xf7, 0x28, 0xb1, 0xfe, 0x04, 0x1b, 0x01, 0xfe, 0x2a, 0x1c, 0xfa, 0xb3,
6206         0x28, 0x7c, 0xfe, 0x2c, 0x01, 0xfe, 0x2f, 0x19, 0x02, 0xc9, 0x2b, 0xfe,
6207         0xf4, 0x1a, 0xfe, 0xfa, 0x10, 0x1c, 0x1a, 0x87, 0x03, 0xfe, 0x64, 0x01,
6208         0xfe, 0x00, 0xf4, 0x24, 0xfe, 0x18, 0x58, 0x03, 0xfe, 0x66, 0x01, 0xfe,
6209         0x19, 0x58, 0xb3, 0x24, 0x01, 0xfe, 0x0e, 0x1f, 0xfe, 0x30, 0xf4, 0x07,
6210         0xfe, 0x3c, 0x50, 0x7c, 0xfe, 0x38, 0x00, 0xfe, 0x0f, 0x79, 0xfe, 0x1c,
6211         0xf7, 0x24, 0xb1, 0xfe, 0x50, 0x1b, 0xfe, 0xd4, 0x14, 0x31, 0x02, 0xc9,
6212         0x2b, 0xfe, 0x26, 0x1b, 0xfe, 0xba, 0x10, 0x1c, 0x1a, 0x87, 0xfe, 0x83,
6213         0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x1d, 0xf7, 0x54, 0xb1,
6214         0xfe, 0x72, 0x1b, 0xfe, 0xb2, 0x14, 0xfc, 0xb3, 0x54, 0x7c, 0x12, 0xfe,
6215         0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00, 0x02, 0xc9, 0x2b, 0xfe, 0x66, 0x1b,
6216         0xfe, 0x8a, 0x10, 0x1c, 0x1a, 0x87, 0x8b, 0x0f, 0xfe, 0x30, 0x90, 0x04,
6217         0xfe, 0xb0, 0x93, 0x3a, 0x0b, 0xfe, 0x18, 0x58, 0xfe, 0x32, 0x90, 0x04,
6218         0xfe, 0xb2, 0x93, 0x3a, 0x0b, 0xfe, 0x19, 0x58, 0x0e, 0xa8, 0xb3, 0x4a,
6219         0x7c, 0x12, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0x4a, 0xb1, 0xfe, 0xc6,
6220         0x1b, 0xfe, 0x5e, 0x14, 0x31, 0x02, 0xc9, 0x2b, 0xfe, 0x96, 0x1b, 0x5c,
6221         0xfe, 0x02, 0xf6, 0x1a, 0x87, 0xfe, 0x18, 0xfe, 0x6a, 0xfe, 0x19, 0xfe,
6222         0x6b, 0x01, 0xfe, 0x1e, 0x1f, 0xfe, 0x1d, 0xf7, 0x65, 0xb1, 0xfe, 0xee,
6223         0x1b, 0xfe, 0x36, 0x14, 0xfe, 0x1c, 0x13, 0xb3, 0x65, 0x3e, 0xfe, 0x83,
6224         0x58, 0xfe, 0xaf, 0x19, 0xfe, 0x80, 0xe7, 0x1a, 0xfe, 0x81, 0xe7, 0x1a,
6225         0x15, 0xfe, 0xdd, 0x00, 0x7a, 0x30, 0x02, 0x7a, 0x30, 0xfe, 0x12, 0x45,
6226         0x2b, 0xfe, 0xdc, 0x1b, 0x1f, 0x07, 0x47, 0xb5, 0xc3, 0x05, 0x35, 0xfe,
6227         0x39, 0xf0, 0x75, 0x26, 0x02, 0xfe, 0x7e, 0x18, 0x23, 0x1d, 0x36, 0x13,
6228         0x11, 0x02, 0x87, 0x03, 0xe3, 0x23, 0x07, 0xfe, 0xef, 0x12, 0xfe, 0xe1,
6229         0x10, 0x90, 0x34, 0x60, 0xfe, 0x02, 0x80, 0x09, 0x56, 0xfe, 0x3c, 0x13,
6230         0xfe, 0x82, 0x14, 0xfe, 0x42, 0x13, 0x51, 0xfe, 0x06, 0x83, 0x0a, 0x5a,
6231         0x01, 0x18, 0xcb, 0xfe, 0x3e, 0x12, 0xfe, 0x41, 0x48, 0xfe, 0x45, 0x48,
6232         0x01, 0xfe, 0xb2, 0x16, 0xfe, 0x00, 0xcc, 0xcb, 0xfe, 0xf3, 0x13, 0x3f,
6233         0x89, 0x09, 0x1a, 0xa5, 0x0a, 0x9d, 0x01, 0x18, 0xfe, 0x80, 0x4c, 0x01,
6234         0x85, 0xfe, 0x16, 0x10, 0x09, 0x9b, 0x4e, 0xfe, 0x40, 0x14, 0xfe, 0x24,
6235         0x12, 0xfe, 0x14, 0x56, 0xfe, 0xd6, 0xf0, 0xfe, 0x52, 0x1c, 0x1c, 0x0d,
6236         0x02, 0xfe, 0x9c, 0xe7, 0x0d, 0x19, 0xfe, 0x15, 0x00, 0x40, 0x8d, 0x30,
6237         0x01, 0xf4, 0x1c, 0x07, 0x02, 0x51, 0xfe, 0x06, 0x83, 0xfe, 0x18, 0x80,
6238         0x61, 0x28, 0x44, 0x15, 0x56, 0x01, 0x85, 0x1c, 0x07, 0x02, 0xfe, 0x38,
6239         0x90, 0xfe, 0xba, 0x90, 0x91, 0xde, 0x7e, 0xdf, 0xfe, 0x48, 0x55, 0x31,
6240         0xfe, 0xc9, 0x55, 0x02, 0x21, 0xb9, 0x88, 0x20, 0xb9, 0x02, 0x0a, 0xba,
6241         0x01, 0x18, 0xfe, 0x41, 0x48, 0x0a, 0x57, 0x01, 0x18, 0xfe, 0x49, 0x44,
6242         0x1b, 0xfe, 0x1e, 0x1d, 0x88, 0x89, 0x02, 0x0a, 0x5a, 0x01, 0x18, 0x09,
6243         0x1a, 0xa4, 0x0a, 0x67, 0x01, 0xa3, 0x0a, 0x57, 0x01, 0x18, 0x88, 0x89,
6244         0x02, 0xfe, 0x4e, 0xe4, 0x1d, 0x7b, 0xfe, 0x52, 0x1d, 0x03, 0xfe, 0x90,
6245         0x00, 0xfe, 0x3a, 0x45, 0xfe, 0x2c, 0x10, 0xfe, 0x4e, 0xe4, 0xdd, 0x7b,
6246         0xfe, 0x64, 0x1d, 0x03, 0xfe, 0x92, 0x00, 0xd1, 0x12, 0xfe, 0x1a, 0x10,
6247         0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x7b, 0xfe, 0x76, 0x1d, 0x03, 0xfe,
6248         0x94, 0x00, 0xd1, 0x24, 0xfe, 0x08, 0x10, 0x03, 0xfe, 0x96, 0x00, 0xd1,
6249         0x63, 0xfe, 0x4e, 0x45, 0x83, 0xca, 0xff, 0x04, 0x68, 0x54, 0xfe, 0xf1,
6250         0x10, 0x23, 0x49, 0xfe, 0x08, 0x1c, 0xfe, 0x67, 0x19, 0xfe, 0x0a, 0x1c,
6251         0xfe, 0x1a, 0xf4, 0xfe, 0x00, 0x04, 0x83, 0xb2, 0x1d, 0x48, 0xfe, 0xaa,
6252         0x1d, 0x13, 0x1d, 0x02, 0x09, 0x92, 0xfe, 0x5a, 0xf0, 0xfe, 0xba, 0x1d,
6253         0x2e, 0x93, 0xfe, 0x34, 0x10, 0x09, 0x12, 0xfe, 0x5a, 0xf0, 0xfe, 0xc8,
6254         0x1d, 0x2e, 0xb4, 0xfe, 0x26, 0x10, 0x09, 0x1d, 0x36, 0x2e, 0x63, 0xfe,
6255         0x1a, 0x10, 0x09, 0x0d, 0x36, 0x2e, 0x94, 0xf2, 0x09, 0x07, 0x36, 0x2e,
6256         0x95, 0xa1, 0xc8, 0x02, 0x1f, 0x93, 0x01, 0x42, 0xfe, 0x04, 0xfe, 0x99,
6257         0x03, 0x9c, 0x8b, 0x02, 0x2a, 0xfe, 0x1c, 0x1e, 0xfe, 0x14, 0xf0, 0x08,
6258         0x2f, 0xfe, 0x0c, 0x1e, 0x2a, 0xfe, 0x1c, 0x1e, 0x8f, 0xfe, 0x1c, 0x1e,
6259         0xfe, 0x82, 0xf0, 0xfe, 0x10, 0x1e, 0x02, 0x0f, 0x3f, 0x04, 0xfe, 0x80,
6260         0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x18, 0x80, 0x04, 0xfe, 0x98,
6261         0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x02, 0x80, 0x04, 0xfe, 0x82,
6262         0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06, 0x80, 0x04, 0xfe, 0x86,
6263         0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x1b, 0x80, 0x04, 0xfe, 0x9b,
6264         0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x04, 0x80, 0x04, 0xfe, 0x84,
6265         0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x80, 0x80, 0x04, 0xfe, 0x80,
6266         0x83, 0xfe, 0xc9, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x19, 0x81, 0x04,
6267         0xfe, 0x99, 0x83, 0xfe, 0xca, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06,
6268         0x83, 0x04, 0xfe, 0x86, 0x83, 0xfe, 0xce, 0x47, 0x0b, 0x0e, 0x02, 0x0f,
6269         0xfe, 0x2c, 0x90, 0x04, 0xfe, 0xac, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
6270         0xfe, 0xae, 0x90, 0x04, 0xfe, 0xae, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f,
6271         0xfe, 0x08, 0x90, 0x04, 0xfe, 0x88, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
6272         0xfe, 0x8a, 0x90, 0x04, 0xfe, 0x8a, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f,
6273         0xfe, 0x0c, 0x90, 0x04, 0xfe, 0x8c, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
6274         0xfe, 0x8e, 0x90, 0x04, 0xfe, 0x8e, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f,
6275         0xfe, 0x3c, 0x90, 0x04, 0xfe, 0xbc, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x8b,
6276         0x0f, 0xfe, 0x03, 0x80, 0x04, 0xfe, 0x83, 0x83, 0x33, 0x0b, 0x77, 0x0e,
6277         0xa8, 0x02, 0xff, 0x66, 0x00, 0x00,
6278 };
6279
6280 static unsigned short _adv_asc38C1600_size = sizeof(_adv_asc38C1600_buf);       /* 0x1673 */
6281 static ADV_DCNT _adv_asc38C1600_chksum = 0x0604EF77UL;  /* Expanded little-endian checksum. */
6282
6283 static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc)
6284 {
6285         PortAddr iop_base;
6286         int i;
6287         ushort lram_addr;
6288
6289         iop_base = asc_dvc->iop_base;
6290         AscPutRiscVarFreeQHead(iop_base, 1);
6291         AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
6292         AscPutVarFreeQHead(iop_base, 1);
6293         AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
6294         AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
6295                          (uchar)((int)asc_dvc->max_total_qng + 1));
6296         AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
6297                          (uchar)((int)asc_dvc->max_total_qng + 2));
6298         AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B,
6299                          asc_dvc->max_total_qng);
6300         AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
6301         AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6302         AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
6303         AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
6304         AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
6305         AscPutQDoneInProgress(iop_base, 0);
6306         lram_addr = ASC_QADR_BEG;
6307         for (i = 0; i < 32; i++, lram_addr += 2) {
6308                 AscWriteLramWord(iop_base, lram_addr, 0);
6309         }
6310 }
6311
6312 static ushort AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc)
6313 {
6314         int i;
6315         ushort warn_code;
6316         PortAddr iop_base;
6317         ASC_PADDR phy_addr;
6318         ASC_DCNT phy_size;
6319
6320         iop_base = asc_dvc->iop_base;
6321         warn_code = 0;
6322         for (i = 0; i <= ASC_MAX_TID; i++) {
6323                 AscPutMCodeInitSDTRAtID(iop_base, i,
6324                                         asc_dvc->cfg->sdtr_period_offset[i]);
6325         }
6326
6327         AscInitQLinkVar(asc_dvc);
6328         AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
6329                          asc_dvc->cfg->disc_enable);
6330         AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
6331                          ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
6332
6333         /* Align overrun buffer on an 8 byte boundary. */
6334         phy_addr = virt_to_bus(asc_dvc->cfg->overrun_buf);
6335         phy_addr = cpu_to_le32((phy_addr + 7) & ~0x7);
6336         AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
6337                                  (uchar *)&phy_addr, 1);
6338         phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE - 8);
6339         AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
6340                                  (uchar *)&phy_size, 1);
6341
6342         asc_dvc->cfg->mcode_date =
6343             AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W);
6344         asc_dvc->cfg->mcode_version =
6345             AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W);
6346
6347         AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
6348         if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
6349                 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
6350                 return warn_code;
6351         }
6352         if (AscStartChip(iop_base) != 1) {
6353                 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
6354                 return warn_code;
6355         }
6356
6357         return warn_code;
6358 }
6359
6360 static ushort AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc)
6361 {
6362         ushort warn_code;
6363         PortAddr iop_base;
6364
6365         iop_base = asc_dvc->iop_base;
6366         warn_code = 0;
6367         if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
6368             !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
6369                 AscResetChipAndScsiBus(asc_dvc);
6370                 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
6371         }
6372         asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
6373         if (asc_dvc->err_code != 0)
6374                 return UW_ERR;
6375         if (!AscFindSignature(asc_dvc->iop_base)) {
6376                 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
6377                 return warn_code;
6378         }
6379         AscDisableInterrupt(iop_base);
6380         warn_code |= AscInitLram(asc_dvc);
6381         if (asc_dvc->err_code != 0)
6382                 return UW_ERR;
6383         ASC_DBG(1, "_asc_mcode_chksum 0x%lx\n", (ulong)_asc_mcode_chksum);
6384         if (AscLoadMicroCode(iop_base, 0, _asc_mcode_buf,
6385                              _asc_mcode_size) != _asc_mcode_chksum) {
6386                 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
6387                 return warn_code;
6388         }
6389         warn_code |= AscInitMicroCodeVar(asc_dvc);
6390         asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
6391         AscEnableInterrupt(iop_base);
6392         return warn_code;
6393 }
6394
6395 /*
6396  * Load the Microcode
6397  *
6398  * Write the microcode image to RISC memory starting at address 0.
6399  *
6400  * The microcode is stored compressed in the following format:
6401  *
6402  *  254 word (508 byte) table indexed by byte code followed
6403  *  by the following byte codes:
6404  *
6405  *    1-Byte Code:
6406  *      00: Emit word 0 in table.
6407  *      01: Emit word 1 in table.
6408  *      .
6409  *      FD: Emit word 253 in table.
6410  *
6411  *    Multi-Byte Code:
6412  *      FE WW WW: (3 byte code) Word to emit is the next word WW WW.
6413  *      FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
6414  *
6415  * Returns 0 or an error if the checksum doesn't match
6416  */
6417 static int AdvLoadMicrocode(AdvPortAddr iop_base, unsigned char *buf, int size,
6418                             int memsize, int chksum)
6419 {
6420         int i, j, end, len = 0;
6421         ADV_DCNT sum;
6422
6423         AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
6424
6425         for (i = 253 * 2; i < size; i++) {
6426                 if (buf[i] == 0xff) {
6427                         unsigned short word = (buf[i + 3] << 8) | buf[i + 2];
6428                         for (j = 0; j < buf[i + 1]; j++) {
6429                                 AdvWriteWordAutoIncLram(iop_base, word);
6430                                 len += 2;
6431                         }
6432                         i += 3;
6433                 } else if (buf[i] == 0xfe) {
6434                         unsigned short word = (buf[i + 2] << 8) | buf[i + 1];
6435                         AdvWriteWordAutoIncLram(iop_base, word);
6436                         i += 2;
6437                         len += 2;
6438                 } else {
6439                         unsigned char off = buf[i] * 2;
6440                         unsigned short word = (buf[off + 1] << 8) | buf[off];
6441                         AdvWriteWordAutoIncLram(iop_base, word);
6442                         len += 2;
6443                 }
6444         }
6445
6446         end = len;
6447
6448         while (len < memsize) {
6449                 AdvWriteWordAutoIncLram(iop_base, 0);
6450                 len += 2;
6451         }
6452
6453         /* Verify the microcode checksum. */
6454         sum = 0;
6455         AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
6456
6457         for (len = 0; len < end; len += 2) {
6458                 sum += AdvReadWordAutoIncLram(iop_base);
6459         }
6460
6461         if (sum != chksum)
6462                 return ASC_IERR_MCODE_CHKSUM;
6463
6464         return 0;
6465 }
6466
6467 static void AdvBuildCarrierFreelist(struct adv_dvc_var *asc_dvc)
6468 {
6469         ADV_CARR_T *carrp;
6470         ADV_SDCNT buf_size;
6471         ADV_PADDR carr_paddr;
6472
6473         carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
6474         asc_dvc->carr_freelist = NULL;
6475         if (carrp == asc_dvc->carrier_buf) {
6476                 buf_size = ADV_CARRIER_BUFSIZE;
6477         } else {
6478                 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
6479         }
6480
6481         do {
6482                 /* Get physical address of the carrier 'carrp'. */
6483                 carr_paddr = cpu_to_le32(virt_to_bus(carrp));
6484
6485                 buf_size -= sizeof(ADV_CARR_T);
6486
6487                 carrp->carr_pa = carr_paddr;
6488                 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
6489
6490                 /*
6491                  * Insert the carrier at the beginning of the freelist.
6492                  */
6493                 carrp->next_vpa =
6494                         cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
6495                 asc_dvc->carr_freelist = carrp;
6496
6497                 carrp++;
6498         } while (buf_size > 0);
6499 }
6500
6501 /*
6502  * Send an idle command to the chip and wait for completion.
6503  *
6504  * Command completion is polled for once per microsecond.
6505  *
6506  * The function can be called from anywhere including an interrupt handler.
6507  * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
6508  * functions to prevent reentrancy.
6509  *
6510  * Return Values:
6511  *   ADV_TRUE - command completed successfully
6512  *   ADV_FALSE - command failed
6513  *   ADV_ERROR - command timed out
6514  */
6515 static int
6516 AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
6517                ushort idle_cmd, ADV_DCNT idle_cmd_parameter)
6518 {
6519         int result;
6520         ADV_DCNT i, j;
6521         AdvPortAddr iop_base;
6522
6523         iop_base = asc_dvc->iop_base;
6524
6525         /*
6526          * Clear the idle command status which is set by the microcode
6527          * to a non-zero value to indicate when the command is completed.
6528          * The non-zero result is one of the IDLE_CMD_STATUS_* values
6529          */
6530         AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0);
6531
6532         /*
6533          * Write the idle command value after the idle command parameter
6534          * has been written to avoid a race condition. If the order is not
6535          * followed, the microcode may process the idle command before the
6536          * parameters have been written to LRAM.
6537          */
6538         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
6539                                 cpu_to_le32(idle_cmd_parameter));
6540         AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
6541
6542         /*
6543          * Tickle the RISC to tell it to process the idle command.
6544          */
6545         AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
6546         if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
6547                 /*
6548                  * Clear the tickle value. In the ASC-3550 the RISC flag
6549                  * command 'clr_tickle_b' does not work unless the host
6550                  * value is cleared.
6551                  */
6552                 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
6553         }
6554
6555         /* Wait for up to 100 millisecond for the idle command to timeout. */
6556         for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
6557                 /* Poll once each microsecond for command completion. */
6558                 for (j = 0; j < SCSI_US_PER_MSEC; j++) {
6559                         AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS,
6560                                         result);
6561                         if (result != 0)
6562                                 return result;
6563                         udelay(1);
6564                 }
6565         }
6566
6567         BUG();          /* The idle command should never timeout. */
6568         return ADV_ERROR;
6569 }
6570
6571 /*
6572  * Reset SCSI Bus and purge all outstanding requests.
6573  *
6574  * Return Value:
6575  *      ADV_TRUE(1) -   All requests are purged and SCSI Bus is reset.
6576  *      ADV_FALSE(0) -  Microcode command failed.
6577  *      ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
6578  *                      may be hung which requires driver recovery.
6579  */
6580 static int AdvResetSB(ADV_DVC_VAR *asc_dvc)
6581 {
6582         int status;
6583
6584         /*
6585          * Send the SCSI Bus Reset idle start idle command which asserts
6586          * the SCSI Bus Reset signal.
6587          */
6588         status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L);
6589         if (status != ADV_TRUE) {
6590                 return status;
6591         }
6592
6593         /*
6594          * Delay for the specified SCSI Bus Reset hold time.
6595          *
6596          * The hold time delay is done on the host because the RISC has no
6597          * microsecond accurate timer.
6598          */
6599         udelay(ASC_SCSI_RESET_HOLD_TIME_US);
6600
6601         /*
6602          * Send the SCSI Bus Reset end idle command which de-asserts
6603          * the SCSI Bus Reset signal and purges any pending requests.
6604          */
6605         status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L);
6606         if (status != ADV_TRUE) {
6607                 return status;
6608         }
6609
6610         mdelay(asc_dvc->scsi_reset_wait * 1000);        /* XXX: msleep? */
6611
6612         return status;
6613 }
6614
6615 /*
6616  * Initialize the ASC-3550.
6617  *
6618  * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
6619  *
6620  * For a non-fatal error return a warning code. If there are no warnings
6621  * then 0 is returned.
6622  *
6623  * Needed after initialization for error recovery.
6624  */
6625 static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
6626 {
6627         AdvPortAddr iop_base;
6628         ushort warn_code;
6629         int begin_addr;
6630         int end_addr;
6631         ushort code_sum;
6632         int word;
6633         int i;
6634         ushort scsi_cfg1;
6635         uchar tid;
6636         ushort bios_mem[ASC_MC_BIOSLEN / 2];    /* BIOS RISC Memory 0x40-0x8F. */
6637         ushort wdtr_able = 0, sdtr_able, tagqng_able;
6638         uchar max_cmd[ADV_MAX_TID + 1];
6639
6640         /* If there is already an error, don't continue. */
6641         if (asc_dvc->err_code != 0)
6642                 return ADV_ERROR;
6643
6644         /*
6645          * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
6646          */
6647         if (asc_dvc->chip_type != ADV_CHIP_ASC3550) {
6648                 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
6649                 return ADV_ERROR;
6650         }
6651
6652         warn_code = 0;
6653         iop_base = asc_dvc->iop_base;
6654
6655         /*
6656          * Save the RISC memory BIOS region before writing the microcode.
6657          * The BIOS may already be loaded and using its RISC LRAM region
6658          * so its region must be saved and restored.
6659          *
6660          * Note: This code makes the assumption, which is currently true,
6661          * that a chip reset does not clear RISC LRAM.
6662          */
6663         for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
6664                 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
6665                                 bios_mem[i]);
6666         }
6667
6668         /*
6669          * Save current per TID negotiated values.
6670          */
6671         if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) {
6672                 ushort bios_version, major, minor;
6673
6674                 bios_version =
6675                     bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2];
6676                 major = (bios_version >> 12) & 0xF;
6677                 minor = (bios_version >> 8) & 0xF;
6678                 if (major < 3 || (major == 3 && minor == 1)) {
6679                         /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
6680                         AdvReadWordLram(iop_base, 0x120, wdtr_able);
6681                 } else {
6682                         AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
6683                 }
6684         }
6685         AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
6686         AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
6687         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
6688                 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
6689                                 max_cmd[tid]);
6690         }
6691
6692         asc_dvc->err_code = AdvLoadMicrocode(iop_base, _adv_asc3550_buf,
6693                                         _adv_asc3550_size, ADV_3550_MEMSIZE,
6694                                         _adv_asc3550_chksum);
6695         if (asc_dvc->err_code)
6696                 return ADV_ERROR;
6697
6698         /*
6699          * Restore the RISC memory BIOS region.
6700          */
6701         for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
6702                 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
6703                                  bios_mem[i]);
6704         }
6705
6706         /*
6707          * Calculate and write the microcode code checksum to the microcode
6708          * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
6709          */
6710         AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
6711         AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
6712         code_sum = 0;
6713         AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
6714         for (word = begin_addr; word < end_addr; word += 2) {
6715                 code_sum += AdvReadWordAutoIncLram(iop_base);
6716         }
6717         AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
6718
6719         /*
6720          * Read and save microcode version and date.
6721          */
6722         AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
6723                         asc_dvc->cfg->mcode_date);
6724         AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
6725                         asc_dvc->cfg->mcode_version);
6726
6727         /*
6728          * Set the chip type to indicate the ASC3550.
6729          */
6730         AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
6731
6732         /*
6733          * If the PCI Configuration Command Register "Parity Error Response
6734          * Control" Bit was clear (0), then set the microcode variable
6735          * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
6736          * to ignore DMA parity errors.
6737          */
6738         if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
6739                 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
6740                 word |= CONTROL_FLAG_IGNORE_PERR;
6741                 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
6742         }
6743
6744         /*
6745          * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
6746          * threshold of 128 bytes. This register is only accessible to the host.
6747          */
6748         AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
6749                              START_CTL_EMFU | READ_CMD_MRM);
6750
6751         /*
6752          * Microcode operating variables for WDTR, SDTR, and command tag
6753          * queuing will be set in slave_configure() based on what a
6754          * device reports it is capable of in Inquiry byte 7.
6755          *
6756          * If SCSI Bus Resets have been disabled, then directly set
6757          * SDTR and WDTR from the EEPROM configuration. This will allow
6758          * the BIOS and warm boot to work without a SCSI bus hang on
6759          * the Inquiry caused by host and target mismatched DTR values.
6760          * Without the SCSI Bus Reset, before an Inquiry a device can't
6761          * be assumed to be in Asynchronous, Narrow mode.
6762          */
6763         if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
6764                 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
6765                                  asc_dvc->wdtr_able);
6766                 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
6767                                  asc_dvc->sdtr_able);
6768         }
6769
6770         /*
6771          * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
6772          * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
6773          * bitmask. These values determine the maximum SDTR speed negotiated
6774          * with a device.
6775          *
6776          * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
6777          * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
6778          * without determining here whether the device supports SDTR.
6779          *
6780          * 4-bit speed  SDTR speed name
6781          * ===========  ===============
6782          * 0000b (0x0)  SDTR disabled
6783          * 0001b (0x1)  5 Mhz
6784          * 0010b (0x2)  10 Mhz
6785          * 0011b (0x3)  20 Mhz (Ultra)
6786          * 0100b (0x4)  40 Mhz (LVD/Ultra2)
6787          * 0101b (0x5)  80 Mhz (LVD2/Ultra3)
6788          * 0110b (0x6)  Undefined
6789          * .
6790          * 1111b (0xF)  Undefined
6791          */
6792         word = 0;
6793         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
6794                 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) {
6795                         /* Set Ultra speed for TID 'tid'. */
6796                         word |= (0x3 << (4 * (tid % 4)));
6797                 } else {
6798                         /* Set Fast speed for TID 'tid'. */
6799                         word |= (0x2 << (4 * (tid % 4)));
6800                 }
6801                 if (tid == 3) { /* Check if done with sdtr_speed1. */
6802                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
6803                         word = 0;
6804                 } else if (tid == 7) {  /* Check if done with sdtr_speed2. */
6805                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
6806                         word = 0;
6807                 } else if (tid == 11) { /* Check if done with sdtr_speed3. */
6808                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
6809                         word = 0;
6810                 } else if (tid == 15) { /* Check if done with sdtr_speed4. */
6811                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
6812                         /* End of loop. */
6813                 }
6814         }
6815
6816         /*
6817          * Set microcode operating variable for the disconnect per TID bitmask.
6818          */
6819         AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
6820                          asc_dvc->cfg->disc_enable);
6821
6822         /*
6823          * Set SCSI_CFG0 Microcode Default Value.
6824          *
6825          * The microcode will set the SCSI_CFG0 register using this value
6826          * after it is started below.
6827          */
6828         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
6829                          PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
6830                          asc_dvc->chip_scsi_id);
6831
6832         /*
6833          * Determine SCSI_CFG1 Microcode Default Value.
6834          *
6835          * The microcode will set the SCSI_CFG1 register using this value
6836          * after it is started below.
6837          */
6838
6839         /* Read current SCSI_CFG1 Register value. */
6840         scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
6841
6842         /*
6843          * If all three connectors are in use, return an error.
6844          */
6845         if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
6846             (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
6847                 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
6848                 return ADV_ERROR;
6849         }
6850
6851         /*
6852          * If the internal narrow cable is reversed all of the SCSI_CTRL
6853          * register signals will be set. Check for and return an error if
6854          * this condition is found.
6855          */
6856         if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
6857                 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
6858                 return ADV_ERROR;
6859         }
6860
6861         /*
6862          * If this is a differential board and a single-ended device
6863          * is attached to one of the connectors, return an error.
6864          */
6865         if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) {
6866                 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
6867                 return ADV_ERROR;
6868         }
6869
6870         /*
6871          * If automatic termination control is enabled, then set the
6872          * termination value based on a table listed in a_condor.h.
6873          *
6874          * If manual termination was specified with an EEPROM setting
6875          * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
6876          * is ready to be 'ored' into SCSI_CFG1.
6877          */
6878         if (asc_dvc->cfg->termination == 0) {
6879                 /*
6880                  * The software always controls termination by setting TERM_CTL_SEL.
6881                  * If TERM_CTL_SEL were set to 0, the hardware would set termination.
6882                  */
6883                 asc_dvc->cfg->termination |= TERM_CTL_SEL;
6884
6885                 switch (scsi_cfg1 & CABLE_DETECT) {
6886                         /* TERM_CTL_H: on, TERM_CTL_L: on */
6887                 case 0x3:
6888                 case 0x7:
6889                 case 0xB:
6890                 case 0xD:
6891                 case 0xE:
6892                 case 0xF:
6893                         asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
6894                         break;
6895
6896                         /* TERM_CTL_H: on, TERM_CTL_L: off */
6897                 case 0x1:
6898                 case 0x5:
6899                 case 0x9:
6900                 case 0xA:
6901                 case 0xC:
6902                         asc_dvc->cfg->termination |= TERM_CTL_H;
6903                         break;
6904
6905                         /* TERM_CTL_H: off, TERM_CTL_L: off */
6906                 case 0x2:
6907                 case 0x6:
6908                         break;
6909                 }
6910         }
6911
6912         /*
6913          * Clear any set TERM_CTL_H and TERM_CTL_L bits.
6914          */
6915         scsi_cfg1 &= ~TERM_CTL;
6916
6917         /*
6918          * Invert the TERM_CTL_H and TERM_CTL_L bits and then
6919          * set 'scsi_cfg1'. The TERM_POL bit does not need to be
6920          * referenced, because the hardware internally inverts
6921          * the Termination High and Low bits if TERM_POL is set.
6922          */
6923         scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
6924
6925         /*
6926          * Set SCSI_CFG1 Microcode Default Value
6927          *
6928          * Set filter value and possibly modified termination control
6929          * bits in the Microcode SCSI_CFG1 Register Value.
6930          *
6931          * The microcode will set the SCSI_CFG1 register using this value
6932          * after it is started below.
6933          */
6934         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
6935                          FLTR_DISABLE | scsi_cfg1);
6936
6937         /*
6938          * Set MEM_CFG Microcode Default Value
6939          *
6940          * The microcode will set the MEM_CFG register using this value
6941          * after it is started below.
6942          *
6943          * MEM_CFG may be accessed as a word or byte, but only bits 0-7
6944          * are defined.
6945          *
6946          * ASC-3550 has 8KB internal memory.
6947          */
6948         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
6949                          BIOS_EN | RAM_SZ_8KB);
6950
6951         /*
6952          * Set SEL_MASK Microcode Default Value
6953          *
6954          * The microcode will set the SEL_MASK register using this value
6955          * after it is started below.
6956          */
6957         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
6958                          ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
6959
6960         AdvBuildCarrierFreelist(asc_dvc);
6961
6962         /*
6963          * Set-up the Host->RISC Initiator Command Queue (ICQ).
6964          */
6965
6966         if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
6967                 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
6968                 return ADV_ERROR;
6969         }
6970         asc_dvc->carr_freelist = (ADV_CARR_T *)
6971             ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
6972
6973         /*
6974          * The first command issued will be placed in the stopper carrier.
6975          */
6976         asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
6977
6978         /*
6979          * Set RISC ICQ physical address start value.
6980          */
6981         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
6982
6983         /*
6984          * Set-up the RISC->Host Initiator Response Queue (IRQ).
6985          */
6986         if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
6987                 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
6988                 return ADV_ERROR;
6989         }
6990         asc_dvc->carr_freelist = (ADV_CARR_T *)
6991             ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
6992
6993         /*
6994          * The first command completed by the RISC will be placed in
6995          * the stopper.
6996          *
6997          * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
6998          * completed the RISC will set the ASC_RQ_STOPPER bit.
6999          */
7000         asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
7001
7002         /*
7003          * Set RISC IRQ physical address start value.
7004          */
7005         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
7006         asc_dvc->carr_pending_cnt = 0;
7007
7008         AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
7009                              (ADV_INTR_ENABLE_HOST_INTR |
7010                               ADV_INTR_ENABLE_GLOBAL_INTR));
7011
7012         AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
7013         AdvWriteWordRegister(iop_base, IOPW_PC, word);
7014
7015         /* finally, finally, gentlemen, start your engine */
7016         AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
7017
7018         /*
7019          * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
7020          * Resets should be performed. The RISC has to be running
7021          * to issue a SCSI Bus Reset.
7022          */
7023         if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
7024                 /*
7025                  * If the BIOS Signature is present in memory, restore the
7026                  * BIOS Handshake Configuration Table and do not perform
7027                  * a SCSI Bus Reset.
7028                  */
7029                 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
7030                     0x55AA) {
7031                         /*
7032                          * Restore per TID negotiated values.
7033                          */
7034                         AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7035                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7036                         AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
7037                                          tagqng_able);
7038                         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
7039                                 AdvWriteByteLram(iop_base,
7040                                                  ASC_MC_NUMBER_OF_MAX_CMD + tid,
7041                                                  max_cmd[tid]);
7042                         }
7043                 } else {
7044                         if (AdvResetSB(asc_dvc) != ADV_TRUE) {
7045                                 warn_code = ASC_WARN_BUSRESET_ERROR;
7046                         }
7047                 }
7048         }
7049
7050         return warn_code;
7051 }
7052
7053 /*
7054  * Initialize the ASC-38C0800.
7055  *
7056  * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
7057  *
7058  * For a non-fatal error return a warning code. If there are no warnings
7059  * then 0 is returned.
7060  *
7061  * Needed after initialization for error recovery.
7062  */
7063 static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
7064 {
7065         AdvPortAddr iop_base;
7066         ushort warn_code;
7067         int begin_addr;
7068         int end_addr;
7069         ushort code_sum;
7070         int word;
7071         int i;
7072         ushort scsi_cfg1;
7073         uchar byte;
7074         uchar tid;
7075         ushort bios_mem[ASC_MC_BIOSLEN / 2];    /* BIOS RISC Memory 0x40-0x8F. */
7076         ushort wdtr_able, sdtr_able, tagqng_able;
7077         uchar max_cmd[ADV_MAX_TID + 1];
7078
7079         /* If there is already an error, don't continue. */
7080         if (asc_dvc->err_code != 0)
7081                 return ADV_ERROR;
7082
7083         /*
7084          * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
7085          */
7086         if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) {
7087                 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
7088                 return ADV_ERROR;
7089         }
7090
7091         warn_code = 0;
7092         iop_base = asc_dvc->iop_base;
7093
7094         /*
7095          * Save the RISC memory BIOS region before writing the microcode.
7096          * The BIOS may already be loaded and using its RISC LRAM region
7097          * so its region must be saved and restored.
7098          *
7099          * Note: This code makes the assumption, which is currently true,
7100          * that a chip reset does not clear RISC LRAM.
7101          */
7102         for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
7103                 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
7104                                 bios_mem[i]);
7105         }
7106
7107         /*
7108          * Save current per TID negotiated values.
7109          */
7110         AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7111         AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7112         AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
7113         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
7114                 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
7115                                 max_cmd[tid]);
7116         }
7117
7118         /*
7119          * RAM BIST (RAM Built-In Self Test)
7120          *
7121          * Address : I/O base + offset 0x38h register (byte).
7122          * Function: Bit 7-6(RW) : RAM mode
7123          *                          Normal Mode   : 0x00
7124          *                          Pre-test Mode : 0x40
7125          *                          RAM Test Mode : 0x80
7126          *           Bit 5       : unused
7127          *           Bit 4(RO)   : Done bit
7128          *           Bit 3-0(RO) : Status
7129          *                          Host Error    : 0x08
7130          *                          Int_RAM Error : 0x04
7131          *                          RISC Error    : 0x02
7132          *                          SCSI Error    : 0x01
7133          *                          No Error      : 0x00
7134          *
7135          * Note: RAM BIST code should be put right here, before loading the
7136          * microcode and after saving the RISC memory BIOS region.
7137          */
7138
7139         /*
7140          * LRAM Pre-test
7141          *
7142          * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
7143          * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
7144          * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
7145          * to NORMAL_MODE, return an error too.
7146          */
7147         for (i = 0; i < 2; i++) {
7148                 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
7149                 mdelay(10);     /* Wait for 10ms before reading back. */
7150                 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
7151                 if ((byte & RAM_TEST_DONE) == 0
7152                     || (byte & 0x0F) != PRE_TEST_VALUE) {
7153                         asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
7154                         return ADV_ERROR;
7155                 }
7156
7157                 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
7158                 mdelay(10);     /* Wait for 10ms before reading back. */
7159                 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
7160                     != NORMAL_VALUE) {
7161                         asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
7162                         return ADV_ERROR;
7163                 }
7164         }
7165
7166         /*
7167          * LRAM Test - It takes about 1.5 ms to run through the test.
7168          *
7169          * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
7170          * If Done bit not set or Status not 0, save register byte, set the
7171          * err_code, and return an error.
7172          */
7173         AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
7174         mdelay(10);     /* Wait for 10ms before checking status. */
7175
7176         byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
7177         if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
7178                 /* Get here if Done bit not set or Status not 0. */
7179                 asc_dvc->bist_err_code = byte;  /* for BIOS display message */
7180                 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
7181                 return ADV_ERROR;
7182         }
7183
7184         /* We need to reset back to normal mode after LRAM test passes. */
7185         AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
7186
7187         asc_dvc->err_code = AdvLoadMicrocode(iop_base, _adv_asc38C0800_buf,
7188                                  _adv_asc38C0800_size, ADV_38C0800_MEMSIZE,
7189                                  _adv_asc38C0800_chksum);
7190         if (asc_dvc->err_code)
7191                 return ADV_ERROR;
7192
7193         /*
7194          * Restore the RISC memory BIOS region.
7195          */
7196         for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
7197                 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
7198                                  bios_mem[i]);
7199         }
7200
7201         /*
7202          * Calculate and write the microcode code checksum to the microcode
7203          * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
7204          */
7205         AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
7206         AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
7207         code_sum = 0;
7208         AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
7209         for (word = begin_addr; word < end_addr; word += 2) {
7210                 code_sum += AdvReadWordAutoIncLram(iop_base);
7211         }
7212         AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
7213
7214         /*
7215          * Read microcode version and date.
7216          */
7217         AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
7218                         asc_dvc->cfg->mcode_date);
7219         AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
7220                         asc_dvc->cfg->mcode_version);
7221
7222         /*
7223          * Set the chip type to indicate the ASC38C0800.
7224          */
7225         AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
7226
7227         /*
7228          * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
7229          * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
7230          * cable detection and then we are able to read C_DET[3:0].
7231          *
7232          * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
7233          * Microcode Default Value' section below.
7234          */
7235         scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
7236         AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
7237                              scsi_cfg1 | DIS_TERM_DRV);
7238
7239         /*
7240          * If the PCI Configuration Command Register "Parity Error Response
7241          * Control" Bit was clear (0), then set the microcode variable
7242          * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
7243          * to ignore DMA parity errors.
7244          */
7245         if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
7246                 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7247                 word |= CONTROL_FLAG_IGNORE_PERR;
7248                 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7249         }
7250
7251         /*
7252          * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
7253          * bits for the default FIFO threshold.
7254          *
7255          * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
7256          *
7257          * For DMA Errata #4 set the BC_THRESH_ENB bit.
7258          */
7259         AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
7260                              BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH |
7261                              READ_CMD_MRM);
7262
7263         /*
7264          * Microcode operating variables for WDTR, SDTR, and command tag
7265          * queuing will be set in slave_configure() based on what a
7266          * device reports it is capable of in Inquiry byte 7.
7267          *
7268          * If SCSI Bus Resets have been disabled, then directly set
7269          * SDTR and WDTR from the EEPROM configuration. This will allow
7270          * the BIOS and warm boot to work without a SCSI bus hang on
7271          * the Inquiry caused by host and target mismatched DTR values.
7272          * Without the SCSI Bus Reset, before an Inquiry a device can't
7273          * be assumed to be in Asynchronous, Narrow mode.
7274          */
7275         if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
7276                 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
7277                                  asc_dvc->wdtr_able);
7278                 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
7279                                  asc_dvc->sdtr_able);
7280         }
7281
7282         /*
7283          * Set microcode operating variables for DISC and SDTR_SPEED1,
7284          * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
7285          * configuration values.
7286          *
7287          * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
7288          * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
7289          * without determining here whether the device supports SDTR.
7290          */
7291         AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
7292                          asc_dvc->cfg->disc_enable);
7293         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
7294         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
7295         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
7296         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
7297
7298         /*
7299          * Set SCSI_CFG0 Microcode Default Value.
7300          *
7301          * The microcode will set the SCSI_CFG0 register using this value
7302          * after it is started below.
7303          */
7304         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
7305                          PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
7306                          asc_dvc->chip_scsi_id);
7307
7308         /*
7309          * Determine SCSI_CFG1 Microcode Default Value.
7310          *
7311          * The microcode will set the SCSI_CFG1 register using this value
7312          * after it is started below.
7313          */
7314
7315         /* Read current SCSI_CFG1 Register value. */
7316         scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
7317
7318         /*
7319          * If the internal narrow cable is reversed all of the SCSI_CTRL
7320          * register signals will be set. Check for and return an error if
7321          * this condition is found.
7322          */
7323         if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
7324                 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
7325                 return ADV_ERROR;
7326         }
7327
7328         /*
7329          * All kind of combinations of devices attached to one of four
7330          * connectors are acceptable except HVD device attached. For example,
7331          * LVD device can be attached to SE connector while SE device attached
7332          * to LVD connector.  If LVD device attached to SE connector, it only
7333          * runs up to Ultra speed.
7334          *
7335          * If an HVD device is attached to one of LVD connectors, return an
7336          * error.  However, there is no way to detect HVD device attached to
7337          * SE connectors.
7338          */
7339         if (scsi_cfg1 & HVD) {
7340                 asc_dvc->err_code = ASC_IERR_HVD_DEVICE;
7341                 return ADV_ERROR;
7342         }
7343
7344         /*
7345          * If either SE or LVD automatic termination control is enabled, then
7346          * set the termination value based on a table listed in a_condor.h.
7347          *
7348          * If manual termination was specified with an EEPROM setting then
7349          * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready
7350          * to be 'ored' into SCSI_CFG1.
7351          */
7352         if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
7353                 /* SE automatic termination control is enabled. */
7354                 switch (scsi_cfg1 & C_DET_SE) {
7355                         /* TERM_SE_HI: on, TERM_SE_LO: on */
7356                 case 0x1:
7357                 case 0x2:
7358                 case 0x3:
7359                         asc_dvc->cfg->termination |= TERM_SE;
7360                         break;
7361
7362                         /* TERM_SE_HI: on, TERM_SE_LO: off */
7363                 case 0x0:
7364                         asc_dvc->cfg->termination |= TERM_SE_HI;
7365                         break;
7366                 }
7367         }
7368
7369         if ((asc_dvc->cfg->termination & TERM_LVD) == 0) {
7370                 /* LVD automatic termination control is enabled. */
7371                 switch (scsi_cfg1 & C_DET_LVD) {
7372                         /* TERM_LVD_HI: on, TERM_LVD_LO: on */
7373                 case 0x4:
7374                 case 0x8:
7375                 case 0xC:
7376                         asc_dvc->cfg->termination |= TERM_LVD;
7377                         break;
7378
7379                         /* TERM_LVD_HI: off, TERM_LVD_LO: off */
7380                 case 0x0:
7381                         break;
7382                 }
7383         }
7384
7385         /*
7386          * Clear any set TERM_SE and TERM_LVD bits.
7387          */
7388         scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
7389
7390         /*
7391          * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
7392          */
7393         scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
7394
7395         /*
7396          * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE
7397          * bits and set possibly modified termination control bits in the
7398          * Microcode SCSI_CFG1 Register Value.
7399          */
7400         scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
7401
7402         /*
7403          * Set SCSI_CFG1 Microcode Default Value
7404          *
7405          * Set possibly modified termination control and reset DIS_TERM_DRV
7406          * bits in the Microcode SCSI_CFG1 Register Value.
7407          *
7408          * The microcode will set the SCSI_CFG1 register using this value
7409          * after it is started below.
7410          */
7411         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
7412
7413         /*
7414          * Set MEM_CFG Microcode Default Value
7415          *
7416          * The microcode will set the MEM_CFG register using this value
7417          * after it is started below.
7418          *
7419          * MEM_CFG may be accessed as a word or byte, but only bits 0-7
7420          * are defined.
7421          *
7422          * ASC-38C0800 has 16KB internal memory.
7423          */
7424         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
7425                          BIOS_EN | RAM_SZ_16KB);
7426
7427         /*
7428          * Set SEL_MASK Microcode Default Value
7429          *
7430          * The microcode will set the SEL_MASK register using this value
7431          * after it is started below.
7432          */
7433         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
7434                          ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
7435
7436         AdvBuildCarrierFreelist(asc_dvc);
7437
7438         /*
7439          * Set-up the Host->RISC Initiator Command Queue (ICQ).
7440          */
7441
7442         if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
7443                 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
7444                 return ADV_ERROR;
7445         }
7446         asc_dvc->carr_freelist = (ADV_CARR_T *)
7447             ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
7448
7449         /*
7450          * The first command issued will be placed in the stopper carrier.
7451          */
7452         asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
7453
7454         /*
7455          * Set RISC ICQ physical address start value.
7456          * carr_pa is LE, must be native before write
7457          */
7458         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
7459
7460         /*
7461          * Set-up the RISC->Host Initiator Response Queue (IRQ).
7462          */
7463         if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
7464                 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
7465                 return ADV_ERROR;
7466         }
7467         asc_dvc->carr_freelist = (ADV_CARR_T *)
7468             ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
7469
7470         /*
7471          * The first command completed by the RISC will be placed in
7472          * the stopper.
7473          *
7474          * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
7475          * completed the RISC will set the ASC_RQ_STOPPER bit.
7476          */
7477         asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
7478
7479         /*
7480          * Set RISC IRQ physical address start value.
7481          *
7482          * carr_pa is LE, must be native before write *
7483          */
7484         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
7485         asc_dvc->carr_pending_cnt = 0;
7486
7487         AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
7488                              (ADV_INTR_ENABLE_HOST_INTR |
7489                               ADV_INTR_ENABLE_GLOBAL_INTR));
7490
7491         AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
7492         AdvWriteWordRegister(iop_base, IOPW_PC, word);
7493
7494         /* finally, finally, gentlemen, start your engine */
7495         AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
7496
7497         /*
7498          * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
7499          * Resets should be performed. The RISC has to be running
7500          * to issue a SCSI Bus Reset.
7501          */
7502         if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
7503                 /*
7504                  * If the BIOS Signature is present in memory, restore the
7505                  * BIOS Handshake Configuration Table and do not perform
7506                  * a SCSI Bus Reset.
7507                  */
7508                 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
7509                     0x55AA) {
7510                         /*
7511                          * Restore per TID negotiated values.
7512                          */
7513                         AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7514                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7515                         AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
7516                                          tagqng_able);
7517                         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
7518                                 AdvWriteByteLram(iop_base,
7519                                                  ASC_MC_NUMBER_OF_MAX_CMD + tid,
7520                                                  max_cmd[tid]);
7521                         }
7522                 } else {
7523                         if (AdvResetSB(asc_dvc) != ADV_TRUE) {
7524                                 warn_code = ASC_WARN_BUSRESET_ERROR;
7525                         }
7526                 }
7527         }
7528
7529         return warn_code;
7530 }
7531
7532 /*
7533  * Initialize the ASC-38C1600.
7534  *
7535  * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
7536  *
7537  * For a non-fatal error return a warning code. If there are no warnings
7538  * then 0 is returned.
7539  *
7540  * Needed after initialization for error recovery.
7541  */
7542 static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
7543 {
7544         AdvPortAddr iop_base;
7545         ushort warn_code;
7546         int begin_addr;
7547         int end_addr;
7548         ushort code_sum;
7549         long word;
7550         int i;
7551         ushort scsi_cfg1;
7552         uchar byte;
7553         uchar tid;
7554         ushort bios_mem[ASC_MC_BIOSLEN / 2];    /* BIOS RISC Memory 0x40-0x8F. */
7555         ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
7556         uchar max_cmd[ASC_MAX_TID + 1];
7557
7558         /* If there is already an error, don't continue. */
7559         if (asc_dvc->err_code != 0) {
7560                 return ADV_ERROR;
7561         }
7562
7563         /*
7564          * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
7565          */
7566         if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
7567                 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
7568                 return ADV_ERROR;
7569         }
7570
7571         warn_code = 0;
7572         iop_base = asc_dvc->iop_base;
7573
7574         /*
7575          * Save the RISC memory BIOS region before writing the microcode.
7576          * The BIOS may already be loaded and using its RISC LRAM region
7577          * so its region must be saved and restored.
7578          *
7579          * Note: This code makes the assumption, which is currently true,
7580          * that a chip reset does not clear RISC LRAM.
7581          */
7582         for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
7583                 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
7584                                 bios_mem[i]);
7585         }
7586
7587         /*
7588          * Save current per TID negotiated values.
7589          */
7590         AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7591         AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7592         AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
7593         AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
7594         for (tid = 0; tid <= ASC_MAX_TID; tid++) {
7595                 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
7596                                 max_cmd[tid]);
7597         }
7598
7599         /*
7600          * RAM BIST (Built-In Self Test)
7601          *
7602          * Address : I/O base + offset 0x38h register (byte).
7603          * Function: Bit 7-6(RW) : RAM mode
7604          *                          Normal Mode   : 0x00
7605          *                          Pre-test Mode : 0x40
7606          *                          RAM Test Mode : 0x80
7607          *           Bit 5       : unused
7608          *           Bit 4(RO)   : Done bit
7609          *           Bit 3-0(RO) : Status
7610          *                          Host Error    : 0x08
7611          *                          Int_RAM Error : 0x04
7612          *                          RISC Error    : 0x02
7613          *                          SCSI Error    : 0x01
7614          *                          No Error      : 0x00
7615          *
7616          * Note: RAM BIST code should be put right here, before loading the
7617          * microcode and after saving the RISC memory BIOS region.
7618          */
7619
7620         /*
7621          * LRAM Pre-test
7622          *
7623          * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
7624          * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
7625          * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
7626          * to NORMAL_MODE, return an error too.
7627          */
7628         for (i = 0; i < 2; i++) {
7629                 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
7630                 mdelay(10);     /* Wait for 10ms before reading back. */
7631                 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
7632                 if ((byte & RAM_TEST_DONE) == 0
7633                     || (byte & 0x0F) != PRE_TEST_VALUE) {
7634                         asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
7635                         return ADV_ERROR;
7636                 }
7637
7638                 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
7639                 mdelay(10);     /* Wait for 10ms before reading back. */
7640                 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
7641                     != NORMAL_VALUE) {
7642                         asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
7643                         return ADV_ERROR;
7644                 }
7645         }
7646
7647         /*
7648          * LRAM Test - It takes about 1.5 ms to run through the test.
7649          *
7650          * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
7651          * If Done bit not set or Status not 0, save register byte, set the
7652          * err_code, and return an error.
7653          */
7654         AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
7655         mdelay(10);     /* Wait for 10ms before checking status. */
7656
7657         byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
7658         if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
7659                 /* Get here if Done bit not set or Status not 0. */
7660                 asc_dvc->bist_err_code = byte;  /* for BIOS display message */
7661                 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
7662                 return ADV_ERROR;
7663         }
7664
7665         /* We need to reset back to normal mode after LRAM test passes. */
7666         AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
7667
7668         asc_dvc->err_code = AdvLoadMicrocode(iop_base, _adv_asc38C1600_buf,
7669                                  _adv_asc38C1600_size, ADV_38C1600_MEMSIZE,
7670                                  _adv_asc38C1600_chksum);
7671         if (asc_dvc->err_code)
7672                 return ADV_ERROR;
7673
7674         /*
7675          * Restore the RISC memory BIOS region.
7676          */
7677         for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
7678                 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
7679                                  bios_mem[i]);
7680         }
7681
7682         /*
7683          * Calculate and write the microcode code checksum to the microcode
7684          * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
7685          */
7686         AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
7687         AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
7688         code_sum = 0;
7689         AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
7690         for (word = begin_addr; word < end_addr; word += 2) {
7691                 code_sum += AdvReadWordAutoIncLram(iop_base);
7692         }
7693         AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
7694
7695         /*
7696          * Read microcode version and date.
7697          */
7698         AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
7699                         asc_dvc->cfg->mcode_date);
7700         AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
7701                         asc_dvc->cfg->mcode_version);
7702
7703         /*
7704          * Set the chip type to indicate the ASC38C1600.
7705          */
7706         AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
7707
7708         /*
7709          * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
7710          * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
7711          * cable detection and then we are able to read C_DET[3:0].
7712          *
7713          * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
7714          * Microcode Default Value' section below.
7715          */
7716         scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
7717         AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
7718                              scsi_cfg1 | DIS_TERM_DRV);
7719
7720         /*
7721          * If the PCI Configuration Command Register "Parity Error Response
7722          * Control" Bit was clear (0), then set the microcode variable
7723          * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
7724          * to ignore DMA parity errors.
7725          */
7726         if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
7727                 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7728                 word |= CONTROL_FLAG_IGNORE_PERR;
7729                 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7730         }
7731
7732         /*
7733          * If the BIOS control flag AIPP (Asynchronous Information
7734          * Phase Protection) disable bit is not set, then set the firmware
7735          * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
7736          * AIPP checking and encoding.
7737          */
7738         if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
7739                 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7740                 word |= CONTROL_FLAG_ENABLE_AIPP;
7741                 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7742         }
7743
7744         /*
7745          * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
7746          * and START_CTL_TH [3:2].
7747          */
7748         AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
7749                              FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
7750
7751         /*
7752          * Microcode operating variables for WDTR, SDTR, and command tag
7753          * queuing will be set in slave_configure() based on what a
7754          * device reports it is capable of in Inquiry byte 7.
7755          *
7756          * If SCSI Bus Resets have been disabled, then directly set
7757          * SDTR and WDTR from the EEPROM configuration. This will allow
7758          * the BIOS and warm boot to work without a SCSI bus hang on
7759          * the Inquiry caused by host and target mismatched DTR values.
7760          * Without the SCSI Bus Reset, before an Inquiry a device can't
7761          * be assumed to be in Asynchronous, Narrow mode.
7762          */
7763         if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
7764                 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
7765                                  asc_dvc->wdtr_able);
7766                 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
7767                                  asc_dvc->sdtr_able);
7768         }
7769
7770         /*
7771          * Set microcode operating variables for DISC and SDTR_SPEED1,
7772          * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
7773          * configuration values.
7774          *
7775          * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
7776          * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
7777          * without determining here whether the device supports SDTR.
7778          */
7779         AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
7780                          asc_dvc->cfg->disc_enable);
7781         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
7782         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
7783         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
7784         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
7785
7786         /*
7787          * Set SCSI_CFG0 Microcode Default Value.
7788          *
7789          * The microcode will set the SCSI_CFG0 register using this value
7790          * after it is started below.
7791          */
7792         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
7793                          PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
7794                          asc_dvc->chip_scsi_id);
7795
7796         /*
7797          * Calculate SCSI_CFG1 Microcode Default Value.
7798          *
7799          * The microcode will set the SCSI_CFG1 register using this value
7800          * after it is started below.
7801          *
7802          * Each ASC-38C1600 function has only two cable detect bits.
7803          * The bus mode override bits are in IOPB_SOFT_OVER_WR.
7804          */
7805         scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
7806
7807         /*
7808          * If the cable is reversed all of the SCSI_CTRL register signals
7809          * will be set. Check for and return an error if this condition is
7810          * found.
7811          */
7812         if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
7813                 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
7814                 return ADV_ERROR;
7815         }
7816
7817         /*
7818          * Each ASC-38C1600 function has two connectors. Only an HVD device
7819          * can not be connected to either connector. An LVD device or SE device
7820          * may be connected to either connecor. If an SE device is connected,
7821          * then at most Ultra speed (20 Mhz) can be used on both connectors.
7822          *
7823          * If an HVD device is attached, return an error.
7824          */
7825         if (scsi_cfg1 & HVD) {
7826                 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
7827                 return ADV_ERROR;
7828         }
7829
7830         /*
7831          * Each function in the ASC-38C1600 uses only the SE cable detect and
7832          * termination because there are two connectors for each function. Each
7833          * function may use either LVD or SE mode. Corresponding the SE automatic
7834          * termination control EEPROM bits are used for each function. Each
7835          * function has its own EEPROM. If SE automatic control is enabled for
7836          * the function, then set the termination value based on a table listed
7837          * in a_condor.h.
7838          *
7839          * If manual termination is specified in the EEPROM for the function,
7840          * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
7841          * ready to be 'ored' into SCSI_CFG1.
7842          */
7843         if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
7844                 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
7845                 /* SE automatic termination control is enabled. */
7846                 switch (scsi_cfg1 & C_DET_SE) {
7847                         /* TERM_SE_HI: on, TERM_SE_LO: on */
7848                 case 0x1:
7849                 case 0x2:
7850                 case 0x3:
7851                         asc_dvc->cfg->termination |= TERM_SE;
7852                         break;
7853
7854                 case 0x0:
7855                         if (PCI_FUNC(pdev->devfn) == 0) {
7856                                 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
7857                         } else {
7858                                 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
7859                                 asc_dvc->cfg->termination |= TERM_SE_HI;
7860                         }
7861                         break;
7862                 }
7863         }
7864
7865         /*
7866          * Clear any set TERM_SE bits.
7867          */
7868         scsi_cfg1 &= ~TERM_SE;
7869
7870         /*
7871          * Invert the TERM_SE bits and then set 'scsi_cfg1'.
7872          */
7873         scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
7874
7875         /*
7876          * Clear Big Endian and Terminator Polarity bits and set possibly
7877          * modified termination control bits in the Microcode SCSI_CFG1
7878          * Register Value.
7879          *
7880          * Big Endian bit is not used even on big endian machines.
7881          */
7882         scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
7883
7884         /*
7885          * Set SCSI_CFG1 Microcode Default Value
7886          *
7887          * Set possibly modified termination control bits in the Microcode
7888          * SCSI_CFG1 Register Value.
7889          *
7890          * The microcode will set the SCSI_CFG1 register using this value
7891          * after it is started below.
7892          */
7893         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
7894
7895         /*
7896          * Set MEM_CFG Microcode Default Value
7897          *
7898          * The microcode will set the MEM_CFG register using this value
7899          * after it is started below.
7900          *
7901          * MEM_CFG may be accessed as a word or byte, but only bits 0-7
7902          * are defined.
7903          *
7904          * ASC-38C1600 has 32KB internal memory.
7905          *
7906          * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
7907          * out a special 16K Adv Library and Microcode version. After the issue
7908          * resolved, we should turn back to the 32K support. Both a_condor.h and
7909          * mcode.sas files also need to be updated.
7910          *
7911          * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
7912          *  BIOS_EN | RAM_SZ_32KB);
7913          */
7914         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
7915                          BIOS_EN | RAM_SZ_16KB);
7916
7917         /*
7918          * Set SEL_MASK Microcode Default Value
7919          *
7920          * The microcode will set the SEL_MASK register using this value
7921          * after it is started below.
7922          */
7923         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
7924                          ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
7925
7926         AdvBuildCarrierFreelist(asc_dvc);
7927
7928         /*
7929          * Set-up the Host->RISC Initiator Command Queue (ICQ).
7930          */
7931         if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
7932                 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
7933                 return ADV_ERROR;
7934         }
7935         asc_dvc->carr_freelist = (ADV_CARR_T *)
7936             ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
7937
7938         /*
7939          * The first command issued will be placed in the stopper carrier.
7940          */
7941         asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
7942
7943         /*
7944          * Set RISC ICQ physical address start value. Initialize the
7945          * COMMA register to the same value otherwise the RISC will
7946          * prematurely detect a command is available.
7947          */
7948         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
7949         AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
7950                               le32_to_cpu(asc_dvc->icq_sp->carr_pa));
7951
7952         /*
7953          * Set-up the RISC->Host Initiator Response Queue (IRQ).
7954          */
7955         if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
7956                 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
7957                 return ADV_ERROR;
7958         }
7959         asc_dvc->carr_freelist = (ADV_CARR_T *)
7960             ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
7961
7962         /*
7963          * The first command completed by the RISC will be placed in
7964          * the stopper.
7965          *
7966          * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
7967          * completed the RISC will set the ASC_RQ_STOPPER bit.
7968          */
7969         asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
7970
7971         /*
7972          * Set RISC IRQ physical address start value.
7973          */
7974         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
7975         asc_dvc->carr_pending_cnt = 0;
7976
7977         AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
7978                              (ADV_INTR_ENABLE_HOST_INTR |
7979                               ADV_INTR_ENABLE_GLOBAL_INTR));
7980         AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
7981         AdvWriteWordRegister(iop_base, IOPW_PC, word);
7982
7983         /* finally, finally, gentlemen, start your engine */
7984         AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
7985
7986         /*
7987          * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
7988          * Resets should be performed. The RISC has to be running
7989          * to issue a SCSI Bus Reset.
7990          */
7991         if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
7992                 /*
7993                  * If the BIOS Signature is present in memory, restore the
7994                  * per TID microcode operating variables.
7995                  */
7996                 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
7997                     0x55AA) {
7998                         /*
7999                          * Restore per TID negotiated values.
8000                          */
8001                         AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
8002                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
8003                         AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
8004                         AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
8005                                          tagqng_able);
8006                         for (tid = 0; tid <= ASC_MAX_TID; tid++) {
8007                                 AdvWriteByteLram(iop_base,
8008                                                  ASC_MC_NUMBER_OF_MAX_CMD + tid,
8009                                                  max_cmd[tid]);
8010                         }
8011                 } else {
8012                         if (AdvResetSB(asc_dvc) != ADV_TRUE) {
8013                                 warn_code = ASC_WARN_BUSRESET_ERROR;
8014                         }
8015                 }
8016         }
8017
8018         return warn_code;
8019 }
8020
8021 /*
8022  * Reset chip and SCSI Bus.
8023  *
8024  * Return Value:
8025  *      ADV_TRUE(1) -   Chip re-initialization and SCSI Bus Reset successful.
8026  *      ADV_FALSE(0) -  Chip re-initialization and SCSI Bus Reset failure.
8027  */
8028 static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
8029 {
8030         int status;
8031         ushort wdtr_able, sdtr_able, tagqng_able;
8032         ushort ppr_able = 0;
8033         uchar tid, max_cmd[ADV_MAX_TID + 1];
8034         AdvPortAddr iop_base;
8035         ushort bios_sig;
8036
8037         iop_base = asc_dvc->iop_base;
8038
8039         /*
8040          * Save current per TID negotiated values.
8041          */
8042         AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
8043         AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
8044         if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8045                 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
8046         }
8047         AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
8048         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
8049                 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
8050                                 max_cmd[tid]);
8051         }
8052
8053         /*
8054          * Force the AdvInitAsc3550/38C0800Driver() function to
8055          * perform a SCSI Bus Reset by clearing the BIOS signature word.
8056          * The initialization functions assumes a SCSI Bus Reset is not
8057          * needed if the BIOS signature word is present.
8058          */
8059         AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
8060         AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
8061
8062         /*
8063          * Stop chip and reset it.
8064          */
8065         AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
8066         AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
8067         mdelay(100);
8068         AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
8069                              ADV_CTRL_REG_CMD_WR_IO_REG);
8070
8071         /*
8072          * Reset Adv Library error code, if any, and try
8073          * re-initializing the chip.
8074          */
8075         asc_dvc->err_code = 0;
8076         if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8077                 status = AdvInitAsc38C1600Driver(asc_dvc);
8078         } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
8079                 status = AdvInitAsc38C0800Driver(asc_dvc);
8080         } else {
8081                 status = AdvInitAsc3550Driver(asc_dvc);
8082         }
8083
8084         /* Translate initialization return value to status value. */
8085         if (status == 0) {
8086                 status = ADV_TRUE;
8087         } else {
8088                 status = ADV_FALSE;
8089         }
8090
8091         /*
8092          * Restore the BIOS signature word.
8093          */
8094         AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
8095
8096         /*
8097          * Restore per TID negotiated values.
8098          */
8099         AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
8100         AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
8101         if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8102                 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
8103         }
8104         AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
8105         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
8106                 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
8107                                  max_cmd[tid]);
8108         }
8109
8110         return status;
8111 }
8112
8113 /*
8114  * adv_async_callback() - Adv Library asynchronous event callback function.
8115  */
8116 static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
8117 {
8118         switch (code) {
8119         case ADV_ASYNC_SCSI_BUS_RESET_DET:
8120                 /*
8121                  * The firmware detected a SCSI Bus reset.
8122                  */
8123                 ASC_DBG(0, "ADV_ASYNC_SCSI_BUS_RESET_DET\n");
8124                 break;
8125
8126         case ADV_ASYNC_RDMA_FAILURE:
8127                 /*
8128                  * Handle RDMA failure by resetting the SCSI Bus and
8129                  * possibly the chip if it is unresponsive. Log the error
8130                  * with a unique code.
8131                  */
8132                 ASC_DBG(0, "ADV_ASYNC_RDMA_FAILURE\n");
8133                 AdvResetChipAndSB(adv_dvc_varp);
8134                 break;
8135
8136         case ADV_HOST_SCSI_BUS_RESET:
8137                 /*
8138                  * Host generated SCSI bus reset occurred.
8139                  */
8140                 ASC_DBG(0, "ADV_HOST_SCSI_BUS_RESET\n");
8141                 break;
8142
8143         default:
8144                 ASC_DBG(0, "unknown code 0x%x\n", code);
8145                 break;
8146         }
8147 }
8148
8149 /*
8150  * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
8151  *
8152  * Callback function for the Wide SCSI Adv Library.
8153  */
8154 static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
8155 {
8156         struct asc_board *boardp;
8157         adv_req_t *reqp;
8158         adv_sgblk_t *sgblkp;
8159         struct scsi_cmnd *scp;
8160         struct Scsi_Host *shost;
8161         ADV_DCNT resid_cnt;
8162
8163         ASC_DBG(1, "adv_dvc_varp 0x%lx, scsiqp 0x%lx\n",
8164                  (ulong)adv_dvc_varp, (ulong)scsiqp);
8165         ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
8166
8167         /*
8168          * Get the adv_req_t structure for the command that has been
8169          * completed. The adv_req_t structure actually contains the
8170          * completed ADV_SCSI_REQ_Q structure.
8171          */
8172         reqp = (adv_req_t *)ADV_U32_TO_VADDR(scsiqp->srb_ptr);
8173         ASC_DBG(1, "reqp 0x%lx\n", (ulong)reqp);
8174         if (reqp == NULL) {
8175                 ASC_PRINT("adv_isr_callback: reqp is NULL\n");
8176                 return;
8177         }
8178
8179         /*
8180          * Get the struct scsi_cmnd structure and Scsi_Host structure for the
8181          * command that has been completed.
8182          *
8183          * Note: The adv_req_t request structure and adv_sgblk_t structure,
8184          * if any, are dropped, because a board structure pointer can not be
8185          * determined.
8186          */
8187         scp = reqp->cmndp;
8188         ASC_DBG(1, "scp 0x%p\n", scp);
8189         if (scp == NULL) {
8190                 ASC_PRINT
8191                     ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
8192                 return;
8193         }
8194         ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
8195
8196         shost = scp->device->host;
8197         ASC_STATS(shost, callback);
8198         ASC_DBG(1, "shost 0x%p\n", shost);
8199
8200         boardp = shost_priv(shost);
8201         BUG_ON(adv_dvc_varp != &boardp->dvc_var.adv_dvc_var);
8202
8203         /*
8204          * 'done_status' contains the command's ending status.
8205          */
8206         switch (scsiqp->done_status) {
8207         case QD_NO_ERROR:
8208                 ASC_DBG(2, "QD_NO_ERROR\n");
8209                 scp->result = 0;
8210
8211                 /*
8212                  * Check for an underrun condition.
8213                  *
8214                  * If there was no error and an underrun condition, then
8215                  * then return the number of underrun bytes.
8216                  */
8217                 resid_cnt = le32_to_cpu(scsiqp->data_cnt);
8218                 if (scsi_bufflen(scp) != 0 && resid_cnt != 0 &&
8219                     resid_cnt <= scsi_bufflen(scp)) {
8220                         ASC_DBG(1, "underrun condition %lu bytes\n",
8221                                  (ulong)resid_cnt);
8222                         scsi_set_resid(scp, resid_cnt);
8223                 }
8224                 break;
8225
8226         case QD_WITH_ERROR:
8227                 ASC_DBG(2, "QD_WITH_ERROR\n");
8228                 switch (scsiqp->host_status) {
8229                 case QHSTA_NO_ERROR:
8230                         if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
8231                                 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
8232                                 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
8233                                                   sizeof(scp->sense_buffer));
8234                                 /*
8235                                  * Note: The 'status_byte()' macro used by
8236                                  * target drivers defined in scsi.h shifts the
8237                                  * status byte returned by host drivers right
8238                                  * by 1 bit.  This is why target drivers also
8239                                  * use right shifted status byte definitions.
8240                                  * For instance target drivers use
8241                                  * CHECK_CONDITION, defined to 0x1, instead of
8242                                  * the SCSI defined check condition value of
8243                                  * 0x2. Host drivers are supposed to return
8244                                  * the status byte as it is defined by SCSI.
8245                                  */
8246                                 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
8247                                     STATUS_BYTE(scsiqp->scsi_status);
8248                         } else {
8249                                 scp->result = STATUS_BYTE(scsiqp->scsi_status);
8250                         }
8251                         break;
8252
8253                 default:
8254                         /* Some other QHSTA error occurred. */
8255                         ASC_DBG(1, "host_status 0x%x\n", scsiqp->host_status);
8256                         scp->result = HOST_BYTE(DID_BAD_TARGET);
8257                         break;
8258                 }
8259                 break;
8260
8261         case QD_ABORTED_BY_HOST:
8262                 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
8263                 scp->result =
8264                     HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
8265                 break;
8266
8267         default:
8268                 ASC_DBG(1, "done_status 0x%x\n", scsiqp->done_status);
8269                 scp->result =
8270                     HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
8271                 break;
8272         }
8273
8274         /*
8275          * If the 'init_tidmask' bit isn't already set for the target and the
8276          * current request finished normally, then set the bit for the target
8277          * to indicate that a device is present.
8278          */
8279         if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
8280             scsiqp->done_status == QD_NO_ERROR &&
8281             scsiqp->host_status == QHSTA_NO_ERROR) {
8282                 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
8283         }
8284
8285         asc_scsi_done(scp);
8286
8287         /*
8288          * Free all 'adv_sgblk_t' structures allocated for the request.
8289          */
8290         while ((sgblkp = reqp->sgblkp) != NULL) {
8291                 /* Remove 'sgblkp' from the request list. */
8292                 reqp->sgblkp = sgblkp->next_sgblkp;
8293
8294                 /* Add 'sgblkp' to the board free list. */
8295                 sgblkp->next_sgblkp = boardp->adv_sgblkp;
8296                 boardp->adv_sgblkp = sgblkp;
8297         }
8298
8299         /*
8300          * Free the adv_req_t structure used with the command by adding
8301          * it back to the board free list.
8302          */
8303         reqp->next_reqp = boardp->adv_reqp;
8304         boardp->adv_reqp = reqp;
8305
8306         ASC_DBG(1, "done\n");
8307 }
8308
8309 /*
8310  * Adv Library Interrupt Service Routine
8311  *
8312  *  This function is called by a driver's interrupt service routine.
8313  *  The function disables and re-enables interrupts.
8314  *
8315  *  When a microcode idle command is completed, the ADV_DVC_VAR
8316  *  'idle_cmd_done' field is set to ADV_TRUE.
8317  *
8318  *  Note: AdvISR() can be called when interrupts are disabled or even
8319  *  when there is no hardware interrupt condition present. It will
8320  *  always check for completed idle commands and microcode requests.
8321  *  This is an important feature that shouldn't be changed because it
8322  *  allows commands to be completed from polling mode loops.
8323  *
8324  * Return:
8325  *   ADV_TRUE(1) - interrupt was pending
8326  *   ADV_FALSE(0) - no interrupt was pending
8327  */
8328 static int AdvISR(ADV_DVC_VAR *asc_dvc)
8329 {
8330         AdvPortAddr iop_base;
8331         uchar int_stat;
8332         ushort target_bit;
8333         ADV_CARR_T *free_carrp;
8334         ADV_VADDR irq_next_vpa;
8335         ADV_SCSI_REQ_Q *scsiq;
8336
8337         iop_base = asc_dvc->iop_base;
8338
8339         /* Reading the register clears the interrupt. */
8340         int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
8341
8342         if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
8343                          ADV_INTR_STATUS_INTRC)) == 0) {
8344                 return ADV_FALSE;
8345         }
8346
8347         /*
8348          * Notify the driver of an asynchronous microcode condition by
8349          * calling the adv_async_callback function. The function
8350          * is passed the microcode ASC_MC_INTRB_CODE byte value.
8351          */
8352         if (int_stat & ADV_INTR_STATUS_INTRB) {
8353                 uchar intrb_code;
8354
8355                 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
8356
8357                 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
8358                     asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
8359                         if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
8360                             asc_dvc->carr_pending_cnt != 0) {
8361                                 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
8362                                                      ADV_TICKLE_A);
8363                                 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
8364                                         AdvWriteByteRegister(iop_base,
8365                                                              IOPB_TICKLE,
8366                                                              ADV_TICKLE_NOP);
8367                                 }
8368                         }
8369                 }
8370
8371                 adv_async_callback(asc_dvc, intrb_code);
8372         }
8373
8374         /*
8375          * Check if the IRQ stopper carrier contains a completed request.
8376          */
8377         while (((irq_next_vpa =
8378                  le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ASC_RQ_DONE) != 0) {
8379                 /*
8380                  * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
8381                  * The RISC will have set 'areq_vpa' to a virtual address.
8382                  *
8383                  * The firmware will have copied the ASC_SCSI_REQ_Q.scsiq_ptr
8384                  * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
8385                  * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr'
8386                  * in AdvExeScsiQueue().
8387                  */
8388                 scsiq = (ADV_SCSI_REQ_Q *)
8389                     ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->areq_vpa));
8390
8391                 /*
8392                  * Request finished with good status and the queue was not
8393                  * DMAed to host memory by the firmware. Set all status fields
8394                  * to indicate good status.
8395                  */
8396                 if ((irq_next_vpa & ASC_RQ_GOOD) != 0) {
8397                         scsiq->done_status = QD_NO_ERROR;
8398                         scsiq->host_status = scsiq->scsi_status = 0;
8399                         scsiq->data_cnt = 0L;
8400                 }
8401
8402                 /*
8403                  * Advance the stopper pointer to the next carrier
8404                  * ignoring the lower four bits. Free the previous
8405                  * stopper carrier.
8406                  */
8407                 free_carrp = asc_dvc->irq_sp;
8408                 asc_dvc->irq_sp = (ADV_CARR_T *)
8409                     ADV_U32_TO_VADDR(ASC_GET_CARRP(irq_next_vpa));
8410
8411                 free_carrp->next_vpa =
8412                     cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
8413                 asc_dvc->carr_freelist = free_carrp;
8414                 asc_dvc->carr_pending_cnt--;
8415
8416                 target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
8417
8418                 /*
8419                  * Clear request microcode control flag.
8420                  */
8421                 scsiq->cntl = 0;
8422
8423                 /*
8424                  * Notify the driver of the completed request by passing
8425                  * the ADV_SCSI_REQ_Q pointer to its callback function.
8426                  */
8427                 scsiq->a_flag |= ADV_SCSIQ_DONE;
8428                 adv_isr_callback(asc_dvc, scsiq);
8429                 /*
8430                  * Note: After the driver callback function is called, 'scsiq'
8431                  * can no longer be referenced.
8432                  *
8433                  * Fall through and continue processing other completed
8434                  * requests...
8435                  */
8436         }
8437         return ADV_TRUE;
8438 }
8439
8440 static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code)
8441 {
8442         if (asc_dvc->err_code == 0) {
8443                 asc_dvc->err_code = err_code;
8444                 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
8445                                  err_code);
8446         }
8447         return err_code;
8448 }
8449
8450 static void AscAckInterrupt(PortAddr iop_base)
8451 {
8452         uchar host_flag;
8453         uchar risc_flag;
8454         ushort loop;
8455
8456         loop = 0;
8457         do {
8458                 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
8459                 if (loop++ > 0x7FFF) {
8460                         break;
8461                 }
8462         } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
8463         host_flag =
8464             AscReadLramByte(iop_base,
8465                             ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
8466         AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
8467                          (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT));
8468         AscSetChipStatus(iop_base, CIW_INT_ACK);
8469         loop = 0;
8470         while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
8471                 AscSetChipStatus(iop_base, CIW_INT_ACK);
8472                 if (loop++ > 3) {
8473                         break;
8474                 }
8475         }
8476         AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
8477 }
8478
8479 static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time)
8480 {
8481         const uchar *period_table;
8482         int max_index;
8483         int min_index;
8484         int i;
8485
8486         period_table = asc_dvc->sdtr_period_tbl;
8487         max_index = (int)asc_dvc->max_sdtr_index;
8488         min_index = (int)asc_dvc->min_sdtr_index;
8489         if ((syn_time <= period_table[max_index])) {
8490                 for (i = min_index; i < (max_index - 1); i++) {
8491                         if (syn_time <= period_table[i]) {
8492                                 return (uchar)i;
8493                         }
8494                 }
8495                 return (uchar)max_index;
8496         } else {
8497                 return (uchar)(max_index + 1);
8498         }
8499 }
8500
8501 static uchar
8502 AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset)
8503 {
8504         EXT_MSG sdtr_buf;
8505         uchar sdtr_period_index;
8506         PortAddr iop_base;
8507
8508         iop_base = asc_dvc->iop_base;
8509         sdtr_buf.msg_type = EXTENDED_MESSAGE;
8510         sdtr_buf.msg_len = MS_SDTR_LEN;
8511         sdtr_buf.msg_req = EXTENDED_SDTR;
8512         sdtr_buf.xfer_period = sdtr_period;
8513         sdtr_offset &= ASC_SYN_MAX_OFFSET;
8514         sdtr_buf.req_ack_offset = sdtr_offset;
8515         sdtr_period_index = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
8516         if (sdtr_period_index <= asc_dvc->max_sdtr_index) {
8517                 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
8518                                         (uchar *)&sdtr_buf,
8519                                         sizeof(EXT_MSG) >> 1);
8520                 return ((sdtr_period_index << 4) | sdtr_offset);
8521         } else {
8522                 sdtr_buf.req_ack_offset = 0;
8523                 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
8524                                         (uchar *)&sdtr_buf,
8525                                         sizeof(EXT_MSG) >> 1);
8526                 return 0;
8527         }
8528 }
8529
8530 static uchar
8531 AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset)
8532 {
8533         uchar byte;
8534         uchar sdtr_period_ix;
8535
8536         sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
8537         if (sdtr_period_ix > asc_dvc->max_sdtr_index)
8538                 return 0xFF;
8539         byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
8540         return byte;
8541 }
8542
8543 static int AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data)
8544 {
8545         ASC_SCSI_BIT_ID_TYPE org_id;
8546         int i;
8547         int sta = TRUE;
8548
8549         AscSetBank(iop_base, 1);
8550         org_id = AscReadChipDvcID(iop_base);
8551         for (i = 0; i <= ASC_MAX_TID; i++) {
8552                 if (org_id == (0x01 << i))
8553                         break;
8554         }
8555         org_id = (ASC_SCSI_BIT_ID_TYPE) i;
8556         AscWriteChipDvcID(iop_base, id);
8557         if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
8558                 AscSetBank(iop_base, 0);
8559                 AscSetChipSyn(iop_base, sdtr_data);
8560                 if (AscGetChipSyn(iop_base) != sdtr_data) {
8561                         sta = FALSE;
8562                 }
8563         } else {
8564                 sta = FALSE;
8565         }
8566         AscSetBank(iop_base, 1);
8567         AscWriteChipDvcID(iop_base, org_id);
8568         AscSetBank(iop_base, 0);
8569         return (sta);
8570 }
8571
8572 static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no)
8573 {
8574         AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
8575         AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
8576 }
8577
8578 static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
8579 {
8580         EXT_MSG ext_msg;
8581         EXT_MSG out_msg;
8582         ushort halt_q_addr;
8583         int sdtr_accept;
8584         ushort int_halt_code;
8585         ASC_SCSI_BIT_ID_TYPE scsi_busy;
8586         ASC_SCSI_BIT_ID_TYPE target_id;
8587         PortAddr iop_base;
8588         uchar tag_code;
8589         uchar q_status;
8590         uchar halt_qp;
8591         uchar sdtr_data;
8592         uchar target_ix;
8593         uchar q_cntl, tid_no;
8594         uchar cur_dvc_qng;
8595         uchar asyn_sdtr;
8596         uchar scsi_status;
8597         struct asc_board *boardp;
8598
8599         BUG_ON(!asc_dvc->drv_ptr);
8600         boardp = asc_dvc->drv_ptr;
8601
8602         iop_base = asc_dvc->iop_base;
8603         int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
8604
8605         halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
8606         halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
8607         target_ix = AscReadLramByte(iop_base,
8608                                     (ushort)(halt_q_addr +
8609                                              (ushort)ASC_SCSIQ_B_TARGET_IX));
8610         q_cntl = AscReadLramByte(iop_base,
8611                             (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL));
8612         tid_no = ASC_TIX_TO_TID(target_ix);
8613         target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no);
8614         if (asc_dvc->pci_fix_asyn_xfer & target_id) {
8615                 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
8616         } else {
8617                 asyn_sdtr = 0;
8618         }
8619         if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
8620                 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
8621                         AscSetChipSDTR(iop_base, 0, tid_no);
8622                         boardp->sdtr_data[tid_no] = 0;
8623                 }
8624                 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8625                 return (0);
8626         } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
8627                 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
8628                         AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
8629                         boardp->sdtr_data[tid_no] = asyn_sdtr;
8630                 }
8631                 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8632                 return (0);
8633         } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
8634                 AscMemWordCopyPtrFromLram(iop_base,
8635                                           ASCV_MSGIN_BEG,
8636                                           (uchar *)&ext_msg,
8637                                           sizeof(EXT_MSG) >> 1);
8638
8639                 if (ext_msg.msg_type == EXTENDED_MESSAGE &&
8640                     ext_msg.msg_req == EXTENDED_SDTR &&
8641                     ext_msg.msg_len == MS_SDTR_LEN) {
8642                         sdtr_accept = TRUE;
8643                         if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
8644
8645                                 sdtr_accept = FALSE;
8646                                 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
8647                         }
8648                         if ((ext_msg.xfer_period <
8649                              asc_dvc->sdtr_period_tbl[asc_dvc->min_sdtr_index])
8650                             || (ext_msg.xfer_period >
8651                                 asc_dvc->sdtr_period_tbl[asc_dvc->
8652                                                          max_sdtr_index])) {
8653                                 sdtr_accept = FALSE;
8654                                 ext_msg.xfer_period =
8655                                     asc_dvc->sdtr_period_tbl[asc_dvc->
8656                                                              min_sdtr_index];
8657                         }
8658                         if (sdtr_accept) {
8659                                 sdtr_data =
8660                                     AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
8661                                                    ext_msg.req_ack_offset);
8662                                 if ((sdtr_data == 0xFF)) {
8663
8664                                         q_cntl |= QC_MSG_OUT;
8665                                         asc_dvc->init_sdtr &= ~target_id;
8666                                         asc_dvc->sdtr_done &= ~target_id;
8667                                         AscSetChipSDTR(iop_base, asyn_sdtr,
8668                                                        tid_no);
8669                                         boardp->sdtr_data[tid_no] = asyn_sdtr;
8670                                 }
8671                         }
8672                         if (ext_msg.req_ack_offset == 0) {
8673
8674                                 q_cntl &= ~QC_MSG_OUT;
8675                                 asc_dvc->init_sdtr &= ~target_id;
8676                                 asc_dvc->sdtr_done &= ~target_id;
8677                                 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
8678                         } else {
8679                                 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
8680                                         q_cntl &= ~QC_MSG_OUT;
8681                                         asc_dvc->sdtr_done |= target_id;
8682                                         asc_dvc->init_sdtr |= target_id;
8683                                         asc_dvc->pci_fix_asyn_xfer &=
8684                                             ~target_id;
8685                                         sdtr_data =
8686                                             AscCalSDTRData(asc_dvc,
8687                                                            ext_msg.xfer_period,
8688                                                            ext_msg.
8689                                                            req_ack_offset);
8690                                         AscSetChipSDTR(iop_base, sdtr_data,
8691                                                        tid_no);
8692                                         boardp->sdtr_data[tid_no] = sdtr_data;
8693                                 } else {
8694                                         q_cntl |= QC_MSG_OUT;
8695                                         AscMsgOutSDTR(asc_dvc,
8696                                                       ext_msg.xfer_period,
8697                                                       ext_msg.req_ack_offset);
8698                                         asc_dvc->pci_fix_asyn_xfer &=
8699                                             ~target_id;
8700                                         sdtr_data =
8701                                             AscCalSDTRData(asc_dvc,
8702                                                            ext_msg.xfer_period,
8703                                                            ext_msg.
8704                                                            req_ack_offset);
8705                                         AscSetChipSDTR(iop_base, sdtr_data,
8706                                                        tid_no);
8707                                         boardp->sdtr_data[tid_no] = sdtr_data;
8708                                         asc_dvc->sdtr_done |= target_id;
8709                                         asc_dvc->init_sdtr |= target_id;
8710                                 }
8711                         }
8712
8713                         AscWriteLramByte(iop_base,
8714                                          (ushort)(halt_q_addr +
8715                                                   (ushort)ASC_SCSIQ_B_CNTL),
8716                                          q_cntl);
8717                         AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8718                         return (0);
8719                 } else if (ext_msg.msg_type == EXTENDED_MESSAGE &&
8720                            ext_msg.msg_req == EXTENDED_WDTR &&
8721                            ext_msg.msg_len == MS_WDTR_LEN) {
8722
8723                         ext_msg.wdtr_width = 0;
8724                         AscMemWordCopyPtrToLram(iop_base,
8725                                                 ASCV_MSGOUT_BEG,
8726                                                 (uchar *)&ext_msg,
8727                                                 sizeof(EXT_MSG) >> 1);
8728                         q_cntl |= QC_MSG_OUT;
8729                         AscWriteLramByte(iop_base,
8730                                          (ushort)(halt_q_addr +
8731                                                   (ushort)ASC_SCSIQ_B_CNTL),
8732                                          q_cntl);
8733                         AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8734                         return (0);
8735                 } else {
8736
8737                         ext_msg.msg_type = MESSAGE_REJECT;
8738                         AscMemWordCopyPtrToLram(iop_base,
8739                                                 ASCV_MSGOUT_BEG,
8740                                                 (uchar *)&ext_msg,
8741                                                 sizeof(EXT_MSG) >> 1);
8742                         q_cntl |= QC_MSG_OUT;
8743                         AscWriteLramByte(iop_base,
8744                                          (ushort)(halt_q_addr +
8745                                                   (ushort)ASC_SCSIQ_B_CNTL),
8746                                          q_cntl);
8747                         AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8748                         return (0);
8749                 }
8750         } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
8751
8752                 q_cntl |= QC_REQ_SENSE;
8753
8754                 if ((asc_dvc->init_sdtr & target_id) != 0) {
8755
8756                         asc_dvc->sdtr_done &= ~target_id;
8757
8758                         sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
8759                         q_cntl |= QC_MSG_OUT;
8760                         AscMsgOutSDTR(asc_dvc,
8761                                       asc_dvc->
8762                                       sdtr_period_tbl[(sdtr_data >> 4) &
8763                                                       (uchar)(asc_dvc->
8764                                                               max_sdtr_index -
8765                                                               1)],
8766                                       (uchar)(sdtr_data & (uchar)
8767                                               ASC_SYN_MAX_OFFSET));
8768                 }
8769
8770                 AscWriteLramByte(iop_base,
8771                                  (ushort)(halt_q_addr +
8772                                           (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
8773
8774                 tag_code = AscReadLramByte(iop_base,
8775                                            (ushort)(halt_q_addr + (ushort)
8776                                                     ASC_SCSIQ_B_TAG_CODE));
8777                 tag_code &= 0xDC;
8778                 if ((asc_dvc->pci_fix_asyn_xfer & target_id)
8779                     && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
8780                     ) {
8781
8782                         tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
8783                                      | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
8784
8785                 }
8786                 AscWriteLramByte(iop_base,
8787                                  (ushort)(halt_q_addr +
8788                                           (ushort)ASC_SCSIQ_B_TAG_CODE),
8789                                  tag_code);
8790
8791                 q_status = AscReadLramByte(iop_base,
8792                                            (ushort)(halt_q_addr + (ushort)
8793                                                     ASC_SCSIQ_B_STATUS));
8794                 q_status |= (QS_READY | QS_BUSY);
8795                 AscWriteLramByte(iop_base,
8796                                  (ushort)(halt_q_addr +
8797                                           (ushort)ASC_SCSIQ_B_STATUS),
8798                                  q_status);
8799
8800                 scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B);
8801                 scsi_busy &= ~target_id;
8802                 AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy);
8803
8804                 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8805                 return (0);
8806         } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
8807
8808                 AscMemWordCopyPtrFromLram(iop_base,
8809                                           ASCV_MSGOUT_BEG,
8810                                           (uchar *)&out_msg,
8811                                           sizeof(EXT_MSG) >> 1);
8812
8813                 if ((out_msg.msg_type == EXTENDED_MESSAGE) &&
8814                     (out_msg.msg_len == MS_SDTR_LEN) &&
8815                     (out_msg.msg_req == EXTENDED_SDTR)) {
8816
8817                         asc_dvc->init_sdtr &= ~target_id;
8818                         asc_dvc->sdtr_done &= ~target_id;
8819                         AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
8820                         boardp->sdtr_data[tid_no] = asyn_sdtr;
8821                 }
8822                 q_cntl &= ~QC_MSG_OUT;
8823                 AscWriteLramByte(iop_base,
8824                                  (ushort)(halt_q_addr +
8825                                           (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
8826                 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8827                 return (0);
8828         } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
8829
8830                 scsi_status = AscReadLramByte(iop_base,
8831                                               (ushort)((ushort)halt_q_addr +
8832                                                        (ushort)
8833                                                        ASC_SCSIQ_SCSI_STATUS));
8834                 cur_dvc_qng =
8835                     AscReadLramByte(iop_base,
8836                                     (ushort)((ushort)ASC_QADR_BEG +
8837                                              (ushort)target_ix));
8838                 if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
8839
8840                         scsi_busy = AscReadLramByte(iop_base,
8841                                                     (ushort)ASCV_SCSIBUSY_B);
8842                         scsi_busy |= target_id;
8843                         AscWriteLramByte(iop_base,
8844                                          (ushort)ASCV_SCSIBUSY_B, scsi_busy);
8845                         asc_dvc->queue_full_or_busy |= target_id;
8846
8847                         if (scsi_status == SAM_STAT_TASK_SET_FULL) {
8848                                 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
8849                                         cur_dvc_qng -= 1;
8850                                         asc_dvc->max_dvc_qng[tid_no] =
8851                                             cur_dvc_qng;
8852
8853                                         AscWriteLramByte(iop_base,
8854                                                          (ushort)((ushort)
8855                                                                   ASCV_MAX_DVC_QNG_BEG
8856                                                                   + (ushort)
8857                                                                   tid_no),
8858                                                          cur_dvc_qng);
8859
8860                                         /*
8861                                          * Set the device queue depth to the
8862                                          * number of active requests when the
8863                                          * QUEUE FULL condition was encountered.
8864                                          */
8865                                         boardp->queue_full |= target_id;
8866                                         boardp->queue_full_cnt[tid_no] =
8867                                             cur_dvc_qng;
8868                                 }
8869                         }
8870                 }
8871                 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8872                 return (0);
8873         }
8874 #if CC_VERY_LONG_SG_LIST
8875         else if (int_halt_code == ASC_HALT_HOST_COPY_SG_LIST_TO_RISC) {
8876                 uchar q_no;
8877                 ushort q_addr;
8878                 uchar sg_wk_q_no;
8879                 uchar first_sg_wk_q_no;
8880                 ASC_SCSI_Q *scsiq;      /* Ptr to driver request. */
8881                 ASC_SG_HEAD *sg_head;   /* Ptr to driver SG request. */
8882                 ASC_SG_LIST_Q scsi_sg_q;        /* Structure written to queue. */
8883                 ushort sg_list_dwords;
8884                 ushort sg_entry_cnt;
8885                 uchar next_qp;
8886                 int i;
8887
8888                 q_no = AscReadLramByte(iop_base, (ushort)ASCV_REQ_SG_LIST_QP);
8889                 if (q_no == ASC_QLINK_END)
8890                         return 0;
8891
8892                 q_addr = ASC_QNO_TO_QADDR(q_no);
8893
8894                 /*
8895                  * Convert the request's SRB pointer to a host ASC_SCSI_REQ
8896                  * structure pointer using a macro provided by the driver.
8897                  * The ASC_SCSI_REQ pointer provides a pointer to the
8898                  * host ASC_SG_HEAD structure.
8899                  */
8900                 /* Read request's SRB pointer. */
8901                 scsiq = (ASC_SCSI_Q *)
8902                     ASC_SRB2SCSIQ(ASC_U32_TO_VADDR(AscReadLramDWord(iop_base,
8903                                                                     (ushort)
8904                                                                     (q_addr +
8905                                                                      ASC_SCSIQ_D_SRBPTR))));
8906
8907                 /*
8908                  * Get request's first and working SG queue.
8909                  */
8910                 sg_wk_q_no = AscReadLramByte(iop_base,
8911                                              (ushort)(q_addr +
8912                                                       ASC_SCSIQ_B_SG_WK_QP));
8913
8914                 first_sg_wk_q_no = AscReadLramByte(iop_base,
8915                                                    (ushort)(q_addr +
8916                                                             ASC_SCSIQ_B_FIRST_SG_WK_QP));
8917
8918                 /*
8919                  * Reset request's working SG queue back to the
8920                  * first SG queue.
8921                  */
8922                 AscWriteLramByte(iop_base,
8923                                  (ushort)(q_addr +
8924                                           (ushort)ASC_SCSIQ_B_SG_WK_QP),
8925                                  first_sg_wk_q_no);
8926
8927                 sg_head = scsiq->sg_head;
8928
8929                 /*
8930                  * Set sg_entry_cnt to the number of SG elements
8931                  * that will be completed on this interrupt.
8932                  *
8933                  * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1
8934                  * SG elements. The data_cnt and data_addr fields which
8935                  * add 1 to the SG element capacity are not used when
8936                  * restarting SG handling after a halt.
8937                  */
8938                 if (scsiq->remain_sg_entry_cnt > (ASC_MAX_SG_LIST - 1)) {
8939                         sg_entry_cnt = ASC_MAX_SG_LIST - 1;
8940
8941                         /*
8942                          * Keep track of remaining number of SG elements that
8943                          * will need to be handled on the next interrupt.
8944                          */
8945                         scsiq->remain_sg_entry_cnt -= (ASC_MAX_SG_LIST - 1);
8946                 } else {
8947                         sg_entry_cnt = scsiq->remain_sg_entry_cnt;
8948                         scsiq->remain_sg_entry_cnt = 0;
8949                 }
8950
8951                 /*
8952                  * Copy SG elements into the list of allocated SG queues.
8953                  *
8954                  * Last index completed is saved in scsiq->next_sg_index.
8955                  */
8956                 next_qp = first_sg_wk_q_no;
8957                 q_addr = ASC_QNO_TO_QADDR(next_qp);
8958                 scsi_sg_q.sg_head_qp = q_no;
8959                 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
8960                 for (i = 0; i < sg_head->queue_cnt; i++) {
8961                         scsi_sg_q.seq_no = i + 1;
8962                         if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
8963                                 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
8964                                 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
8965                                 /*
8966                                  * After very first SG queue RISC FW uses next
8967                                  * SG queue first element then checks sg_list_cnt
8968                                  * against zero and then decrements, so set
8969                                  * sg_list_cnt 1 less than number of SG elements
8970                                  * in each SG queue.
8971                                  */
8972                                 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
8973                                 scsi_sg_q.sg_cur_list_cnt =
8974                                     ASC_SG_LIST_PER_Q - 1;
8975                         } else {
8976                                 /*
8977                                  * This is the last SG queue in the list of
8978                                  * allocated SG queues. If there are more
8979                                  * SG elements than will fit in the allocated
8980                                  * queues, then set the QCSG_SG_XFER_MORE flag.
8981                                  */
8982                                 if (scsiq->remain_sg_entry_cnt != 0) {
8983                                         scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
8984                                 } else {
8985                                         scsi_sg_q.cntl |= QCSG_SG_XFER_END;
8986                                 }
8987                                 /* equals sg_entry_cnt * 2 */
8988                                 sg_list_dwords = sg_entry_cnt << 1;
8989                                 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
8990                                 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
8991                                 sg_entry_cnt = 0;
8992                         }
8993
8994                         scsi_sg_q.q_no = next_qp;
8995                         AscMemWordCopyPtrToLram(iop_base,
8996                                                 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
8997                                                 (uchar *)&scsi_sg_q,
8998                                                 sizeof(ASC_SG_LIST_Q) >> 1);
8999
9000                         AscMemDWordCopyPtrToLram(iop_base,
9001                                                  q_addr + ASC_SGQ_LIST_BEG,
9002                                                  (uchar *)&sg_head->
9003                                                  sg_list[scsiq->next_sg_index],
9004                                                  sg_list_dwords);
9005
9006                         scsiq->next_sg_index += ASC_SG_LIST_PER_Q;
9007
9008                         /*
9009                          * If the just completed SG queue contained the
9010                          * last SG element, then no more SG queues need
9011                          * to be written.
9012                          */
9013                         if (scsi_sg_q.cntl & QCSG_SG_XFER_END) {
9014                                 break;
9015                         }
9016
9017                         next_qp = AscReadLramByte(iop_base,
9018                                                   (ushort)(q_addr +
9019                                                            ASC_SCSIQ_B_FWD));
9020                         q_addr = ASC_QNO_TO_QADDR(next_qp);
9021                 }
9022
9023                 /*
9024                  * Clear the halt condition so the RISC will be restarted
9025                  * after the return.
9026                  */
9027                 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9028                 return (0);
9029         }
9030 #endif /* CC_VERY_LONG_SG_LIST */
9031         return (0);
9032 }
9033
9034 /*
9035  * void
9036  * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
9037  *
9038  * Calling/Exit State:
9039  *    none
9040  *
9041  * Description:
9042  *     Input an ASC_QDONE_INFO structure from the chip
9043  */
9044 static void
9045 DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
9046 {
9047         int i;
9048         ushort word;
9049
9050         AscSetChipLramAddr(iop_base, s_addr);
9051         for (i = 0; i < 2 * words; i += 2) {
9052                 if (i == 10) {
9053                         continue;
9054                 }
9055                 word = inpw(iop_base + IOP_RAM_DATA);
9056                 inbuf[i] = word & 0xff;
9057                 inbuf[i + 1] = (word >> 8) & 0xff;
9058         }
9059         ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
9060 }
9061
9062 static uchar
9063 _AscCopyLramScsiDoneQ(PortAddr iop_base,
9064                       ushort q_addr,
9065                       ASC_QDONE_INFO *scsiq, ASC_DCNT max_dma_count)
9066 {
9067         ushort _val;
9068         uchar sg_queue_cnt;
9069
9070         DvcGetQinfo(iop_base,
9071                     q_addr + ASC_SCSIQ_DONE_INFO_BEG,
9072                     (uchar *)scsiq,
9073                     (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2);
9074
9075         _val = AscReadLramWord(iop_base,
9076                                (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS));
9077         scsiq->q_status = (uchar)_val;
9078         scsiq->q_no = (uchar)(_val >> 8);
9079         _val = AscReadLramWord(iop_base,
9080                                (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL));
9081         scsiq->cntl = (uchar)_val;
9082         sg_queue_cnt = (uchar)(_val >> 8);
9083         _val = AscReadLramWord(iop_base,
9084                                (ushort)(q_addr +
9085                                         (ushort)ASC_SCSIQ_B_SENSE_LEN));
9086         scsiq->sense_len = (uchar)_val;
9087         scsiq->extra_bytes = (uchar)(_val >> 8);
9088
9089         /*
9090          * Read high word of remain bytes from alternate location.
9091          */
9092         scsiq->remain_bytes = (((ADV_DCNT)AscReadLramWord(iop_base,
9093                                                           (ushort)(q_addr +
9094                                                                    (ushort)
9095                                                                    ASC_SCSIQ_W_ALT_DC1)))
9096                                << 16);
9097         /*
9098          * Read low word of remain bytes from original location.
9099          */
9100         scsiq->remain_bytes += AscReadLramWord(iop_base,
9101                                                (ushort)(q_addr + (ushort)
9102                                                         ASC_SCSIQ_DW_REMAIN_XFER_CNT));
9103
9104         scsiq->remain_bytes &= max_dma_count;
9105         return sg_queue_cnt;
9106 }
9107
9108 /*
9109  * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
9110  *
9111  * Interrupt callback function for the Narrow SCSI Asc Library.
9112  */
9113 static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
9114 {
9115         struct asc_board *boardp;
9116         struct scsi_cmnd *scp;
9117         struct Scsi_Host *shost;
9118
9119         ASC_DBG(1, "asc_dvc_varp 0x%p, qdonep 0x%p\n", asc_dvc_varp, qdonep);
9120         ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
9121
9122         scp = advansys_srb_to_ptr(asc_dvc_varp, qdonep->d2.srb_ptr);
9123         if (!scp)
9124                 return;
9125
9126         ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
9127
9128         shost = scp->device->host;
9129         ASC_STATS(shost, callback);
9130         ASC_DBG(1, "shost 0x%p\n", shost);
9131
9132         boardp = shost_priv(shost);
9133         BUG_ON(asc_dvc_varp != &boardp->dvc_var.asc_dvc_var);
9134
9135         dma_unmap_single(boardp->dev, scp->SCp.dma_handle,
9136                         sizeof(scp->sense_buffer), DMA_FROM_DEVICE);
9137         /*
9138          * 'qdonep' contains the command's ending status.
9139          */
9140         switch (qdonep->d3.done_stat) {
9141         case QD_NO_ERROR:
9142                 ASC_DBG(2, "QD_NO_ERROR\n");
9143                 scp->result = 0;
9144
9145                 /*
9146                  * Check for an underrun condition.
9147                  *
9148                  * If there was no error and an underrun condition, then
9149                  * return the number of underrun bytes.
9150                  */
9151                 if (scsi_bufflen(scp) != 0 && qdonep->remain_bytes != 0 &&
9152                     qdonep->remain_bytes <= scsi_bufflen(scp)) {
9153                         ASC_DBG(1, "underrun condition %u bytes\n",
9154                                  (unsigned)qdonep->remain_bytes);
9155                         scsi_set_resid(scp, qdonep->remain_bytes);
9156                 }
9157                 break;
9158
9159         case QD_WITH_ERROR:
9160                 ASC_DBG(2, "QD_WITH_ERROR\n");
9161                 switch (qdonep->d3.host_stat) {
9162                 case QHSTA_NO_ERROR:
9163                         if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
9164                                 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
9165                                 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
9166                                                   sizeof(scp->sense_buffer));
9167                                 /*
9168                                  * Note: The 'status_byte()' macro used by
9169                                  * target drivers defined in scsi.h shifts the
9170                                  * status byte returned by host drivers right
9171                                  * by 1 bit.  This is why target drivers also
9172                                  * use right shifted status byte definitions.
9173                                  * For instance target drivers use
9174                                  * CHECK_CONDITION, defined to 0x1, instead of
9175                                  * the SCSI defined check condition value of
9176                                  * 0x2. Host drivers are supposed to return
9177                                  * the status byte as it is defined by SCSI.
9178                                  */
9179                                 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
9180                                     STATUS_BYTE(qdonep->d3.scsi_stat);
9181                         } else {
9182                                 scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
9183                         }
9184                         break;
9185
9186                 default:
9187                         /* QHSTA error occurred */
9188                         ASC_DBG(1, "host_stat 0x%x\n", qdonep->d3.host_stat);
9189                         scp->result = HOST_BYTE(DID_BAD_TARGET);
9190                         break;
9191                 }
9192                 break;
9193
9194         case QD_ABORTED_BY_HOST:
9195                 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
9196                 scp->result =
9197                     HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.
9198                                                     scsi_msg) |
9199                     STATUS_BYTE(qdonep->d3.scsi_stat);
9200                 break;
9201
9202         default:
9203                 ASC_DBG(1, "done_stat 0x%x\n", qdonep->d3.done_stat);
9204                 scp->result =
9205                     HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.
9206                                                     scsi_msg) |
9207                     STATUS_BYTE(qdonep->d3.scsi_stat);
9208                 break;
9209         }
9210
9211         /*
9212          * If the 'init_tidmask' bit isn't already set for the target and the
9213          * current request finished normally, then set the bit for the target
9214          * to indicate that a device is present.
9215          */
9216         if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
9217             qdonep->d3.done_stat == QD_NO_ERROR &&
9218             qdonep->d3.host_stat == QHSTA_NO_ERROR) {
9219                 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
9220         }
9221
9222         asc_scsi_done(scp);
9223 }
9224
9225 static int AscIsrQDone(ASC_DVC_VAR *asc_dvc)
9226 {
9227         uchar next_qp;
9228         uchar n_q_used;
9229         uchar sg_list_qp;
9230         uchar sg_queue_cnt;
9231         uchar q_cnt;
9232         uchar done_q_tail;
9233         uchar tid_no;
9234         ASC_SCSI_BIT_ID_TYPE scsi_busy;
9235         ASC_SCSI_BIT_ID_TYPE target_id;
9236         PortAddr iop_base;
9237         ushort q_addr;
9238         ushort sg_q_addr;
9239         uchar cur_target_qng;
9240         ASC_QDONE_INFO scsiq_buf;
9241         ASC_QDONE_INFO *scsiq;
9242         int false_overrun;
9243
9244         iop_base = asc_dvc->iop_base;
9245         n_q_used = 1;
9246         scsiq = (ASC_QDONE_INFO *)&scsiq_buf;
9247         done_q_tail = (uchar)AscGetVarDoneQTail(iop_base);
9248         q_addr = ASC_QNO_TO_QADDR(done_q_tail);
9249         next_qp = AscReadLramByte(iop_base,
9250                                   (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD));
9251         if (next_qp != ASC_QLINK_END) {
9252                 AscPutVarDoneQTail(iop_base, next_qp);
9253                 q_addr = ASC_QNO_TO_QADDR(next_qp);
9254                 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
9255                                                      asc_dvc->max_dma_count);
9256                 AscWriteLramByte(iop_base,
9257                                  (ushort)(q_addr +
9258                                           (ushort)ASC_SCSIQ_B_STATUS),
9259                                  (uchar)(scsiq->
9260                                          q_status & (uchar)~(QS_READY |
9261                                                              QS_ABORTED)));
9262                 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
9263                 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
9264                 if ((scsiq->cntl & QC_SG_HEAD) != 0) {
9265                         sg_q_addr = q_addr;
9266                         sg_list_qp = next_qp;
9267                         for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
9268                                 sg_list_qp = AscReadLramByte(iop_base,
9269                                                              (ushort)(sg_q_addr
9270                                                                       + (ushort)
9271                                                                       ASC_SCSIQ_B_FWD));
9272                                 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
9273                                 if (sg_list_qp == ASC_QLINK_END) {
9274                                         AscSetLibErrorCode(asc_dvc,
9275                                                            ASCQ_ERR_SG_Q_LINKS);
9276                                         scsiq->d3.done_stat = QD_WITH_ERROR;
9277                                         scsiq->d3.host_stat =
9278                                             QHSTA_D_QDONE_SG_LIST_CORRUPTED;
9279                                         goto FATAL_ERR_QDONE;
9280                                 }
9281                                 AscWriteLramByte(iop_base,
9282                                                  (ushort)(sg_q_addr + (ushort)
9283                                                           ASC_SCSIQ_B_STATUS),
9284                                                  QS_FREE);
9285                         }
9286                         n_q_used = sg_queue_cnt + 1;
9287                         AscPutVarDoneQTail(iop_base, sg_list_qp);
9288                 }
9289                 if (asc_dvc->queue_full_or_busy & target_id) {
9290                         cur_target_qng = AscReadLramByte(iop_base,
9291                                                          (ushort)((ushort)
9292                                                                   ASC_QADR_BEG
9293                                                                   + (ushort)
9294                                                                   scsiq->d2.
9295                                                                   target_ix));
9296                         if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
9297                                 scsi_busy = AscReadLramByte(iop_base, (ushort)
9298                                                             ASCV_SCSIBUSY_B);
9299                                 scsi_busy &= ~target_id;
9300                                 AscWriteLramByte(iop_base,
9301                                                  (ushort)ASCV_SCSIBUSY_B,
9302                                                  scsi_busy);
9303                                 asc_dvc->queue_full_or_busy &= ~target_id;
9304                         }
9305                 }
9306                 if (asc_dvc->cur_total_qng >= n_q_used) {
9307                         asc_dvc->cur_total_qng -= n_q_used;
9308                         if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
9309                                 asc_dvc->cur_dvc_qng[tid_no]--;
9310                         }
9311                 } else {
9312                         AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
9313                         scsiq->d3.done_stat = QD_WITH_ERROR;
9314                         goto FATAL_ERR_QDONE;
9315                 }
9316                 if ((scsiq->d2.srb_ptr == 0UL) ||
9317                     ((scsiq->q_status & QS_ABORTED) != 0)) {
9318                         return (0x11);
9319                 } else if (scsiq->q_status == QS_DONE) {
9320                         false_overrun = FALSE;
9321                         if (scsiq->extra_bytes != 0) {
9322                                 scsiq->remain_bytes +=
9323                                     (ADV_DCNT)scsiq->extra_bytes;
9324                         }
9325                         if (scsiq->d3.done_stat == QD_WITH_ERROR) {
9326                                 if (scsiq->d3.host_stat ==
9327                                     QHSTA_M_DATA_OVER_RUN) {
9328                                         if ((scsiq->
9329                                              cntl & (QC_DATA_IN | QC_DATA_OUT))
9330                                             == 0) {
9331                                                 scsiq->d3.done_stat =
9332                                                     QD_NO_ERROR;
9333                                                 scsiq->d3.host_stat =
9334                                                     QHSTA_NO_ERROR;
9335                                         } else if (false_overrun) {
9336                                                 scsiq->d3.done_stat =
9337                                                     QD_NO_ERROR;
9338                                                 scsiq->d3.host_stat =
9339                                                     QHSTA_NO_ERROR;
9340                                         }
9341                                 } else if (scsiq->d3.host_stat ==
9342                                            QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
9343                                         AscStopChip(iop_base);
9344                                         AscSetChipControl(iop_base,
9345                                                           (uchar)(CC_SCSI_RESET
9346                                                                   | CC_HALT));
9347                                         udelay(60);
9348                                         AscSetChipControl(iop_base, CC_HALT);
9349                                         AscSetChipStatus(iop_base,
9350                                                          CIW_CLR_SCSI_RESET_INT);
9351                                         AscSetChipStatus(iop_base, 0);
9352                                         AscSetChipControl(iop_base, 0);
9353                                 }
9354                         }
9355                         if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
9356                                 asc_isr_callback(asc_dvc, scsiq);
9357                         } else {
9358                                 if ((AscReadLramByte(iop_base,
9359                                                      (ushort)(q_addr + (ushort)
9360                                                               ASC_SCSIQ_CDB_BEG))
9361                                      == START_STOP)) {
9362                                         asc_dvc->unit_not_ready &= ~target_id;
9363                                         if (scsiq->d3.done_stat != QD_NO_ERROR) {
9364                                                 asc_dvc->start_motor &=
9365                                                     ~target_id;
9366                                         }
9367                                 }
9368                         }
9369                         return (1);
9370                 } else {
9371                         AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
9372  FATAL_ERR_QDONE:
9373                         if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
9374                                 asc_isr_callback(asc_dvc, scsiq);
9375                         }
9376                         return (0x80);
9377                 }
9378         }
9379         return (0);
9380 }
9381
9382 static int AscISR(ASC_DVC_VAR *asc_dvc)
9383 {
9384         ASC_CS_TYPE chipstat;
9385         PortAddr iop_base;
9386         ushort saved_ram_addr;
9387         uchar ctrl_reg;
9388         uchar saved_ctrl_reg;
9389         int int_pending;
9390         int status;
9391         uchar host_flag;
9392
9393         iop_base = asc_dvc->iop_base;
9394         int_pending = FALSE;
9395
9396         if (AscIsIntPending(iop_base) == 0)
9397                 return int_pending;
9398
9399         if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) {
9400                 return ERR;
9401         }
9402         if (asc_dvc->in_critical_cnt != 0) {
9403                 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
9404                 return ERR;
9405         }
9406         if (asc_dvc->is_in_int) {
9407                 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
9408                 return ERR;
9409         }
9410         asc_dvc->is_in_int = TRUE;
9411         ctrl_reg = AscGetChipControl(iop_base);
9412         saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
9413                                        CC_SINGLE_STEP | CC_DIAG | CC_TEST));
9414         chipstat = AscGetChipStatus(iop_base);
9415         if (chipstat & CSW_SCSI_RESET_LATCH) {
9416                 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
9417                         int i = 10;
9418                         int_pending = TRUE;
9419                         asc_dvc->sdtr_done = 0;
9420                         saved_ctrl_reg &= (uchar)(~CC_HALT);
9421                         while ((AscGetChipStatus(iop_base) &
9422                                 CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) {
9423                                 mdelay(100);
9424                         }
9425                         AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
9426                         AscSetChipControl(iop_base, CC_HALT);
9427                         AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
9428                         AscSetChipStatus(iop_base, 0);
9429                         chipstat = AscGetChipStatus(iop_base);
9430                 }
9431         }
9432         saved_ram_addr = AscGetChipLramAddr(iop_base);
9433         host_flag = AscReadLramByte(iop_base,
9434                                     ASCV_HOST_FLAG_B) &
9435             (uchar)(~ASC_HOST_FLAG_IN_ISR);
9436         AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
9437                          (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR));
9438         if ((chipstat & CSW_INT_PENDING) || (int_pending)) {
9439                 AscAckInterrupt(iop_base);
9440                 int_pending = TRUE;
9441                 if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) {
9442                         if (AscIsrChipHalted(asc_dvc) == ERR) {
9443                                 goto ISR_REPORT_QDONE_FATAL_ERROR;
9444                         } else {
9445                                 saved_ctrl_reg &= (uchar)(~CC_HALT);
9446                         }
9447                 } else {
9448  ISR_REPORT_QDONE_FATAL_ERROR:
9449                         if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
9450                                 while (((status =
9451                                          AscIsrQDone(asc_dvc)) & 0x01) != 0) {
9452                                 }
9453                         } else {
9454                                 do {
9455                                         if ((status =
9456                                              AscIsrQDone(asc_dvc)) == 1) {
9457                                                 break;
9458                                         }
9459                                 } while (status == 0x11);
9460                         }
9461                         if ((status & 0x80) != 0)
9462                                 int_pending = ERR;
9463                 }
9464         }
9465         AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
9466         AscSetChipLramAddr(iop_base, saved_ram_addr);
9467         AscSetChipControl(iop_base, saved_ctrl_reg);
9468         asc_dvc->is_in_int = FALSE;
9469         return int_pending;
9470 }
9471
9472 /*
9473  * advansys_reset()
9474  *
9475  * Reset the bus associated with the command 'scp'.
9476  *
9477  * This function runs its own thread. Interrupts must be blocked but
9478  * sleeping is allowed and no locking other than for host structures is
9479  * required. Returns SUCCESS or FAILED.
9480  */
9481 static int advansys_reset(struct scsi_cmnd *scp)
9482 {
9483         struct Scsi_Host *shost = scp->device->host;
9484         struct asc_board *boardp = shost_priv(shost);
9485         unsigned long flags;
9486         int status;
9487         int ret = SUCCESS;
9488
9489         ASC_DBG(1, "0x%p\n", scp);
9490
9491         ASC_STATS(shost, reset);
9492
9493         scmd_printk(KERN_INFO, scp, "SCSI bus reset started...\n");
9494
9495         if (ASC_NARROW_BOARD(boardp)) {
9496                 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
9497
9498                 /* Reset the chip and SCSI bus. */
9499                 ASC_DBG(1, "before AscInitAsc1000Driver()\n");
9500                 status = AscInitAsc1000Driver(asc_dvc);
9501
9502                 /* Refer to ASC_IERR_* defintions for meaning of 'err_code'. */
9503                 if (asc_dvc->err_code) {
9504                         scmd_printk(KERN_INFO, scp, "SCSI bus reset error: "
9505                                     "0x%x\n", asc_dvc->err_code);
9506                         ret = FAILED;
9507                 } else if (status) {
9508                         scmd_printk(KERN_INFO, scp, "SCSI bus reset warning: "
9509                                     "0x%x\n", status);
9510                 } else {
9511                         scmd_printk(KERN_INFO, scp, "SCSI bus reset "
9512                                     "successful\n");
9513                 }
9514
9515                 ASC_DBG(1, "after AscInitAsc1000Driver()\n");
9516                 spin_lock_irqsave(shost->host_lock, flags);
9517         } else {
9518                 /*
9519                  * If the suggest reset bus flags are set, then reset the bus.
9520                  * Otherwise only reset the device.
9521                  */
9522                 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
9523
9524                 /*
9525                  * Reset the target's SCSI bus.
9526                  */
9527                 ASC_DBG(1, "before AdvResetChipAndSB()\n");
9528                 switch (AdvResetChipAndSB(adv_dvc)) {
9529                 case ASC_TRUE:
9530                         scmd_printk(KERN_INFO, scp, "SCSI bus reset "
9531                                     "successful\n");
9532                         break;
9533                 case ASC_FALSE:
9534                 default:
9535                         scmd_printk(KERN_INFO, scp, "SCSI bus reset error\n");
9536                         ret = FAILED;
9537                         break;
9538                 }
9539                 spin_lock_irqsave(shost->host_lock, flags);
9540                 AdvISR(adv_dvc);
9541         }
9542
9543         /* Save the time of the most recently completed reset. */
9544         boardp->last_reset = jiffies;
9545         spin_unlock_irqrestore(shost->host_lock, flags);
9546
9547         ASC_DBG(1, "ret %d\n", ret);
9548
9549         return ret;
9550 }
9551
9552 /*
9553  * advansys_biosparam()
9554  *
9555  * Translate disk drive geometry if the "BIOS greater than 1 GB"
9556  * support is enabled for a drive.
9557  *
9558  * ip (information pointer) is an int array with the following definition:
9559  * ip[0]: heads
9560  * ip[1]: sectors
9561  * ip[2]: cylinders
9562  */
9563 static int
9564 advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
9565                    sector_t capacity, int ip[])
9566 {
9567         struct asc_board *boardp = shost_priv(sdev->host);
9568
9569         ASC_DBG(1, "begin\n");
9570         ASC_STATS(sdev->host, biosparam);
9571         if (ASC_NARROW_BOARD(boardp)) {
9572                 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
9573                      ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
9574                         ip[0] = 255;
9575                         ip[1] = 63;
9576                 } else {
9577                         ip[0] = 64;
9578                         ip[1] = 32;
9579                 }
9580         } else {
9581                 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
9582                      BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
9583                         ip[0] = 255;
9584                         ip[1] = 63;
9585                 } else {
9586                         ip[0] = 64;
9587                         ip[1] = 32;
9588                 }
9589         }
9590         ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
9591         ASC_DBG(1, "end\n");
9592         return 0;
9593 }
9594
9595 /*
9596  * First-level interrupt handler.
9597  *
9598  * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host.
9599  */
9600 static irqreturn_t advansys_interrupt(int irq, void *dev_id)
9601 {
9602         struct Scsi_Host *shost = dev_id;
9603         struct asc_board *boardp = shost_priv(shost);
9604         irqreturn_t result = IRQ_NONE;
9605
9606         ASC_DBG(2, "boardp 0x%p\n", boardp);
9607         spin_lock(shost->host_lock);
9608         if (ASC_NARROW_BOARD(boardp)) {
9609                 if (AscIsIntPending(shost->io_port)) {
9610                         result = IRQ_HANDLED;
9611                         ASC_STATS(shost, interrupt);
9612                         ASC_DBG(1, "before AscISR()\n");
9613                         AscISR(&boardp->dvc_var.asc_dvc_var);
9614                 }
9615         } else {
9616                 ASC_DBG(1, "before AdvISR()\n");
9617                 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
9618                         result = IRQ_HANDLED;
9619                         ASC_STATS(shost, interrupt);
9620                 }
9621         }
9622         spin_unlock(shost->host_lock);
9623
9624         ASC_DBG(1, "end\n");
9625         return result;
9626 }
9627
9628 static int AscHostReqRiscHalt(PortAddr iop_base)
9629 {
9630         int count = 0;
9631         int sta = 0;
9632         uchar saved_stop_code;
9633
9634         if (AscIsChipHalted(iop_base))
9635                 return (1);
9636         saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B);
9637         AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
9638                          ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP);
9639         do {
9640                 if (AscIsChipHalted(iop_base)) {
9641                         sta = 1;
9642                         break;
9643                 }
9644                 mdelay(100);
9645         } while (count++ < 20);
9646         AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code);
9647         return (sta);
9648 }
9649
9650 static int
9651 AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data)
9652 {
9653         int sta = FALSE;
9654
9655         if (AscHostReqRiscHalt(iop_base)) {
9656                 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
9657                 AscStartChip(iop_base);
9658         }
9659         return sta;
9660 }
9661
9662 static void AscAsyncFix(ASC_DVC_VAR *asc_dvc, struct scsi_device *sdev)
9663 {
9664         char type = sdev->type;
9665         ASC_SCSI_BIT_ID_TYPE tid_bits = 1 << sdev->id;
9666
9667         if (!(asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN))
9668                 return;
9669         if (asc_dvc->init_sdtr & tid_bits)
9670                 return;
9671
9672         if ((type == TYPE_ROM) && (strncmp(sdev->vendor, "HP ", 3) == 0))
9673                 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits;
9674
9675         asc_dvc->pci_fix_asyn_xfer |= tid_bits;
9676         if ((type == TYPE_PROCESSOR) || (type == TYPE_SCANNER) ||
9677             (type == TYPE_ROM) || (type == TYPE_TAPE))
9678                 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits;
9679
9680         if (asc_dvc->pci_fix_asyn_xfer & tid_bits)
9681                 AscSetRunChipSynRegAtID(asc_dvc->iop_base, sdev->id,
9682                                         ASYN_SDTR_DATA_FIX_PCI_REV_AB);
9683 }
9684
9685 static void
9686 advansys_narrow_slave_configure(struct scsi_device *sdev, ASC_DVC_VAR *asc_dvc)
9687 {
9688         ASC_SCSI_BIT_ID_TYPE tid_bit = 1 << sdev->id;
9689         ASC_SCSI_BIT_ID_TYPE orig_use_tagged_qng = asc_dvc->use_tagged_qng;
9690
9691         if (sdev->lun == 0) {
9692                 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr = asc_dvc->init_sdtr;
9693                 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && sdev->sdtr) {
9694                         asc_dvc->init_sdtr |= tid_bit;
9695                 } else {
9696                         asc_dvc->init_sdtr &= ~tid_bit;
9697                 }
9698
9699                 if (orig_init_sdtr != asc_dvc->init_sdtr)
9700                         AscAsyncFix(asc_dvc, sdev);
9701         }
9702
9703         if (sdev->tagged_supported) {
9704                 if (asc_dvc->cfg->cmd_qng_enabled & tid_bit) {
9705                         if (sdev->lun == 0) {
9706                                 asc_dvc->cfg->can_tagged_qng |= tid_bit;
9707                                 asc_dvc->use_tagged_qng |= tid_bit;
9708                         }
9709                         scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG,
9710                                                 asc_dvc->max_dvc_qng[sdev->id]);
9711                 }
9712         } else {
9713                 if (sdev->lun == 0) {
9714                         asc_dvc->cfg->can_tagged_qng &= ~tid_bit;
9715                         asc_dvc->use_tagged_qng &= ~tid_bit;
9716                 }
9717                 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
9718         }
9719
9720         if ((sdev->lun == 0) &&
9721             (orig_use_tagged_qng != asc_dvc->use_tagged_qng)) {
9722                 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B,
9723                                  asc_dvc->cfg->disc_enable);
9724                 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B,
9725                                  asc_dvc->use_tagged_qng);
9726                 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B,
9727                                  asc_dvc->cfg->can_tagged_qng);
9728
9729                 asc_dvc->max_dvc_qng[sdev->id] =
9730                                         asc_dvc->cfg->max_tag_qng[sdev->id];
9731                 AscWriteLramByte(asc_dvc->iop_base,
9732                                  (ushort)(ASCV_MAX_DVC_QNG_BEG + sdev->id),
9733                                  asc_dvc->max_dvc_qng[sdev->id]);
9734         }
9735 }
9736
9737 /*
9738  * Wide Transfers
9739  *
9740  * If the EEPROM enabled WDTR for the device and the device supports wide
9741  * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and
9742  * write the new value to the microcode.
9743  */
9744 static void
9745 advansys_wide_enable_wdtr(AdvPortAddr iop_base, unsigned short tidmask)
9746 {
9747         unsigned short cfg_word;
9748         AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
9749         if ((cfg_word & tidmask) != 0)
9750                 return;
9751
9752         cfg_word |= tidmask;
9753         AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
9754
9755         /*
9756          * Clear the microcode SDTR and WDTR negotiation done indicators for
9757          * the target to cause it to negotiate with the new setting set above.
9758          * WDTR when accepted causes the target to enter asynchronous mode, so
9759          * SDTR must be negotiated.
9760          */
9761         AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
9762         cfg_word &= ~tidmask;
9763         AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
9764         AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
9765         cfg_word &= ~tidmask;
9766         AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
9767 }
9768
9769 /*
9770  * Synchronous Transfers
9771  *
9772  * If the EEPROM enabled SDTR for the device and the device
9773  * supports synchronous transfers, then turn on the device's
9774  * 'sdtr_able' bit. Write the new value to the microcode.
9775  */
9776 static void
9777 advansys_wide_enable_sdtr(AdvPortAddr iop_base, unsigned short tidmask)
9778 {
9779         unsigned short cfg_word;
9780         AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
9781         if ((cfg_word & tidmask) != 0)
9782                 return;
9783
9784         cfg_word |= tidmask;
9785         AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
9786
9787         /*
9788          * Clear the microcode "SDTR negotiation" done indicator for the
9789          * target to cause it to negotiate with the new setting set above.
9790          */
9791         AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
9792         cfg_word &= ~tidmask;
9793         AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
9794 }
9795
9796 /*
9797  * PPR (Parallel Protocol Request) Capable
9798  *
9799  * If the device supports DT mode, then it must be PPR capable.
9800  * The PPR message will be used in place of the SDTR and WDTR
9801  * messages to negotiate synchronous speed and offset, transfer
9802  * width, and protocol options.
9803  */
9804 static void advansys_wide_enable_ppr(ADV_DVC_VAR *adv_dvc,
9805                                 AdvPortAddr iop_base, unsigned short tidmask)
9806 {
9807         AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
9808         adv_dvc->ppr_able |= tidmask;
9809         AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
9810 }
9811
9812 static void
9813 advansys_wide_slave_configure(struct scsi_device *sdev, ADV_DVC_VAR *adv_dvc)
9814 {
9815         AdvPortAddr iop_base = adv_dvc->iop_base;
9816         unsigned short tidmask = 1 << sdev->id;
9817
9818         if (sdev->lun == 0) {
9819                 /*
9820                  * Handle WDTR, SDTR, and Tag Queuing. If the feature
9821                  * is enabled in the EEPROM and the device supports the
9822                  * feature, then enable it in the microcode.
9823                  */
9824
9825                 if ((adv_dvc->wdtr_able & tidmask) && sdev->wdtr)
9826                         advansys_wide_enable_wdtr(iop_base, tidmask);
9827                 if ((adv_dvc->sdtr_able & tidmask) && sdev->sdtr)
9828                         advansys_wide_enable_sdtr(iop_base, tidmask);
9829                 if (adv_dvc->chip_type == ADV_CHIP_ASC38C1600 && sdev->ppr)
9830                         advansys_wide_enable_ppr(adv_dvc, iop_base, tidmask);
9831
9832                 /*
9833                  * Tag Queuing is disabled for the BIOS which runs in polled
9834                  * mode and would see no benefit from Tag Queuing. Also by
9835                  * disabling Tag Queuing in the BIOS devices with Tag Queuing
9836                  * bugs will at least work with the BIOS.
9837                  */
9838                 if ((adv_dvc->tagqng_able & tidmask) &&
9839                     sdev->tagged_supported) {
9840                         unsigned short cfg_word;
9841                         AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
9842                         cfg_word |= tidmask;
9843                         AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
9844                                          cfg_word);
9845                         AdvWriteByteLram(iop_base,
9846                                          ASC_MC_NUMBER_OF_MAX_CMD + sdev->id,
9847                                          adv_dvc->max_dvc_qng);
9848                 }
9849         }
9850
9851         if ((adv_dvc->tagqng_able & tidmask) && sdev->tagged_supported) {
9852                 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG,
9853                                         adv_dvc->max_dvc_qng);
9854         } else {
9855                 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
9856         }
9857 }
9858
9859 /*
9860  * Set the number of commands to queue per device for the
9861  * specified host adapter.
9862  */
9863 static int advansys_slave_configure(struct scsi_device *sdev)
9864 {
9865         struct asc_board *boardp = shost_priv(sdev->host);
9866
9867         if (ASC_NARROW_BOARD(boardp))
9868                 advansys_narrow_slave_configure(sdev,
9869                                                 &boardp->dvc_var.asc_dvc_var);
9870         else
9871                 advansys_wide_slave_configure(sdev,
9872                                                 &boardp->dvc_var.adv_dvc_var);
9873
9874         return 0;
9875 }
9876
9877 static __le32 advansys_get_sense_buffer_dma(struct scsi_cmnd *scp)
9878 {
9879         struct asc_board *board = shost_priv(scp->device->host);
9880         scp->SCp.dma_handle = dma_map_single(board->dev, scp->sense_buffer,
9881                                 sizeof(scp->sense_buffer), DMA_FROM_DEVICE);
9882         dma_cache_sync(board->dev, scp->sense_buffer,
9883                                 sizeof(scp->sense_buffer), DMA_FROM_DEVICE);
9884         return cpu_to_le32(scp->SCp.dma_handle);
9885 }
9886
9887 static int asc_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
9888                         struct asc_scsi_q *asc_scsi_q)
9889 {
9890         struct asc_dvc_var *asc_dvc = &boardp->dvc_var.asc_dvc_var;
9891         int use_sg;
9892
9893         memset(asc_scsi_q, 0, sizeof(*asc_scsi_q));
9894
9895         /*
9896          * Point the ASC_SCSI_Q to the 'struct scsi_cmnd'.
9897          */
9898         asc_scsi_q->q2.srb_ptr = advansys_ptr_to_srb(asc_dvc, scp);
9899         if (asc_scsi_q->q2.srb_ptr == BAD_SRB) {
9900                 scp->result = HOST_BYTE(DID_SOFT_ERROR);
9901                 return ASC_ERROR;
9902         }
9903
9904         /*
9905          * Build the ASC_SCSI_Q request.
9906          */
9907         asc_scsi_q->cdbptr = &scp->cmnd[0];
9908         asc_scsi_q->q2.cdb_len = scp->cmd_len;
9909         asc_scsi_q->q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id);
9910         asc_scsi_q->q1.target_lun = scp->device->lun;
9911         asc_scsi_q->q2.target_ix =
9912             ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun);
9913         asc_scsi_q->q1.sense_addr = advansys_get_sense_buffer_dma(scp);
9914         asc_scsi_q->q1.sense_len = sizeof(scp->sense_buffer);
9915
9916         /*
9917          * If there are any outstanding requests for the current target,
9918          * then every 255th request send an ORDERED request. This heuristic
9919          * tries to retain the benefit of request sorting while preventing
9920          * request starvation. 255 is the max number of tags or pending commands
9921          * a device may have outstanding.
9922          *
9923          * The request count is incremented below for every successfully
9924          * started request.
9925          *
9926          */
9927         if ((asc_dvc->cur_dvc_qng[scp->device->id] > 0) &&
9928             (boardp->reqcnt[scp->device->id] % 255) == 0) {
9929                 asc_scsi_q->q2.tag_code = MSG_ORDERED_TAG;
9930         } else {
9931                 asc_scsi_q->q2.tag_code = MSG_SIMPLE_TAG;
9932         }
9933
9934         /* Build ASC_SCSI_Q */
9935         use_sg = scsi_dma_map(scp);
9936         if (use_sg != 0) {
9937                 int sgcnt;
9938                 struct scatterlist *slp;
9939                 struct asc_sg_head *asc_sg_head;
9940
9941                 if (use_sg > scp->device->host->sg_tablesize) {
9942                         scmd_printk(KERN_ERR, scp, "use_sg %d > "
9943                                 "sg_tablesize %d\n", use_sg,
9944                                 scp->device->host->sg_tablesize);
9945                         scsi_dma_unmap(scp);
9946                         scp->result = HOST_BYTE(DID_ERROR);
9947                         return ASC_ERROR;
9948                 }
9949
9950                 asc_sg_head = kzalloc(sizeof(asc_scsi_q->sg_head) +
9951                         use_sg * sizeof(struct asc_sg_list), GFP_ATOMIC);
9952                 if (!asc_sg_head) {
9953                         scsi_dma_unmap(scp);
9954                         scp->result = HOST_BYTE(DID_SOFT_ERROR);
9955                         return ASC_ERROR;
9956                 }
9957
9958                 asc_scsi_q->q1.cntl |= QC_SG_HEAD;
9959                 asc_scsi_q->sg_head = asc_sg_head;
9960                 asc_scsi_q->q1.data_cnt = 0;
9961                 asc_scsi_q->q1.data_addr = 0;
9962                 /* This is a byte value, otherwise it would need to be swapped. */
9963                 asc_sg_head->entry_cnt = asc_scsi_q->q1.sg_queue_cnt = use_sg;
9964                 ASC_STATS_ADD(scp->device->host, xfer_elem,
9965                               asc_sg_head->entry_cnt);
9966
9967                 /*
9968                  * Convert scatter-gather list into ASC_SG_HEAD list.
9969                  */
9970                 scsi_for_each_sg(scp, slp, use_sg, sgcnt) {
9971                         asc_sg_head->sg_list[sgcnt].addr =
9972                             cpu_to_le32(sg_dma_address(slp));
9973                         asc_sg_head->sg_list[sgcnt].bytes =
9974                             cpu_to_le32(sg_dma_len(slp));
9975                         ASC_STATS_ADD(scp->device->host, xfer_sect,
9976                                       DIV_ROUND_UP(sg_dma_len(slp), 512));
9977                 }
9978         }
9979
9980         ASC_STATS(scp->device->host, xfer_cnt);
9981
9982         ASC_DBG_PRT_ASC_SCSI_Q(2, asc_scsi_q);
9983         ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
9984
9985         return ASC_NOERROR;
9986 }
9987
9988 /*
9989  * Build scatter-gather list for Adv Library (Wide Board).
9990  *
9991  * Additional ADV_SG_BLOCK structures will need to be allocated
9992  * if the total number of scatter-gather elements exceeds
9993  * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
9994  * assumed to be physically contiguous.
9995  *
9996  * Return:
9997  *      ADV_SUCCESS(1) - SG List successfully created
9998  *      ADV_ERROR(-1) - SG List creation failed
9999  */
10000 static int
10001 adv_get_sglist(struct asc_board *boardp, adv_req_t *reqp, struct scsi_cmnd *scp,
10002                int use_sg)
10003 {
10004         adv_sgblk_t *sgblkp;
10005         ADV_SCSI_REQ_Q *scsiqp;
10006         struct scatterlist *slp;
10007         int sg_elem_cnt;
10008         ADV_SG_BLOCK *sg_block, *prev_sg_block;
10009         ADV_PADDR sg_block_paddr;
10010         int i;
10011
10012         scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
10013         slp = scsi_sglist(scp);
10014         sg_elem_cnt = use_sg;
10015         prev_sg_block = NULL;
10016         reqp->sgblkp = NULL;
10017
10018         for (;;) {
10019                 /*
10020                  * Allocate a 'adv_sgblk_t' structure from the board free
10021                  * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
10022                  * (15) scatter-gather elements.
10023                  */
10024                 if ((sgblkp = boardp->adv_sgblkp) == NULL) {
10025                         ASC_DBG(1, "no free adv_sgblk_t\n");
10026                         ASC_STATS(scp->device->host, adv_build_nosg);
10027
10028                         /*
10029                          * Allocation failed. Free 'adv_sgblk_t' structures
10030                          * already allocated for the request.
10031                          */
10032                         while ((sgblkp = reqp->sgblkp) != NULL) {
10033                                 /* Remove 'sgblkp' from the request list. */
10034                                 reqp->sgblkp = sgblkp->next_sgblkp;
10035
10036                                 /* Add 'sgblkp' to the board free list. */
10037                                 sgblkp->next_sgblkp = boardp->adv_sgblkp;
10038                                 boardp->adv_sgblkp = sgblkp;
10039                         }
10040                         return ASC_BUSY;
10041                 }
10042
10043                 /* Complete 'adv_sgblk_t' board allocation. */
10044                 boardp->adv_sgblkp = sgblkp->next_sgblkp;
10045                 sgblkp->next_sgblkp = NULL;
10046
10047                 /*
10048                  * Get 8 byte aligned virtual and physical addresses
10049                  * for the allocated ADV_SG_BLOCK structure.
10050                  */
10051                 sg_block = (ADV_SG_BLOCK *)ADV_8BALIGN(&sgblkp->sg_block);
10052                 sg_block_paddr = virt_to_bus(sg_block);
10053
10054                 /*
10055                  * Check if this is the first 'adv_sgblk_t' for the
10056                  * request.
10057                  */
10058                 if (reqp->sgblkp == NULL) {
10059                         /* Request's first scatter-gather block. */
10060                         reqp->sgblkp = sgblkp;
10061
10062                         /*
10063                          * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
10064                          * address pointers.
10065                          */
10066                         scsiqp->sg_list_ptr = sg_block;
10067                         scsiqp->sg_real_addr = cpu_to_le32(sg_block_paddr);
10068                 } else {
10069                         /* Request's second or later scatter-gather block. */
10070                         sgblkp->next_sgblkp = reqp->sgblkp;
10071                         reqp->sgblkp = sgblkp;
10072
10073                         /*
10074                          * Point the previous ADV_SG_BLOCK structure to
10075                          * the newly allocated ADV_SG_BLOCK structure.
10076                          */
10077                         prev_sg_block->sg_ptr = cpu_to_le32(sg_block_paddr);
10078                 }
10079
10080                 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
10081                         sg_block->sg_list[i].sg_addr =
10082                                         cpu_to_le32(sg_dma_address(slp));
10083                         sg_block->sg_list[i].sg_count =
10084                                         cpu_to_le32(sg_dma_len(slp));
10085                         ASC_STATS_ADD(scp->device->host, xfer_sect,
10086                                       DIV_ROUND_UP(sg_dma_len(slp), 512));
10087
10088                         if (--sg_elem_cnt == 0) {       /* Last ADV_SG_BLOCK and scatter-gather entry. */
10089                                 sg_block->sg_cnt = i + 1;
10090                                 sg_block->sg_ptr = 0L;  /* Last ADV_SG_BLOCK in list. */
10091                                 return ADV_SUCCESS;
10092                         }
10093                         slp++;
10094                 }
10095                 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
10096                 prev_sg_block = sg_block;
10097         }
10098 }
10099
10100 /*
10101  * Build a request structure for the Adv Library (Wide Board).
10102  *
10103  * If an adv_req_t can not be allocated to issue the request,
10104  * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
10105  *
10106  * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the
10107  * microcode for DMA addresses or math operations are byte swapped
10108  * to little-endian order.
10109  */
10110 static int
10111 adv_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
10112               ADV_SCSI_REQ_Q **adv_scsiqpp)
10113 {
10114         adv_req_t *reqp;
10115         ADV_SCSI_REQ_Q *scsiqp;
10116         int i;
10117         int ret;
10118         int use_sg;
10119
10120         /*
10121          * Allocate an adv_req_t structure from the board to execute
10122          * the command.
10123          */
10124         if (boardp->adv_reqp == NULL) {
10125                 ASC_DBG(1, "no free adv_req_t\n");
10126                 ASC_STATS(scp->device->host, adv_build_noreq);
10127                 return ASC_BUSY;
10128         } else {
10129                 reqp = boardp->adv_reqp;
10130                 boardp->adv_reqp = reqp->next_reqp;
10131                 reqp->next_reqp = NULL;
10132         }
10133
10134         /*
10135          * Get 32-byte aligned ADV_SCSI_REQ_Q and ADV_SG_BLOCK pointers.
10136          */
10137         scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
10138
10139         /*
10140          * Initialize the structure.
10141          */
10142         scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
10143
10144         /*
10145          * Set the ADV_SCSI_REQ_Q 'srb_ptr' to point to the adv_req_t structure.
10146          */
10147         scsiqp->srb_ptr = ADV_VADDR_TO_U32(reqp);
10148
10149         /*
10150          * Set the adv_req_t 'cmndp' to point to the struct scsi_cmnd structure.
10151          */
10152         reqp->cmndp = scp;
10153
10154         /*
10155          * Build the ADV_SCSI_REQ_Q request.
10156          */
10157
10158         /* Set CDB length and copy it to the request structure.  */
10159         scsiqp->cdb_len = scp->cmd_len;
10160         /* Copy first 12 CDB bytes to cdb[]. */
10161         for (i = 0; i < scp->cmd_len && i < 12; i++) {
10162                 scsiqp->cdb[i] = scp->cmnd[i];
10163         }
10164         /* Copy last 4 CDB bytes, if present, to cdb16[]. */
10165         for (; i < scp->cmd_len; i++) {
10166                 scsiqp->cdb16[i - 12] = scp->cmnd[i];
10167         }
10168
10169         scsiqp->target_id = scp->device->id;
10170         scsiqp->target_lun = scp->device->lun;
10171
10172         scsiqp->sense_addr = cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
10173         scsiqp->sense_len = sizeof(scp->sense_buffer);
10174
10175         /* Build ADV_SCSI_REQ_Q */
10176
10177         use_sg = scsi_dma_map(scp);
10178         if (use_sg == 0) {
10179                 /* Zero-length transfer */
10180                 reqp->sgblkp = NULL;
10181                 scsiqp->data_cnt = 0;
10182                 scsiqp->vdata_addr = NULL;
10183
10184                 scsiqp->data_addr = 0;
10185                 scsiqp->sg_list_ptr = NULL;
10186                 scsiqp->sg_real_addr = 0;
10187         } else {
10188                 if (use_sg > ADV_MAX_SG_LIST) {
10189                         scmd_printk(KERN_ERR, scp, "use_sg %d > "
10190                                    "ADV_MAX_SG_LIST %d\n", use_sg,
10191                                    scp->device->host->sg_tablesize);
10192                         scsi_dma_unmap(scp);
10193                         scp->result = HOST_BYTE(DID_ERROR);
10194
10195                         /*
10196                          * Free the 'adv_req_t' structure by adding it back
10197                          * to the board free list.
10198                          */
10199                         reqp->next_reqp = boardp->adv_reqp;
10200                         boardp->adv_reqp = reqp;
10201
10202                         return ASC_ERROR;
10203                 }
10204
10205                 scsiqp->data_cnt = cpu_to_le32(scsi_bufflen(scp));
10206
10207                 ret = adv_get_sglist(boardp, reqp, scp, use_sg);
10208                 if (ret != ADV_SUCCESS) {
10209                         /*
10210                          * Free the adv_req_t structure by adding it back to
10211                          * the board free list.
10212                          */
10213                         reqp->next_reqp = boardp->adv_reqp;
10214                         boardp->adv_reqp = reqp;
10215
10216                         return ret;
10217                 }
10218
10219                 ASC_STATS_ADD(scp->device->host, xfer_elem, use_sg);
10220         }
10221
10222         ASC_STATS(scp->device->host, xfer_cnt);
10223
10224         ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
10225         ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
10226
10227         *adv_scsiqpp = scsiqp;
10228
10229         return ASC_NOERROR;
10230 }
10231
10232 static int AscSgListToQueue(int sg_list)
10233 {
10234         int n_sg_list_qs;
10235
10236         n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
10237         if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
10238                 n_sg_list_qs++;
10239         return n_sg_list_qs + 1;
10240 }
10241
10242 static uint
10243 AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs)
10244 {
10245         uint cur_used_qs;
10246         uint cur_free_qs;
10247         ASC_SCSI_BIT_ID_TYPE target_id;
10248         uchar tid_no;
10249
10250         target_id = ASC_TIX_TO_TARGET_ID(target_ix);
10251         tid_no = ASC_TIX_TO_TID(target_ix);
10252         if ((asc_dvc->unit_not_ready & target_id) ||
10253             (asc_dvc->queue_full_or_busy & target_id)) {
10254                 return 0;
10255         }
10256         if (n_qs == 1) {
10257                 cur_used_qs = (uint) asc_dvc->cur_total_qng +
10258                     (uint) asc_dvc->last_q_shortage + (uint) ASC_MIN_FREE_Q;
10259         } else {
10260                 cur_used_qs = (uint) asc_dvc->cur_total_qng +
10261                     (uint) ASC_MIN_FREE_Q;
10262         }
10263         if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) {
10264                 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs;
10265                 if (asc_dvc->cur_dvc_qng[tid_no] >=
10266                     asc_dvc->max_dvc_qng[tid_no]) {
10267                         return 0;
10268                 }
10269                 return cur_free_qs;
10270         }
10271         if (n_qs > 1) {
10272                 if ((n_qs > asc_dvc->last_q_shortage)
10273                     && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) {
10274                         asc_dvc->last_q_shortage = n_qs;
10275                 }
10276         }
10277         return 0;
10278 }
10279
10280 static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head)
10281 {
10282         ushort q_addr;
10283         uchar next_qp;
10284         uchar q_status;
10285
10286         q_addr = ASC_QNO_TO_QADDR(free_q_head);
10287         q_status = (uchar)AscReadLramByte(iop_base,
10288                                           (ushort)(q_addr +
10289                                                    ASC_SCSIQ_B_STATUS));
10290         next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD));
10291         if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END))
10292                 return next_qp;
10293         return ASC_QLINK_END;
10294 }
10295
10296 static uchar
10297 AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q)
10298 {
10299         uchar i;
10300
10301         for (i = 0; i < n_free_q; i++) {
10302                 free_q_head = AscAllocFreeQueue(iop_base, free_q_head);
10303                 if (free_q_head == ASC_QLINK_END)
10304                         break;
10305         }
10306         return free_q_head;
10307 }
10308
10309 /*
10310  * void
10311  * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
10312  *
10313  * Calling/Exit State:
10314  *    none
10315  *
10316  * Description:
10317  *     Output an ASC_SCSI_Q structure to the chip
10318  */
10319 static void
10320 DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
10321 {
10322         int i;
10323
10324         ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words);
10325         AscSetChipLramAddr(iop_base, s_addr);
10326         for (i = 0; i < 2 * words; i += 2) {
10327                 if (i == 4 || i == 20) {
10328                         continue;
10329                 }
10330                 outpw(iop_base + IOP_RAM_DATA,
10331                       ((ushort)outbuf[i + 1] << 8) | outbuf[i]);
10332         }
10333 }
10334
10335 static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
10336 {
10337         ushort q_addr;
10338         uchar tid_no;
10339         uchar sdtr_data;
10340         uchar syn_period_ix;
10341         uchar syn_offset;
10342         PortAddr iop_base;
10343
10344         iop_base = asc_dvc->iop_base;
10345         if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) &&
10346             ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) {
10347                 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
10348                 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
10349                 syn_period_ix =
10350                     (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1);
10351                 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
10352                 AscMsgOutSDTR(asc_dvc,
10353                               asc_dvc->sdtr_period_tbl[syn_period_ix],
10354                               syn_offset);
10355                 scsiq->q1.cntl |= QC_MSG_OUT;
10356         }
10357         q_addr = ASC_QNO_TO_QADDR(q_no);
10358         if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
10359                 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
10360         }
10361         scsiq->q1.status = QS_FREE;
10362         AscMemWordCopyPtrToLram(iop_base,
10363                                 q_addr + ASC_SCSIQ_CDB_BEG,
10364                                 (uchar *)scsiq->cdbptr, scsiq->q2.cdb_len >> 1);
10365
10366         DvcPutScsiQ(iop_base,
10367                     q_addr + ASC_SCSIQ_CPY_BEG,
10368                     (uchar *)&scsiq->q1.cntl,
10369                     ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
10370         AscWriteLramWord(iop_base,
10371                          (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS),
10372                          (ushort)(((ushort)scsiq->q1.
10373                                    q_no << 8) | (ushort)QS_READY));
10374         return 1;
10375 }
10376
10377 static int
10378 AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
10379 {
10380         int sta;
10381         int i;
10382         ASC_SG_HEAD *sg_head;
10383         ASC_SG_LIST_Q scsi_sg_q;
10384         ASC_DCNT saved_data_addr;
10385         ASC_DCNT saved_data_cnt;
10386         PortAddr iop_base;
10387         ushort sg_list_dwords;
10388         ushort sg_index;
10389         ushort sg_entry_cnt;
10390         ushort q_addr;
10391         uchar next_qp;
10392
10393         iop_base = asc_dvc->iop_base;
10394         sg_head = scsiq->sg_head;
10395         saved_data_addr = scsiq->q1.data_addr;
10396         saved_data_cnt = scsiq->q1.data_cnt;
10397         scsiq->q1.data_addr = (ASC_PADDR) sg_head->sg_list[0].addr;
10398         scsiq->q1.data_cnt = (ASC_DCNT) sg_head->sg_list[0].bytes;
10399 #if CC_VERY_LONG_SG_LIST
10400         /*
10401          * If sg_head->entry_cnt is greater than ASC_MAX_SG_LIST
10402          * then not all SG elements will fit in the allocated queues.
10403          * The rest of the SG elements will be copied when the RISC
10404          * completes the SG elements that fit and halts.
10405          */
10406         if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
10407                 /*
10408                  * Set sg_entry_cnt to be the number of SG elements that
10409                  * will fit in the allocated SG queues. It is minus 1, because
10410                  * the first SG element is handled above. ASC_MAX_SG_LIST is
10411                  * already inflated by 1 to account for this. For example it
10412                  * may be 50 which is 1 + 7 queues * 7 SG elements.
10413                  */
10414                 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
10415
10416                 /*
10417                  * Keep track of remaining number of SG elements that will
10418                  * need to be handled from a_isr.c.
10419                  */
10420                 scsiq->remain_sg_entry_cnt =
10421                     sg_head->entry_cnt - ASC_MAX_SG_LIST;
10422         } else {
10423 #endif /* CC_VERY_LONG_SG_LIST */
10424                 /*
10425                  * Set sg_entry_cnt to be the number of SG elements that
10426                  * will fit in the allocated SG queues. It is minus 1, because
10427                  * the first SG element is handled above.
10428                  */
10429                 sg_entry_cnt = sg_head->entry_cnt - 1;
10430 #if CC_VERY_LONG_SG_LIST
10431         }
10432 #endif /* CC_VERY_LONG_SG_LIST */
10433         if (sg_entry_cnt != 0) {
10434                 scsiq->q1.cntl |= QC_SG_HEAD;
10435                 q_addr = ASC_QNO_TO_QADDR(q_no);
10436                 sg_index = 1;
10437                 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
10438                 scsi_sg_q.sg_head_qp = q_no;
10439                 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
10440                 for (i = 0; i < sg_head->queue_cnt; i++) {
10441                         scsi_sg_q.seq_no = i + 1;
10442                         if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
10443                                 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
10444                                 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
10445                                 if (i == 0) {
10446                                         scsi_sg_q.sg_list_cnt =
10447                                             ASC_SG_LIST_PER_Q;
10448                                         scsi_sg_q.sg_cur_list_cnt =
10449                                             ASC_SG_LIST_PER_Q;
10450                                 } else {
10451                                         scsi_sg_q.sg_list_cnt =
10452                                             ASC_SG_LIST_PER_Q - 1;
10453                                         scsi_sg_q.sg_cur_list_cnt =
10454                                             ASC_SG_LIST_PER_Q - 1;
10455                                 }
10456                         } else {
10457 #if CC_VERY_LONG_SG_LIST
10458                                 /*
10459                                  * This is the last SG queue in the list of
10460                                  * allocated SG queues. If there are more
10461                                  * SG elements than will fit in the allocated
10462                                  * queues, then set the QCSG_SG_XFER_MORE flag.
10463                                  */
10464                                 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
10465                                         scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
10466                                 } else {
10467 #endif /* CC_VERY_LONG_SG_LIST */
10468                                         scsi_sg_q.cntl |= QCSG_SG_XFER_END;
10469 #if CC_VERY_LONG_SG_LIST
10470                                 }
10471 #endif /* CC_VERY_LONG_SG_LIST */
10472                                 sg_list_dwords = sg_entry_cnt << 1;
10473                                 if (i == 0) {
10474                                         scsi_sg_q.sg_list_cnt = sg_entry_cnt;
10475                                         scsi_sg_q.sg_cur_list_cnt =
10476                                             sg_entry_cnt;
10477                                 } else {
10478                                         scsi_sg_q.sg_list_cnt =
10479                                             sg_entry_cnt - 1;
10480                                         scsi_sg_q.sg_cur_list_cnt =
10481                                             sg_entry_cnt - 1;
10482                                 }
10483                                 sg_entry_cnt = 0;
10484                         }
10485                         next_qp = AscReadLramByte(iop_base,
10486                                                   (ushort)(q_addr +
10487                                                            ASC_SCSIQ_B_FWD));
10488                         scsi_sg_q.q_no = next_qp;
10489                         q_addr = ASC_QNO_TO_QADDR(next_qp);
10490                         AscMemWordCopyPtrToLram(iop_base,
10491                                                 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
10492                                                 (uchar *)&scsi_sg_q,
10493                                                 sizeof(ASC_SG_LIST_Q) >> 1);
10494                         AscMemDWordCopyPtrToLram(iop_base,
10495                                                  q_addr + ASC_SGQ_LIST_BEG,
10496                                                  (uchar *)&sg_head->
10497                                                  sg_list[sg_index],
10498                                                  sg_list_dwords);
10499                         sg_index += ASC_SG_LIST_PER_Q;
10500                         scsiq->next_sg_index = sg_index;
10501                 }
10502         } else {
10503                 scsiq->q1.cntl &= ~QC_SG_HEAD;
10504         }
10505         sta = AscPutReadyQueue(asc_dvc, scsiq, q_no);
10506         scsiq->q1.data_addr = saved_data_addr;
10507         scsiq->q1.data_cnt = saved_data_cnt;
10508         return (sta);
10509 }
10510
10511 static int
10512 AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required)
10513 {
10514         PortAddr iop_base;
10515         uchar free_q_head;
10516         uchar next_qp;
10517         uchar tid_no;
10518         uchar target_ix;
10519         int sta;
10520
10521         iop_base = asc_dvc->iop_base;
10522         target_ix = scsiq->q2.target_ix;
10523         tid_no = ASC_TIX_TO_TID(target_ix);
10524         sta = 0;
10525         free_q_head = (uchar)AscGetVarFreeQHead(iop_base);
10526         if (n_q_required > 1) {
10527                 next_qp = AscAllocMultipleFreeQueue(iop_base, free_q_head,
10528                                                     (uchar)n_q_required);
10529                 if (next_qp != ASC_QLINK_END) {
10530                         asc_dvc->last_q_shortage = 0;
10531                         scsiq->sg_head->queue_cnt = n_q_required - 1;
10532                         scsiq->q1.q_no = free_q_head;
10533                         sta = AscPutReadySgListQueue(asc_dvc, scsiq,
10534                                                      free_q_head);
10535                 }
10536         } else if (n_q_required == 1) {
10537                 next_qp = AscAllocFreeQueue(iop_base, free_q_head);
10538                 if (next_qp != ASC_QLINK_END) {
10539                         scsiq->q1.q_no = free_q_head;
10540                         sta = AscPutReadyQueue(asc_dvc, scsiq, free_q_head);
10541                 }
10542         }
10543         if (sta == 1) {
10544                 AscPutVarFreeQHead(iop_base, next_qp);
10545                 asc_dvc->cur_total_qng += n_q_required;
10546                 asc_dvc->cur_dvc_qng[tid_no]++;
10547         }
10548         return sta;
10549 }
10550
10551 #define ASC_SYN_OFFSET_ONE_DISABLE_LIST  16
10552 static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = {
10553         INQUIRY,
10554         REQUEST_SENSE,
10555         READ_CAPACITY,
10556         READ_TOC,
10557         MODE_SELECT,
10558         MODE_SENSE,
10559         MODE_SELECT_10,
10560         MODE_SENSE_10,
10561         0xFF,
10562         0xFF,
10563         0xFF,
10564         0xFF,
10565         0xFF,
10566         0xFF,
10567         0xFF,
10568         0xFF
10569 };
10570
10571 static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq)
10572 {
10573         PortAddr iop_base;
10574         int sta;
10575         int n_q_required;
10576         int disable_syn_offset_one_fix;
10577         int i;
10578         ASC_PADDR addr;
10579         ushort sg_entry_cnt = 0;
10580         ushort sg_entry_cnt_minus_one = 0;
10581         uchar target_ix;
10582         uchar tid_no;
10583         uchar sdtr_data;
10584         uchar extra_bytes;
10585         uchar scsi_cmd;
10586         uchar disable_cmd;
10587         ASC_SG_HEAD *sg_head;
10588         ASC_DCNT data_cnt;
10589
10590         iop_base = asc_dvc->iop_base;
10591         sg_head = scsiq->sg_head;
10592         if (asc_dvc->err_code != 0)
10593                 return (ERR);
10594         scsiq->q1.q_no = 0;
10595         if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) {
10596                 scsiq->q1.extra_bytes = 0;
10597         }
10598         sta = 0;
10599         target_ix = scsiq->q2.target_ix;
10600         tid_no = ASC_TIX_TO_TID(target_ix);
10601         n_q_required = 1;
10602         if (scsiq->cdbptr[0] == REQUEST_SENSE) {
10603                 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) {
10604                         asc_dvc->sdtr_done &= ~scsiq->q1.target_id;
10605                         sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
10606                         AscMsgOutSDTR(asc_dvc,
10607                                       asc_dvc->
10608                                       sdtr_period_tbl[(sdtr_data >> 4) &
10609                                                       (uchar)(asc_dvc->
10610                                                               max_sdtr_index -
10611                                                               1)],
10612                                       (uchar)(sdtr_data & (uchar)
10613                                               ASC_SYN_MAX_OFFSET));
10614                         scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
10615                 }
10616         }
10617         if (asc_dvc->in_critical_cnt != 0) {
10618                 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY);
10619                 return (ERR);
10620         }
10621         asc_dvc->in_critical_cnt++;
10622         if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
10623                 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) {
10624                         asc_dvc->in_critical_cnt--;
10625                         return (ERR);
10626                 }
10627 #if !CC_VERY_LONG_SG_LIST
10628                 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
10629                         asc_dvc->in_critical_cnt--;
10630                         return (ERR);
10631                 }
10632 #endif /* !CC_VERY_LONG_SG_LIST */
10633                 if (sg_entry_cnt == 1) {
10634                         scsiq->q1.data_addr =
10635                             (ADV_PADDR)sg_head->sg_list[0].addr;
10636                         scsiq->q1.data_cnt =
10637                             (ADV_DCNT)sg_head->sg_list[0].bytes;
10638                         scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
10639                 }
10640                 sg_entry_cnt_minus_one = sg_entry_cnt - 1;
10641         }
10642         scsi_cmd = scsiq->cdbptr[0];
10643         disable_syn_offset_one_fix = FALSE;
10644         if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
10645             !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
10646                 if (scsiq->q1.cntl & QC_SG_HEAD) {
10647                         data_cnt = 0;
10648                         for (i = 0; i < sg_entry_cnt; i++) {
10649                                 data_cnt +=
10650                                     (ADV_DCNT)le32_to_cpu(sg_head->sg_list[i].
10651                                                           bytes);
10652                         }
10653                 } else {
10654                         data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
10655                 }
10656                 if (data_cnt != 0UL) {
10657                         if (data_cnt < 512UL) {
10658                                 disable_syn_offset_one_fix = TRUE;
10659                         } else {
10660                                 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST;
10661                                      i++) {
10662                                         disable_cmd =
10663                                             _syn_offset_one_disable_cmd[i];
10664                                         if (disable_cmd == 0xFF) {
10665                                                 break;
10666                                         }
10667                                         if (scsi_cmd == disable_cmd) {
10668                                                 disable_syn_offset_one_fix =
10669                                                     TRUE;
10670                                                 break;
10671                                         }
10672                                 }
10673                         }
10674                 }
10675         }
10676         if (disable_syn_offset_one_fix) {
10677                 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
10678                 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
10679                                        ASC_TAG_FLAG_DISABLE_DISCONNECT);
10680         } else {
10681                 scsiq->q2.tag_code &= 0x27;
10682         }
10683         if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
10684                 if (asc_dvc->bug_fix_cntl) {
10685                         if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
10686                                 if ((scsi_cmd == READ_6) ||
10687                                     (scsi_cmd == READ_10)) {
10688                                         addr =
10689                                             (ADV_PADDR)le32_to_cpu(sg_head->
10690                                                                    sg_list
10691                                                                    [sg_entry_cnt_minus_one].
10692                                                                    addr) +
10693                                             (ADV_DCNT)le32_to_cpu(sg_head->
10694                                                                   sg_list
10695                                                                   [sg_entry_cnt_minus_one].
10696                                                                   bytes);
10697                                         extra_bytes =
10698                                             (uchar)((ushort)addr & 0x0003);
10699                                         if ((extra_bytes != 0)
10700                                             &&
10701                                             ((scsiq->q2.
10702                                               tag_code &
10703                                               ASC_TAG_FLAG_EXTRA_BYTES)
10704                                              == 0)) {
10705                                                 scsiq->q2.tag_code |=
10706                                                     ASC_TAG_FLAG_EXTRA_BYTES;
10707                                                 scsiq->q1.extra_bytes =
10708                                                     extra_bytes;
10709                                                 data_cnt =
10710                                                     le32_to_cpu(sg_head->
10711                                                                 sg_list
10712                                                                 [sg_entry_cnt_minus_one].
10713                                                                 bytes);
10714                                                 data_cnt -=
10715                                                     (ASC_DCNT) extra_bytes;
10716                                                 sg_head->
10717                                                     sg_list
10718                                                     [sg_entry_cnt_minus_one].
10719                                                     bytes =
10720                                                     cpu_to_le32(data_cnt);
10721                                         }
10722                                 }
10723                         }
10724                 }
10725                 sg_head->entry_to_copy = sg_head->entry_cnt;
10726 #if CC_VERY_LONG_SG_LIST
10727                 /*
10728                  * Set the sg_entry_cnt to the maximum possible. The rest of
10729                  * the SG elements will be copied when the RISC completes the
10730                  * SG elements that fit and halts.
10731                  */
10732                 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
10733                         sg_entry_cnt = ASC_MAX_SG_LIST;
10734                 }
10735 #endif /* CC_VERY_LONG_SG_LIST */
10736                 n_q_required = AscSgListToQueue(sg_entry_cnt);
10737                 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >=
10738                      (uint) n_q_required)
10739                     || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
10740                         if ((sta =
10741                              AscSendScsiQueue(asc_dvc, scsiq,
10742                                               n_q_required)) == 1) {
10743                                 asc_dvc->in_critical_cnt--;
10744                                 return (sta);
10745                         }
10746                 }
10747         } else {
10748                 if (asc_dvc->bug_fix_cntl) {
10749                         if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
10750                                 if ((scsi_cmd == READ_6) ||
10751                                     (scsi_cmd == READ_10)) {
10752                                         addr =
10753                                             le32_to_cpu(scsiq->q1.data_addr) +
10754                                             le32_to_cpu(scsiq->q1.data_cnt);
10755                                         extra_bytes =
10756                                             (uchar)((ushort)addr & 0x0003);
10757                                         if ((extra_bytes != 0)
10758                                             &&
10759                                             ((scsiq->q2.
10760                                               tag_code &
10761                                               ASC_TAG_FLAG_EXTRA_BYTES)
10762                                              == 0)) {
10763                                                 data_cnt =
10764                                                     le32_to_cpu(scsiq->q1.
10765                                                                 data_cnt);
10766                                                 if (((ushort)data_cnt & 0x01FF)
10767                                                     == 0) {
10768                                                         scsiq->q2.tag_code |=
10769                                                             ASC_TAG_FLAG_EXTRA_BYTES;
10770                                                         data_cnt -= (ASC_DCNT)
10771                                                             extra_bytes;
10772                                                         scsiq->q1.data_cnt =
10773                                                             cpu_to_le32
10774                                                             (data_cnt);
10775                                                         scsiq->q1.extra_bytes =
10776                                                             extra_bytes;
10777                                                 }
10778                                         }
10779                                 }
10780                         }
10781                 }
10782                 n_q_required = 1;
10783                 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) ||
10784                     ((scsiq->q1.cntl & QC_URGENT) != 0)) {
10785                         if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
10786                                                     n_q_required)) == 1) {
10787                                 asc_dvc->in_critical_cnt--;
10788                                 return (sta);
10789                         }
10790                 }
10791         }
10792         asc_dvc->in_critical_cnt--;
10793         return (sta);
10794 }
10795
10796 /*
10797  * AdvExeScsiQueue() - Send a request to the RISC microcode program.
10798  *
10799  *   Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
10800  *   add the carrier to the ICQ (Initiator Command Queue), and tickle the
10801  *   RISC to notify it a new command is ready to be executed.
10802  *
10803  * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
10804  * set to SCSI_MAX_RETRY.
10805  *
10806  * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the microcode
10807  * for DMA addresses or math operations are byte swapped to little-endian
10808  * order.
10809  *
10810  * Return:
10811  *      ADV_SUCCESS(1) - The request was successfully queued.
10812  *      ADV_BUSY(0) -    Resource unavailable; Retry again after pending
10813  *                       request completes.
10814  *      ADV_ERROR(-1) -  Invalid ADV_SCSI_REQ_Q request structure
10815  *                       host IC error.
10816  */
10817 static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq)
10818 {
10819         AdvPortAddr iop_base;
10820         ADV_PADDR req_paddr;
10821         ADV_CARR_T *new_carrp;
10822
10823         /*
10824          * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
10825          */
10826         if (scsiq->target_id > ADV_MAX_TID) {
10827                 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
10828                 scsiq->done_status = QD_WITH_ERROR;
10829                 return ADV_ERROR;
10830         }
10831
10832         iop_base = asc_dvc->iop_base;
10833
10834         /*
10835          * Allocate a carrier ensuring at least one carrier always
10836          * remains on the freelist and initialize fields.
10837          */
10838         if ((new_carrp = asc_dvc->carr_freelist) == NULL) {
10839                 return ADV_BUSY;
10840         }
10841         asc_dvc->carr_freelist = (ADV_CARR_T *)
10842             ADV_U32_TO_VADDR(le32_to_cpu(new_carrp->next_vpa));
10843         asc_dvc->carr_pending_cnt++;
10844
10845         /*
10846          * Set the carrier to be a stopper by setting 'next_vpa'
10847          * to the stopper value. The current stopper will be changed
10848          * below to point to the new stopper.
10849          */
10850         new_carrp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
10851
10852         /*
10853          * Clear the ADV_SCSI_REQ_Q done flag.
10854          */
10855         scsiq->a_flag &= ~ADV_SCSIQ_DONE;
10856
10857         req_paddr = virt_to_bus(scsiq);
10858         BUG_ON(req_paddr & 31);
10859         /* Wait for assertion before making little-endian */
10860         req_paddr = cpu_to_le32(req_paddr);
10861
10862         /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
10863         scsiq->scsiq_ptr = cpu_to_le32(ADV_VADDR_TO_U32(scsiq));
10864         scsiq->scsiq_rptr = req_paddr;
10865
10866         scsiq->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->icq_sp));
10867         /*
10868          * Every ADV_CARR_T.carr_pa is byte swapped to little-endian
10869          * order during initialization.
10870          */
10871         scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
10872
10873         /*
10874          * Use the current stopper to send the ADV_SCSI_REQ_Q command to
10875          * the microcode. The newly allocated stopper will become the new
10876          * stopper.
10877          */
10878         asc_dvc->icq_sp->areq_vpa = req_paddr;
10879
10880         /*
10881          * Set the 'next_vpa' pointer for the old stopper to be the
10882          * physical address of the new stopper. The RISC can only
10883          * follow physical addresses.
10884          */
10885         asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
10886
10887         /*
10888          * Set the host adapter stopper pointer to point to the new carrier.
10889          */
10890         asc_dvc->icq_sp = new_carrp;
10891
10892         if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
10893             asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
10894                 /*
10895                  * Tickle the RISC to tell it to read its Command Queue Head pointer.
10896                  */
10897                 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
10898                 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
10899                         /*
10900                          * Clear the tickle value. In the ASC-3550 the RISC flag
10901                          * command 'clr_tickle_a' does not work unless the host
10902                          * value is cleared.
10903                          */
10904                         AdvWriteByteRegister(iop_base, IOPB_TICKLE,
10905                                              ADV_TICKLE_NOP);
10906                 }
10907         } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
10908                 /*
10909                  * Notify the RISC a carrier is ready by writing the physical
10910                  * address of the new carrier stopper to the COMMA register.
10911                  */
10912                 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
10913                                       le32_to_cpu(new_carrp->carr_pa));
10914         }
10915
10916         return ADV_SUCCESS;
10917 }
10918
10919 /*
10920  * Execute a single 'Scsi_Cmnd'.
10921  */
10922 static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp)
10923 {
10924         int ret, err_code;
10925         struct asc_board *boardp = shost_priv(scp->device->host);
10926
10927         ASC_DBG(1, "scp 0x%p\n", scp);
10928
10929         if (ASC_NARROW_BOARD(boardp)) {
10930                 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
10931                 struct asc_scsi_q asc_scsi_q;
10932
10933                 /* asc_build_req() can not return ASC_BUSY. */
10934                 ret = asc_build_req(boardp, scp, &asc_scsi_q);
10935                 if (ret == ASC_ERROR) {
10936                         ASC_STATS(scp->device->host, build_error);
10937                         return ASC_ERROR;
10938                 }
10939
10940                 ret = AscExeScsiQueue(asc_dvc, &asc_scsi_q);
10941                 kfree(asc_scsi_q.sg_head);
10942                 err_code = asc_dvc->err_code;
10943         } else {
10944                 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
10945                 ADV_SCSI_REQ_Q *adv_scsiqp;
10946
10947                 switch (adv_build_req(boardp, scp, &adv_scsiqp)) {
10948                 case ASC_NOERROR:
10949                         ASC_DBG(3, "adv_build_req ASC_NOERROR\n");
10950                         break;
10951                 case ASC_BUSY:
10952                         ASC_DBG(1, "adv_build_req ASC_BUSY\n");
10953                         /*
10954                          * The asc_stats fields 'adv_build_noreq' and
10955                          * 'adv_build_nosg' count wide board busy conditions.
10956                          * They are updated in adv_build_req and
10957                          * adv_get_sglist, respectively.
10958                          */
10959                         return ASC_BUSY;
10960                 case ASC_ERROR:
10961                 default:
10962                         ASC_DBG(1, "adv_build_req ASC_ERROR\n");
10963                         ASC_STATS(scp->device->host, build_error);
10964                         return ASC_ERROR;
10965                 }
10966
10967                 ret = AdvExeScsiQueue(adv_dvc, adv_scsiqp);
10968                 err_code = adv_dvc->err_code;
10969         }
10970
10971         switch (ret) {
10972         case ASC_NOERROR:
10973                 ASC_STATS(scp->device->host, exe_noerror);
10974                 /*
10975                  * Increment monotonically increasing per device
10976                  * successful request counter. Wrapping doesn't matter.
10977                  */
10978                 boardp->reqcnt[scp->device->id]++;
10979                 ASC_DBG(1, "ExeScsiQueue() ASC_NOERROR\n");
10980                 break;
10981         case ASC_BUSY:
10982                 ASC_STATS(scp->device->host, exe_busy);
10983                 break;
10984         case ASC_ERROR:
10985                 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() ASC_ERROR, "
10986                         "err_code 0x%x\n", err_code);
10987                 ASC_STATS(scp->device->host, exe_error);
10988                 scp->result = HOST_BYTE(DID_ERROR);
10989                 break;
10990         default:
10991                 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() unknown, "
10992                         "err_code 0x%x\n", err_code);
10993                 ASC_STATS(scp->device->host, exe_unknown);
10994                 scp->result = HOST_BYTE(DID_ERROR);
10995                 break;
10996         }
10997
10998         ASC_DBG(1, "end\n");
10999         return ret;
11000 }
11001
11002 /*
11003  * advansys_queuecommand() - interrupt-driven I/O entrypoint.
11004  *
11005  * This function always returns 0. Command return status is saved
11006  * in the 'scp' result field.
11007  */
11008 static int
11009 advansys_queuecommand(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *))
11010 {
11011         struct Scsi_Host *shost = scp->device->host;
11012         int asc_res, result = 0;
11013
11014         ASC_STATS(shost, queuecommand);
11015         scp->scsi_done = done;
11016
11017         asc_res = asc_execute_scsi_cmnd(scp);
11018
11019         switch (asc_res) {
11020         case ASC_NOERROR:
11021                 break;
11022         case ASC_BUSY:
11023                 result = SCSI_MLQUEUE_HOST_BUSY;
11024                 break;
11025         case ASC_ERROR:
11026         default:
11027                 asc_scsi_done(scp);
11028                 break;
11029         }
11030
11031         return result;
11032 }
11033
11034 static ushort __devinit AscGetEisaChipCfg(PortAddr iop_base)
11035 {
11036         PortAddr eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
11037             (PortAddr) (ASC_EISA_CFG_IOP_MASK);
11038         return inpw(eisa_cfg_iop);
11039 }
11040
11041 /*
11042  * Return the BIOS address of the adapter at the specified
11043  * I/O port and with the specified bus type.
11044  */
11045 static unsigned short __devinit
11046 AscGetChipBiosAddress(PortAddr iop_base, unsigned short bus_type)
11047 {
11048         unsigned short cfg_lsw;
11049         unsigned short bios_addr;
11050
11051         /*
11052          * The PCI BIOS is re-located by the motherboard BIOS. Because
11053          * of this the driver can not determine where a PCI BIOS is
11054          * loaded and executes.
11055          */
11056         if (bus_type & ASC_IS_PCI)
11057                 return 0;
11058
11059         if ((bus_type & ASC_IS_EISA) != 0) {
11060                 cfg_lsw = AscGetEisaChipCfg(iop_base);
11061                 cfg_lsw &= 0x000F;
11062                 bios_addr = ASC_BIOS_MIN_ADDR + cfg_lsw * ASC_BIOS_BANK_SIZE;
11063                 return bios_addr;
11064         }
11065
11066         cfg_lsw = AscGetChipCfgLsw(iop_base);
11067
11068         /*
11069          *  ISA PnP uses the top bit as the 32K BIOS flag
11070          */
11071         if (bus_type == ASC_IS_ISAPNP)
11072                 cfg_lsw &= 0x7FFF;
11073         bios_addr = ASC_BIOS_MIN_ADDR + (cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE;
11074         return bios_addr;
11075 }
11076
11077 static uchar __devinit AscSetChipScsiID(PortAddr iop_base, uchar new_host_id)
11078 {
11079         ushort cfg_lsw;
11080
11081         if (AscGetChipScsiID(iop_base) == new_host_id) {
11082                 return (new_host_id);
11083         }
11084         cfg_lsw = AscGetChipCfgLsw(iop_base);
11085         cfg_lsw &= 0xF8FF;
11086         cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8);
11087         AscSetChipCfgLsw(iop_base, cfg_lsw);
11088         return (AscGetChipScsiID(iop_base));
11089 }
11090
11091 static unsigned char __devinit AscGetChipScsiCtrl(PortAddr iop_base)
11092 {
11093         unsigned char sc;
11094
11095         AscSetBank(iop_base, 1);
11096         sc = inp(iop_base + IOP_REG_SC);
11097         AscSetBank(iop_base, 0);
11098         return sc;
11099 }
11100
11101 static unsigned char __devinit
11102 AscGetChipVersion(PortAddr iop_base, unsigned short bus_type)
11103 {
11104         if (bus_type & ASC_IS_EISA) {
11105                 PortAddr eisa_iop;
11106                 unsigned char revision;
11107                 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
11108                     (PortAddr) ASC_EISA_REV_IOP_MASK;
11109                 revision = inp(eisa_iop);
11110                 return ASC_CHIP_MIN_VER_EISA - 1 + revision;
11111         }
11112         return AscGetChipVerNo(iop_base);
11113 }
11114
11115 #ifdef CONFIG_ISA
11116 static void __devinit AscEnableIsaDma(uchar dma_channel)
11117 {
11118         if (dma_channel < 4) {
11119                 outp(0x000B, (ushort)(0xC0 | dma_channel));
11120                 outp(0x000A, dma_channel);
11121         } else if (dma_channel < 8) {
11122                 outp(0x00D6, (ushort)(0xC0 | (dma_channel - 4)));
11123                 outp(0x00D4, (ushort)(dma_channel - 4));
11124         }
11125 }
11126 #endif /* CONFIG_ISA */
11127
11128 static int AscStopQueueExe(PortAddr iop_base)
11129 {
11130         int count = 0;
11131
11132         if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) {
11133                 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
11134                                  ASC_STOP_REQ_RISC_STOP);
11135                 do {
11136                         if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) &
11137                             ASC_STOP_ACK_RISC_STOP) {
11138                                 return (1);
11139                         }
11140                         mdelay(100);
11141                 } while (count++ < 20);
11142         }
11143         return (0);
11144 }
11145
11146 static ASC_DCNT __devinit AscGetMaxDmaCount(ushort bus_type)
11147 {
11148         if (bus_type & ASC_IS_ISA)
11149                 return ASC_MAX_ISA_DMA_COUNT;
11150         else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
11151                 return ASC_MAX_VL_DMA_COUNT;
11152         return ASC_MAX_PCI_DMA_COUNT;
11153 }
11154
11155 #ifdef CONFIG_ISA
11156 static ushort __devinit AscGetIsaDmaChannel(PortAddr iop_base)
11157 {
11158         ushort channel;
11159
11160         channel = AscGetChipCfgLsw(iop_base) & 0x0003;
11161         if (channel == 0x03)
11162                 return (0);
11163         else if (channel == 0x00)
11164                 return (7);
11165         return (channel + 4);
11166 }
11167
11168 static ushort __devinit AscSetIsaDmaChannel(PortAddr iop_base, ushort dma_channel)
11169 {
11170         ushort cfg_lsw;
11171         uchar value;
11172
11173         if ((dma_channel >= 5) && (dma_channel <= 7)) {
11174                 if (dma_channel == 7)
11175                         value = 0x00;
11176                 else
11177                         value = dma_channel - 4;
11178                 cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC;
11179                 cfg_lsw |= value;
11180                 AscSetChipCfgLsw(iop_base, cfg_lsw);
11181                 return (AscGetIsaDmaChannel(iop_base));
11182         }
11183         return 0;
11184 }
11185
11186 static uchar __devinit AscGetIsaDmaSpeed(PortAddr iop_base)
11187 {
11188         uchar speed_value;
11189
11190         AscSetBank(iop_base, 1);
11191         speed_value = AscReadChipDmaSpeed(iop_base);
11192         speed_value &= 0x07;
11193         AscSetBank(iop_base, 0);
11194         return speed_value;
11195 }
11196
11197 static uchar __devinit AscSetIsaDmaSpeed(PortAddr iop_base, uchar speed_value)
11198 {
11199         speed_value &= 0x07;
11200         AscSetBank(iop_base, 1);
11201         AscWriteChipDmaSpeed(iop_base, speed_value);
11202         AscSetBank(iop_base, 0);
11203         return AscGetIsaDmaSpeed(iop_base);
11204 }
11205 #endif /* CONFIG_ISA */
11206
11207 static ushort __devinit AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc)
11208 {
11209         int i;
11210         PortAddr iop_base;
11211         ushort warn_code;
11212         uchar chip_version;
11213
11214         iop_base = asc_dvc->iop_base;
11215         warn_code = 0;
11216         asc_dvc->err_code = 0;
11217         if ((asc_dvc->bus_type &
11218              (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) {
11219                 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE;
11220         }
11221         AscSetChipControl(iop_base, CC_HALT);
11222         AscSetChipStatus(iop_base, 0);
11223         asc_dvc->bug_fix_cntl = 0;
11224         asc_dvc->pci_fix_asyn_xfer = 0;
11225         asc_dvc->pci_fix_asyn_xfer_always = 0;
11226         /* asc_dvc->init_state initalized in AscInitGetConfig(). */
11227         asc_dvc->sdtr_done = 0;
11228         asc_dvc->cur_total_qng = 0;
11229         asc_dvc->is_in_int = 0;
11230         asc_dvc->in_critical_cnt = 0;
11231         asc_dvc->last_q_shortage = 0;
11232         asc_dvc->use_tagged_qng = 0;
11233         asc_dvc->no_scam = 0;
11234         asc_dvc->unit_not_ready = 0;
11235         asc_dvc->queue_full_or_busy = 0;
11236         asc_dvc->redo_scam = 0;
11237         asc_dvc->res2 = 0;
11238         asc_dvc->min_sdtr_index = 0;
11239         asc_dvc->cfg->can_tagged_qng = 0;
11240         asc_dvc->cfg->cmd_qng_enabled = 0;
11241         asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
11242         asc_dvc->init_sdtr = 0;
11243         asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
11244         asc_dvc->scsi_reset_wait = 3;
11245         asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
11246         asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type);
11247         asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
11248         asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
11249         asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
11250         chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
11251         asc_dvc->cfg->chip_version = chip_version;
11252         asc_dvc->sdtr_period_tbl = asc_syn_xfer_period;
11253         asc_dvc->max_sdtr_index = 7;
11254         if ((asc_dvc->bus_type & ASC_IS_PCI) &&
11255             (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
11256                 asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
11257                 asc_dvc->sdtr_period_tbl = asc_syn_ultra_xfer_period;
11258                 asc_dvc->max_sdtr_index = 15;
11259                 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) {
11260                         AscSetExtraControl(iop_base,
11261                                            (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
11262                 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) {
11263                         AscSetExtraControl(iop_base,
11264                                            (SEC_ACTIVE_NEGATE |
11265                                             SEC_ENABLE_FILTER));
11266                 }
11267         }
11268         if (asc_dvc->bus_type == ASC_IS_PCI) {
11269                 AscSetExtraControl(iop_base,
11270                                    (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
11271         }
11272
11273         asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
11274 #ifdef CONFIG_ISA
11275         if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) {
11276                 if (chip_version >= ASC_CHIP_MIN_VER_ISA_PNP) {
11277                         AscSetChipIFC(iop_base, IFC_INIT_DEFAULT);
11278                         asc_dvc->bus_type = ASC_IS_ISAPNP;
11279                 }
11280                 asc_dvc->cfg->isa_dma_channel =
11281                     (uchar)AscGetIsaDmaChannel(iop_base);
11282         }
11283 #endif /* CONFIG_ISA */
11284         for (i = 0; i <= ASC_MAX_TID; i++) {
11285                 asc_dvc->cur_dvc_qng[i] = 0;
11286                 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
11287                 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *)0L;
11288                 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *)0L;
11289                 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
11290         }
11291         return warn_code;
11292 }
11293
11294 static int __devinit AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg)
11295 {
11296         int retry;
11297
11298         for (retry = 0; retry < ASC_EEP_MAX_RETRY; retry++) {
11299                 unsigned char read_back;
11300                 AscSetChipEEPCmd(iop_base, cmd_reg);
11301                 mdelay(1);
11302                 read_back = AscGetChipEEPCmd(iop_base);
11303                 if (read_back == cmd_reg)
11304                         return 1;
11305         }
11306         return 0;
11307 }
11308
11309 static void __devinit AscWaitEEPRead(void)
11310 {
11311         mdelay(1);
11312 }
11313
11314 static ushort __devinit AscReadEEPWord(PortAddr iop_base, uchar addr)
11315 {
11316         ushort read_wval;
11317         uchar cmd_reg;
11318
11319         AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
11320         AscWaitEEPRead();
11321         cmd_reg = addr | ASC_EEP_CMD_READ;
11322         AscWriteEEPCmdReg(iop_base, cmd_reg);
11323         AscWaitEEPRead();
11324         read_wval = AscGetChipEEPData(iop_base);
11325         AscWaitEEPRead();
11326         return read_wval;
11327 }
11328
11329 static ushort __devinit
11330 AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
11331 {
11332         ushort wval;
11333         ushort sum;
11334         ushort *wbuf;
11335         int cfg_beg;
11336         int cfg_end;
11337         int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
11338         int s_addr;
11339
11340         wbuf = (ushort *)cfg_buf;
11341         sum = 0;
11342         /* Read two config words; Byte-swapping done by AscReadEEPWord(). */
11343         for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
11344                 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
11345                 sum += *wbuf;
11346         }
11347         if (bus_type & ASC_IS_VL) {
11348                 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
11349                 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
11350         } else {
11351                 cfg_beg = ASC_EEP_DVC_CFG_BEG;
11352                 cfg_end = ASC_EEP_MAX_DVC_ADDR;
11353         }
11354         for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
11355                 wval = AscReadEEPWord(iop_base, (uchar)s_addr);
11356                 if (s_addr <= uchar_end_in_config) {
11357                         /*
11358                          * Swap all char fields - must unswap bytes already swapped
11359                          * by AscReadEEPWord().
11360                          */
11361                         *wbuf = le16_to_cpu(wval);
11362                 } else {
11363                         /* Don't swap word field at the end - cntl field. */
11364                         *wbuf = wval;
11365                 }
11366                 sum += wval;    /* Checksum treats all EEPROM data as words. */
11367         }
11368         /*
11369          * Read the checksum word which will be compared against 'sum'
11370          * by the caller. Word field already swapped.
11371          */
11372         *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
11373         return sum;
11374 }
11375
11376 static int __devinit AscTestExternalLram(ASC_DVC_VAR *asc_dvc)
11377 {
11378         PortAddr iop_base;
11379         ushort q_addr;
11380         ushort saved_word;
11381         int sta;
11382
11383         iop_base = asc_dvc->iop_base;
11384         sta = 0;
11385         q_addr = ASC_QNO_TO_QADDR(241);
11386         saved_word = AscReadLramWord(iop_base, q_addr);
11387         AscSetChipLramAddr(iop_base, q_addr);
11388         AscSetChipLramData(iop_base, 0x55AA);
11389         mdelay(10);
11390         AscSetChipLramAddr(iop_base, q_addr);
11391         if (AscGetChipLramData(iop_base) == 0x55AA) {
11392                 sta = 1;
11393                 AscWriteLramWord(iop_base, q_addr, saved_word);
11394         }
11395         return (sta);
11396 }
11397
11398 static void __devinit AscWaitEEPWrite(void)
11399 {
11400         mdelay(20);
11401 }
11402
11403 static int __devinit AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg)
11404 {
11405         ushort read_back;
11406         int retry;
11407
11408         retry = 0;
11409         while (TRUE) {
11410                 AscSetChipEEPData(iop_base, data_reg);
11411                 mdelay(1);
11412                 read_back = AscGetChipEEPData(iop_base);
11413                 if (read_back == data_reg) {
11414                         return (1);
11415                 }
11416                 if (retry++ > ASC_EEP_MAX_RETRY) {
11417                         return (0);
11418                 }
11419         }
11420 }
11421
11422 static ushort __devinit
11423 AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val)
11424 {
11425         ushort read_wval;
11426
11427         read_wval = AscReadEEPWord(iop_base, addr);
11428         if (read_wval != word_val) {
11429                 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE);
11430                 AscWaitEEPRead();
11431                 AscWriteEEPDataReg(iop_base, word_val);
11432                 AscWaitEEPRead();
11433                 AscWriteEEPCmdReg(iop_base,
11434                                   (uchar)((uchar)ASC_EEP_CMD_WRITE | addr));
11435                 AscWaitEEPWrite();
11436                 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
11437                 AscWaitEEPRead();
11438                 return (AscReadEEPWord(iop_base, addr));
11439         }
11440         return (read_wval);
11441 }
11442
11443 static int __devinit
11444 AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
11445 {
11446         int n_error;
11447         ushort *wbuf;
11448         ushort word;
11449         ushort sum;
11450         int s_addr;
11451         int cfg_beg;
11452         int cfg_end;
11453         int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
11454
11455         wbuf = (ushort *)cfg_buf;
11456         n_error = 0;
11457         sum = 0;
11458         /* Write two config words; AscWriteEEPWord() will swap bytes. */
11459         for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
11460                 sum += *wbuf;
11461                 if (*wbuf != AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
11462                         n_error++;
11463                 }
11464         }
11465         if (bus_type & ASC_IS_VL) {
11466                 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
11467                 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
11468         } else {
11469                 cfg_beg = ASC_EEP_DVC_CFG_BEG;
11470                 cfg_end = ASC_EEP_MAX_DVC_ADDR;
11471         }
11472         for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
11473                 if (s_addr <= uchar_end_in_config) {
11474                         /*
11475                          * This is a char field. Swap char fields before they are
11476                          * swapped again by AscWriteEEPWord().
11477                          */
11478                         word = cpu_to_le16(*wbuf);
11479                         if (word !=
11480                             AscWriteEEPWord(iop_base, (uchar)s_addr, word)) {
11481                                 n_error++;
11482                         }
11483                 } else {
11484                         /* Don't swap word field at the end - cntl field. */
11485                         if (*wbuf !=
11486                             AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
11487                                 n_error++;
11488                         }
11489                 }
11490                 sum += *wbuf;   /* Checksum calculated from word values. */
11491         }
11492         /* Write checksum word. It will be swapped by AscWriteEEPWord(). */
11493         *wbuf = sum;
11494         if (sum != AscWriteEEPWord(iop_base, (uchar)s_addr, sum)) {
11495                 n_error++;
11496         }
11497
11498         /* Read EEPROM back again. */
11499         wbuf = (ushort *)cfg_buf;
11500         /*
11501          * Read two config words; Byte-swapping done by AscReadEEPWord().
11502          */
11503         for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
11504                 if (*wbuf != AscReadEEPWord(iop_base, (uchar)s_addr)) {
11505                         n_error++;
11506                 }
11507         }
11508         if (bus_type & ASC_IS_VL) {
11509                 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
11510                 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
11511         } else {
11512                 cfg_beg = ASC_EEP_DVC_CFG_BEG;
11513                 cfg_end = ASC_EEP_MAX_DVC_ADDR;
11514         }
11515         for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
11516                 if (s_addr <= uchar_end_in_config) {
11517                         /*
11518                          * Swap all char fields. Must unswap bytes already swapped
11519                          * by AscReadEEPWord().
11520                          */
11521                         word =
11522                             le16_to_cpu(AscReadEEPWord
11523                                         (iop_base, (uchar)s_addr));
11524                 } else {
11525                         /* Don't swap word field at the end - cntl field. */
11526                         word = AscReadEEPWord(iop_base, (uchar)s_addr);
11527                 }
11528                 if (*wbuf != word) {
11529                         n_error++;
11530                 }
11531         }
11532         /* Read checksum; Byte swapping not needed. */
11533         if (AscReadEEPWord(iop_base, (uchar)s_addr) != sum) {
11534                 n_error++;
11535         }
11536         return n_error;
11537 }
11538
11539 static int __devinit
11540 AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
11541 {
11542         int retry;
11543         int n_error;
11544
11545         retry = 0;
11546         while (TRUE) {
11547                 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
11548                                                    bus_type)) == 0) {
11549                         break;
11550                 }
11551                 if (++retry > ASC_EEP_MAX_RETRY) {
11552                         break;
11553                 }
11554         }
11555         return n_error;
11556 }
11557
11558 static ushort __devinit AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
11559 {
11560         ASCEEP_CONFIG eep_config_buf;
11561         ASCEEP_CONFIG *eep_config;
11562         PortAddr iop_base;
11563         ushort chksum;
11564         ushort warn_code;
11565         ushort cfg_msw, cfg_lsw;
11566         int i;
11567         int write_eep = 0;
11568
11569         iop_base = asc_dvc->iop_base;
11570         warn_code = 0;
11571         AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
11572         AscStopQueueExe(iop_base);
11573         if ((AscStopChip(iop_base) == FALSE) ||
11574             (AscGetChipScsiCtrl(iop_base) != 0)) {
11575                 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
11576                 AscResetChipAndScsiBus(asc_dvc);
11577                 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
11578         }
11579         if (AscIsChipHalted(iop_base) == FALSE) {
11580                 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
11581                 return (warn_code);
11582         }
11583         AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
11584         if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
11585                 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
11586                 return (warn_code);
11587         }
11588         eep_config = (ASCEEP_CONFIG *)&eep_config_buf;
11589         cfg_msw = AscGetChipCfgMsw(iop_base);
11590         cfg_lsw = AscGetChipCfgLsw(iop_base);
11591         if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
11592                 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
11593                 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
11594                 AscSetChipCfgMsw(iop_base, cfg_msw);
11595         }
11596         chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type);
11597         ASC_DBG(1, "chksum 0x%x\n", chksum);
11598         if (chksum == 0) {
11599                 chksum = 0xaa55;
11600         }
11601         if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
11602                 warn_code |= ASC_WARN_AUTO_CONFIG;
11603                 if (asc_dvc->cfg->chip_version == 3) {
11604                         if (eep_config->cfg_lsw != cfg_lsw) {
11605                                 warn_code |= ASC_WARN_EEPROM_RECOVER;
11606                                 eep_config->cfg_lsw =
11607                                     AscGetChipCfgLsw(iop_base);
11608                         }
11609                         if (eep_config->cfg_msw != cfg_msw) {
11610                                 warn_code |= ASC_WARN_EEPROM_RECOVER;
11611                                 eep_config->cfg_msw =
11612                                     AscGetChipCfgMsw(iop_base);
11613                         }
11614                 }
11615         }
11616         eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
11617         eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
11618         ASC_DBG(1, "eep_config->chksum 0x%x\n", eep_config->chksum);
11619         if (chksum != eep_config->chksum) {
11620                 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) ==
11621                     ASC_CHIP_VER_PCI_ULTRA_3050) {
11622                         ASC_DBG(1, "chksum error ignored; EEPROM-less board\n");
11623                         eep_config->init_sdtr = 0xFF;
11624                         eep_config->disc_enable = 0xFF;
11625                         eep_config->start_motor = 0xFF;
11626                         eep_config->use_cmd_qng = 0;
11627                         eep_config->max_total_qng = 0xF0;
11628                         eep_config->max_tag_qng = 0x20;
11629                         eep_config->cntl = 0xBFFF;
11630                         ASC_EEP_SET_CHIP_ID(eep_config, 7);
11631                         eep_config->no_scam = 0;
11632                         eep_config->adapter_info[0] = 0;
11633                         eep_config->adapter_info[1] = 0;
11634                         eep_config->adapter_info[2] = 0;
11635                         eep_config->adapter_info[3] = 0;
11636                         eep_config->adapter_info[4] = 0;
11637                         /* Indicate EEPROM-less board. */
11638                         eep_config->adapter_info[5] = 0xBB;
11639                 } else {
11640                         ASC_PRINT
11641                             ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
11642                         write_eep = 1;
11643                         warn_code |= ASC_WARN_EEPROM_CHKSUM;
11644                 }
11645         }
11646         asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr;
11647         asc_dvc->cfg->disc_enable = eep_config->disc_enable;
11648         asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng;
11649         asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config);
11650         asc_dvc->start_motor = eep_config->start_motor;
11651         asc_dvc->dvc_cntl = eep_config->cntl;
11652         asc_dvc->no_scam = eep_config->no_scam;
11653         asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0];
11654         asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1];
11655         asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2];
11656         asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3];
11657         asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4];
11658         asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5];
11659         if (!AscTestExternalLram(asc_dvc)) {
11660                 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) ==
11661                      ASC_IS_PCI_ULTRA)) {
11662                         eep_config->max_total_qng =
11663                             ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
11664                         eep_config->max_tag_qng =
11665                             ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
11666                 } else {
11667                         eep_config->cfg_msw |= 0x0800;
11668                         cfg_msw |= 0x0800;
11669                         AscSetChipCfgMsw(iop_base, cfg_msw);
11670                         eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
11671                         eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
11672                 }
11673         } else {
11674         }
11675         if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) {
11676                 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
11677         }
11678         if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) {
11679                 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
11680         }
11681         if (eep_config->max_tag_qng > eep_config->max_total_qng) {
11682                 eep_config->max_tag_qng = eep_config->max_total_qng;
11683         }
11684         if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) {
11685                 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
11686         }
11687         asc_dvc->max_total_qng = eep_config->max_total_qng;
11688         if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
11689             eep_config->use_cmd_qng) {
11690                 eep_config->disc_enable = eep_config->use_cmd_qng;
11691                 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
11692         }
11693         ASC_EEP_SET_CHIP_ID(eep_config,
11694                             ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID);
11695         asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
11696         if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
11697             !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
11698                 asc_dvc->min_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
11699         }
11700
11701         for (i = 0; i <= ASC_MAX_TID; i++) {
11702                 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i];
11703                 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
11704                 asc_dvc->cfg->sdtr_period_offset[i] =
11705                     (uchar)(ASC_DEF_SDTR_OFFSET |
11706                             (asc_dvc->min_sdtr_index << 4));
11707         }
11708         eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
11709         if (write_eep) {
11710                 if ((i = AscSetEEPConfig(iop_base, eep_config,
11711                                      asc_dvc->bus_type)) != 0) {
11712                         ASC_PRINT1
11713                             ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n",
11714                              i);
11715                 } else {
11716                         ASC_PRINT
11717                             ("AscInitFromEEP: Successfully re-wrote EEPROM.\n");
11718                 }
11719         }
11720         return (warn_code);
11721 }
11722
11723 static int __devinit AscInitGetConfig(struct Scsi_Host *shost)
11724 {
11725         struct asc_board *board = shost_priv(shost);
11726         ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
11727         unsigned short warn_code = 0;
11728
11729         asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG;
11730         if (asc_dvc->err_code != 0)
11731                 return asc_dvc->err_code;
11732
11733         if (AscFindSignature(asc_dvc->iop_base)) {
11734                 warn_code |= AscInitAscDvcVar(asc_dvc);
11735                 warn_code |= AscInitFromEEP(asc_dvc);
11736                 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG;
11737                 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
11738                         asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
11739         } else {
11740                 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
11741         }
11742
11743         switch (warn_code) {
11744         case 0: /* No error */
11745                 break;
11746         case ASC_WARN_IO_PORT_ROTATE:
11747                 shost_printk(KERN_WARNING, shost, "I/O port address "
11748                                 "modified\n");
11749                 break;
11750         case ASC_WARN_AUTO_CONFIG:
11751                 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
11752                                 "enabled\n");
11753                 break;
11754         case ASC_WARN_EEPROM_CHKSUM:
11755                 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
11756                 break;
11757         case ASC_WARN_IRQ_MODIFIED:
11758                 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
11759                 break;
11760         case ASC_WARN_CMD_QNG_CONFLICT:
11761                 shost_printk(KERN_WARNING, shost, "tag queuing enabled w/o "
11762                                 "disconnects\n");
11763                 break;
11764         default:
11765                 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
11766                                 warn_code);
11767                 break;
11768         }
11769
11770         if (asc_dvc->err_code != 0)
11771                 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
11772                         "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
11773
11774         return asc_dvc->err_code;
11775 }
11776
11777 static int __devinit AscInitSetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
11778 {
11779         struct asc_board *board = shost_priv(shost);
11780         ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
11781         PortAddr iop_base = asc_dvc->iop_base;
11782         unsigned short cfg_msw;
11783         unsigned short warn_code = 0;
11784
11785         asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG;
11786         if (asc_dvc->err_code != 0)
11787                 return asc_dvc->err_code;
11788         if (!AscFindSignature(asc_dvc->iop_base)) {
11789                 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
11790                 return asc_dvc->err_code;
11791         }
11792
11793         cfg_msw = AscGetChipCfgMsw(iop_base);
11794         if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
11795                 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
11796                 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
11797                 AscSetChipCfgMsw(iop_base, cfg_msw);
11798         }
11799         if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) !=
11800             asc_dvc->cfg->cmd_qng_enabled) {
11801                 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled;
11802                 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
11803         }
11804         if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
11805                 warn_code |= ASC_WARN_AUTO_CONFIG;
11806         }
11807 #ifdef CONFIG_PCI
11808         if (asc_dvc->bus_type & ASC_IS_PCI) {
11809                 cfg_msw &= 0xFFC0;
11810                 AscSetChipCfgMsw(iop_base, cfg_msw);
11811                 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) {
11812                 } else {
11813                         if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
11814                             (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
11815                                 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
11816                                 asc_dvc->bug_fix_cntl |=
11817                                     ASC_BUG_FIX_ASYN_USE_SYN;
11818                         }
11819                 }
11820         } else
11821 #endif /* CONFIG_PCI */
11822         if (asc_dvc->bus_type == ASC_IS_ISAPNP) {
11823                 if (AscGetChipVersion(iop_base, asc_dvc->bus_type)
11824                     == ASC_CHIP_VER_ASYN_BUG) {
11825                         asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
11826                 }
11827         }
11828         if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) !=
11829             asc_dvc->cfg->chip_scsi_id) {
11830                 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID;
11831         }
11832 #ifdef CONFIG_ISA
11833         if (asc_dvc->bus_type & ASC_IS_ISA) {
11834                 AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel);
11835                 AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed);
11836         }
11837 #endif /* CONFIG_ISA */
11838
11839         asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG;
11840
11841         switch (warn_code) {
11842         case 0: /* No error. */
11843                 break;
11844         case ASC_WARN_IO_PORT_ROTATE:
11845                 shost_printk(KERN_WARNING, shost, "I/O port address "
11846                                 "modified\n");
11847                 break;
11848         case ASC_WARN_AUTO_CONFIG:
11849                 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
11850                                 "enabled\n");
11851                 break;
11852         case ASC_WARN_EEPROM_CHKSUM:
11853                 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
11854                 break;
11855         case ASC_WARN_IRQ_MODIFIED:
11856                 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
11857                 break;
11858         case ASC_WARN_CMD_QNG_CONFLICT:
11859                 shost_printk(KERN_WARNING, shost, "tag queuing w/o "
11860                                 "disconnects\n");
11861                 break;
11862         default:
11863                 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
11864                                 warn_code);
11865                 break;
11866         }
11867
11868         if (asc_dvc->err_code != 0)
11869                 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
11870                         "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
11871
11872         return asc_dvc->err_code;
11873 }
11874
11875 /*
11876  * EEPROM Configuration.
11877  *
11878  * All drivers should use this structure to set the default EEPROM
11879  * configuration. The BIOS now uses this structure when it is built.
11880  * Additional structure information can be found in a_condor.h where
11881  * the structure is defined.
11882  *
11883  * The *_Field_IsChar structs are needed to correct for endianness.
11884  * These values are read from the board 16 bits at a time directly
11885  * into the structs. Because some fields are char, the values will be
11886  * in the wrong order. The *_Field_IsChar tells when to flip the
11887  * bytes. Data read and written to PCI memory is automatically swapped
11888  * on big-endian platforms so char fields read as words are actually being
11889  * unswapped on big-endian platforms.
11890  */
11891 static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config __devinitdata = {
11892         ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */
11893         0x0000,                 /* cfg_msw */
11894         0xFFFF,                 /* disc_enable */
11895         0xFFFF,                 /* wdtr_able */
11896         0xFFFF,                 /* sdtr_able */
11897         0xFFFF,                 /* start_motor */
11898         0xFFFF,                 /* tagqng_able */
11899         0xFFFF,                 /* bios_scan */
11900         0,                      /* scam_tolerant */
11901         7,                      /* adapter_scsi_id */
11902         0,                      /* bios_boot_delay */
11903         3,                      /* scsi_reset_delay */
11904         0,                      /* bios_id_lun */
11905         0,                      /* termination */
11906         0,                      /* reserved1 */
11907         0xFFE7,                 /* bios_ctrl */
11908         0xFFFF,                 /* ultra_able */
11909         0,                      /* reserved2 */
11910         ASC_DEF_MAX_HOST_QNG,   /* max_host_qng */
11911         ASC_DEF_MAX_DVC_QNG,    /* max_dvc_qng */
11912         0,                      /* dvc_cntl */
11913         0,                      /* bug_fix */
11914         0,                      /* serial_number_word1 */
11915         0,                      /* serial_number_word2 */
11916         0,                      /* serial_number_word3 */
11917         0,                      /* check_sum */
11918         {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
11919         ,                       /* oem_name[16] */
11920         0,                      /* dvc_err_code */
11921         0,                      /* adv_err_code */
11922         0,                      /* adv_err_addr */
11923         0,                      /* saved_dvc_err_code */
11924         0,                      /* saved_adv_err_code */
11925         0,                      /* saved_adv_err_addr */
11926         0                       /* num_of_err */
11927 };
11928
11929 static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar __devinitdata = {
11930         0,                      /* cfg_lsw */
11931         0,                      /* cfg_msw */
11932         0,                      /* -disc_enable */
11933         0,                      /* wdtr_able */
11934         0,                      /* sdtr_able */
11935         0,                      /* start_motor */
11936         0,                      /* tagqng_able */
11937         0,                      /* bios_scan */
11938         0,                      /* scam_tolerant */
11939         1,                      /* adapter_scsi_id */
11940         1,                      /* bios_boot_delay */
11941         1,                      /* scsi_reset_delay */
11942         1,                      /* bios_id_lun */
11943         1,                      /* termination */
11944         1,                      /* reserved1 */
11945         0,                      /* bios_ctrl */
11946         0,                      /* ultra_able */
11947         0,                      /* reserved2 */
11948         1,                      /* max_host_qng */
11949         1,                      /* max_dvc_qng */
11950         0,                      /* dvc_cntl */
11951         0,                      /* bug_fix */
11952         0,                      /* serial_number_word1 */
11953         0,                      /* serial_number_word2 */
11954         0,                      /* serial_number_word3 */
11955         0,                      /* check_sum */
11956         {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
11957         ,                       /* oem_name[16] */
11958         0,                      /* dvc_err_code */
11959         0,                      /* adv_err_code */
11960         0,                      /* adv_err_addr */
11961         0,                      /* saved_dvc_err_code */
11962         0,                      /* saved_adv_err_code */
11963         0,                      /* saved_adv_err_addr */
11964         0                       /* num_of_err */
11965 };
11966
11967 static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config __devinitdata = {
11968         ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
11969         0x0000,                 /* 01 cfg_msw */
11970         0xFFFF,                 /* 02 disc_enable */
11971         0xFFFF,                 /* 03 wdtr_able */
11972         0x4444,                 /* 04 sdtr_speed1 */
11973         0xFFFF,                 /* 05 start_motor */
11974         0xFFFF,                 /* 06 tagqng_able */
11975         0xFFFF,                 /* 07 bios_scan */
11976         0,                      /* 08 scam_tolerant */
11977         7,                      /* 09 adapter_scsi_id */
11978         0,                      /*    bios_boot_delay */
11979         3,                      /* 10 scsi_reset_delay */
11980         0,                      /*    bios_id_lun */
11981         0,                      /* 11 termination_se */
11982         0,                      /*    termination_lvd */
11983         0xFFE7,                 /* 12 bios_ctrl */
11984         0x4444,                 /* 13 sdtr_speed2 */
11985         0x4444,                 /* 14 sdtr_speed3 */
11986         ASC_DEF_MAX_HOST_QNG,   /* 15 max_host_qng */
11987         ASC_DEF_MAX_DVC_QNG,    /*    max_dvc_qng */
11988         0,                      /* 16 dvc_cntl */
11989         0x4444,                 /* 17 sdtr_speed4 */
11990         0,                      /* 18 serial_number_word1 */
11991         0,                      /* 19 serial_number_word2 */
11992         0,                      /* 20 serial_number_word3 */
11993         0,                      /* 21 check_sum */
11994         {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
11995         ,                       /* 22-29 oem_name[16] */
11996         0,                      /* 30 dvc_err_code */
11997         0,                      /* 31 adv_err_code */
11998         0,                      /* 32 adv_err_addr */
11999         0,                      /* 33 saved_dvc_err_code */
12000         0,                      /* 34 saved_adv_err_code */
12001         0,                      /* 35 saved_adv_err_addr */
12002         0,                      /* 36 reserved */
12003         0,                      /* 37 reserved */
12004         0,                      /* 38 reserved */
12005         0,                      /* 39 reserved */
12006         0,                      /* 40 reserved */
12007         0,                      /* 41 reserved */
12008         0,                      /* 42 reserved */
12009         0,                      /* 43 reserved */
12010         0,                      /* 44 reserved */
12011         0,                      /* 45 reserved */
12012         0,                      /* 46 reserved */
12013         0,                      /* 47 reserved */
12014         0,                      /* 48 reserved */
12015         0,                      /* 49 reserved */
12016         0,                      /* 50 reserved */
12017         0,                      /* 51 reserved */
12018         0,                      /* 52 reserved */
12019         0,                      /* 53 reserved */
12020         0,                      /* 54 reserved */
12021         0,                      /* 55 reserved */
12022         0,                      /* 56 cisptr_lsw */
12023         0,                      /* 57 cisprt_msw */
12024         PCI_VENDOR_ID_ASP,      /* 58 subsysvid */
12025         PCI_DEVICE_ID_38C0800_REV1,     /* 59 subsysid */
12026         0,                      /* 60 reserved */
12027         0,                      /* 61 reserved */
12028         0,                      /* 62 reserved */
12029         0                       /* 63 reserved */
12030 };
12031
12032 static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar __devinitdata = {
12033         0,                      /* 00 cfg_lsw */
12034         0,                      /* 01 cfg_msw */
12035         0,                      /* 02 disc_enable */
12036         0,                      /* 03 wdtr_able */
12037         0,                      /* 04 sdtr_speed1 */
12038         0,                      /* 05 start_motor */
12039         0,                      /* 06 tagqng_able */
12040         0,                      /* 07 bios_scan */
12041         0,                      /* 08 scam_tolerant */
12042         1,                      /* 09 adapter_scsi_id */
12043         1,                      /*    bios_boot_delay */
12044         1,                      /* 10 scsi_reset_delay */
12045         1,                      /*    bios_id_lun */
12046         1,                      /* 11 termination_se */
12047         1,                      /*    termination_lvd */
12048         0,                      /* 12 bios_ctrl */
12049         0,                      /* 13 sdtr_speed2 */
12050         0,                      /* 14 sdtr_speed3 */
12051         1,                      /* 15 max_host_qng */
12052         1,                      /*    max_dvc_qng */
12053         0,                      /* 16 dvc_cntl */
12054         0,                      /* 17 sdtr_speed4 */
12055         0,                      /* 18 serial_number_word1 */
12056         0,                      /* 19 serial_number_word2 */
12057         0,                      /* 20 serial_number_word3 */
12058         0,                      /* 21 check_sum */
12059         {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
12060         ,                       /* 22-29 oem_name[16] */
12061         0,                      /* 30 dvc_err_code */
12062         0,                      /* 31 adv_err_code */
12063         0,                      /* 32 adv_err_addr */
12064         0,                      /* 33 saved_dvc_err_code */
12065         0,                      /* 34 saved_adv_err_code */
12066         0,                      /* 35 saved_adv_err_addr */
12067         0,                      /* 36 reserved */
12068         0,                      /* 37 reserved */
12069         0,                      /* 38 reserved */
12070         0,                      /* 39 reserved */
12071         0,                      /* 40 reserved */
12072         0,                      /* 41 reserved */
12073         0,                      /* 42 reserved */
12074         0,                      /* 43 reserved */
12075         0,                      /* 44 reserved */
12076         0,                      /* 45 reserved */
12077         0,                      /* 46 reserved */
12078         0,                      /* 47 reserved */
12079         0,                      /* 48 reserved */
12080         0,                      /* 49 reserved */
12081         0,                      /* 50 reserved */
12082         0,                      /* 51 reserved */
12083         0,                      /* 52 reserved */
12084         0,                      /* 53 reserved */
12085         0,                      /* 54 reserved */
12086         0,                      /* 55 reserved */
12087         0,                      /* 56 cisptr_lsw */
12088         0,                      /* 57 cisprt_msw */
12089         0,                      /* 58 subsysvid */
12090         0,                      /* 59 subsysid */
12091         0,                      /* 60 reserved */
12092         0,                      /* 61 reserved */
12093         0,                      /* 62 reserved */
12094         0                       /* 63 reserved */
12095 };
12096
12097 static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config __devinitdata = {
12098         ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
12099         0x0000,                 /* 01 cfg_msw */
12100         0xFFFF,                 /* 02 disc_enable */
12101         0xFFFF,                 /* 03 wdtr_able */
12102         0x5555,                 /* 04 sdtr_speed1 */
12103         0xFFFF,                 /* 05 start_motor */
12104         0xFFFF,                 /* 06 tagqng_able */
12105         0xFFFF,                 /* 07 bios_scan */
12106         0,                      /* 08 scam_tolerant */
12107         7,                      /* 09 adapter_scsi_id */
12108         0,                      /*    bios_boot_delay */
12109         3,                      /* 10 scsi_reset_delay */
12110         0,                      /*    bios_id_lun */
12111         0,                      /* 11 termination_se */
12112         0,                      /*    termination_lvd */
12113         0xFFE7,                 /* 12 bios_ctrl */
12114         0x5555,                 /* 13 sdtr_speed2 */
12115         0x5555,                 /* 14 sdtr_speed3 */
12116         ASC_DEF_MAX_HOST_QNG,   /* 15 max_host_qng */
12117         ASC_DEF_MAX_DVC_QNG,    /*    max_dvc_qng */
12118         0,                      /* 16 dvc_cntl */
12119         0x5555,                 /* 17 sdtr_speed4 */
12120         0,                      /* 18 serial_number_word1 */
12121         0,                      /* 19 serial_number_word2 */
12122         0,                      /* 20 serial_number_word3 */
12123         0,                      /* 21 check_sum */
12124         {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
12125         ,                       /* 22-29 oem_name[16] */
12126         0,                      /* 30 dvc_err_code */
12127         0,                      /* 31 adv_err_code */
12128         0,                      /* 32 adv_err_addr */
12129         0,                      /* 33 saved_dvc_err_code */
12130         0,                      /* 34 saved_adv_err_code */
12131         0,                      /* 35 saved_adv_err_addr */
12132         0,                      /* 36 reserved */
12133         0,                      /* 37 reserved */
12134         0,                      /* 38 reserved */
12135         0,                      /* 39 reserved */
12136         0,                      /* 40 reserved */
12137         0,                      /* 41 reserved */
12138         0,                      /* 42 reserved */
12139         0,                      /* 43 reserved */
12140         0,                      /* 44 reserved */
12141         0,                      /* 45 reserved */
12142         0,                      /* 46 reserved */
12143         0,                      /* 47 reserved */
12144         0,                      /* 48 reserved */
12145         0,                      /* 49 reserved */
12146         0,                      /* 50 reserved */
12147         0,                      /* 51 reserved */
12148         0,                      /* 52 reserved */
12149         0,                      /* 53 reserved */
12150         0,                      /* 54 reserved */
12151         0,                      /* 55 reserved */
12152         0,                      /* 56 cisptr_lsw */
12153         0,                      /* 57 cisprt_msw */
12154         PCI_VENDOR_ID_ASP,      /* 58 subsysvid */
12155         PCI_DEVICE_ID_38C1600_REV1,     /* 59 subsysid */
12156         0,                      /* 60 reserved */
12157         0,                      /* 61 reserved */
12158         0,                      /* 62 reserved */
12159         0                       /* 63 reserved */
12160 };
12161
12162 static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar __devinitdata = {
12163         0,                      /* 00 cfg_lsw */
12164         0,                      /* 01 cfg_msw */
12165         0,                      /* 02 disc_enable */
12166         0,                      /* 03 wdtr_able */
12167         0,                      /* 04 sdtr_speed1 */
12168         0,                      /* 05 start_motor */
12169         0,                      /* 06 tagqng_able */
12170         0,                      /* 07 bios_scan */
12171         0,                      /* 08 scam_tolerant */
12172         1,                      /* 09 adapter_scsi_id */
12173         1,                      /*    bios_boot_delay */
12174         1,                      /* 10 scsi_reset_delay */
12175         1,                      /*    bios_id_lun */
12176         1,                      /* 11 termination_se */
12177         1,                      /*    termination_lvd */
12178         0,                      /* 12 bios_ctrl */
12179         0,                      /* 13 sdtr_speed2 */
12180         0,                      /* 14 sdtr_speed3 */
12181         1,                      /* 15 max_host_qng */
12182         1,                      /*    max_dvc_qng */
12183         0,                      /* 16 dvc_cntl */
12184         0,                      /* 17 sdtr_speed4 */
12185         0,                      /* 18 serial_number_word1 */
12186         0,                      /* 19 serial_number_word2 */
12187         0,                      /* 20 serial_number_word3 */
12188         0,                      /* 21 check_sum */
12189         {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
12190         ,                       /* 22-29 oem_name[16] */
12191         0,                      /* 30 dvc_err_code */
12192         0,                      /* 31 adv_err_code */
12193         0,                      /* 32 adv_err_addr */
12194         0,                      /* 33 saved_dvc_err_code */
12195         0,                      /* 34 saved_adv_err_code */
12196         0,                      /* 35 saved_adv_err_addr */
12197         0,                      /* 36 reserved */
12198         0,                      /* 37 reserved */
12199         0,                      /* 38 reserved */
12200         0,                      /* 39 reserved */
12201         0,                      /* 40 reserved */
12202         0,                      /* 41 reserved */
12203         0,                      /* 42 reserved */
12204         0,                      /* 43 reserved */
12205         0,                      /* 44 reserved */
12206         0,                      /* 45 reserved */
12207         0,                      /* 46 reserved */
12208         0,                      /* 47 reserved */
12209         0,                      /* 48 reserved */
12210         0,                      /* 49 reserved */
12211         0,                      /* 50 reserved */
12212         0,                      /* 51 reserved */
12213         0,                      /* 52 reserved */
12214         0,                      /* 53 reserved */
12215         0,                      /* 54 reserved */
12216         0,                      /* 55 reserved */
12217         0,                      /* 56 cisptr_lsw */
12218         0,                      /* 57 cisprt_msw */
12219         0,                      /* 58 subsysvid */
12220         0,                      /* 59 subsysid */
12221         0,                      /* 60 reserved */
12222         0,                      /* 61 reserved */
12223         0,                      /* 62 reserved */
12224         0                       /* 63 reserved */
12225 };
12226
12227 #ifdef CONFIG_PCI
12228 /*
12229  * Wait for EEPROM command to complete
12230  */
12231 static void __devinit AdvWaitEEPCmd(AdvPortAddr iop_base)
12232 {
12233         int eep_delay_ms;
12234
12235         for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++) {
12236                 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) &
12237                     ASC_EEP_CMD_DONE) {
12238                         break;
12239                 }
12240                 mdelay(1);
12241         }
12242         if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) ==
12243             0)
12244                 BUG();
12245 }
12246
12247 /*
12248  * Read the EEPROM from specified location
12249  */
12250 static ushort __devinit AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
12251 {
12252         AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12253                              ASC_EEP_CMD_READ | eep_word_addr);
12254         AdvWaitEEPCmd(iop_base);
12255         return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
12256 }
12257
12258 /*
12259  * Write the EEPROM from 'cfg_buf'.
12260  */
12261 void __devinit
12262 AdvSet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
12263 {
12264         ushort *wbuf;
12265         ushort addr, chksum;
12266         ushort *charfields;
12267
12268         wbuf = (ushort *)cfg_buf;
12269         charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
12270         chksum = 0;
12271
12272         AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
12273         AdvWaitEEPCmd(iop_base);
12274
12275         /*
12276          * Write EEPROM from word 0 to word 20.
12277          */
12278         for (addr = ADV_EEP_DVC_CFG_BEGIN;
12279              addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
12280                 ushort word;
12281
12282                 if (*charfields++) {
12283                         word = cpu_to_le16(*wbuf);
12284                 } else {
12285                         word = *wbuf;
12286                 }
12287                 chksum += *wbuf;        /* Checksum is calculated from word values. */
12288                 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12289                 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12290                                      ASC_EEP_CMD_WRITE | addr);
12291                 AdvWaitEEPCmd(iop_base);
12292                 mdelay(ADV_EEP_DELAY_MS);
12293         }
12294
12295         /*
12296          * Write EEPROM checksum at word 21.
12297          */
12298         AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
12299         AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
12300         AdvWaitEEPCmd(iop_base);
12301         wbuf++;
12302         charfields++;
12303
12304         /*
12305          * Write EEPROM OEM name at words 22 to 29.
12306          */
12307         for (addr = ADV_EEP_DVC_CTL_BEGIN;
12308              addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
12309                 ushort word;
12310
12311                 if (*charfields++) {
12312                         word = cpu_to_le16(*wbuf);
12313                 } else {
12314                         word = *wbuf;
12315                 }
12316                 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12317                 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12318                                      ASC_EEP_CMD_WRITE | addr);
12319                 AdvWaitEEPCmd(iop_base);
12320         }
12321         AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
12322         AdvWaitEEPCmd(iop_base);
12323 }
12324
12325 /*
12326  * Write the EEPROM from 'cfg_buf'.
12327  */
12328 void __devinit
12329 AdvSet38C0800EEPConfig(AdvPortAddr iop_base, ADVEEP_38C0800_CONFIG *cfg_buf)
12330 {
12331         ushort *wbuf;
12332         ushort *charfields;
12333         ushort addr, chksum;
12334
12335         wbuf = (ushort *)cfg_buf;
12336         charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
12337         chksum = 0;
12338
12339         AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
12340         AdvWaitEEPCmd(iop_base);
12341
12342         /*
12343          * Write EEPROM from word 0 to word 20.
12344          */
12345         for (addr = ADV_EEP_DVC_CFG_BEGIN;
12346              addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
12347                 ushort word;
12348
12349                 if (*charfields++) {
12350                         word = cpu_to_le16(*wbuf);
12351                 } else {
12352                         word = *wbuf;
12353                 }
12354                 chksum += *wbuf;        /* Checksum is calculated from word values. */
12355                 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12356                 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12357                                      ASC_EEP_CMD_WRITE | addr);
12358                 AdvWaitEEPCmd(iop_base);
12359                 mdelay(ADV_EEP_DELAY_MS);
12360         }
12361
12362         /*
12363          * Write EEPROM checksum at word 21.
12364          */
12365         AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
12366         AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
12367         AdvWaitEEPCmd(iop_base);
12368         wbuf++;
12369         charfields++;
12370
12371         /*
12372          * Write EEPROM OEM name at words 22 to 29.
12373          */
12374         for (addr = ADV_EEP_DVC_CTL_BEGIN;
12375              addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
12376                 ushort word;
12377
12378                 if (*charfields++) {
12379                         word = cpu_to_le16(*wbuf);
12380                 } else {
12381                         word = *wbuf;
12382                 }
12383                 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12384                 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12385                                      ASC_EEP_CMD_WRITE | addr);
12386                 AdvWaitEEPCmd(iop_base);
12387         }
12388         AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
12389         AdvWaitEEPCmd(iop_base);
12390 }
12391
12392 /*
12393  * Write the EEPROM from 'cfg_buf'.
12394  */
12395 void __devinit
12396 AdvSet38C1600EEPConfig(AdvPortAddr iop_base, ADVEEP_38C1600_CONFIG *cfg_buf)
12397 {
12398         ushort *wbuf;
12399         ushort *charfields;
12400         ushort addr, chksum;
12401
12402         wbuf = (ushort *)cfg_buf;
12403         charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
12404         chksum = 0;
12405
12406         AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
12407         AdvWaitEEPCmd(iop_base);
12408
12409         /*
12410          * Write EEPROM from word 0 to word 20.
12411          */
12412         for (addr = ADV_EEP_DVC_CFG_BEGIN;
12413              addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
12414                 ushort word;
12415
12416                 if (*charfields++) {
12417                         word = cpu_to_le16(*wbuf);
12418                 } else {
12419                         word = *wbuf;
12420                 }
12421                 chksum += *wbuf;        /* Checksum is calculated from word values. */
12422                 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12423                 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12424                                      ASC_EEP_CMD_WRITE | addr);
12425                 AdvWaitEEPCmd(iop_base);
12426                 mdelay(ADV_EEP_DELAY_MS);
12427         }
12428
12429         /*
12430          * Write EEPROM checksum at word 21.
12431          */
12432         AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
12433         AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
12434         AdvWaitEEPCmd(iop_base);
12435         wbuf++;
12436         charfields++;
12437
12438         /*
12439          * Write EEPROM OEM name at words 22 to 29.
12440          */
12441         for (addr = ADV_EEP_DVC_CTL_BEGIN;
12442              addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
12443                 ushort word;
12444
12445                 if (*charfields++) {
12446                         word = cpu_to_le16(*wbuf);
12447                 } else {
12448                         word = *wbuf;
12449                 }
12450                 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12451                 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12452                                      ASC_EEP_CMD_WRITE | addr);
12453                 AdvWaitEEPCmd(iop_base);
12454         }
12455         AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
12456         AdvWaitEEPCmd(iop_base);
12457 }
12458
12459 /*
12460  * Read EEPROM configuration into the specified buffer.
12461  *
12462  * Return a checksum based on the EEPROM configuration read.
12463  */
12464 static ushort __devinit
12465 AdvGet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
12466 {
12467         ushort wval, chksum;
12468         ushort *wbuf;
12469         int eep_addr;
12470         ushort *charfields;
12471
12472         charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
12473         wbuf = (ushort *)cfg_buf;
12474         chksum = 0;
12475
12476         for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
12477              eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
12478                 wval = AdvReadEEPWord(iop_base, eep_addr);
12479                 chksum += wval; /* Checksum is calculated from word values. */
12480                 if (*charfields++) {
12481                         *wbuf = le16_to_cpu(wval);
12482                 } else {
12483                         *wbuf = wval;
12484                 }
12485         }
12486         /* Read checksum word. */
12487         *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12488         wbuf++;
12489         charfields++;
12490
12491         /* Read rest of EEPROM not covered by the checksum. */
12492         for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
12493              eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
12494                 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12495                 if (*charfields++) {
12496                         *wbuf = le16_to_cpu(*wbuf);
12497                 }
12498         }
12499         return chksum;
12500 }
12501
12502 /*
12503  * Read EEPROM configuration into the specified buffer.
12504  *
12505  * Return a checksum based on the EEPROM configuration read.
12506  */
12507 static ushort __devinit
12508 AdvGet38C0800EEPConfig(AdvPortAddr iop_base, ADVEEP_38C0800_CONFIG *cfg_buf)
12509 {
12510         ushort wval, chksum;
12511         ushort *wbuf;
12512         int eep_addr;
12513         ushort *charfields;
12514
12515         charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
12516         wbuf = (ushort *)cfg_buf;
12517         chksum = 0;
12518
12519         for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
12520              eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
12521                 wval = AdvReadEEPWord(iop_base, eep_addr);
12522                 chksum += wval; /* Checksum is calculated from word values. */
12523                 if (*charfields++) {
12524                         *wbuf = le16_to_cpu(wval);
12525                 } else {
12526                         *wbuf = wval;
12527                 }
12528         }
12529         /* Read checksum word. */
12530         *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12531         wbuf++;
12532         charfields++;
12533
12534         /* Read rest of EEPROM not covered by the checksum. */
12535         for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
12536              eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
12537                 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12538                 if (*charfields++) {
12539                         *wbuf = le16_to_cpu(*wbuf);
12540                 }
12541         }
12542         return chksum;
12543 }
12544
12545 /*
12546  * Read EEPROM configuration into the specified buffer.
12547  *
12548  * Return a checksum based on the EEPROM configuration read.
12549  */
12550 static ushort __devinit
12551 AdvGet38C1600EEPConfig(AdvPortAddr iop_base, ADVEEP_38C1600_CONFIG *cfg_buf)
12552 {
12553         ushort wval, chksum;
12554         ushort *wbuf;
12555         int eep_addr;
12556         ushort *charfields;
12557
12558         charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
12559         wbuf = (ushort *)cfg_buf;
12560         chksum = 0;
12561
12562         for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
12563              eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
12564                 wval = AdvReadEEPWord(iop_base, eep_addr);
12565                 chksum += wval; /* Checksum is calculated from word values. */
12566                 if (*charfields++) {
12567                         *wbuf = le16_to_cpu(wval);
12568                 } else {
12569                         *wbuf = wval;
12570                 }
12571         }
12572         /* Read checksum word. */
12573         *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12574         wbuf++;
12575         charfields++;
12576
12577         /* Read rest of EEPROM not covered by the checksum. */
12578         for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
12579              eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
12580                 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12581                 if (*charfields++) {
12582                         *wbuf = le16_to_cpu(*wbuf);
12583                 }
12584         }
12585         return chksum;
12586 }
12587
12588 /*
12589  * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
12590  * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
12591  * all of this is done.
12592  *
12593  * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
12594  *
12595  * For a non-fatal error return a warning code. If there are no warnings
12596  * then 0 is returned.
12597  *
12598  * Note: Chip is stopped on entry.
12599  */
12600 static int __devinit AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
12601 {
12602         AdvPortAddr iop_base;
12603         ushort warn_code;
12604         ADVEEP_3550_CONFIG eep_config;
12605
12606         iop_base = asc_dvc->iop_base;
12607
12608         warn_code = 0;
12609
12610         /*
12611          * Read the board's EEPROM configuration.
12612          *
12613          * Set default values if a bad checksum is found.
12614          */
12615         if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum) {
12616                 warn_code |= ASC_WARN_EEPROM_CHKSUM;
12617
12618                 /*
12619                  * Set EEPROM default values.
12620                  */
12621                 memcpy(&eep_config, &Default_3550_EEPROM_Config,
12622                         sizeof(ADVEEP_3550_CONFIG));
12623
12624                 /*
12625                  * Assume the 6 byte board serial number that was read from
12626                  * EEPROM is correct even if the EEPROM checksum failed.
12627                  */
12628                 eep_config.serial_number_word3 =
12629                     AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
12630
12631                 eep_config.serial_number_word2 =
12632                     AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
12633
12634                 eep_config.serial_number_word1 =
12635                     AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
12636
12637                 AdvSet3550EEPConfig(iop_base, &eep_config);
12638         }
12639         /*
12640          * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
12641          * EEPROM configuration that was read.
12642          *
12643          * This is the mapping of EEPROM fields to Adv Library fields.
12644          */
12645         asc_dvc->wdtr_able = eep_config.wdtr_able;
12646         asc_dvc->sdtr_able = eep_config.sdtr_able;
12647         asc_dvc->ultra_able = eep_config.ultra_able;
12648         asc_dvc->tagqng_able = eep_config.tagqng_able;
12649         asc_dvc->cfg->disc_enable = eep_config.disc_enable;
12650         asc_dvc->max_host_qng = eep_config.max_host_qng;
12651         asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
12652         asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
12653         asc_dvc->start_motor = eep_config.start_motor;
12654         asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
12655         asc_dvc->bios_ctrl = eep_config.bios_ctrl;
12656         asc_dvc->no_scam = eep_config.scam_tolerant;
12657         asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
12658         asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
12659         asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
12660
12661         /*
12662          * Set the host maximum queuing (max. 253, min. 16) and the per device
12663          * maximum queuing (max. 63, min. 4).
12664          */
12665         if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
12666                 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
12667         } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
12668                 /* If the value is zero, assume it is uninitialized. */
12669                 if (eep_config.max_host_qng == 0) {
12670                         eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
12671                 } else {
12672                         eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
12673                 }
12674         }
12675
12676         if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
12677                 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
12678         } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
12679                 /* If the value is zero, assume it is uninitialized. */
12680                 if (eep_config.max_dvc_qng == 0) {
12681                         eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
12682                 } else {
12683                         eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
12684                 }
12685         }
12686
12687         /*
12688          * If 'max_dvc_qng' is greater than 'max_host_qng', then
12689          * set 'max_dvc_qng' to 'max_host_qng'.
12690          */
12691         if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
12692                 eep_config.max_dvc_qng = eep_config.max_host_qng;
12693         }
12694
12695         /*
12696          * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
12697          * values based on possibly adjusted EEPROM values.
12698          */
12699         asc_dvc->max_host_qng = eep_config.max_host_qng;
12700         asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
12701
12702         /*
12703          * If the EEPROM 'termination' field is set to automatic (0), then set
12704          * the ADV_DVC_CFG 'termination' field to automatic also.
12705          *
12706          * If the termination is specified with a non-zero 'termination'
12707          * value check that a legal value is set and set the ADV_DVC_CFG
12708          * 'termination' field appropriately.
12709          */
12710         if (eep_config.termination == 0) {
12711                 asc_dvc->cfg->termination = 0;  /* auto termination */
12712         } else {
12713                 /* Enable manual control with low off / high off. */
12714                 if (eep_config.termination == 1) {
12715                         asc_dvc->cfg->termination = TERM_CTL_SEL;
12716
12717                         /* Enable manual control with low off / high on. */
12718                 } else if (eep_config.termination == 2) {
12719                         asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
12720
12721                         /* Enable manual control with low on / high on. */
12722                 } else if (eep_config.termination == 3) {
12723                         asc_dvc->cfg->termination =
12724                             TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
12725                 } else {
12726                         /*
12727                          * The EEPROM 'termination' field contains a bad value. Use
12728                          * automatic termination instead.
12729                          */
12730                         asc_dvc->cfg->termination = 0;
12731                         warn_code |= ASC_WARN_EEPROM_TERMINATION;
12732                 }
12733         }
12734
12735         return warn_code;
12736 }
12737
12738 /*
12739  * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
12740  * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
12741  * all of this is done.
12742  *
12743  * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
12744  *
12745  * For a non-fatal error return a warning code. If there are no warnings
12746  * then 0 is returned.
12747  *
12748  * Note: Chip is stopped on entry.
12749  */
12750 static int __devinit AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
12751 {
12752         AdvPortAddr iop_base;
12753         ushort warn_code;
12754         ADVEEP_38C0800_CONFIG eep_config;
12755         uchar tid, termination;
12756         ushort sdtr_speed = 0;
12757
12758         iop_base = asc_dvc->iop_base;
12759
12760         warn_code = 0;
12761
12762         /*
12763          * Read the board's EEPROM configuration.
12764          *
12765          * Set default values if a bad checksum is found.
12766          */
12767         if (AdvGet38C0800EEPConfig(iop_base, &eep_config) !=
12768             eep_config.check_sum) {
12769                 warn_code |= ASC_WARN_EEPROM_CHKSUM;
12770
12771                 /*
12772                  * Set EEPROM default values.
12773                  */
12774                 memcpy(&eep_config, &Default_38C0800_EEPROM_Config,
12775                         sizeof(ADVEEP_38C0800_CONFIG));
12776
12777                 /*
12778                  * Assume the 6 byte board serial number that was read from
12779                  * EEPROM is correct even if the EEPROM checksum failed.
12780                  */
12781                 eep_config.serial_number_word3 =
12782                     AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
12783
12784                 eep_config.serial_number_word2 =
12785                     AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
12786
12787                 eep_config.serial_number_word1 =
12788                     AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
12789
12790                 AdvSet38C0800EEPConfig(iop_base, &eep_config);
12791         }
12792         /*
12793          * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
12794          * EEPROM configuration that was read.
12795          *
12796          * This is the mapping of EEPROM fields to Adv Library fields.
12797          */
12798         asc_dvc->wdtr_able = eep_config.wdtr_able;
12799         asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
12800         asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
12801         asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
12802         asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
12803         asc_dvc->tagqng_able = eep_config.tagqng_able;
12804         asc_dvc->cfg->disc_enable = eep_config.disc_enable;
12805         asc_dvc->max_host_qng = eep_config.max_host_qng;
12806         asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
12807         asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
12808         asc_dvc->start_motor = eep_config.start_motor;
12809         asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
12810         asc_dvc->bios_ctrl = eep_config.bios_ctrl;
12811         asc_dvc->no_scam = eep_config.scam_tolerant;
12812         asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
12813         asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
12814         asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
12815
12816         /*
12817          * For every Target ID if any of its 'sdtr_speed[1234]' bits
12818          * are set, then set an 'sdtr_able' bit for it.
12819          */
12820         asc_dvc->sdtr_able = 0;
12821         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
12822                 if (tid == 0) {
12823                         sdtr_speed = asc_dvc->sdtr_speed1;
12824                 } else if (tid == 4) {
12825                         sdtr_speed = asc_dvc->sdtr_speed2;
12826                 } else if (tid == 8) {
12827                         sdtr_speed = asc_dvc->sdtr_speed3;
12828                 } else if (tid == 12) {
12829                         sdtr_speed = asc_dvc->sdtr_speed4;
12830                 }
12831                 if (sdtr_speed & ADV_MAX_TID) {
12832                         asc_dvc->sdtr_able |= (1 << tid);
12833                 }
12834                 sdtr_speed >>= 4;
12835         }
12836
12837         /*
12838          * Set the host maximum queuing (max. 253, min. 16) and the per device
12839          * maximum queuing (max. 63, min. 4).
12840          */
12841         if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
12842                 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
12843         } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
12844                 /* If the value is zero, assume it is uninitialized. */
12845                 if (eep_config.max_host_qng == 0) {
12846                         eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
12847                 } else {
12848                         eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
12849                 }
12850         }
12851
12852         if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
12853                 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
12854         } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
12855                 /* If the value is zero, assume it is uninitialized. */
12856                 if (eep_config.max_dvc_qng == 0) {
12857                         eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
12858                 } else {
12859                         eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
12860                 }
12861         }
12862
12863         /*
12864          * If 'max_dvc_qng' is greater than 'max_host_qng', then
12865          * set 'max_dvc_qng' to 'max_host_qng'.
12866          */
12867         if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
12868                 eep_config.max_dvc_qng = eep_config.max_host_qng;
12869         }
12870
12871         /*
12872          * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
12873          * values based on possibly adjusted EEPROM values.
12874          */
12875         asc_dvc->max_host_qng = eep_config.max_host_qng;
12876         asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
12877
12878         /*
12879          * If the EEPROM 'termination' field is set to automatic (0), then set
12880          * the ADV_DVC_CFG 'termination' field to automatic also.
12881          *
12882          * If the termination is specified with a non-zero 'termination'
12883          * value check that a legal value is set and set the ADV_DVC_CFG
12884          * 'termination' field appropriately.
12885          */
12886         if (eep_config.termination_se == 0) {
12887                 termination = 0;        /* auto termination for SE */
12888         } else {
12889                 /* Enable manual control with low off / high off. */
12890                 if (eep_config.termination_se == 1) {
12891                         termination = 0;
12892
12893                         /* Enable manual control with low off / high on. */
12894                 } else if (eep_config.termination_se == 2) {
12895                         termination = TERM_SE_HI;
12896
12897                         /* Enable manual control with low on / high on. */
12898                 } else if (eep_config.termination_se == 3) {
12899                         termination = TERM_SE;
12900                 } else {
12901                         /*
12902                          * The EEPROM 'termination_se' field contains a bad value.
12903                          * Use automatic termination instead.
12904                          */
12905                         termination = 0;
12906                         warn_code |= ASC_WARN_EEPROM_TERMINATION;
12907                 }
12908         }
12909
12910         if (eep_config.termination_lvd == 0) {
12911                 asc_dvc->cfg->termination = termination;        /* auto termination for LVD */
12912         } else {
12913                 /* Enable manual control with low off / high off. */
12914                 if (eep_config.termination_lvd == 1) {
12915                         asc_dvc->cfg->termination = termination;
12916
12917                         /* Enable manual control with low off / high on. */
12918                 } else if (eep_config.termination_lvd == 2) {
12919                         asc_dvc->cfg->termination = termination | TERM_LVD_HI;
12920
12921                         /* Enable manual control with low on / high on. */
12922                 } else if (eep_config.termination_lvd == 3) {
12923                         asc_dvc->cfg->termination = termination | TERM_LVD;
12924                 } else {
12925                         /*
12926                          * The EEPROM 'termination_lvd' field contains a bad value.
12927                          * Use automatic termination instead.
12928                          */
12929                         asc_dvc->cfg->termination = termination;
12930                         warn_code |= ASC_WARN_EEPROM_TERMINATION;
12931                 }
12932         }
12933
12934         return warn_code;
12935 }
12936
12937 /*
12938  * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
12939  * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
12940  * all of this is done.
12941  *
12942  * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
12943  *
12944  * For a non-fatal error return a warning code. If there are no warnings
12945  * then 0 is returned.
12946  *
12947  * Note: Chip is stopped on entry.
12948  */
12949 static int __devinit AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
12950 {
12951         AdvPortAddr iop_base;
12952         ushort warn_code;
12953         ADVEEP_38C1600_CONFIG eep_config;
12954         uchar tid, termination;
12955         ushort sdtr_speed = 0;
12956
12957         iop_base = asc_dvc->iop_base;
12958
12959         warn_code = 0;
12960
12961         /*
12962          * Read the board's EEPROM configuration.
12963          *
12964          * Set default values if a bad checksum is found.
12965          */
12966         if (AdvGet38C1600EEPConfig(iop_base, &eep_config) !=
12967             eep_config.check_sum) {
12968                 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
12969                 warn_code |= ASC_WARN_EEPROM_CHKSUM;
12970
12971                 /*
12972                  * Set EEPROM default values.
12973                  */
12974                 memcpy(&eep_config, &Default_38C1600_EEPROM_Config,
12975                         sizeof(ADVEEP_38C1600_CONFIG));
12976
12977                 if (PCI_FUNC(pdev->devfn) != 0) {
12978                         u8 ints;
12979                         /*
12980                          * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60
12981                          * and old Mac system booting problem. The Expansion
12982                          * ROM must be disabled in Function 1 for these systems
12983                          */
12984                         eep_config.cfg_lsw &= ~ADV_EEPROM_BIOS_ENABLE;
12985                         /*
12986                          * Clear the INTAB (bit 11) if the GPIO 0 input
12987                          * indicates the Function 1 interrupt line is wired
12988                          * to INTB.
12989                          *
12990                          * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
12991                          *   1 - Function 1 interrupt line wired to INT A.
12992                          *   0 - Function 1 interrupt line wired to INT B.
12993                          *
12994                          * Note: Function 0 is always wired to INTA.
12995                          * Put all 5 GPIO bits in input mode and then read
12996                          * their input values.
12997                          */
12998                         AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0);
12999                         ints = AdvReadByteRegister(iop_base, IOPB_GPIO_DATA);
13000                         if ((ints & 0x01) == 0)
13001                                 eep_config.cfg_lsw &= ~ADV_EEPROM_INTAB;
13002                 }
13003
13004                 /*
13005                  * Assume the 6 byte board serial number that was read from
13006                  * EEPROM is correct even if the EEPROM checksum failed.
13007                  */
13008                 eep_config.serial_number_word3 =
13009                         AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
13010                 eep_config.serial_number_word2 =
13011                         AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
13012                 eep_config.serial_number_word1 =
13013                         AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
13014
13015                 AdvSet38C1600EEPConfig(iop_base, &eep_config);
13016         }
13017
13018         /*
13019          * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
13020          * EEPROM configuration that was read.
13021          *
13022          * This is the mapping of EEPROM fields to Adv Library fields.
13023          */
13024         asc_dvc->wdtr_able = eep_config.wdtr_able;
13025         asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
13026         asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
13027         asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
13028         asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
13029         asc_dvc->ppr_able = 0;
13030         asc_dvc->tagqng_able = eep_config.tagqng_able;
13031         asc_dvc->cfg->disc_enable = eep_config.disc_enable;
13032         asc_dvc->max_host_qng = eep_config.max_host_qng;
13033         asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13034         asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
13035         asc_dvc->start_motor = eep_config.start_motor;
13036         asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
13037         asc_dvc->bios_ctrl = eep_config.bios_ctrl;
13038         asc_dvc->no_scam = eep_config.scam_tolerant;
13039
13040         /*
13041          * For every Target ID if any of its 'sdtr_speed[1234]' bits
13042          * are set, then set an 'sdtr_able' bit for it.
13043          */
13044         asc_dvc->sdtr_able = 0;
13045         for (tid = 0; tid <= ASC_MAX_TID; tid++) {
13046                 if (tid == 0) {
13047                         sdtr_speed = asc_dvc->sdtr_speed1;
13048                 } else if (tid == 4) {
13049                         sdtr_speed = asc_dvc->sdtr_speed2;
13050                 } else if (tid == 8) {
13051                         sdtr_speed = asc_dvc->sdtr_speed3;
13052                 } else if (tid == 12) {
13053                         sdtr_speed = asc_dvc->sdtr_speed4;
13054                 }
13055                 if (sdtr_speed & ASC_MAX_TID) {
13056                         asc_dvc->sdtr_able |= (1 << tid);
13057                 }
13058                 sdtr_speed >>= 4;
13059         }
13060
13061         /*
13062          * Set the host maximum queuing (max. 253, min. 16) and the per device
13063          * maximum queuing (max. 63, min. 4).
13064          */
13065         if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
13066                 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13067         } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
13068                 /* If the value is zero, assume it is uninitialized. */
13069                 if (eep_config.max_host_qng == 0) {
13070                         eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13071                 } else {
13072                         eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
13073                 }
13074         }
13075
13076         if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
13077                 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13078         } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
13079                 /* If the value is zero, assume it is uninitialized. */
13080                 if (eep_config.max_dvc_qng == 0) {
13081                         eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13082                 } else {
13083                         eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
13084                 }
13085         }
13086
13087         /*
13088          * If 'max_dvc_qng' is greater than 'max_host_qng', then
13089          * set 'max_dvc_qng' to 'max_host_qng'.
13090          */
13091         if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
13092                 eep_config.max_dvc_qng = eep_config.max_host_qng;
13093         }
13094
13095         /*
13096          * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
13097          * values based on possibly adjusted EEPROM values.
13098          */
13099         asc_dvc->max_host_qng = eep_config.max_host_qng;
13100         asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13101
13102         /*
13103          * If the EEPROM 'termination' field is set to automatic (0), then set
13104          * the ASC_DVC_CFG 'termination' field to automatic also.
13105          *
13106          * If the termination is specified with a non-zero 'termination'
13107          * value check that a legal value is set and set the ASC_DVC_CFG
13108          * 'termination' field appropriately.
13109          */
13110         if (eep_config.termination_se == 0) {
13111                 termination = 0;        /* auto termination for SE */
13112         } else {
13113                 /* Enable manual control with low off / high off. */
13114                 if (eep_config.termination_se == 1) {
13115                         termination = 0;
13116
13117                         /* Enable manual control with low off / high on. */
13118                 } else if (eep_config.termination_se == 2) {
13119                         termination = TERM_SE_HI;
13120
13121                         /* Enable manual control with low on / high on. */
13122                 } else if (eep_config.termination_se == 3) {
13123                         termination = TERM_SE;
13124                 } else {
13125                         /*
13126                          * The EEPROM 'termination_se' field contains a bad value.
13127                          * Use automatic termination instead.
13128                          */
13129                         termination = 0;
13130                         warn_code |= ASC_WARN_EEPROM_TERMINATION;
13131                 }
13132         }
13133
13134         if (eep_config.termination_lvd == 0) {
13135                 asc_dvc->cfg->termination = termination;        /* auto termination for LVD */
13136         } else {
13137                 /* Enable manual control with low off / high off. */
13138                 if (eep_config.termination_lvd == 1) {
13139                         asc_dvc->cfg->termination = termination;
13140
13141                         /* Enable manual control with low off / high on. */
13142                 } else if (eep_config.termination_lvd == 2) {
13143                         asc_dvc->cfg->termination = termination | TERM_LVD_HI;
13144
13145                         /* Enable manual control with low on / high on. */
13146                 } else if (eep_config.termination_lvd == 3) {
13147                         asc_dvc->cfg->termination = termination | TERM_LVD;
13148                 } else {
13149                         /*
13150                          * The EEPROM 'termination_lvd' field contains a bad value.
13151                          * Use automatic termination instead.
13152                          */
13153                         asc_dvc->cfg->termination = termination;
13154                         warn_code |= ASC_WARN_EEPROM_TERMINATION;
13155                 }
13156         }
13157
13158         return warn_code;
13159 }
13160
13161 /*
13162  * Initialize the ADV_DVC_VAR structure.
13163  *
13164  * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
13165  *
13166  * For a non-fatal error return a warning code. If there are no warnings
13167  * then 0 is returned.
13168  */
13169 static int __devinit
13170 AdvInitGetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
13171 {
13172         struct asc_board *board = shost_priv(shost);
13173         ADV_DVC_VAR *asc_dvc = &board->dvc_var.adv_dvc_var;
13174         unsigned short warn_code = 0;
13175         AdvPortAddr iop_base = asc_dvc->iop_base;
13176         u16 cmd;
13177         int status;
13178
13179         asc_dvc->err_code = 0;
13180
13181         /*
13182          * Save the state of the PCI Configuration Command Register
13183          * "Parity Error Response Control" Bit. If the bit is clear (0),
13184          * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
13185          * DMA parity errors.
13186          */
13187         asc_dvc->cfg->control_flag = 0;
13188         pci_read_config_word(pdev, PCI_COMMAND, &cmd);
13189         if ((cmd & PCI_COMMAND_PARITY) == 0)
13190                 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR;
13191
13192         asc_dvc->cfg->chip_version =
13193             AdvGetChipVersion(iop_base, asc_dvc->bus_type);
13194
13195         ASC_DBG(1, "iopb_chip_id_1: 0x%x 0x%x\n",
13196                  (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
13197                  (ushort)ADV_CHIP_ID_BYTE);
13198
13199         ASC_DBG(1, "iopw_chip_id_0: 0x%x 0x%x\n",
13200                  (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
13201                  (ushort)ADV_CHIP_ID_WORD);
13202
13203         /*
13204          * Reset the chip to start and allow register writes.
13205          */
13206         if (AdvFindSignature(iop_base) == 0) {
13207                 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
13208                 return ADV_ERROR;
13209         } else {
13210                 /*
13211                  * The caller must set 'chip_type' to a valid setting.
13212                  */
13213                 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 &&
13214                     asc_dvc->chip_type != ADV_CHIP_ASC38C0800 &&
13215                     asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
13216                         asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
13217                         return ADV_ERROR;
13218                 }
13219
13220                 /*
13221                  * Reset Chip.
13222                  */
13223                 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
13224                                      ADV_CTRL_REG_CMD_RESET);
13225                 mdelay(100);
13226                 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
13227                                      ADV_CTRL_REG_CMD_WR_IO_REG);
13228
13229                 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
13230                         status = AdvInitFrom38C1600EEP(asc_dvc);
13231                 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
13232                         status = AdvInitFrom38C0800EEP(asc_dvc);
13233                 } else {
13234                         status = AdvInitFrom3550EEP(asc_dvc);
13235                 }
13236                 warn_code |= status;
13237         }
13238
13239         if (warn_code != 0)
13240                 shost_printk(KERN_WARNING, shost, "warning: 0x%x\n", warn_code);
13241
13242         if (asc_dvc->err_code)
13243                 shost_printk(KERN_ERR, shost, "error code 0x%x\n",
13244                                 asc_dvc->err_code);
13245
13246         return asc_dvc->err_code;
13247 }
13248 #endif
13249
13250 static struct scsi_host_template advansys_template = {
13251         .proc_name = DRV_NAME,
13252 #ifdef CONFIG_PROC_FS
13253         .proc_info = advansys_proc_info,
13254 #endif
13255         .name = DRV_NAME,
13256         .info = advansys_info,
13257         .queuecommand = advansys_queuecommand,
13258         .eh_bus_reset_handler = advansys_reset,
13259         .bios_param = advansys_biosparam,
13260         .slave_configure = advansys_slave_configure,
13261         /*
13262          * Because the driver may control an ISA adapter 'unchecked_isa_dma'
13263          * must be set. The flag will be cleared in advansys_board_found
13264          * for non-ISA adapters.
13265          */
13266         .unchecked_isa_dma = 1,
13267         /*
13268          * All adapters controlled by this driver are capable of large
13269          * scatter-gather lists. According to the mid-level SCSI documentation
13270          * this obviates any performance gain provided by setting
13271          * 'use_clustering'. But empirically while CPU utilization is increased
13272          * by enabling clustering, I/O throughput increases as well.
13273          */
13274         .use_clustering = ENABLE_CLUSTERING,
13275 };
13276
13277 static int __devinit advansys_wide_init_chip(struct Scsi_Host *shost)
13278 {
13279         struct asc_board *board = shost_priv(shost);
13280         struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
13281         int req_cnt = 0;
13282         adv_req_t *reqp = NULL;
13283         int sg_cnt = 0;
13284         adv_sgblk_t *sgp;
13285         int warn_code, err_code;
13286
13287         /*
13288          * Allocate buffer carrier structures. The total size
13289          * is about 4 KB, so allocate all at once.
13290          */
13291         adv_dvc->carrier_buf = kmalloc(ADV_CARRIER_BUFSIZE, GFP_KERNEL);
13292         ASC_DBG(1, "carrier_buf 0x%p\n", adv_dvc->carrier_buf);
13293
13294         if (!adv_dvc->carrier_buf)
13295                 goto kmalloc_failed;
13296
13297         /*
13298          * Allocate up to 'max_host_qng' request structures for the Wide
13299          * board. The total size is about 16 KB, so allocate all at once.
13300          * If the allocation fails decrement and try again.
13301          */
13302         for (req_cnt = adv_dvc->max_host_qng; req_cnt > 0; req_cnt--) {
13303                 reqp = kmalloc(sizeof(adv_req_t) * req_cnt, GFP_KERNEL);
13304
13305                 ASC_DBG(1, "reqp 0x%p, req_cnt %d, bytes %lu\n", reqp, req_cnt,
13306                          (ulong)sizeof(adv_req_t) * req_cnt);
13307
13308                 if (reqp)
13309                         break;
13310         }
13311
13312         if (!reqp)
13313                 goto kmalloc_failed;
13314
13315         adv_dvc->orig_reqp = reqp;
13316
13317         /*
13318          * Allocate up to ADV_TOT_SG_BLOCK request structures for
13319          * the Wide board. Each structure is about 136 bytes.
13320          */
13321         board->adv_sgblkp = NULL;
13322         for (sg_cnt = 0; sg_cnt < ADV_TOT_SG_BLOCK; sg_cnt++) {
13323                 sgp = kmalloc(sizeof(adv_sgblk_t), GFP_KERNEL);
13324
13325                 if (!sgp)
13326                         break;
13327
13328                 sgp->next_sgblkp = board->adv_sgblkp;
13329                 board->adv_sgblkp = sgp;
13330
13331         }
13332
13333         ASC_DBG(1, "sg_cnt %d * %u = %u bytes\n", sg_cnt, sizeof(adv_sgblk_t),
13334                  (unsigned)(sizeof(adv_sgblk_t) * sg_cnt));
13335
13336         if (!board->adv_sgblkp)
13337                 goto kmalloc_failed;
13338
13339         /*
13340          * Point 'adv_reqp' to the request structures and
13341          * link them together.
13342          */
13343         req_cnt--;
13344         reqp[req_cnt].next_reqp = NULL;
13345         for (; req_cnt > 0; req_cnt--) {
13346                 reqp[req_cnt - 1].next_reqp = &reqp[req_cnt];
13347         }
13348         board->adv_reqp = &reqp[0];
13349
13350         if (adv_dvc->chip_type == ADV_CHIP_ASC3550) {
13351                 ASC_DBG(2, "AdvInitAsc3550Driver()\n");
13352                 warn_code = AdvInitAsc3550Driver(adv_dvc);
13353         } else if (adv_dvc->chip_type == ADV_CHIP_ASC38C0800) {
13354                 ASC_DBG(2, "AdvInitAsc38C0800Driver()\n");
13355                 warn_code = AdvInitAsc38C0800Driver(adv_dvc);
13356         } else {
13357                 ASC_DBG(2, "AdvInitAsc38C1600Driver()\n");
13358                 warn_code = AdvInitAsc38C1600Driver(adv_dvc);
13359         }
13360         err_code = adv_dvc->err_code;
13361
13362         if (warn_code || err_code) {
13363                 shost_printk(KERN_WARNING, shost, "error: warn 0x%x, error "
13364                         "0x%x\n", warn_code, err_code);
13365         }
13366
13367         goto exit;
13368
13369  kmalloc_failed:
13370         shost_printk(KERN_ERR, shost, "error: kmalloc() failed\n");
13371         err_code = ADV_ERROR;
13372  exit:
13373         return err_code;
13374 }
13375
13376 static void advansys_wide_free_mem(struct asc_board *board)
13377 {
13378         struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
13379         kfree(adv_dvc->carrier_buf);
13380         adv_dvc->carrier_buf = NULL;
13381         kfree(adv_dvc->orig_reqp);
13382         adv_dvc->orig_reqp = board->adv_reqp = NULL;
13383         while (board->adv_sgblkp) {
13384                 adv_sgblk_t *sgp = board->adv_sgblkp;
13385                 board->adv_sgblkp = sgp->next_sgblkp;
13386                 kfree(sgp);
13387         }
13388 }
13389
13390 static int __devinit advansys_board_found(struct Scsi_Host *shost,
13391                                           unsigned int iop, int bus_type)
13392 {
13393         struct pci_dev *pdev;
13394         struct asc_board *boardp = shost_priv(shost);
13395         ASC_DVC_VAR *asc_dvc_varp = NULL;
13396         ADV_DVC_VAR *adv_dvc_varp = NULL;
13397         int share_irq, warn_code, ret;
13398
13399         pdev = (bus_type == ASC_IS_PCI) ? to_pci_dev(boardp->dev) : NULL;
13400
13401         if (ASC_NARROW_BOARD(boardp)) {
13402                 ASC_DBG(1, "narrow board\n");
13403                 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
13404                 asc_dvc_varp->bus_type = bus_type;
13405                 asc_dvc_varp->drv_ptr = boardp;
13406                 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
13407                 asc_dvc_varp->cfg->overrun_buf = &overrun_buf[0];
13408                 asc_dvc_varp->iop_base = iop;
13409         } else {
13410 #ifdef CONFIG_PCI
13411                 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
13412                 adv_dvc_varp->drv_ptr = boardp;
13413                 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
13414                 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW) {
13415                         ASC_DBG(1, "wide board ASC-3550\n");
13416                         adv_dvc_varp->chip_type = ADV_CHIP_ASC3550;
13417                 } else if (pdev->device == PCI_DEVICE_ID_38C0800_REV1) {
13418                         ASC_DBG(1, "wide board ASC-38C0800\n");
13419                         adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800;
13420                 } else {
13421                         ASC_DBG(1, "wide board ASC-38C1600\n");
13422                         adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600;
13423                 }
13424
13425                 boardp->asc_n_io_port = pci_resource_len(pdev, 1);
13426                 boardp->ioremap_addr = ioremap(pci_resource_start(pdev, 1),
13427                                                boardp->asc_n_io_port);
13428                 if (!boardp->ioremap_addr) {
13429                         shost_printk(KERN_ERR, shost, "ioremap(%x, %d) "
13430                                         "returned NULL\n",
13431                                         pci_resource_start(pdev, 1),
13432                                         boardp->asc_n_io_port);
13433                         ret = -ENODEV;
13434                         goto err_shost;
13435                 }
13436                 adv_dvc_varp->iop_base = (AdvPortAddr)boardp->ioremap_addr;
13437                 ASC_DBG(1, "iop_base: 0x%p\n", adv_dvc_varp->iop_base);
13438
13439                 /*
13440                  * Even though it isn't used to access wide boards, other
13441                  * than for the debug line below, save I/O Port address so
13442                  * that it can be reported.
13443                  */
13444                 boardp->ioport = iop;
13445
13446                 ASC_DBG(1, "iopb_chip_id_1 0x%x, iopw_chip_id_0 0x%x\n",
13447                                 (ushort)inp(iop + 1), (ushort)inpw(iop));
13448 #endif /* CONFIG_PCI */
13449         }
13450
13451 #ifdef CONFIG_PROC_FS
13452         /*
13453          * Allocate buffer for printing information from
13454          * /proc/scsi/advansys/[0...].
13455          */
13456         boardp->prtbuf = kmalloc(ASC_PRTBUF_SIZE, GFP_KERNEL);
13457         if (!boardp->prtbuf) {
13458                 shost_printk(KERN_ERR, shost, "kmalloc(%d) returned NULL\n",
13459                                 ASC_PRTBUF_SIZE);
13460                 ret = -ENOMEM;
13461                 goto err_unmap;
13462         }
13463 #endif /* CONFIG_PROC_FS */
13464
13465         if (ASC_NARROW_BOARD(boardp)) {
13466                 /*
13467                  * Set the board bus type and PCI IRQ before
13468                  * calling AscInitGetConfig().
13469                  */
13470                 switch (asc_dvc_varp->bus_type) {
13471 #ifdef CONFIG_ISA
13472                 case ASC_IS_ISA:
13473                         shost->unchecked_isa_dma = TRUE;
13474                         share_irq = 0;
13475                         break;
13476                 case ASC_IS_VL:
13477                         shost->unchecked_isa_dma = FALSE;
13478                         share_irq = 0;
13479                         break;
13480                 case ASC_IS_EISA:
13481                         shost->unchecked_isa_dma = FALSE;
13482                         share_irq = IRQF_SHARED;
13483                         break;
13484 #endif /* CONFIG_ISA */
13485 #ifdef CONFIG_PCI
13486                 case ASC_IS_PCI:
13487                         shost->unchecked_isa_dma = FALSE;
13488                         share_irq = IRQF_SHARED;
13489                         break;
13490 #endif /* CONFIG_PCI */
13491                 default:
13492                         shost_printk(KERN_ERR, shost, "unknown adapter type: "
13493                                         "%d\n", asc_dvc_varp->bus_type);
13494                         shost->unchecked_isa_dma = TRUE;
13495                         share_irq = 0;
13496                         break;
13497                 }
13498
13499                 /*
13500                  * NOTE: AscInitGetConfig() may change the board's
13501                  * bus_type value. The bus_type value should no
13502                  * longer be used. If the bus_type field must be
13503                  * referenced only use the bit-wise AND operator "&".
13504                  */
13505                 ASC_DBG(2, "AscInitGetConfig()\n");
13506                 ret = AscInitGetConfig(shost) ? -ENODEV : 0;
13507         } else {
13508 #ifdef CONFIG_PCI
13509                 /*
13510                  * For Wide boards set PCI information before calling
13511                  * AdvInitGetConfig().
13512                  */
13513                 shost->unchecked_isa_dma = FALSE;
13514                 share_irq = IRQF_SHARED;
13515                 ASC_DBG(2, "AdvInitGetConfig()\n");
13516
13517                 ret = AdvInitGetConfig(pdev, shost) ? -ENODEV : 0;
13518 #endif /* CONFIG_PCI */
13519         }
13520
13521         if (ret)
13522                 goto err_free_proc;
13523
13524         /*
13525          * Save the EEPROM configuration so that it can be displayed
13526          * from /proc/scsi/advansys/[0...].
13527          */
13528         if (ASC_NARROW_BOARD(boardp)) {
13529
13530                 ASCEEP_CONFIG *ep;
13531
13532                 /*
13533                  * Set the adapter's target id bit in the 'init_tidmask' field.
13534                  */
13535                 boardp->init_tidmask |=
13536                     ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id);
13537
13538                 /*
13539                  * Save EEPROM settings for the board.
13540                  */
13541                 ep = &boardp->eep_config.asc_eep;
13542
13543                 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable;
13544                 ep->disc_enable = asc_dvc_varp->cfg->disc_enable;
13545                 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled;
13546                 ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed);
13547                 ep->start_motor = asc_dvc_varp->start_motor;
13548                 ep->cntl = asc_dvc_varp->dvc_cntl;
13549                 ep->no_scam = asc_dvc_varp->no_scam;
13550                 ep->max_total_qng = asc_dvc_varp->max_total_qng;
13551                 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id);
13552                 /* 'max_tag_qng' is set to the same value for every device. */
13553                 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0];
13554                 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0];
13555                 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1];
13556                 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2];
13557                 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3];
13558                 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4];
13559                 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5];
13560
13561                 /*
13562                  * Modify board configuration.
13563                  */
13564                 ASC_DBG(2, "AscInitSetConfig()\n");
13565                 ret = AscInitSetConfig(pdev, shost) ? -ENODEV : 0;
13566                 if (ret)
13567                         goto err_free_proc;
13568         } else {
13569                 ADVEEP_3550_CONFIG *ep_3550;
13570                 ADVEEP_38C0800_CONFIG *ep_38C0800;
13571                 ADVEEP_38C1600_CONFIG *ep_38C1600;
13572
13573                 /*
13574                  * Save Wide EEP Configuration Information.
13575                  */
13576                 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
13577                         ep_3550 = &boardp->eep_config.adv_3550_eep;
13578
13579                         ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
13580                         ep_3550->max_host_qng = adv_dvc_varp->max_host_qng;
13581                         ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
13582                         ep_3550->termination = adv_dvc_varp->cfg->termination;
13583                         ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable;
13584                         ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl;
13585                         ep_3550->wdtr_able = adv_dvc_varp->wdtr_able;
13586                         ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;
13587                         ep_3550->ultra_able = adv_dvc_varp->ultra_able;
13588                         ep_3550->tagqng_able = adv_dvc_varp->tagqng_able;
13589                         ep_3550->start_motor = adv_dvc_varp->start_motor;
13590                         ep_3550->scsi_reset_delay =
13591                             adv_dvc_varp->scsi_reset_wait;
13592                         ep_3550->serial_number_word1 =
13593                             adv_dvc_varp->cfg->serial1;
13594                         ep_3550->serial_number_word2 =
13595                             adv_dvc_varp->cfg->serial2;
13596                         ep_3550->serial_number_word3 =
13597                             adv_dvc_varp->cfg->serial3;
13598                 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
13599                         ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
13600
13601                         ep_38C0800->adapter_scsi_id =
13602                             adv_dvc_varp->chip_scsi_id;
13603                         ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng;
13604                         ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
13605                         ep_38C0800->termination_lvd =
13606                             adv_dvc_varp->cfg->termination;
13607                         ep_38C0800->disc_enable =
13608                             adv_dvc_varp->cfg->disc_enable;
13609                         ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl;
13610                         ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able;
13611                         ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
13612                         ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
13613                         ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
13614                         ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
13615                         ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
13616                         ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
13617                         ep_38C0800->start_motor = adv_dvc_varp->start_motor;
13618                         ep_38C0800->scsi_reset_delay =
13619                             adv_dvc_varp->scsi_reset_wait;
13620                         ep_38C0800->serial_number_word1 =
13621                             adv_dvc_varp->cfg->serial1;
13622                         ep_38C0800->serial_number_word2 =
13623                             adv_dvc_varp->cfg->serial2;
13624                         ep_38C0800->serial_number_word3 =
13625                             adv_dvc_varp->cfg->serial3;
13626                 } else {
13627                         ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
13628
13629                         ep_38C1600->adapter_scsi_id =
13630                             adv_dvc_varp->chip_scsi_id;
13631                         ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng;
13632                         ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
13633                         ep_38C1600->termination_lvd =
13634                             adv_dvc_varp->cfg->termination;
13635                         ep_38C1600->disc_enable =
13636                             adv_dvc_varp->cfg->disc_enable;
13637                         ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl;
13638                         ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able;
13639                         ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
13640                         ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
13641                         ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
13642                         ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
13643                         ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
13644                         ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
13645                         ep_38C1600->start_motor = adv_dvc_varp->start_motor;
13646                         ep_38C1600->scsi_reset_delay =
13647                             adv_dvc_varp->scsi_reset_wait;
13648                         ep_38C1600->serial_number_word1 =
13649                             adv_dvc_varp->cfg->serial1;
13650                         ep_38C1600->serial_number_word2 =
13651                             adv_dvc_varp->cfg->serial2;
13652                         ep_38C1600->serial_number_word3 =
13653                             adv_dvc_varp->cfg->serial3;
13654                 }
13655
13656                 /*
13657                  * Set the adapter's target id bit in the 'init_tidmask' field.
13658                  */
13659                 boardp->init_tidmask |=
13660                     ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id);
13661         }
13662
13663         /*
13664          * Channels are numbered beginning with 0. For AdvanSys one host
13665          * structure supports one channel. Multi-channel boards have a
13666          * separate host structure for each channel.
13667          */
13668         shost->max_channel = 0;
13669         if (ASC_NARROW_BOARD(boardp)) {
13670                 shost->max_id = ASC_MAX_TID + 1;
13671                 shost->max_lun = ASC_MAX_LUN + 1;
13672                 shost->max_cmd_len = ASC_MAX_CDB_LEN;
13673
13674                 shost->io_port = asc_dvc_varp->iop_base;
13675                 boardp->asc_n_io_port = ASC_IOADR_GAP;
13676                 shost->this_id = asc_dvc_varp->cfg->chip_scsi_id;
13677
13678                 /* Set maximum number of queues the adapter can handle. */
13679                 shost->can_queue = asc_dvc_varp->max_total_qng;
13680         } else {
13681                 shost->max_id = ADV_MAX_TID + 1;
13682                 shost->max_lun = ADV_MAX_LUN + 1;
13683                 shost->max_cmd_len = ADV_MAX_CDB_LEN;
13684
13685                 /*
13686                  * Save the I/O Port address and length even though
13687                  * I/O ports are not used to access Wide boards.
13688                  * Instead the Wide boards are accessed with
13689                  * PCI Memory Mapped I/O.
13690                  */
13691                 shost->io_port = iop;
13692
13693                 shost->this_id = adv_dvc_varp->chip_scsi_id;
13694
13695                 /* Set maximum number of queues the adapter can handle. */
13696                 shost->can_queue = adv_dvc_varp->max_host_qng;
13697         }
13698
13699         /*
13700          * Following v1.3.89, 'cmd_per_lun' is no longer needed
13701          * and should be set to zero.
13702          *
13703          * But because of a bug introduced in v1.3.89 if the driver is
13704          * compiled as a module and 'cmd_per_lun' is zero, the Mid-Level
13705          * SCSI function 'allocate_device' will panic. To allow the driver
13706          * to work as a module in these kernels set 'cmd_per_lun' to 1.
13707          *
13708          * Note: This is wrong.  cmd_per_lun should be set to the depth
13709          * you want on untagged devices always.
13710          #ifdef MODULE
13711          */
13712         shost->cmd_per_lun = 1;
13713 /* #else
13714             shost->cmd_per_lun = 0;
13715 #endif */
13716
13717         /*
13718          * Set the maximum number of scatter-gather elements the
13719          * adapter can handle.
13720          */
13721         if (ASC_NARROW_BOARD(boardp)) {
13722                 /*
13723                  * Allow two commands with 'sg_tablesize' scatter-gather
13724                  * elements to be executed simultaneously. This value is
13725                  * the theoretical hardware limit. It may be decreased
13726                  * below.
13727                  */
13728                 shost->sg_tablesize =
13729                     (((asc_dvc_varp->max_total_qng - 2) / 2) *
13730                      ASC_SG_LIST_PER_Q) + 1;
13731         } else {
13732                 shost->sg_tablesize = ADV_MAX_SG_LIST;
13733         }
13734
13735         /*
13736          * The value of 'sg_tablesize' can not exceed the SCSI
13737          * mid-level driver definition of SG_ALL. SG_ALL also
13738          * must not be exceeded, because it is used to define the
13739          * size of the scatter-gather table in 'struct asc_sg_head'.
13740          */
13741         if (shost->sg_tablesize > SG_ALL) {
13742                 shost->sg_tablesize = SG_ALL;
13743         }
13744
13745         ASC_DBG(1, "sg_tablesize: %d\n", shost->sg_tablesize);
13746
13747         /* BIOS start address. */
13748         if (ASC_NARROW_BOARD(boardp)) {
13749                 shost->base = AscGetChipBiosAddress(asc_dvc_varp->iop_base,
13750                                                     asc_dvc_varp->bus_type);
13751         } else {
13752                 /*
13753                  * Fill-in BIOS board variables. The Wide BIOS saves
13754                  * information in LRAM that is used by the driver.
13755                  */
13756                 AdvReadWordLram(adv_dvc_varp->iop_base,
13757                                 BIOS_SIGNATURE, boardp->bios_signature);
13758                 AdvReadWordLram(adv_dvc_varp->iop_base,
13759                                 BIOS_VERSION, boardp->bios_version);
13760                 AdvReadWordLram(adv_dvc_varp->iop_base,
13761                                 BIOS_CODESEG, boardp->bios_codeseg);
13762                 AdvReadWordLram(adv_dvc_varp->iop_base,
13763                                 BIOS_CODELEN, boardp->bios_codelen);
13764
13765                 ASC_DBG(1, "bios_signature 0x%x, bios_version 0x%x\n",
13766                          boardp->bios_signature, boardp->bios_version);
13767
13768                 ASC_DBG(1, "bios_codeseg 0x%x, bios_codelen 0x%x\n",
13769                          boardp->bios_codeseg, boardp->bios_codelen);
13770
13771                 /*
13772                  * If the BIOS saved a valid signature, then fill in
13773                  * the BIOS code segment base address.
13774                  */
13775                 if (boardp->bios_signature == 0x55AA) {
13776                         /*
13777                          * Convert x86 realmode code segment to a linear
13778                          * address by shifting left 4.
13779                          */
13780                         shost->base = ((ulong)boardp->bios_codeseg << 4);
13781                 } else {
13782                         shost->base = 0;
13783                 }
13784         }
13785
13786         /*
13787          * Register Board Resources - I/O Port, DMA, IRQ
13788          */
13789
13790         /* Register DMA Channel for Narrow boards. */
13791         shost->dma_channel = NO_ISA_DMA;        /* Default to no ISA DMA. */
13792 #ifdef CONFIG_ISA
13793         if (ASC_NARROW_BOARD(boardp)) {
13794                 /* Register DMA channel for ISA bus. */
13795                 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
13796                         shost->dma_channel = asc_dvc_varp->cfg->isa_dma_channel;
13797                         ret = request_dma(shost->dma_channel, DRV_NAME);
13798                         if (ret) {
13799                                 shost_printk(KERN_ERR, shost, "request_dma() "
13800                                                 "%d failed %d\n",
13801                                                 shost->dma_channel, ret);
13802                                 goto err_free_proc;
13803                         }
13804                         AscEnableIsaDma(shost->dma_channel);
13805                 }
13806         }
13807 #endif /* CONFIG_ISA */
13808
13809         /* Register IRQ Number. */
13810         ASC_DBG(2, "request_irq(%d, %p)\n", boardp->irq, shost);
13811
13812         ret = request_irq(boardp->irq, advansys_interrupt, share_irq,
13813                           DRV_NAME, shost);
13814
13815         if (ret) {
13816                 if (ret == -EBUSY) {
13817                         shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
13818                                         "already in use\n", boardp->irq);
13819                 } else if (ret == -EINVAL) {
13820                         shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
13821                                         "not valid\n", boardp->irq);
13822                 } else {
13823                         shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
13824                                         "failed with %d\n", boardp->irq, ret);
13825                 }
13826                 goto err_free_dma;
13827         }
13828
13829         /*
13830          * Initialize board RISC chip and enable interrupts.
13831          */
13832         if (ASC_NARROW_BOARD(boardp)) {
13833                 ASC_DBG(2, "AscInitAsc1000Driver()\n");
13834                 warn_code = AscInitAsc1000Driver(asc_dvc_varp);
13835
13836                 if (warn_code || asc_dvc_varp->err_code) {
13837                         shost_printk(KERN_ERR, shost, "error: init_state 0x%x, "
13838                                         "warn 0x%x, error 0x%x\n",
13839                                         asc_dvc_varp->init_state, warn_code,
13840                                         asc_dvc_varp->err_code);
13841                         if (asc_dvc_varp->err_code)
13842                                 ret = -ENODEV;
13843                 }
13844         } else {
13845                 if (advansys_wide_init_chip(shost))
13846                         ret = -ENODEV;
13847         }
13848
13849         if (ret)
13850                 goto err_free_wide_mem;
13851
13852         ASC_DBG_PRT_SCSI_HOST(2, shost);
13853
13854         ret = scsi_add_host(shost, boardp->dev);
13855         if (ret)
13856                 goto err_free_wide_mem;
13857
13858         scsi_scan_host(shost);
13859         return 0;
13860
13861  err_free_wide_mem:
13862         advansys_wide_free_mem(boardp);
13863         free_irq(boardp->irq, shost);
13864  err_free_dma:
13865         if (shost->dma_channel != NO_ISA_DMA)
13866                 free_dma(shost->dma_channel);
13867  err_free_proc:
13868         kfree(boardp->prtbuf);
13869  err_unmap:
13870         if (boardp->ioremap_addr)
13871                 iounmap(boardp->ioremap_addr);
13872  err_shost:
13873         return ret;
13874 }
13875
13876 /*
13877  * advansys_release()
13878  *
13879  * Release resources allocated for a single AdvanSys adapter.
13880  */
13881 static int advansys_release(struct Scsi_Host *shost)
13882 {
13883         struct asc_board *boardp = shost_priv(shost);
13884         ASC_DBG(1, "begin\n");
13885         scsi_remove_host(shost);
13886         free_irq(boardp->irq, shost);
13887         if (shost->dma_channel != NO_ISA_DMA) {
13888                 ASC_DBG(1, "free_dma()\n");
13889                 free_dma(shost->dma_channel);
13890         }
13891         if (!ASC_NARROW_BOARD(boardp)) {
13892                 iounmap(boardp->ioremap_addr);
13893                 advansys_wide_free_mem(boardp);
13894         }
13895         kfree(boardp->prtbuf);
13896         scsi_host_put(shost);
13897         ASC_DBG(1, "end\n");
13898         return 0;
13899 }
13900
13901 #define ASC_IOADR_TABLE_MAX_IX  11
13902
13903 static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] __devinitdata = {
13904         0x100, 0x0110, 0x120, 0x0130, 0x140, 0x0150, 0x0190,
13905         0x0210, 0x0230, 0x0250, 0x0330
13906 };
13907
13908 /*
13909  * The ISA IRQ number is found in bits 2 and 3 of the CfgLsw.  It decodes as:
13910  * 00: 10
13911  * 01: 11
13912  * 10: 12
13913  * 11: 15
13914  */
13915 static unsigned int __devinit advansys_isa_irq_no(PortAddr iop_base)
13916 {
13917         unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
13918         unsigned int chip_irq = ((cfg_lsw >> 2) & 0x03) + 10;
13919         if (chip_irq == 13)
13920                 chip_irq = 15;
13921         return chip_irq;
13922 }
13923
13924 static int __devinit advansys_isa_probe(struct device *dev, unsigned int id)
13925 {
13926         int err = -ENODEV;
13927         PortAddr iop_base = _asc_def_iop_base[id];
13928         struct Scsi_Host *shost;
13929         struct asc_board *board;
13930
13931         if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
13932                 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
13933                 return -ENODEV;
13934         }
13935         ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
13936         if (!AscFindSignature(iop_base))
13937                 goto release_region;
13938         if (!(AscGetChipVersion(iop_base, ASC_IS_ISA) & ASC_CHIP_VER_ISA_BIT))
13939                 goto release_region;
13940
13941         err = -ENOMEM;
13942         shost = scsi_host_alloc(&advansys_template, sizeof(*board));
13943         if (!shost)
13944                 goto release_region;
13945
13946         board = shost_priv(shost);
13947         board->irq = advansys_isa_irq_no(iop_base);
13948         board->dev = dev;
13949
13950         err = advansys_board_found(shost, iop_base, ASC_IS_ISA);
13951         if (err)
13952                 goto free_host;
13953
13954         dev_set_drvdata(dev, shost);
13955         return 0;
13956
13957  free_host:
13958         scsi_host_put(shost);
13959  release_region:
13960         release_region(iop_base, ASC_IOADR_GAP);
13961         return err;
13962 }
13963
13964 static int __devexit advansys_isa_remove(struct device *dev, unsigned int id)
13965 {
13966         int ioport = _asc_def_iop_base[id];
13967         advansys_release(dev_get_drvdata(dev));
13968         release_region(ioport, ASC_IOADR_GAP);
13969         return 0;
13970 }
13971
13972 static struct isa_driver advansys_isa_driver = {
13973         .probe          = advansys_isa_probe,
13974         .remove         = __devexit_p(advansys_isa_remove),
13975         .driver = {
13976                 .owner  = THIS_MODULE,
13977                 .name   = DRV_NAME,
13978         },
13979 };
13980
13981 /*
13982  * The VLB IRQ number is found in bits 2 to 4 of the CfgLsw.  It decodes as:
13983  * 000: invalid
13984  * 001: 10
13985  * 010: 11
13986  * 011: 12
13987  * 100: invalid
13988  * 101: 14
13989  * 110: 15
13990  * 111: invalid
13991  */
13992 static unsigned int __devinit advansys_vlb_irq_no(PortAddr iop_base)
13993 {
13994         unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
13995         unsigned int chip_irq = ((cfg_lsw >> 2) & 0x07) + 9;
13996         if ((chip_irq < 10) || (chip_irq == 13) || (chip_irq > 15))
13997                 return 0;
13998         return chip_irq;
13999 }
14000
14001 static int __devinit advansys_vlb_probe(struct device *dev, unsigned int id)
14002 {
14003         int err = -ENODEV;
14004         PortAddr iop_base = _asc_def_iop_base[id];
14005         struct Scsi_Host *shost;
14006         struct asc_board *board;
14007
14008         if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
14009                 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
14010                 return -ENODEV;
14011         }
14012         ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
14013         if (!AscFindSignature(iop_base))
14014                 goto release_region;
14015         /*
14016          * I don't think this condition can actually happen, but the old
14017          * driver did it, and the chances of finding a VLB setup in 2007
14018          * to do testing with is slight to none.
14019          */
14020         if (AscGetChipVersion(iop_base, ASC_IS_VL) > ASC_CHIP_MAX_VER_VL)
14021                 goto release_region;
14022
14023         err = -ENOMEM;
14024         shost = scsi_host_alloc(&advansys_template, sizeof(*board));
14025         if (!shost)
14026                 goto release_region;
14027
14028         board = shost_priv(shost);
14029         board->irq = advansys_vlb_irq_no(iop_base);
14030         board->dev = dev;
14031
14032         err = advansys_board_found(shost, iop_base, ASC_IS_VL);
14033         if (err)
14034                 goto free_host;
14035
14036         dev_set_drvdata(dev, shost);
14037         return 0;
14038
14039  free_host:
14040         scsi_host_put(shost);
14041  release_region:
14042         release_region(iop_base, ASC_IOADR_GAP);
14043         return -ENODEV;
14044 }
14045
14046 static struct isa_driver advansys_vlb_driver = {
14047         .probe          = advansys_vlb_probe,
14048         .remove         = __devexit_p(advansys_isa_remove),
14049         .driver = {
14050                 .owner  = THIS_MODULE,
14051                 .name   = "advansys_vlb",
14052         },
14053 };
14054
14055 static struct eisa_device_id advansys_eisa_table[] __devinitdata = {
14056         { "ABP7401" },
14057         { "ABP7501" },
14058         { "" }
14059 };
14060
14061 MODULE_DEVICE_TABLE(eisa, advansys_eisa_table);
14062
14063 /*
14064  * EISA is a little more tricky than PCI; each EISA device may have two
14065  * channels, and this driver is written to make each channel its own Scsi_Host
14066  */
14067 struct eisa_scsi_data {
14068         struct Scsi_Host *host[2];
14069 };
14070
14071 /*
14072  * The EISA IRQ number is found in bits 8 to 10 of the CfgLsw.  It decodes as:
14073  * 000: 10
14074  * 001: 11
14075  * 010: 12
14076  * 011: invalid
14077  * 100: 14
14078  * 101: 15
14079  * 110: invalid
14080  * 111: invalid
14081  */
14082 static unsigned int __devinit advansys_eisa_irq_no(struct eisa_device *edev)
14083 {
14084         unsigned short cfg_lsw = inw(edev->base_addr + 0xc86);
14085         unsigned int chip_irq = ((cfg_lsw >> 8) & 0x07) + 10;
14086         if ((chip_irq == 13) || (chip_irq > 15))
14087                 return 0;
14088         return chip_irq;
14089 }
14090
14091 static int __devinit advansys_eisa_probe(struct device *dev)
14092 {
14093         int i, ioport, irq = 0;
14094         int err;
14095         struct eisa_device *edev = to_eisa_device(dev);
14096         struct eisa_scsi_data *data;
14097
14098         err = -ENOMEM;
14099         data = kzalloc(sizeof(*data), GFP_KERNEL);
14100         if (!data)
14101                 goto fail;
14102         ioport = edev->base_addr + 0xc30;
14103
14104         err = -ENODEV;
14105         for (i = 0; i < 2; i++, ioport += 0x20) {
14106                 struct asc_board *board;
14107                 struct Scsi_Host *shost;
14108                 if (!request_region(ioport, ASC_IOADR_GAP, DRV_NAME)) {
14109                         printk(KERN_WARNING "Region %x-%x busy\n", ioport,
14110                                ioport + ASC_IOADR_GAP - 1);
14111                         continue;
14112                 }
14113                 if (!AscFindSignature(ioport)) {
14114                         release_region(ioport, ASC_IOADR_GAP);
14115                         continue;
14116                 }
14117
14118                 /*
14119                  * I don't know why we need to do this for EISA chips, but
14120                  * not for any others.  It looks to be equivalent to
14121                  * AscGetChipCfgMsw, but I may have overlooked something,
14122                  * so I'm not converting it until I get an EISA board to
14123                  * test with.
14124                  */
14125                 inw(ioport + 4);
14126
14127                 if (!irq)
14128                         irq = advansys_eisa_irq_no(edev);
14129
14130                 err = -ENOMEM;
14131                 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
14132                 if (!shost)
14133                         goto release_region;
14134
14135                 board = shost_priv(shost);
14136                 board->irq = irq;
14137                 board->dev = dev;
14138
14139                 err = advansys_board_found(shost, ioport, ASC_IS_EISA);
14140                 if (!err) {
14141                         data->host[i] = shost;
14142                         continue;
14143                 }
14144
14145                 scsi_host_put(shost);
14146  release_region:
14147                 release_region(ioport, ASC_IOADR_GAP);
14148                 break;
14149         }
14150
14151         if (err)
14152                 goto free_data;
14153         dev_set_drvdata(dev, data);
14154         return 0;
14155
14156  free_data:
14157         kfree(data->host[0]);
14158         kfree(data->host[1]);
14159         kfree(data);
14160  fail:
14161         return err;
14162 }
14163
14164 static __devexit int advansys_eisa_remove(struct device *dev)
14165 {
14166         int i;
14167         struct eisa_scsi_data *data = dev_get_drvdata(dev);
14168
14169         for (i = 0; i < 2; i++) {
14170                 int ioport;
14171                 struct Scsi_Host *shost = data->host[i];
14172                 if (!shost)
14173                         continue;
14174                 ioport = shost->io_port;
14175                 advansys_release(shost);
14176                 release_region(ioport, ASC_IOADR_GAP);
14177         }
14178
14179         kfree(data);
14180         return 0;
14181 }
14182
14183 static struct eisa_driver advansys_eisa_driver = {
14184         .id_table =             advansys_eisa_table,
14185         .driver = {
14186                 .name =         DRV_NAME,
14187                 .probe =        advansys_eisa_probe,
14188                 .remove =       __devexit_p(advansys_eisa_remove),
14189         }
14190 };
14191
14192 /* PCI Devices supported by this driver */
14193 static struct pci_device_id advansys_pci_tbl[] __devinitdata = {
14194         {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A,
14195          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14196         {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940,
14197          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14198         {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U,
14199          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14200         {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW,
14201          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14202         {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1,
14203          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14204         {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1,
14205          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14206         {}
14207 };
14208
14209 MODULE_DEVICE_TABLE(pci, advansys_pci_tbl);
14210
14211 static void __devinit advansys_set_latency(struct pci_dev *pdev)
14212 {
14213         if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
14214             (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
14215                 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0);
14216         } else {
14217                 u8 latency;
14218                 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency);
14219                 if (latency < 0x20)
14220                         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
14221         }
14222 }
14223
14224 static int __devinit
14225 advansys_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
14226 {
14227         int err, ioport;
14228         struct Scsi_Host *shost;
14229         struct asc_board *board;
14230
14231         err = pci_enable_device(pdev);
14232         if (err)
14233                 goto fail;
14234         err = pci_request_regions(pdev, DRV_NAME);
14235         if (err)
14236                 goto disable_device;
14237         pci_set_master(pdev);
14238         advansys_set_latency(pdev);
14239
14240         err = -ENODEV;
14241         if (pci_resource_len(pdev, 0) == 0)
14242                 goto release_region;
14243
14244         ioport = pci_resource_start(pdev, 0);
14245
14246         err = -ENOMEM;
14247         shost = scsi_host_alloc(&advansys_template, sizeof(*board));
14248         if (!shost)
14249                 goto release_region;
14250
14251         board = shost_priv(shost);
14252         board->irq = pdev->irq;
14253         board->dev = &pdev->dev;
14254
14255         if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW ||
14256             pdev->device == PCI_DEVICE_ID_38C0800_REV1 ||
14257             pdev->device == PCI_DEVICE_ID_38C1600_REV1) {
14258                 board->flags |= ASC_IS_WIDE_BOARD;
14259         }
14260
14261         err = advansys_board_found(shost, ioport, ASC_IS_PCI);
14262         if (err)
14263                 goto free_host;
14264
14265         pci_set_drvdata(pdev, shost);
14266         return 0;
14267
14268  free_host:
14269         scsi_host_put(shost);
14270  release_region:
14271         pci_release_regions(pdev);
14272  disable_device:
14273         pci_disable_device(pdev);
14274  fail:
14275         return err;
14276 }
14277
14278 static void __devexit advansys_pci_remove(struct pci_dev *pdev)
14279 {
14280         advansys_release(pci_get_drvdata(pdev));
14281         pci_release_regions(pdev);
14282         pci_disable_device(pdev);
14283 }
14284
14285 static struct pci_driver advansys_pci_driver = {
14286         .name =         DRV_NAME,
14287         .id_table =     advansys_pci_tbl,
14288         .probe =        advansys_pci_probe,
14289         .remove =       __devexit_p(advansys_pci_remove),
14290 };
14291
14292 static int __init advansys_init(void)
14293 {
14294         int error;
14295
14296         error = isa_register_driver(&advansys_isa_driver,
14297                                     ASC_IOADR_TABLE_MAX_IX);
14298         if (error)
14299                 goto fail;
14300
14301         error = isa_register_driver(&advansys_vlb_driver,
14302                                     ASC_IOADR_TABLE_MAX_IX);
14303         if (error)
14304                 goto unregister_isa;
14305
14306         error = eisa_driver_register(&advansys_eisa_driver);
14307         if (error)
14308                 goto unregister_vlb;
14309
14310         error = pci_register_driver(&advansys_pci_driver);
14311         if (error)
14312                 goto unregister_eisa;
14313
14314         return 0;
14315
14316  unregister_eisa:
14317         eisa_driver_unregister(&advansys_eisa_driver);
14318  unregister_vlb:
14319         isa_unregister_driver(&advansys_vlb_driver);
14320  unregister_isa:
14321         isa_unregister_driver(&advansys_isa_driver);
14322  fail:
14323         return error;
14324 }
14325
14326 static void __exit advansys_exit(void)
14327 {
14328         pci_unregister_driver(&advansys_pci_driver);
14329         eisa_driver_unregister(&advansys_eisa_driver);
14330         isa_unregister_driver(&advansys_vlb_driver);
14331         isa_unregister_driver(&advansys_isa_driver);
14332 }
14333
14334 module_init(advansys_init);
14335 module_exit(advansys_exit);
14336
14337 MODULE_LICENSE("GPL");