2 * Copyright (c) 1996-2004 Russell King.
4 * Please note that this platform does not support 32-bit IDE IO.
7 #include <linux/string.h>
8 #include <linux/module.h>
9 #include <linux/ioport.h>
10 #include <linux/slab.h>
11 #include <linux/blkdev.h>
12 #include <linux/errno.h>
13 #include <linux/hdreg.h>
14 #include <linux/ide.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/device.h>
17 #include <linux/init.h>
18 #include <linux/scatterlist.h>
22 #include <asm/ecard.h>
24 #define ICS_IDENT_OFFSET 0x2280
26 #define ICS_ARCIN_V5_INTRSTAT 0x0000
27 #define ICS_ARCIN_V5_INTROFFSET 0x0004
28 #define ICS_ARCIN_V5_IDEOFFSET 0x2800
29 #define ICS_ARCIN_V5_IDEALTOFFSET 0x2b80
30 #define ICS_ARCIN_V5_IDESTEPPING 6
32 #define ICS_ARCIN_V6_IDEOFFSET_1 0x2000
33 #define ICS_ARCIN_V6_INTROFFSET_1 0x2200
34 #define ICS_ARCIN_V6_INTRSTAT_1 0x2290
35 #define ICS_ARCIN_V6_IDEALTOFFSET_1 0x2380
36 #define ICS_ARCIN_V6_IDEOFFSET_2 0x3000
37 #define ICS_ARCIN_V6_INTROFFSET_2 0x3200
38 #define ICS_ARCIN_V6_INTRSTAT_2 0x3290
39 #define ICS_ARCIN_V6_IDEALTOFFSET_2 0x3380
40 #define ICS_ARCIN_V6_IDESTEPPING 6
43 unsigned int dataoffset;
44 unsigned int ctrloffset;
45 unsigned int stepping;
48 static struct cardinfo icside_cardinfo_v5 = {
49 .dataoffset = ICS_ARCIN_V5_IDEOFFSET,
50 .ctrloffset = ICS_ARCIN_V5_IDEALTOFFSET,
51 .stepping = ICS_ARCIN_V5_IDESTEPPING,
54 static struct cardinfo icside_cardinfo_v6_1 = {
55 .dataoffset = ICS_ARCIN_V6_IDEOFFSET_1,
56 .ctrloffset = ICS_ARCIN_V6_IDEALTOFFSET_1,
57 .stepping = ICS_ARCIN_V6_IDESTEPPING,
60 static struct cardinfo icside_cardinfo_v6_2 = {
61 .dataoffset = ICS_ARCIN_V6_IDEOFFSET_2,
62 .ctrloffset = ICS_ARCIN_V6_IDEALTOFFSET_2,
63 .stepping = ICS_ARCIN_V6_IDESTEPPING,
69 void __iomem *irq_port;
70 void __iomem *ioc_base;
76 #define ICS_TYPE_A3IN 0
77 #define ICS_TYPE_A3USER 1
79 #define ICS_TYPE_V5 15
80 #define ICS_TYPE_NOTYPE ((unsigned int)-1)
82 /* ---------------- Version 5 PCB Support Functions --------------------- */
83 /* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
84 * Purpose : enable interrupts from card
86 static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
88 struct icside_state *state = ec->irq_data;
90 writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
93 /* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
94 * Purpose : disable interrupts from card
96 static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
98 struct icside_state *state = ec->irq_data;
100 readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
103 static const expansioncard_ops_t icside_ops_arcin_v5 = {
104 .irqenable = icside_irqenable_arcin_v5,
105 .irqdisable = icside_irqdisable_arcin_v5,
109 /* ---------------- Version 6 PCB Support Functions --------------------- */
110 /* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
111 * Purpose : enable interrupts from card
113 static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
115 struct icside_state *state = ec->irq_data;
116 void __iomem *base = state->irq_port;
120 switch (state->channel) {
122 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
123 readb(base + ICS_ARCIN_V6_INTROFFSET_2);
126 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
127 readb(base + ICS_ARCIN_V6_INTROFFSET_1);
132 /* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
133 * Purpose : disable interrupts from card
135 static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
137 struct icside_state *state = ec->irq_data;
141 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
142 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
145 /* Prototype: icside_irqprobe(struct expansion_card *ec)
146 * Purpose : detect an active interrupt from card
148 static int icside_irqpending_arcin_v6(struct expansion_card *ec)
150 struct icside_state *state = ec->irq_data;
152 return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
153 readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
156 static const expansioncard_ops_t icside_ops_arcin_v6 = {
157 .irqenable = icside_irqenable_arcin_v6,
158 .irqdisable = icside_irqdisable_arcin_v6,
159 .irqpending = icside_irqpending_arcin_v6,
163 * Handle routing of interrupts. This is called before
164 * we write the command to the drive.
166 static void icside_maskproc(ide_drive_t *drive, int mask)
168 ide_hwif_t *hwif = HWIF(drive);
169 struct expansion_card *ec = ECARD_DEV(hwif->dev);
170 struct icside_state *state = ecard_get_drvdata(ec);
173 local_irq_save(flags);
175 state->channel = hwif->channel;
177 if (state->enabled && !mask) {
178 switch (hwif->channel) {
180 writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
181 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
184 writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
185 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
189 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
190 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
193 local_irq_restore(flags);
196 static const struct ide_port_ops icside_v6_no_dma_port_ops = {
197 .maskproc = icside_maskproc,
200 #ifdef CONFIG_BLK_DEV_IDEDMA_ICS
204 * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
205 * There is only one DMA controller per card, which means that only
206 * one drive can be accessed at one time. NOTE! We do not enforce that
207 * here, but we rely on the main IDE driver spotting that both
208 * interfaces use the same IRQ, which should guarantee this.
212 * Configure the IOMD to give the appropriate timings for the transfer
213 * mode being requested. We take the advice of the ATA standards, and
214 * calculate the cycle time based on the transfer mode, and the EIDE
215 * MW DMA specs that the drive provides in the IDENTIFY command.
217 * We have the following IOMD DMA modes to choose from:
219 * Type Active Recovery Cycle
220 * A 250 (250) 312 (550) 562 (800)
222 * C 125 (125) 125 (375) 250 (500)
225 * (figures in brackets are actual measured timings)
227 * However, we also need to take care of the read/write active and
231 * Mode Active -- Recovery -- Cycle IOMD type
232 * MW0 215 50 215 480 A
236 static void icside_set_dma_mode(ide_drive_t *drive, const u8 xfer_mode)
238 int cycle_time, use_dma_info = 0;
263 * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
264 * take care to note the values in the ID...
266 if (use_dma_info && drive->id->eide_dma_time > cycle_time)
267 cycle_time = drive->id->eide_dma_time;
269 drive->drive_data = cycle_time;
271 printk("%s: %s selected (peak %dMB/s)\n", drive->name,
272 ide_xfer_verbose(xfer_mode), 2000 / drive->drive_data);
275 static const struct ide_port_ops icside_v6_port_ops = {
276 .set_dma_mode = icside_set_dma_mode,
277 .maskproc = icside_maskproc,
280 static void icside_dma_host_set(ide_drive_t *drive, int on)
284 static int icside_dma_end(ide_drive_t *drive)
286 ide_hwif_t *hwif = HWIF(drive);
287 struct expansion_card *ec = ECARD_DEV(hwif->dev);
289 drive->waiting_for_dma = 0;
291 disable_dma(ec->dma);
293 /* Teardown mappings after DMA has completed. */
294 ide_destroy_dmatable(drive);
296 return get_dma_residue(ec->dma) != 0;
299 static void icside_dma_start(ide_drive_t *drive)
301 ide_hwif_t *hwif = HWIF(drive);
302 struct expansion_card *ec = ECARD_DEV(hwif->dev);
304 /* We can not enable DMA on both channels simultaneously. */
305 BUG_ON(dma_channel_active(ec->dma));
309 static int icside_dma_setup(ide_drive_t *drive)
311 ide_hwif_t *hwif = HWIF(drive);
312 struct expansion_card *ec = ECARD_DEV(hwif->dev);
313 struct icside_state *state = ecard_get_drvdata(ec);
314 struct request *rq = hwif->hwgroup->rq;
315 unsigned int dma_mode;
318 dma_mode = DMA_MODE_WRITE;
320 dma_mode = DMA_MODE_READ;
323 * We can not enable DMA on both channels.
325 BUG_ON(dma_channel_active(ec->dma));
327 hwif->sg_nents = ide_build_sglist(drive, rq);
330 * Ensure that we have the right interrupt routed.
332 icside_maskproc(drive, 0);
335 * Route the DMA signals to the correct interface.
337 writeb(state->sel | hwif->channel, state->ioc_base);
340 * Select the correct timing for this drive.
342 set_dma_speed(ec->dma, drive->drive_data);
345 * Tell the DMA engine about the SG table and
348 set_dma_sg(ec->dma, hwif->sg_table, hwif->sg_nents);
349 set_dma_mode(ec->dma, dma_mode);
351 drive->waiting_for_dma = 1;
356 static void icside_dma_exec_cmd(ide_drive_t *drive, u8 cmd)
358 /* issue cmd to drive */
359 ide_execute_command(drive, cmd, ide_dma_intr, 2 * WAIT_CMD, NULL);
362 static int icside_dma_test_irq(ide_drive_t *drive)
364 ide_hwif_t *hwif = HWIF(drive);
365 struct expansion_card *ec = ECARD_DEV(hwif->dev);
366 struct icside_state *state = ecard_get_drvdata(ec);
368 return readb(state->irq_port +
370 ICS_ARCIN_V6_INTRSTAT_2 :
371 ICS_ARCIN_V6_INTRSTAT_1)) & 1;
374 static void icside_dma_timeout(ide_drive_t *drive)
376 printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
378 if (icside_dma_test_irq(drive))
381 ide_dump_status(drive, "DMA timeout", ide_read_status(drive));
383 icside_dma_end(drive);
386 static void icside_dma_lost_irq(ide_drive_t *drive)
388 printk(KERN_ERR "%s: IRQ lost\n", drive->name);
391 static int icside_dma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
393 hwif->dmatable_cpu = NULL;
394 hwif->dmatable_dma = 0;
399 static const struct ide_dma_ops icside_v6_dma_ops = {
400 .dma_host_set = icside_dma_host_set,
401 .dma_setup = icside_dma_setup,
402 .dma_exec_cmd = icside_dma_exec_cmd,
403 .dma_start = icside_dma_start,
404 .dma_end = icside_dma_end,
405 .dma_test_irq = icside_dma_test_irq,
406 .dma_timeout = icside_dma_timeout,
407 .dma_lost_irq = icside_dma_lost_irq,
410 #define icside_v6_dma_ops NULL
413 static int icside_dma_off_init(ide_hwif_t *hwif, const struct ide_port_info *d)
418 static void icside_setup_ports(hw_regs_t *hw, void __iomem *base,
419 struct cardinfo *info, struct expansion_card *ec)
421 unsigned long port = (unsigned long)base + info->dataoffset;
423 hw->io_ports.data_addr = port;
424 hw->io_ports.error_addr = port + (1 << info->stepping);
425 hw->io_ports.nsect_addr = port + (2 << info->stepping);
426 hw->io_ports.lbal_addr = port + (3 << info->stepping);
427 hw->io_ports.lbam_addr = port + (4 << info->stepping);
428 hw->io_ports.lbah_addr = port + (5 << info->stepping);
429 hw->io_ports.device_addr = port + (6 << info->stepping);
430 hw->io_ports.status_addr = port + (7 << info->stepping);
431 hw->io_ports.ctl_addr = (unsigned long)base + info->ctrloffset;
435 hw->chipset = ide_acorn;
439 icside_register_v5(struct icside_state *state, struct expansion_card *ec)
443 u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
446 base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0);
450 state->irq_port = base;
452 ec->irqaddr = base + ICS_ARCIN_V5_INTRSTAT;
455 ecard_setirq(ec, &icside_ops_arcin_v5, state);
458 * Be on the safe side - disable interrupts
460 icside_irqdisable_arcin_v5(ec, 0);
462 icside_setup_ports(&hw, base, &icside_cardinfo_v5, ec);
464 hwif = ide_find_port();
468 ide_init_port_hw(hwif, &hw);
469 default_hwif_mmiops(hwif);
471 state->hwif[0] = hwif;
473 ecard_set_drvdata(ec, state);
475 idx[0] = hwif->index;
477 ide_device_add(idx, NULL);
482 static const struct ide_port_info icside_v6_port_info __initdata = {
483 .init_dma = icside_dma_off_init,
484 .port_ops = &icside_v6_no_dma_port_ops,
485 .dma_ops = &icside_v6_dma_ops,
486 .host_flags = IDE_HFLAG_SERIALIZE | IDE_HFLAG_MMIO,
487 .mwdma_mask = ATA_MWDMA2,
488 .swdma_mask = ATA_SWDMA2,
492 icside_register_v6(struct icside_state *state, struct expansion_card *ec)
494 ide_hwif_t *hwif, *mate;
495 void __iomem *ioc_base, *easi_base;
496 unsigned int sel = 0;
498 u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
499 struct ide_port_info d = icside_v6_port_info;
502 ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
508 easi_base = ioc_base;
510 if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
511 easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
518 * Enable access to the EASI region.
523 writeb(sel, ioc_base);
525 ecard_setirq(ec, &icside_ops_arcin_v6, state);
527 state->irq_port = easi_base;
528 state->ioc_base = ioc_base;
532 * Be on the safe side - disable interrupts
534 icside_irqdisable_arcin_v6(ec, 0);
536 icside_setup_ports(&hw[0], easi_base, &icside_cardinfo_v6_1, ec);
537 icside_setup_ports(&hw[1], easi_base, &icside_cardinfo_v6_2, ec);
540 * Find and register the interfaces.
542 hwif = ide_find_port();
546 ide_init_port_hw(hwif, &hw[0]);
547 default_hwif_mmiops(hwif);
549 mate = ide_find_port();
553 ide_init_port_hw(mate, &hw[1]);
554 default_hwif_mmiops(mate);
556 state->hwif[0] = hwif;
557 state->hwif[1] = mate;
559 ecard_set_drvdata(ec, state);
561 if (ec->dma != NO_DMA && !request_dma(ec->dma, hwif->name)) {
562 d.init_dma = icside_dma_init;
563 d.port_ops = &icside_v6_port_ops;
567 idx[0] = hwif->index;
568 idx[1] = mate->index;
570 ide_device_add(idx, &d);
579 icside_probe(struct expansion_card *ec, const struct ecard_id *id)
581 struct icside_state *state;
585 ret = ecard_request_resources(ec);
589 state = kzalloc(sizeof(struct icside_state), GFP_KERNEL);
595 state->type = ICS_TYPE_NOTYPE;
597 idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
601 type = readb(idmem + ICS_IDENT_OFFSET) & 1;
602 type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
603 type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
604 type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
605 ecardm_iounmap(ec, idmem);
610 switch (state->type) {
612 dev_warn(&ec->dev, "A3IN unsupported\n");
616 case ICS_TYPE_A3USER:
617 dev_warn(&ec->dev, "A3USER unsupported\n");
622 ret = icside_register_v5(state, ec);
626 ret = icside_register_v6(state, ec);
630 dev_warn(&ec->dev, "unknown interface type\n");
640 ecard_release_resources(ec);
645 static void __devexit icside_remove(struct expansion_card *ec)
647 struct icside_state *state = ecard_get_drvdata(ec);
649 switch (state->type) {
651 /* FIXME: tell IDE to stop using the interface */
653 /* Disable interrupts */
654 icside_irqdisable_arcin_v5(ec, 0);
658 /* FIXME: tell IDE to stop using the interface */
659 if (ec->dma != NO_DMA)
662 /* Disable interrupts */
663 icside_irqdisable_arcin_v6(ec, 0);
665 /* Reset the ROM pointer/EASI selection */
666 writeb(0, state->ioc_base);
670 ecard_set_drvdata(ec, NULL);
673 ecard_release_resources(ec);
676 static void icside_shutdown(struct expansion_card *ec)
678 struct icside_state *state = ecard_get_drvdata(ec);
682 * Disable interrupts from this card. We need to do
683 * this before disabling EASI since we may be accessing
684 * this register via that region.
686 local_irq_save(flags);
687 ec->ops->irqdisable(ec, 0);
688 local_irq_restore(flags);
691 * Reset the ROM pointer so that we can read the ROM
692 * after a soft reboot. This also disables access to
693 * the IDE taskfile via the EASI region.
696 writeb(0, state->ioc_base);
699 static const struct ecard_id icside_ids[] = {
700 { MANU_ICS, PROD_ICS_IDE },
701 { MANU_ICS2, PROD_ICS2_IDE },
705 static struct ecard_driver icside_driver = {
706 .probe = icside_probe,
707 .remove = __devexit_p(icside_remove),
708 .shutdown = icside_shutdown,
709 .id_table = icside_ids,
715 static int __init icside_init(void)
717 return ecard_register_driver(&icside_driver);
720 MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
721 MODULE_LICENSE("GPL");
722 MODULE_DESCRIPTION("ICS IDE driver");
724 module_init(icside_init);