Merge branch 'for-linus' of git://one.firstfloor.org/home/andi/git/linux-2.6
[linux-2.6] / arch / frv / kernel / setup.c
1 /* setup.c: FRV specific setup
2  *
3  * Copyright (C) 2003-5 Red Hat, Inc. All Rights Reserved.
4  * Written by David Howells (dhowells@redhat.com)
5  * - Derived from arch/m68k/kernel/setup.c
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License
9  * as published by the Free Software Foundation; either version
10  * 2 of the License, or (at your option) any later version.
11  */
12
13 #include <linux/utsrelease.h>
14 #include <linux/kernel.h>
15 #include <linux/sched.h>
16 #include <linux/delay.h>
17 #include <linux/interrupt.h>
18 #include <linux/fs.h>
19 #include <linux/mm.h>
20 #include <linux/fb.h>
21 #include <linux/console.h>
22 #include <linux/genhd.h>
23 #include <linux/errno.h>
24 #include <linux/string.h>
25 #include <linux/major.h>
26 #include <linux/bootmem.h>
27 #include <linux/highmem.h>
28 #include <linux/seq_file.h>
29 #include <linux/serial.h>
30 #include <linux/serial_core.h>
31 #include <linux/serial_reg.h>
32
33 #include <asm/setup.h>
34 #include <asm/serial.h>
35 #include <asm/irq.h>
36 #include <asm/sections.h>
37 #include <asm/pgalloc.h>
38 #include <asm/busctl-regs.h>
39 #include <asm/serial-regs.h>
40 #include <asm/timer-regs.h>
41 #include <asm/irc-regs.h>
42 #include <asm/spr-regs.h>
43 #include <asm/mb-regs.h>
44 #include <asm/mb93493-regs.h>
45 #include <asm/gdb-stub.h>
46 #include <asm/io.h>
47
48 #ifdef CONFIG_BLK_DEV_INITRD
49 #include <linux/blk.h>
50 #include <asm/pgtable.h>
51 #endif
52
53 #include "local.h"
54
55 #ifdef CONFIG_MB93090_MB00
56 static void __init mb93090_display(void);
57 #endif
58 #ifdef CONFIG_MMU
59 static void __init setup_linux_memory(void);
60 #else
61 static void __init setup_uclinux_memory(void);
62 #endif
63
64 #ifdef CONFIG_CONSOLE
65 extern struct consw *conswitchp;
66 #endif
67
68 #ifdef CONFIG_MB93090_MB00
69 static char __initdata mb93090_banner[] = "FJ/RH FR-V Linux";
70 static char __initdata mb93090_version[] = UTS_RELEASE;
71
72 int __nongprelbss mb93090_mb00_detected;
73 #endif
74
75 const char __frv_unknown_system[] = "unknown";
76 const char __frv_mb93091_cb10[] = "mb93091-cb10";
77 const char __frv_mb93091_cb11[] = "mb93091-cb11";
78 const char __frv_mb93091_cb30[] = "mb93091-cb30";
79 const char __frv_mb93091_cb41[] = "mb93091-cb41";
80 const char __frv_mb93091_cb60[] = "mb93091-cb60";
81 const char __frv_mb93091_cb70[] = "mb93091-cb70";
82 const char __frv_mb93091_cb451[] = "mb93091-cb451";
83 const char __frv_mb93090_mb00[] = "mb93090-mb00";
84
85 const char __frv_mb93493[] = "mb93493";
86
87 const char __frv_mb93093[] = "mb93093";
88
89 static const char *__nongprelbss cpu_series;
90 static const char *__nongprelbss cpu_core;
91 static const char *__nongprelbss cpu_silicon;
92 static const char *__nongprelbss cpu_mmu;
93 static const char *__nongprelbss cpu_system;
94 static const char *__nongprelbss cpu_board1;
95 static const char *__nongprelbss cpu_board2;
96
97 static unsigned long __nongprelbss cpu_psr_all;
98 static unsigned long __nongprelbss cpu_hsr0_all;
99
100 unsigned long __nongprelbss pdm_suspend_mode;
101
102 unsigned long __nongprelbss rom_length;
103 unsigned long __nongprelbss memory_start;
104 unsigned long __nongprelbss memory_end;
105
106 unsigned long __nongprelbss dma_coherent_mem_start;
107 unsigned long __nongprelbss dma_coherent_mem_end;
108
109 unsigned long __initdata __sdram_old_base;
110 unsigned long __initdata num_mappedpages;
111
112 struct cpuinfo_frv __nongprelbss boot_cpu_data;
113
114 char command_line[COMMAND_LINE_SIZE];
115 char __initdata redboot_command_line[COMMAND_LINE_SIZE];
116
117 #ifdef CONFIG_PM
118 #define __pminit
119 #define __pminitdata
120 #else
121 #define __pminit __init
122 #define __pminitdata __initdata
123 #endif
124
125 struct clock_cmode {
126         uint8_t xbus, sdram, corebus, core, dsu;
127 };
128
129 #define _frac(N,D) ((N)<<4 | (D))
130 #define _x0_16  _frac(1,6)
131 #define _x0_25  _frac(1,4)
132 #define _x0_33  _frac(1,3)
133 #define _x0_375 _frac(3,8)
134 #define _x0_5   _frac(1,2)
135 #define _x0_66  _frac(2,3)
136 #define _x0_75  _frac(3,4)
137 #define _x1     _frac(1,1)
138 #define _x1_5   _frac(3,2)
139 #define _x2     _frac(2,1)
140 #define _x3     _frac(3,1)
141 #define _x4     _frac(4,1)
142 #define _x4_5   _frac(9,2)
143 #define _x6     _frac(6,1)
144 #define _x8     _frac(8,1)
145 #define _x9     _frac(9,1)
146
147 int __nongprelbss clock_p0_current;
148 int __nongprelbss clock_cm_current;
149 int __nongprelbss clock_cmode_current;
150 #ifdef CONFIG_PM
151 int __nongprelbss clock_cmodes_permitted;
152 unsigned long __nongprelbss clock_bits_settable;
153 #endif
154
155 static struct clock_cmode __pminitdata undef_clock_cmode = { _x1, _x1, _x1, _x1, _x1 };
156
157 static struct clock_cmode __pminitdata clock_cmodes_fr401_fr403[16] = {
158         [4]     = {     _x1,    _x1,    _x2,    _x2,    _x0_25  },
159         [5]     = {     _x1,    _x2,    _x4,    _x4,    _x0_5   },
160         [8]     = {     _x1,    _x1,    _x1,    _x2,    _x0_25  },
161         [9]     = {     _x1,    _x2,    _x2,    _x4,    _x0_5   },
162         [11]    = {     _x1,    _x4,    _x4,    _x8,    _x1     },
163         [12]    = {     _x1,    _x1,    _x2,    _x4,    _x0_5   },
164         [13]    = {     _x1,    _x2,    _x4,    _x8,    _x1     },
165 };
166
167 static struct clock_cmode __pminitdata clock_cmodes_fr405[16] = {
168         [0]     = {     _x1,    _x1,    _x1,    _x1,    _x0_5   },
169         [1]     = {     _x1,    _x1,    _x1,    _x3,    _x0_25  },
170         [2]     = {     _x1,    _x1,    _x2,    _x6,    _x0_5   },
171         [3]     = {     _x1,    _x2,    _x2,    _x6,    _x0_5   },
172         [4]     = {     _x1,    _x1,    _x2,    _x2,    _x0_16  },
173         [8]     = {     _x1,    _x1,    _x1,    _x2,    _x0_16  },
174         [9]     = {     _x1,    _x2,    _x2,    _x4,    _x0_33  },
175         [12]    = {     _x1,    _x1,    _x2,    _x4,    _x0_33  },
176         [14]    = {     _x1,    _x3,    _x3,    _x9,    _x0_75  },
177         [15]    = {     _x1,    _x1_5,  _x1_5,  _x4_5,  _x0_375 },
178
179 #define CLOCK_CMODES_PERMITTED_FR405 0xd31f
180 };
181
182 static struct clock_cmode __pminitdata clock_cmodes_fr555[16] = {
183         [0]     = {     _x1,    _x2,    _x2,    _x4,    _x0_33  },
184         [1]     = {     _x1,    _x3,    _x3,    _x6,    _x0_5   },
185         [2]     = {     _x1,    _x2,    _x4,    _x8,    _x0_66  },
186         [3]     = {     _x1,    _x1_5,  _x3,    _x6,    _x0_5   },
187         [4]     = {     _x1,    _x3,    _x3,    _x9,    _x0_75  },
188         [5]     = {     _x1,    _x2,    _x2,    _x6,    _x0_5   },
189         [6]     = {     _x1,    _x1_5,  _x1_5,  _x4_5,  _x0_375 },
190 };
191
192 static const struct clock_cmode __pminitdata *clock_cmodes;
193 static int __pminitdata clock_doubled;
194
195 static struct uart_port __initdata __frv_uart0 = {
196         .uartclk                = 0,
197         .membase                = (char *) UART0_BASE,
198         .irq                    = IRQ_CPU_UART0,
199         .regshift               = 3,
200         .iotype                 = UPIO_MEM,
201         .flags                  = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
202 };
203
204 static struct uart_port __initdata __frv_uart1 = {
205         .uartclk                = 0,
206         .membase                = (char *) UART1_BASE,
207         .irq                    = IRQ_CPU_UART1,
208         .regshift               = 3,
209         .iotype                 = UPIO_MEM,
210         .flags                  = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
211 };
212
213 #if 0
214 static void __init printk_xampr(unsigned long ampr, unsigned long amlr, char i_d, int n)
215 {
216         unsigned long phys, virt, cxn, size;
217
218 #ifdef CONFIG_MMU
219         virt = amlr & 0xffffc000;
220         cxn = amlr & 0x3fff;
221 #else
222         virt = ampr & 0xffffc000;
223         cxn = 0;
224 #endif
225         phys = ampr & xAMPRx_PPFN;
226         size = 1 << (((ampr & xAMPRx_SS) >> 4) + 17);
227
228         printk("%cAMPR%d: va %08lx-%08lx [pa %08lx] %c%c%c%c [cxn:%04lx]\n",
229                i_d, n,
230                virt, virt + size - 1,
231                phys,
232                ampr & xAMPRx_S  ? 'S' : '-',
233                ampr & xAMPRx_C  ? 'C' : '-',
234                ampr & DAMPRx_WP ? 'W' : '-',
235                ampr & xAMPRx_V  ? 'V' : '-',
236                cxn
237                );
238 }
239 #endif
240
241 /*****************************************************************************/
242 /*
243  * dump the memory map
244  */
245 static void __init dump_memory_map(void)
246 {
247
248 #if 0
249         /* dump the protection map */
250         printk_xampr(__get_IAMPR(0),  __get_IAMLR(0),  'I', 0);
251         printk_xampr(__get_IAMPR(1),  __get_IAMLR(1),  'I', 1);
252         printk_xampr(__get_IAMPR(2),  __get_IAMLR(2),  'I', 2);
253         printk_xampr(__get_IAMPR(3),  __get_IAMLR(3),  'I', 3);
254         printk_xampr(__get_IAMPR(4),  __get_IAMLR(4),  'I', 4);
255         printk_xampr(__get_IAMPR(5),  __get_IAMLR(5),  'I', 5);
256         printk_xampr(__get_IAMPR(6),  __get_IAMLR(6),  'I', 6);
257         printk_xampr(__get_IAMPR(7),  __get_IAMLR(7),  'I', 7);
258         printk_xampr(__get_IAMPR(8),  __get_IAMLR(8),  'I', 8);
259         printk_xampr(__get_IAMPR(9),  __get_IAMLR(9),  'i', 9);
260         printk_xampr(__get_IAMPR(10), __get_IAMLR(10), 'I', 10);
261         printk_xampr(__get_IAMPR(11), __get_IAMLR(11), 'I', 11);
262         printk_xampr(__get_IAMPR(12), __get_IAMLR(12), 'I', 12);
263         printk_xampr(__get_IAMPR(13), __get_IAMLR(13), 'I', 13);
264         printk_xampr(__get_IAMPR(14), __get_IAMLR(14), 'I', 14);
265         printk_xampr(__get_IAMPR(15), __get_IAMLR(15), 'I', 15);
266
267         printk_xampr(__get_DAMPR(0),  __get_DAMLR(0),  'D', 0);
268         printk_xampr(__get_DAMPR(1),  __get_DAMLR(1),  'D', 1);
269         printk_xampr(__get_DAMPR(2),  __get_DAMLR(2),  'D', 2);
270         printk_xampr(__get_DAMPR(3),  __get_DAMLR(3),  'D', 3);
271         printk_xampr(__get_DAMPR(4),  __get_DAMLR(4),  'D', 4);
272         printk_xampr(__get_DAMPR(5),  __get_DAMLR(5),  'D', 5);
273         printk_xampr(__get_DAMPR(6),  __get_DAMLR(6),  'D', 6);
274         printk_xampr(__get_DAMPR(7),  __get_DAMLR(7),  'D', 7);
275         printk_xampr(__get_DAMPR(8),  __get_DAMLR(8),  'D', 8);
276         printk_xampr(__get_DAMPR(9),  __get_DAMLR(9),  'D', 9);
277         printk_xampr(__get_DAMPR(10), __get_DAMLR(10), 'D', 10);
278         printk_xampr(__get_DAMPR(11), __get_DAMLR(11), 'D', 11);
279         printk_xampr(__get_DAMPR(12), __get_DAMLR(12), 'D', 12);
280         printk_xampr(__get_DAMPR(13), __get_DAMLR(13), 'D', 13);
281         printk_xampr(__get_DAMPR(14), __get_DAMLR(14), 'D', 14);
282         printk_xampr(__get_DAMPR(15), __get_DAMLR(15), 'D', 15);
283 #endif
284
285 #if 0
286         /* dump the bus controller registers */
287         printk("LGCR: %08lx\n", __get_LGCR());
288         printk("Master: %08lx-%08lx CR=%08lx\n",
289                __get_LEMBR(), __get_LEMBR() + __get_LEMAM(),
290                __get_LMAICR());
291
292         int loop;
293         for (loop = 1; loop <= 7; loop++) {
294                 unsigned long lcr = __get_LCR(loop), lsbr = __get_LSBR(loop);
295                 printk("CS#%d: %08lx-%08lx %c%c%c%c%c%c%c%c%c\n",
296                        loop,
297                        lsbr, lsbr + __get_LSAM(loop),
298                        lcr & 0x80000000 ? 'r' : '-',
299                        lcr & 0x40000000 ? 'w' : '-',
300                        lcr & 0x08000000 ? 'b' : '-',
301                        lcr & 0x04000000 ? 'B' : '-',
302                        lcr & 0x02000000 ? 'C' : '-',
303                        lcr & 0x01000000 ? 'D' : '-',
304                        lcr & 0x00800000 ? 'W' : '-',
305                        lcr & 0x00400000 ? 'R' : '-',
306                        (lcr & 0x00030000) == 0x00000000 ? '4' :
307                        (lcr & 0x00030000) == 0x00010000 ? '2' :
308                        (lcr & 0x00030000) == 0x00020000 ? '1' :
309                        '-'
310                        );
311         }
312 #endif
313
314 #if 0
315         printk("\n");
316 #endif
317 } /* end dump_memory_map() */
318
319 /*****************************************************************************/
320 /*
321  * attempt to detect a VDK motherboard and DAV daughter board on an MB93091 system
322  */
323 #ifdef CONFIG_MB93091_VDK
324 static void __init detect_mb93091(void)
325 {
326 #ifdef CONFIG_MB93090_MB00
327         /* Detect CB70 without motherboard */
328         if (!(cpu_system == __frv_mb93091_cb70 && ((*(unsigned short *)0xffc00030) & 0x100))) {
329                 cpu_board1 = __frv_mb93090_mb00;
330                 mb93090_mb00_detected = 1;
331         }
332 #endif
333
334 #ifdef CONFIG_FUJITSU_MB93493
335         cpu_board2 = __frv_mb93493;
336 #endif
337
338 } /* end detect_mb93091() */
339 #endif
340
341 /*****************************************************************************/
342 /*
343  * determine the CPU type and set appropriate parameters
344  *
345  * Family     Series      CPU Core    Silicon    Imple  Vers
346  * ----------------------------------------------------------
347  * FR-V --+-> FR400 --+-> FR401 --+-> MB93401     02     00 [1]
348  *        |           |           |
349  *        |           |           +-> MB93401/A   02     01
350  *        |           |           |
351  *        |           |           +-> MB93403     02     02
352  *        |           |
353  *        |           +-> FR405 ----> MB93405     04     00
354  *        |
355  *        +-> FR450 ----> FR451 ----> MB93451     05     00
356  *        |
357  *        +-> FR500 ----> FR501 --+-> MB93501     01     01 [2]
358  *        |                       |
359  *        |                       +-> MB93501/A   01     02
360  *        |
361  *        +-> FR550 --+-> FR551 ----> MB93555     03     01
362  *
363  *  [1] The MB93401 is an obsolete CPU replaced by the MB93401A
364  *  [2] The MB93501 is an obsolete CPU replaced by the MB93501A
365  *
366  * Imple is PSR(Processor Status Register)[31:28].
367  * Vers is PSR(Processor Status Register)[27:24].
368  *
369  * A "Silicon" consists of CPU core and some on-chip peripherals.
370  */
371 static void __init determine_cpu(void)
372 {
373         unsigned long hsr0 = __get_HSR(0);
374         unsigned long psr = __get_PSR();
375
376         /* work out what selectable services the CPU supports */
377         __set_PSR(psr | PSR_EM | PSR_EF | PSR_CM | PSR_NEM);
378         cpu_psr_all = __get_PSR();
379         __set_PSR(psr);
380
381         __set_HSR(0, hsr0 | HSR0_GRLE | HSR0_GRHE | HSR0_FRLE | HSR0_FRHE);
382         cpu_hsr0_all = __get_HSR(0);
383         __set_HSR(0, hsr0);
384
385         /* derive other service specs from the CPU type */
386         cpu_series              = "unknown";
387         cpu_core                = "unknown";
388         cpu_silicon             = "unknown";
389         cpu_mmu                 = "Prot";
390         cpu_system              = __frv_unknown_system;
391         clock_cmodes            = NULL;
392         clock_doubled           = 0;
393 #ifdef CONFIG_PM
394         clock_bits_settable     = CLOCK_BIT_CM_H | CLOCK_BIT_CM_M | CLOCK_BIT_P0;
395 #endif
396
397         switch (PSR_IMPLE(psr)) {
398         case PSR_IMPLE_FR401:
399                 cpu_series      = "fr400";
400                 cpu_core        = "fr401";
401                 pdm_suspend_mode = HSR0_PDM_PLL_RUN;
402
403                 switch (PSR_VERSION(psr)) {
404                 case PSR_VERSION_FR401_MB93401:
405                         cpu_silicon     = "mb93401";
406                         cpu_system      = __frv_mb93091_cb10;
407                         clock_cmodes    = clock_cmodes_fr401_fr403;
408                         clock_doubled   = 1;
409                         break;
410                 case PSR_VERSION_FR401_MB93401A:
411                         cpu_silicon     = "mb93401/A";
412                         cpu_system      = __frv_mb93091_cb11;
413                         clock_cmodes    = clock_cmodes_fr401_fr403;
414                         break;
415                 case PSR_VERSION_FR401_MB93403:
416                         cpu_silicon     = "mb93403";
417 #ifndef CONFIG_MB93093_PDK
418                         cpu_system      = __frv_mb93091_cb30;
419 #else
420                         cpu_system      = __frv_mb93093;
421 #endif
422                         clock_cmodes    = clock_cmodes_fr401_fr403;
423                         break;
424                 default:
425                         break;
426                 }
427                 break;
428
429         case PSR_IMPLE_FR405:
430                 cpu_series      = "fr400";
431                 cpu_core        = "fr405";
432                 pdm_suspend_mode = HSR0_PDM_PLL_STOP;
433
434                 switch (PSR_VERSION(psr)) {
435                 case PSR_VERSION_FR405_MB93405:
436                         cpu_silicon     = "mb93405";
437                         cpu_system      = __frv_mb93091_cb60;
438                         clock_cmodes    = clock_cmodes_fr405;
439 #ifdef CONFIG_PM
440                         clock_bits_settable |= CLOCK_BIT_CMODE;
441                         clock_cmodes_permitted = CLOCK_CMODES_PERMITTED_FR405;
442 #endif
443
444                         /* the FPGA on the CB70 has extra registers
445                          * - it has 0x0046 in the VDK_ID FPGA register at 0x1a0, which is
446                          *   how we tell the difference between it and a CB60
447                          */
448                         if (*(volatile unsigned short *) 0xffc001a0 == 0x0046)
449                                 cpu_system = __frv_mb93091_cb70;
450                         break;
451                 default:
452                         break;
453                 }
454                 break;
455
456         case PSR_IMPLE_FR451:
457                 cpu_series      = "fr450";
458                 cpu_core        = "fr451";
459                 pdm_suspend_mode = HSR0_PDM_PLL_STOP;
460 #ifdef CONFIG_PM
461                 clock_bits_settable |= CLOCK_BIT_CMODE;
462                 clock_cmodes_permitted = CLOCK_CMODES_PERMITTED_FR405;
463 #endif
464                 switch (PSR_VERSION(psr)) {
465                 case PSR_VERSION_FR451_MB93451:
466                         cpu_silicon     = "mb93451";
467                         cpu_mmu         = "Prot, SAT, xSAT, DAT";
468                         cpu_system      = __frv_mb93091_cb451;
469                         clock_cmodes    = clock_cmodes_fr405;
470                         break;
471                 default:
472                         break;
473                 }
474                 break;
475
476         case PSR_IMPLE_FR501:
477                 cpu_series      = "fr500";
478                 cpu_core        = "fr501";
479                 pdm_suspend_mode = HSR0_PDM_PLL_STOP;
480
481                 switch (PSR_VERSION(psr)) {
482                 case PSR_VERSION_FR501_MB93501:  cpu_silicon = "mb93501";   break;
483                 case PSR_VERSION_FR501_MB93501A: cpu_silicon = "mb93501/A"; break;
484                 default:
485                         break;
486                 }
487                 break;
488
489         case PSR_IMPLE_FR551:
490                 cpu_series      = "fr550";
491                 cpu_core        = "fr551";
492                 pdm_suspend_mode = HSR0_PDM_PLL_RUN;
493
494                 switch (PSR_VERSION(psr)) {
495                 case PSR_VERSION_FR551_MB93555:
496                         cpu_silicon     = "mb93555";
497                         cpu_mmu         = "Prot, SAT";
498                         cpu_system      = __frv_mb93091_cb41;
499                         clock_cmodes    = clock_cmodes_fr555;
500                         clock_doubled   = 1;
501                         break;
502                 default:
503                         break;
504                 }
505                 break;
506
507         default:
508                 break;
509         }
510
511         printk("- Series:%s CPU:%s Silicon:%s\n",
512                cpu_series, cpu_core, cpu_silicon);
513
514 #ifdef CONFIG_MB93091_VDK
515         detect_mb93091();
516 #endif
517
518 #if defined(CONFIG_MB93093_PDK) && defined(CONFIG_FUJITSU_MB93493)
519         cpu_board2 = __frv_mb93493;
520 #endif
521
522 } /* end determine_cpu() */
523
524 /*****************************************************************************/
525 /*
526  * calculate the bus clock speed
527  */
528 void __pminit determine_clocks(int verbose)
529 {
530         const struct clock_cmode *mode, *tmode;
531         unsigned long clkc, psr, quot;
532
533         clkc = __get_CLKC();
534         psr = __get_PSR();
535
536         clock_p0_current = !!(clkc & CLKC_P0);
537         clock_cm_current = clkc & CLKC_CM;
538         clock_cmode_current = (clkc & CLKC_CMODE) >> CLKC_CMODE_s;
539
540         if (verbose)
541                 printk("psr=%08lx hsr0=%08lx clkc=%08lx\n", psr, __get_HSR(0), clkc);
542
543         /* the CB70 has some alternative ways of setting the clock speed through switches accessed
544          * through the FPGA.  */
545         if (cpu_system == __frv_mb93091_cb70) {
546                 unsigned short clkswr = *(volatile unsigned short *) 0xffc00104UL & 0x1fffUL;
547
548                 if (clkswr & 0x1000)
549                         __clkin_clock_speed_HZ = 60000000UL;
550                 else
551                         __clkin_clock_speed_HZ =
552                                 ((clkswr >> 8) & 0xf) * 10000000 +
553                                 ((clkswr >> 4) & 0xf) * 1000000 +
554                                 ((clkswr     ) & 0xf) * 100000;
555         }
556         /* the FR451 is currently fixed at 24MHz */
557         else if (cpu_system == __frv_mb93091_cb451) {
558                 //__clkin_clock_speed_HZ = 24000000UL; // CB451-FPGA
559                 unsigned short clkswr = *(volatile unsigned short *) 0xffc00104UL & 0x1fffUL;
560
561                 if (clkswr & 0x1000)
562                         __clkin_clock_speed_HZ = 60000000UL;
563                 else
564                         __clkin_clock_speed_HZ =
565                                 ((clkswr >> 8) & 0xf) * 10000000 +
566                                 ((clkswr >> 4) & 0xf) * 1000000 +
567                                 ((clkswr     ) & 0xf) * 100000;
568         }
569         /* otherwise determine the clockspeed from VDK or other registers */
570         else {
571                 __clkin_clock_speed_HZ = __get_CLKIN();
572         }
573
574         /* look up the appropriate clock relationships table entry */
575         mode = &undef_clock_cmode;
576         if (clock_cmodes) {
577                 tmode = &clock_cmodes[(clkc & CLKC_CMODE) >> CLKC_CMODE_s];
578                 if (tmode->xbus)
579                         mode = tmode;
580         }
581
582 #define CLOCK(SRC,RATIO) ((SRC) * (((RATIO) >> 4) & 0x0f) / ((RATIO) & 0x0f))
583
584         if (clock_doubled)
585                 __clkin_clock_speed_HZ <<= 1;
586
587         __ext_bus_clock_speed_HZ        = CLOCK(__clkin_clock_speed_HZ, mode->xbus);
588         __sdram_clock_speed_HZ          = CLOCK(__clkin_clock_speed_HZ, mode->sdram);
589         __dsu_clock_speed_HZ            = CLOCK(__clkin_clock_speed_HZ, mode->dsu);
590
591         switch (clkc & CLKC_CM) {
592         case 0: /* High */
593                 __core_bus_clock_speed_HZ       = CLOCK(__clkin_clock_speed_HZ, mode->corebus);
594                 __core_clock_speed_HZ           = CLOCK(__clkin_clock_speed_HZ, mode->core);
595                 break;
596         case 1: /* Medium */
597                 __core_bus_clock_speed_HZ       = CLOCK(__clkin_clock_speed_HZ, mode->sdram);
598                 __core_clock_speed_HZ           = CLOCK(__clkin_clock_speed_HZ, mode->sdram);
599                 break;
600         case 2: /* Low; not supported */
601         case 3: /* UNDEF */
602                 printk("Unsupported CLKC CM %ld\n", clkc & CLKC_CM);
603                 panic("Bye");
604         }
605
606         __res_bus_clock_speed_HZ = __ext_bus_clock_speed_HZ;
607         if (clkc & CLKC_P0)
608                 __res_bus_clock_speed_HZ >>= 1;
609
610         if (verbose) {
611                 printk("CLKIN: %lu.%3.3luMHz\n",
612                        __clkin_clock_speed_HZ / 1000000,
613                        (__clkin_clock_speed_HZ / 1000) % 1000);
614
615                 printk("CLKS:"
616                        " ext=%luMHz res=%luMHz sdram=%luMHz cbus=%luMHz core=%luMHz dsu=%luMHz\n",
617                        __ext_bus_clock_speed_HZ / 1000000,
618                        __res_bus_clock_speed_HZ / 1000000,
619                        __sdram_clock_speed_HZ / 1000000,
620                        __core_bus_clock_speed_HZ / 1000000,
621                        __core_clock_speed_HZ / 1000000,
622                        __dsu_clock_speed_HZ / 1000000
623                        );
624         }
625
626         /* calculate the number of __delay() loop iterations per sec (2 insn loop) */
627         __delay_loops_MHz = __core_clock_speed_HZ / (1000000 * 2);
628
629         /* set the serial prescaler */
630         __serial_clock_speed_HZ = __res_bus_clock_speed_HZ;
631         quot = 1;
632         while (__serial_clock_speed_HZ / quot / 16 / 65536 > 3000)
633                 quot += 1;
634
635         /* double the divisor if P0 is clear, so that if/when P0 is set, it's still achievable
636          * - we have to be careful - dividing too much can mean we can't get 115200 baud
637          */
638         if (__serial_clock_speed_HZ > 32000000 && !(clkc & CLKC_P0))
639                 quot <<= 1;
640
641         __serial_clock_speed_HZ /= quot;
642         __frv_uart0.uartclk = __serial_clock_speed_HZ;
643         __frv_uart1.uartclk = __serial_clock_speed_HZ;
644
645         if (verbose)
646                 printk("      uart=%luMHz\n", __serial_clock_speed_HZ / 1000000 * quot);
647
648         while (!(__get_UART0_LSR() & UART_LSR_TEMT))
649                 continue;
650
651         while (!(__get_UART1_LSR() & UART_LSR_TEMT))
652                 continue;
653
654         __set_UCPVR(quot);
655         __set_UCPSR(0);
656 } /* end determine_clocks() */
657
658 /*****************************************************************************/
659 /*
660  * reserve some DMA consistent memory
661  */
662 #ifdef CONFIG_RESERVE_DMA_COHERENT
663 static void __init reserve_dma_coherent(void)
664 {
665         unsigned long ampr;
666
667         /* find the first non-kernel memory tile and steal it */
668 #define __steal_AMPR(r)                                         \
669         if (__get_DAMPR(r) & xAMPRx_V) {                        \
670                 ampr = __get_DAMPR(r);                          \
671                 __set_DAMPR(r, ampr | xAMPRx_S | xAMPRx_C);     \
672                 __set_IAMPR(r, 0);                              \
673                 goto found;                                     \
674         }
675
676         __steal_AMPR(1);
677         __steal_AMPR(2);
678         __steal_AMPR(3);
679         __steal_AMPR(4);
680         __steal_AMPR(5);
681         __steal_AMPR(6);
682
683         if (PSR_IMPLE(__get_PSR()) == PSR_IMPLE_FR551) {
684                 __steal_AMPR(7);
685                 __steal_AMPR(8);
686                 __steal_AMPR(9);
687                 __steal_AMPR(10);
688                 __steal_AMPR(11);
689                 __steal_AMPR(12);
690                 __steal_AMPR(13);
691                 __steal_AMPR(14);
692         }
693
694         /* unable to grant any DMA consistent memory */
695         printk("No DMA consistent memory reserved\n");
696         return;
697
698  found:
699         dma_coherent_mem_start = ampr & xAMPRx_PPFN;
700         ampr &= xAMPRx_SS;
701         ampr >>= 4;
702         ampr = 1 << (ampr - 3 + 20);
703         dma_coherent_mem_end = dma_coherent_mem_start + ampr;
704
705         printk("DMA consistent memory reserved %lx-%lx\n",
706                dma_coherent_mem_start, dma_coherent_mem_end);
707
708 } /* end reserve_dma_coherent() */
709 #endif
710
711 /*****************************************************************************/
712 /*
713  * calibrate the delay loop
714  */
715 void __init calibrate_delay(void)
716 {
717         loops_per_jiffy = __delay_loops_MHz * (1000000 / HZ);
718
719         printk("Calibrating delay loop... %lu.%02lu BogoMIPS\n",
720                loops_per_jiffy / (500000 / HZ),
721                (loops_per_jiffy / (5000 / HZ)) % 100);
722
723 } /* end calibrate_delay() */
724
725 /*****************************************************************************/
726 /*
727  * look through the command line for some things we need to know immediately
728  */
729 static void __init parse_cmdline_early(char *cmdline)
730 {
731         if (!cmdline)
732                 return;
733
734         while (*cmdline) {
735                 if (*cmdline == ' ')
736                         cmdline++;
737
738                 /* "mem=XXX[kKmM]" sets SDRAM size to <mem>, overriding the value we worked
739                  * out from the SDRAM controller mask register
740                  */
741                 if (!memcmp(cmdline, "mem=", 4)) {
742                         unsigned long long mem_size;
743
744                         mem_size = memparse(cmdline + 4, &cmdline);
745                         memory_end = memory_start + mem_size;
746                 }
747
748                 while (*cmdline && *cmdline != ' ')
749                         cmdline++;
750         }
751
752 } /* end parse_cmdline_early() */
753
754 /*****************************************************************************/
755 /*
756  *
757  */
758 void __init setup_arch(char **cmdline_p)
759 {
760 #ifdef CONFIG_MMU
761         printk("Linux FR-V port done by Red Hat Inc <dhowells@redhat.com>\n");
762 #else
763         printk("uClinux FR-V port done by Red Hat Inc <dhowells@redhat.com>\n");
764 #endif
765
766         memcpy(saved_command_line, redboot_command_line, COMMAND_LINE_SIZE);
767
768         determine_cpu();
769         determine_clocks(1);
770
771         /* For printk-directly-beats-on-serial-hardware hack */
772         console_set_baud(115200);
773 #ifdef CONFIG_GDBSTUB
774         gdbstub_set_baud(115200);
775 #endif
776
777 #ifdef CONFIG_RESERVE_DMA_COHERENT
778         reserve_dma_coherent();
779 #endif
780         dump_memory_map();
781
782 #ifdef CONFIG_MB93090_MB00
783         if (mb93090_mb00_detected)
784                 mb93090_display();
785 #endif
786
787         /* register those serial ports that are available */
788 #ifdef CONFIG_FRV_ONCPU_SERIAL
789 #ifndef CONFIG_GDBSTUB_UART0
790         __reg(UART0_BASE + UART_IER * 8) = 0;
791         early_serial_setup(&__frv_uart0);
792 #endif
793 #ifndef CONFIG_GDBSTUB_UART1
794         __reg(UART1_BASE + UART_IER * 8) = 0;
795         early_serial_setup(&__frv_uart1);
796 #endif
797 #endif
798
799 #if defined(CONFIG_CHR_DEV_FLASH) || defined(CONFIG_BLK_DEV_FLASH)
800         /* we need to initialize the Flashrom device here since we might
801          * do things with flash early on in the boot
802          */
803         flash_probe();
804 #endif
805
806         /* deal with the command line - RedBoot may have passed one to the kernel */
807         memcpy(command_line, saved_command_line, sizeof(command_line));
808         *cmdline_p = &command_line[0];
809         parse_cmdline_early(command_line);
810
811         /* set up the memory description
812          * - by now the stack is part of the init task */
813         printk("Memory %08lx-%08lx\n", memory_start, memory_end);
814
815         BUG_ON(memory_start == memory_end);
816
817         init_mm.start_code = (unsigned long) &_stext;
818         init_mm.end_code = (unsigned long) &_etext;
819         init_mm.end_data = (unsigned long) &_edata;
820 #if 0 /* DAVIDM - don't set brk just incase someone decides to use it */
821         init_mm.brk = (unsigned long) &_end;
822 #else
823         init_mm.brk = (unsigned long) 0;
824 #endif
825
826 #ifdef DEBUG
827         printk("KERNEL -> TEXT=0x%06x-0x%06x DATA=0x%06x-0x%06x BSS=0x%06x-0x%06x\n",
828                (int) &_stext, (int) &_etext,
829                (int) &_sdata, (int) &_edata,
830                (int) &_sbss, (int) &_ebss);
831 #endif
832
833 #ifdef CONFIG_VT
834 #if defined(CONFIG_VGA_CONSOLE)
835         conswitchp = &vga_con;
836 #elif defined(CONFIG_DUMMY_CONSOLE)
837         conswitchp = &dummy_con;
838 #endif
839 #endif
840
841 #ifdef CONFIG_BLK_DEV_BLKMEM
842         ROOT_DEV = MKDEV(BLKMEM_MAJOR,0);
843 #endif
844         /*rom_length = (unsigned long)&_flashend - (unsigned long)&_romvec;*/
845
846 #ifdef CONFIG_MMU
847         setup_linux_memory();
848 #else
849         setup_uclinux_memory();
850 #endif
851
852         /* get kmalloc into gear */
853         paging_init();
854
855         /* init DMA */
856         frv_dma_init();
857 #ifdef DEBUG
858         printk("Done setup_arch\n");
859 #endif
860
861         /* start the decrement timer running */
862 //      asm volatile("movgs %0,timerd" :: "r"(10000000));
863 //      __set_HSR(0, __get_HSR(0) | HSR0_ETMD);
864
865 } /* end setup_arch() */
866
867 #if 0
868 /*****************************************************************************/
869 /*
870  *
871  */
872 static int __devinit setup_arch_serial(void)
873 {
874         /* register those serial ports that are available */
875 #ifndef CONFIG_GDBSTUB_UART0
876         early_serial_setup(&__frv_uart0);
877 #endif
878 #ifndef CONFIG_GDBSTUB_UART1
879         early_serial_setup(&__frv_uart1);
880 #endif
881
882         return 0;
883 } /* end setup_arch_serial() */
884
885 late_initcall(setup_arch_serial);
886 #endif
887
888 /*****************************************************************************/
889 /*
890  * set up the memory map for normal MMU linux
891  */
892 #ifdef CONFIG_MMU
893 static void __init setup_linux_memory(void)
894 {
895         unsigned long bootmap_size, low_top_pfn, kstart, kend, high_mem;
896
897         kstart  = (unsigned long) &__kernel_image_start - PAGE_OFFSET;
898         kend    = (unsigned long) &__kernel_image_end - PAGE_OFFSET;
899
900         kstart = kstart & PAGE_MASK;
901         kend = (kend + PAGE_SIZE - 1) & PAGE_MASK;
902
903         /* give all the memory to the bootmap allocator,  tell it to put the
904          * boot mem_map immediately following the kernel image
905          */
906         bootmap_size = init_bootmem_node(NODE_DATA(0),
907                                          kend >> PAGE_SHIFT,            /* map addr */
908                                          memory_start >> PAGE_SHIFT,    /* start of RAM */
909                                          memory_end >> PAGE_SHIFT       /* end of RAM */
910                                          );
911
912         /* pass the memory that the kernel can immediately use over to the bootmem allocator */
913         max_mapnr = num_physpages = (memory_end - memory_start) >> PAGE_SHIFT;
914         low_top_pfn = (KERNEL_LOWMEM_END - KERNEL_LOWMEM_START) >> PAGE_SHIFT;
915         high_mem = 0;
916
917         if (num_physpages > low_top_pfn) {
918 #ifdef CONFIG_HIGHMEM
919                 high_mem = num_physpages - low_top_pfn;
920 #else
921                 max_mapnr = num_physpages = low_top_pfn;
922 #endif
923         }
924         else {
925                 low_top_pfn = num_physpages;
926         }
927
928         min_low_pfn = memory_start >> PAGE_SHIFT;
929         max_low_pfn = low_top_pfn;
930         max_pfn = memory_end >> PAGE_SHIFT;
931
932         num_mappedpages = low_top_pfn;
933
934         printk(KERN_NOTICE "%ldMB LOWMEM available.\n", low_top_pfn >> (20 - PAGE_SHIFT));
935
936         free_bootmem(memory_start, low_top_pfn << PAGE_SHIFT);
937
938 #ifdef CONFIG_HIGHMEM
939         if (high_mem)
940                 printk(KERN_NOTICE "%ldMB HIGHMEM available.\n", high_mem >> (20 - PAGE_SHIFT));
941 #endif
942
943         /* take back the memory occupied by the kernel image and the bootmem alloc map */
944         reserve_bootmem(kstart, kend - kstart + bootmap_size);
945
946         /* reserve the memory occupied by the initial ramdisk */
947 #ifdef CONFIG_BLK_DEV_INITRD
948         if (LOADER_TYPE && INITRD_START) {
949                 if (INITRD_START + INITRD_SIZE <= (low_top_pfn << PAGE_SHIFT)) {
950                         reserve_bootmem(INITRD_START, INITRD_SIZE);
951                         initrd_start = INITRD_START ? INITRD_START + PAGE_OFFSET : 0;
952                         initrd_end = initrd_start + INITRD_SIZE;
953                 }
954                 else {
955                         printk(KERN_ERR
956                                "initrd extends beyond end of memory (0x%08lx > 0x%08lx)\n"
957                                "disabling initrd\n",
958                                INITRD_START + INITRD_SIZE,
959                                low_top_pfn << PAGE_SHIFT);
960                         initrd_start = 0;
961                 }
962         }
963 #endif
964
965 } /* end setup_linux_memory() */
966 #endif
967
968 /*****************************************************************************/
969 /*
970  * set up the memory map for uClinux
971  */
972 #ifndef CONFIG_MMU
973 static void __init setup_uclinux_memory(void)
974 {
975 #ifdef CONFIG_PROTECT_KERNEL
976         unsigned long dampr;
977 #endif
978         unsigned long kend;
979         int bootmap_size;
980
981         kend = (unsigned long) &__kernel_image_end;
982         kend = (kend + PAGE_SIZE - 1) & PAGE_MASK;
983
984         /* give all the memory to the bootmap allocator,  tell it to put the
985          * boot mem_map immediately following the kernel image
986          */
987         bootmap_size = init_bootmem_node(NODE_DATA(0),
988                                          kend >> PAGE_SHIFT,            /* map addr */
989                                          memory_start >> PAGE_SHIFT,    /* start of RAM */
990                                          memory_end >> PAGE_SHIFT       /* end of RAM */
991                                          );
992
993         /* free all the usable memory */
994         free_bootmem(memory_start, memory_end - memory_start);
995
996         high_memory = (void *) (memory_end & PAGE_MASK);
997         max_mapnr = num_physpages = ((unsigned long) high_memory - PAGE_OFFSET) >> PAGE_SHIFT;
998
999         min_low_pfn = memory_start >> PAGE_SHIFT;
1000         max_low_pfn = memory_end >> PAGE_SHIFT;
1001         max_pfn = max_low_pfn;
1002
1003         /* now take back the bits the core kernel is occupying */
1004 #ifndef CONFIG_PROTECT_KERNEL
1005         reserve_bootmem(kend, bootmap_size);
1006         reserve_bootmem((unsigned long) &__kernel_image_start,
1007                         kend - (unsigned long) &__kernel_image_start);
1008
1009 #else
1010         dampr = __get_DAMPR(0);
1011         dampr &= xAMPRx_SS;
1012         dampr = (dampr >> 4) + 17;
1013         dampr = 1 << dampr;
1014
1015         reserve_bootmem(__get_DAMPR(0) & xAMPRx_PPFN, dampr);
1016 #endif
1017
1018         /* reserve some memory to do uncached DMA through if requested */
1019 #ifdef CONFIG_RESERVE_DMA_COHERENT
1020         if (dma_coherent_mem_start)
1021                 reserve_bootmem(dma_coherent_mem_start,
1022                                 dma_coherent_mem_end - dma_coherent_mem_start);
1023 #endif
1024
1025 } /* end setup_uclinux_memory() */
1026 #endif
1027
1028 /*****************************************************************************/
1029 /*
1030  * get CPU information for use by procfs
1031  */
1032 static int show_cpuinfo(struct seq_file *m, void *v)
1033 {
1034         const char *gr, *fr, *fm, *fp, *cm, *nem, *ble;
1035 #ifdef CONFIG_PM
1036         const char *sep;
1037 #endif
1038
1039         gr  = cpu_hsr0_all & HSR0_GRHE  ? "gr0-63"      : "gr0-31";
1040         fr  = cpu_hsr0_all & HSR0_FRHE  ? "fr0-63"      : "fr0-31";
1041         fm  = cpu_psr_all  & PSR_EM     ? ", Media"     : "";
1042         fp  = cpu_psr_all  & PSR_EF     ? ", FPU"       : "";
1043         cm  = cpu_psr_all  & PSR_CM     ? ", CCCR"      : "";
1044         nem = cpu_psr_all  & PSR_NEM    ? ", NE"        : "";
1045         ble = cpu_psr_all  & PSR_BE     ? "BE"          : "LE";
1046
1047         seq_printf(m,
1048                    "CPU-Series:\t%s\n"
1049                    "CPU-Core:\t%s, %s, %s%s%s\n"
1050                    "CPU:\t\t%s\n"
1051                    "MMU:\t\t%s\n"
1052                    "FP-Media:\t%s%s%s\n"
1053                    "System:\t\t%s",
1054                    cpu_series,
1055                    cpu_core, gr, ble, cm, nem,
1056                    cpu_silicon,
1057                    cpu_mmu,
1058                    fr, fm, fp,
1059                    cpu_system);
1060
1061         if (cpu_board1)
1062                 seq_printf(m, ", %s", cpu_board1);
1063
1064         if (cpu_board2)
1065                 seq_printf(m, ", %s", cpu_board2);
1066
1067         seq_printf(m, "\n");
1068
1069 #ifdef CONFIG_PM
1070         seq_printf(m, "PM-Controls:");
1071         sep = "\t";
1072
1073         if (clock_bits_settable & CLOCK_BIT_CMODE) {
1074                 seq_printf(m, "%scmode=0x%04hx", sep, clock_cmodes_permitted);
1075                 sep = ", ";
1076         }
1077
1078         if (clock_bits_settable & CLOCK_BIT_CM) {
1079                 seq_printf(m, "%scm=0x%lx", sep, clock_bits_settable & CLOCK_BIT_CM);
1080                 sep = ", ";
1081         }
1082
1083         if (clock_bits_settable & CLOCK_BIT_P0) {
1084                 seq_printf(m, "%sp0=0x3", sep);
1085                 sep = ", ";
1086         }
1087
1088         seq_printf(m, "%ssuspend=0x22\n", sep);
1089 #endif
1090
1091         seq_printf(m,
1092                    "PM-Status:\tcmode=%d, cm=%d, p0=%d\n",
1093                    clock_cmode_current, clock_cm_current, clock_p0_current);
1094
1095 #define print_clk(TAG, VAR) \
1096         seq_printf(m, "Clock-" TAG ":\t%lu.%2.2lu MHz\n", VAR / 1000000, (VAR / 10000) % 100)
1097
1098         print_clk("In",    __clkin_clock_speed_HZ);
1099         print_clk("Core",  __core_clock_speed_HZ);
1100         print_clk("SDRAM", __sdram_clock_speed_HZ);
1101         print_clk("CBus",  __core_bus_clock_speed_HZ);
1102         print_clk("Res",   __res_bus_clock_speed_HZ);
1103         print_clk("Ext",   __ext_bus_clock_speed_HZ);
1104         print_clk("DSU",   __dsu_clock_speed_HZ);
1105
1106         seq_printf(m,
1107                    "BogoMips:\t%lu.%02lu\n",
1108                    (loops_per_jiffy * HZ) / 500000, ((loops_per_jiffy * HZ) / 5000) % 100);
1109
1110         return 0;
1111 } /* end show_cpuinfo() */
1112
1113 static void *c_start(struct seq_file *m, loff_t *pos)
1114 {
1115         return *pos < NR_CPUS ? (void *) 0x12345678 : NULL;
1116 }
1117
1118 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1119 {
1120         ++*pos;
1121         return c_start(m, pos);
1122 }
1123
1124 static void c_stop(struct seq_file *m, void *v)
1125 {
1126 }
1127
1128 struct seq_operations cpuinfo_op = {
1129         .start  = c_start,
1130         .next   = c_next,
1131         .stop   = c_stop,
1132         .show   = show_cpuinfo,
1133 };
1134
1135 void arch_gettod(int *year, int *mon, int *day, int *hour,
1136                  int *min, int *sec)
1137 {
1138         *year = *mon = *day = *hour = *min = *sec = 0;
1139 }
1140
1141 /*****************************************************************************/
1142 /*
1143  *
1144  */
1145 #ifdef CONFIG_MB93090_MB00
1146 static void __init mb93090_sendlcdcmd(uint32_t cmd)
1147 {
1148         unsigned long base = __addr_LCD();
1149         int loop;
1150
1151         /* request reading of the busy flag */
1152         __set_LCD(base, LCD_CMD_READ_BUSY);
1153         __set_LCD(base, LCD_CMD_READ_BUSY & ~LCD_E);
1154
1155         /* wait for the busy flag to become clear */
1156         for (loop = 10000; loop > 0; loop--)
1157                 if (!(__get_LCD(base) & 0x80))
1158                         break;
1159
1160         /* send the command */
1161         __set_LCD(base, cmd);
1162         __set_LCD(base, cmd & ~LCD_E);
1163
1164 } /* end mb93090_sendlcdcmd() */
1165
1166 /*****************************************************************************/
1167 /*
1168  * write to the MB93090 LEDs and LCD
1169  */
1170 static void __init mb93090_display(void)
1171 {
1172         const char *p;
1173
1174         __set_LEDS(0);
1175
1176         /* set up the LCD */
1177         mb93090_sendlcdcmd(LCD_CMD_CLEAR);
1178         mb93090_sendlcdcmd(LCD_CMD_FUNCSET(1,1,0));
1179         mb93090_sendlcdcmd(LCD_CMD_ON(0,0));
1180         mb93090_sendlcdcmd(LCD_CMD_HOME);
1181
1182         mb93090_sendlcdcmd(LCD_CMD_SET_DD_ADDR(0));
1183         for (p = mb93090_banner; *p; p++)
1184                 mb93090_sendlcdcmd(LCD_DATA_WRITE(*p));
1185
1186         mb93090_sendlcdcmd(LCD_CMD_SET_DD_ADDR(64));
1187         for (p = mb93090_version; *p; p++)
1188                 mb93090_sendlcdcmd(LCD_DATA_WRITE(*p));
1189
1190 } /* end mb93090_display() */
1191
1192 #endif // CONFIG_MB93090_MB00