1 #ifndef __ASM_CPU_SH3_DMA_H
2 #define __ASM_CPU_SH3_DMA_H
5 #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
6 defined(CONFIG_CPU_SUBTYPE_SH7721)
7 #define SH_DMAC_BASE 0xa4010020
9 #define SH_DMAC_BASE 0xa4000020
12 #if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7709)
21 /* Definitions for the SuperH DMAC */
22 #define TM_BURST 0x00000020
23 #define TS_8 0x00000000
24 #define TS_16 0x00000008
25 #define TS_32 0x00000010
26 #define TS_128 0x00000018
28 #define CHCR_TS_MASK 0x18
29 #define CHCR_TS_SHIFT 3
31 #define DMAOR_INIT DMAOR_DME
34 * The SuperH DMAC supports a number of transmit sizes, we list them here,
35 * with their respective values as they appear in the CHCR registers.
44 static unsigned int ts_shift[] __maybe_unused = {
51 #endif /* __ASM_CPU_SH3_DMA_H */