2 /* low-level asm for "intrigue" (PA8500-8700 CPU perf counters)
4 * Copyright (C) 2001 Randolph Chung <tausq at parisc-linux.org>
5 * Copyright (C) 2001 Hewlett-Packard (Grant Grundler)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <asm/assembly.h>
26 #endif /* CONFIG_64BIT */
28 #define MTDIAG_1(gr) .word 0x14201840 + gr*0x10000
29 #define MTDIAG_2(gr) .word 0x14401840 + gr*0x10000
30 #define MFDIAG_1(gr) .word 0x142008A0 + gr
31 #define MFDIAG_2(gr) .word 0x144008A0 + gr
32 #define STDIAG(dr) .word 0x14000AA0 + dr*0x200000
33 #define SFDIAG(dr) .word 0x14000BA0 + dr*0x200000
34 #define DR2_SLOW_RET 53
38 ; Enable the performance counters
40 ; The coprocessor only needs to be enabled when
41 ; starting/stopping the coprocessor with the pmenb/pmdis.
46 .export perf_intrigue_enable_perf_counters,code
47 perf_intrigue_enable_perf_counters:
49 .callinfo frame=0,NO_CALLS
52 ldi 0x20,%r25 ; load up perfmon bit
53 mfctl ccr,%r26 ; get coprocessor register
54 or %r25,%r26,%r26 ; set bit
55 mtctl %r26,ccr ; turn on performance coprocessor
56 pmenb ; enable performance monitor
57 ssm 0,0 ; dummy op to ensure completion
59 andcm %r26,%r25,%r26 ; clear bit now
60 mtctl %r26,ccr ; turn off performance coprocessor
61 nop ; NOPs as specified in ERS
73 .export perf_intrigue_disable_perf_counters,code
74 perf_intrigue_disable_perf_counters:
76 .callinfo frame=0,NO_CALLS
78 ldi 0x20,%r25 ; load up perfmon bit
79 mfctl ccr,%r26 ; get coprocessor register
80 or %r25,%r26,%r26 ; set bit
81 mtctl %r26,ccr ; turn on performance coprocessor
82 pmdis ; disable performance monitor
83 ssm 0,0 ; dummy op to ensure completion
84 andcm %r26,%r25,%r26 ; clear bit now
86 mtctl %r26,ccr ; turn off performance coprocessor
90 ;***********************************************************************
92 ;* Name: perf_rdr_shift_in_W
95 ;* This routine shifts data in from the RDR in arg0 and returns
96 ;* the result in ret0. If the RDR is <= 64 bits in length, it
97 ;* is shifted shifted backup immediately. This is to compensate
98 ;* for RDR10 which has bits that preclude PDC stack operations
99 ;* when they are in the wrong state.
102 ;* arg0 : rdr to be read
103 ;* arg1 : bit length of rdr
106 ;* ret0 = next 64 bits of rdr data from staging register
109 ;* arg0 : rdr to be read
110 ;* arg1 : bit length of rdr
111 ;* %r24 - original DR2 value
116 ;* ret0 = RDR data (right justified)
118 ;***********************************************************************
120 .export perf_rdr_shift_in_W,code
123 .callinfo frame=0,NO_CALLS
126 ; read(shift in) the RDR.
129 ; NOTE: The PCX-W ERS states that DR2_SLOW_RET must be set before any
130 ; shifting is done, from or to, remote diagnose registers.
133 depdi,z 1,DR2_SLOW_RET,1,%r29
136 MTDIAG_2 (29) ; set DR2_SLOW_RET
144 ; Cacheline start (32-byte cacheline)
149 extrd,u arg1,63,6,%r1 ; setup shift amount by bits to move
152 shladd arg0,2,%r0,%r1 ; %r1 = 4 * RDR number
153 blr %r1,%r0 ; branch to 8-instruction sequence
157 ; Cacheline start (32-byte cacheline)
166 shrpd ret0,%r0,%sar,%r1
167 MTDIAG_1 (1) ; mtdiag %dr1, %r1
170 b,n perf_rdr_shift_in_W_leave
181 b,n perf_rdr_shift_in_W_leave
185 ; RDR 2 read sequence
190 shrpd ret0,%r0,%sar,%r1
194 b,n perf_rdr_shift_in_W_leave
197 ; RDR 3 read sequence
199 b,n perf_rdr_shift_in_W_leave
209 ; RDR 4 read sequence
216 b,n perf_rdr_shift_in_W_leave
221 ; RDR 5 read sequence
228 b,n perf_rdr_shift_in_W_leave
233 ; RDR 6 read sequence
240 b,n perf_rdr_shift_in_W_leave
245 ; RDR 7 read sequence
247 b,n perf_rdr_shift_in_W_leave
257 ; RDR 8 read sequence
259 b,n perf_rdr_shift_in_W_leave
269 ; RDR 9 read sequence
271 b,n perf_rdr_shift_in_W_leave
281 ; RDR 10 read sequence
286 shrpd ret0,%r0,%sar,%r1
290 b,n perf_rdr_shift_in_W_leave
293 ; RDR 11 read sequence
298 shrpd ret0,%r0,%sar,%r1
302 b,n perf_rdr_shift_in_W_leave
305 ; RDR 12 read sequence
307 b,n perf_rdr_shift_in_W_leave
317 ; RDR 13 read sequence
324 b,n perf_rdr_shift_in_W_leave
329 ; RDR 14 read sequence
334 shrpd ret0,%r0,%sar,%r1
338 b,n perf_rdr_shift_in_W_leave
341 ; RDR 15 read sequence
349 b,n perf_rdr_shift_in_W_leave
353 ; RDR 16 read sequence
360 b,n perf_rdr_shift_in_W_leave
365 ; RDR 17 read sequence
370 shrpd ret0,%r0,%sar,%r1
374 b,n perf_rdr_shift_in_W_leave
377 ; RDR 18 read sequence
382 shrpd ret0,%r0,%sar,%r1
386 b,n perf_rdr_shift_in_W_leave
389 ; RDR 19 read sequence
391 b,n perf_rdr_shift_in_W_leave
401 ; RDR 20 read sequence
408 b,n perf_rdr_shift_in_W_leave
413 ; RDR 21 read sequence
420 b,n perf_rdr_shift_in_W_leave
425 ; RDR 22 read sequence
432 b,n perf_rdr_shift_in_W_leave
437 ; RDR 23 read sequence
444 b,n perf_rdr_shift_in_W_leave
449 ; RDR 24 read sequence
456 b,n perf_rdr_shift_in_W_leave
461 ; RDR 25 read sequence
468 b,n perf_rdr_shift_in_W_leave
473 ; RDR 26 read sequence
478 shrpd ret0,%r0,%sar,%r1
482 b,n perf_rdr_shift_in_W_leave
485 ; RDR 27 read sequence
490 shrpd ret0,%r0,%sar,%r1
494 b,n perf_rdr_shift_in_W_leave
497 ; RDR 28 read sequence
504 b,n perf_rdr_shift_in_W_leave
509 ; RDR 29 read sequence
516 b,n perf_rdr_shift_in_W_leave
521 ; RDR 30 read sequence
526 shrpd ret0,%r0,%sar,%r1
530 b,n perf_rdr_shift_in_W_leave
533 ; RDR 31 read sequence
548 perf_rdr_shift_in_W_leave:
551 MTDIAG_2 (24) ; restore DR2
555 ;***********************************************************************
557 ;* Name: perf_rdr_shift_out_W
560 ;* This routine moves data to the RDR's. The double-word that
561 ;* arg1 points to is loaded and moved into the staging register.
562 ;* Then the STDIAG instruction for the RDR # in arg0 is called
563 ;* to move the data to the RDR.
567 ;* arg1 = 64-bit value to write
568 ;* %r24 - DR2 | DR2_SLOW_RET
569 ;* %r23 - original DR2 value
576 ;***********************************************************************
578 .export perf_rdr_shift_out_W,code
579 perf_rdr_shift_out_W:
581 .callinfo frame=0,NO_CALLS
584 ; NOTE: The PCX-W ERS states that DR2_SLOW_RET must be set before any
585 ; shifting is done, from or to, the remote diagnose registers.
588 depdi,z 1,DR2_SLOW_RET,1,%r24
591 MTDIAG_2 (24) ; set DR2_SLOW_RET
592 MTDIAG_1 (25) ; data to the staging register
593 shladd arg0,2,%r0,%r1 ; %r1 = 4 * RDR number
594 blr %r1,%r0 ; branch to 8-instruction sequence
598 ; RDR 0 write sequence
600 sync ; RDR 0 write sequence
604 b,n perf_rdr_shift_out_W_leave
610 ; RDR 1 write sequence
616 b,n perf_rdr_shift_out_W_leave
622 ; RDR 2 write sequence
628 b,n perf_rdr_shift_out_W_leave
634 ; RDR 3 write sequence
640 b,n perf_rdr_shift_out_W_leave
646 ; RDR 4 write sequence
652 b,n perf_rdr_shift_out_W_leave
658 ; RDR 5 write sequence
664 b,n perf_rdr_shift_out_W_leave
670 ; RDR 6 write sequence
676 b,n perf_rdr_shift_out_W_leave
682 ; RDR 7 write sequence
688 b,n perf_rdr_shift_out_W_leave
694 ; RDR 8 write sequence
700 b,n perf_rdr_shift_out_W_leave
706 ; RDR 9 write sequence
712 b,n perf_rdr_shift_out_W_leave
718 ; RDR 10 write sequence
725 b,n perf_rdr_shift_out_W_leave
730 ; RDR 11 write sequence
737 b,n perf_rdr_shift_out_W_leave
742 ; RDR 12 write sequence
748 b,n perf_rdr_shift_out_W_leave
754 ; RDR 13 write sequence
760 b,n perf_rdr_shift_out_W_leave
766 ; RDR 14 write sequence
772 b,n perf_rdr_shift_out_W_leave
778 ; RDR 15 write sequence
784 b,n perf_rdr_shift_out_W_leave
790 ; RDR 16 write sequence
796 b,n perf_rdr_shift_out_W_leave
802 ; RDR 17 write sequence
808 b,n perf_rdr_shift_out_W_leave
814 ; RDR 18 write sequence
820 b,n perf_rdr_shift_out_W_leave
826 ; RDR 19 write sequence
832 b,n perf_rdr_shift_out_W_leave
838 ; RDR 20 write sequence
844 b,n perf_rdr_shift_out_W_leave
850 ; RDR 21 write sequence
856 b,n perf_rdr_shift_out_W_leave
862 ; RDR 22 write sequence
868 b,n perf_rdr_shift_out_W_leave
874 ; RDR 23 write sequence
880 b,n perf_rdr_shift_out_W_leave
886 ; RDR 24 write sequence
892 b,n perf_rdr_shift_out_W_leave
898 ; RDR 25 write sequence
904 b,n perf_rdr_shift_out_W_leave
910 ; RDR 26 write sequence
917 b,n perf_rdr_shift_out_W_leave
922 ; RDR 27 write sequence
929 b,n perf_rdr_shift_out_W_leave
934 ; RDR 28 write sequence
940 b,n perf_rdr_shift_out_W_leave
946 ; RDR 29 write sequence
952 b,n perf_rdr_shift_out_W_leave
958 ; RDR 30 write sequence
964 b,n perf_rdr_shift_out_W_leave
970 ; RDR 31 write sequence
976 b,n perf_rdr_shift_out_W_leave
981 perf_rdr_shift_out_W_leave:
984 MTDIAG_2 (23) ; restore DR2
988 ;***********************************************************************
990 ;* Name: rdr_shift_in_U
993 ;* This routine shifts data in from the RDR in arg0 and returns
994 ;* the result in ret0. If the RDR is <= 64 bits in length, it
995 ;* is shifted shifted backup immediately. This is to compensate
996 ;* for RDR10 which has bits that preclude PDC stack operations
997 ;* when they are in the wrong state.
1000 ;* arg0 : rdr to be read
1001 ;* arg1 : bit length of rdr
1004 ;* ret0 = next 64 bits of rdr data from staging register
1007 ;* arg0 : rdr to be read
1008 ;* arg1 : bit length of rdr
1009 ;* %r24 - original DR2 value
1010 ;* %r23 - DR2 | DR2_SLOW_RET
1013 ;***********************************************************************
1015 .export perf_rdr_shift_in_U,code
1016 perf_rdr_shift_in_U:
1018 .callinfo frame=0,NO_CALLS
1021 ; read(shift in) the RDR.
1023 ; NOTE: The PCX-U ERS states that DR2_SLOW_RET must be set before any
1024 ; shifting is done, from or to, remote diagnose registers.
1026 depdi,z 1,DR2_SLOW_RET,1,%r29
1029 MTDIAG_2 (29) ; set DR2_SLOW_RET
1037 ; Start of next 32-byte cacheline
1042 extrd,u arg1,63,6,%r1
1045 shladd arg0,2,%r0,%r1 ; %r1 = 4 * RDR number
1046 blr %r1,%r0 ; branch to 8-instruction sequence
1050 ; Start of next 32-byte cacheline
1052 SFDIAG (0) ; RDR 0 read sequence
1055 shrpd ret0,%r0,%sar,%r1
1059 b,n perf_rdr_shift_in_U_leave
1061 SFDIAG (1) ; RDR 1 read sequence
1064 shrpd ret0,%r0,%sar,%r1
1068 b,n perf_rdr_shift_in_U_leave
1070 sync ; RDR 2 read sequence
1075 b,n perf_rdr_shift_in_U_leave
1079 sync ; RDR 3 read sequence
1084 b,n perf_rdr_shift_in_U_leave
1088 sync ; RDR 4 read sequence
1093 b,n perf_rdr_shift_in_U_leave
1097 sync ; RDR 5 read sequence
1102 b,n perf_rdr_shift_in_U_leave
1106 sync ; RDR 6 read sequence
1111 b,n perf_rdr_shift_in_U_leave
1115 sync ; RDR 7 read sequence
1120 b,n perf_rdr_shift_in_U_leave
1124 b,n perf_rdr_shift_in_U_leave
1133 SFDIAG (9) ; RDR 9 read sequence
1136 shrpd ret0,%r0,%sar,%r1
1140 b,n perf_rdr_shift_in_U_leave
1142 SFDIAG (10) ; RDR 10 read sequence
1145 shrpd ret0,%r0,%sar,%r1
1149 b,n perf_rdr_shift_in_U_leave
1151 SFDIAG (11) ; RDR 11 read sequence
1154 shrpd ret0,%r0,%sar,%r1
1158 b,n perf_rdr_shift_in_U_leave
1160 SFDIAG (12) ; RDR 12 read sequence
1163 shrpd ret0,%r0,%sar,%r1
1167 b,n perf_rdr_shift_in_U_leave
1169 SFDIAG (13) ; RDR 13 read sequence
1172 shrpd ret0,%r0,%sar,%r1
1176 b,n perf_rdr_shift_in_U_leave
1178 SFDIAG (14) ; RDR 14 read sequence
1181 shrpd ret0,%r0,%sar,%r1
1185 b,n perf_rdr_shift_in_U_leave
1187 SFDIAG (15) ; RDR 15 read sequence
1190 shrpd ret0,%r0,%sar,%r1
1194 b,n perf_rdr_shift_in_U_leave
1196 sync ; RDR 16 read sequence
1201 b,n perf_rdr_shift_in_U_leave
1205 SFDIAG (17) ; RDR 17 read sequence
1208 shrpd ret0,%r0,%sar,%r1
1212 b,n perf_rdr_shift_in_U_leave
1214 SFDIAG (18) ; RDR 18 read sequence
1217 shrpd ret0,%r0,%sar,%r1
1221 b,n perf_rdr_shift_in_U_leave
1223 b,n perf_rdr_shift_in_U_leave
1232 sync ; RDR 20 read sequence
1237 b,n perf_rdr_shift_in_U_leave
1241 sync ; RDR 21 read sequence
1246 b,n perf_rdr_shift_in_U_leave
1250 sync ; RDR 22 read sequence
1255 b,n perf_rdr_shift_in_U_leave
1259 sync ; RDR 23 read sequence
1264 b,n perf_rdr_shift_in_U_leave
1268 sync ; RDR 24 read sequence
1273 b,n perf_rdr_shift_in_U_leave
1277 sync ; RDR 25 read sequence
1282 b,n perf_rdr_shift_in_U_leave
1286 SFDIAG (26) ; RDR 26 read sequence
1289 shrpd ret0,%r0,%sar,%r1
1293 b,n perf_rdr_shift_in_U_leave
1295 SFDIAG (27) ; RDR 27 read sequence
1298 shrpd ret0,%r0,%sar,%r1
1302 b,n perf_rdr_shift_in_U_leave
1304 sync ; RDR 28 read sequence
1309 b,n perf_rdr_shift_in_U_leave
1313 b,n perf_rdr_shift_in_U_leave
1322 SFDIAG (30) ; RDR 30 read sequence
1325 shrpd ret0,%r0,%sar,%r1
1329 b,n perf_rdr_shift_in_U_leave
1331 SFDIAG (31) ; RDR 31 read sequence
1334 shrpd ret0,%r0,%sar,%r1
1338 b,n perf_rdr_shift_in_U_leave
1341 perf_rdr_shift_in_U_leave:
1344 MTDIAG_2 (24) ; restore DR2
1347 ;***********************************************************************
1349 ;* Name: rdr_shift_out_U
1352 ;* This routine moves data to the RDR's. The double-word that
1353 ;* arg1 points to is loaded and moved into the staging register.
1354 ;* Then the STDIAG instruction for the RDR # in arg0 is called
1355 ;* to move the data to the RDR.
1358 ;* arg0 = rdr target
1359 ;* arg1 = buffer pointer
1365 ;* arg0 = rdr target
1366 ;* arg1 = buffer pointer
1367 ;* %r24 - DR2 | DR2_SLOW_RET
1368 ;* %r23 - original DR2 value
1370 ;***********************************************************************
1372 .export perf_rdr_shift_out_U,code
1373 perf_rdr_shift_out_U:
1375 .callinfo frame=0,NO_CALLS
1379 ; NOTE: The PCX-U ERS states that DR2_SLOW_RET must be set before any
1380 ; shifting is done, from or to, the remote diagnose registers.
1383 depdi,z 1,DR2_SLOW_RET,1,%r24
1386 MTDIAG_2 (24) ; set DR2_SLOW_RET
1388 MTDIAG_1 (25) ; data to the staging register
1389 shladd arg0,2,%r0,%r1 ; %r1 = 4 * RDR number
1390 blr %r1,%r0 ; branch to 8-instruction sequence
1394 ; 32-byte cachline aligned
1397 sync ; RDR 0 write sequence
1401 b,n perf_rdr_shift_out_U_leave
1406 sync ; RDR 1 write sequence
1410 b,n perf_rdr_shift_out_U_leave
1415 sync ; RDR 2 write sequence
1419 b,n perf_rdr_shift_out_U_leave
1424 sync ; RDR 3 write sequence
1428 b,n perf_rdr_shift_out_U_leave
1433 sync ; RDR 4 write sequence
1437 b,n perf_rdr_shift_out_U_leave
1442 sync ; RDR 5 write sequence
1446 b,n perf_rdr_shift_out_U_leave
1451 sync ; RDR 6 write sequence
1455 b,n perf_rdr_shift_out_U_leave
1460 sync ; RDR 7 write sequence
1464 b,n perf_rdr_shift_out_U_leave
1469 sync ; RDR 8 write sequence
1473 b,n perf_rdr_shift_out_U_leave
1478 sync ; RDR 9 write sequence
1482 b,n perf_rdr_shift_out_U_leave
1487 sync ; RDR 10 write sequence
1491 b,n perf_rdr_shift_out_U_leave
1496 sync ; RDR 11 write sequence
1500 b,n perf_rdr_shift_out_U_leave
1505 sync ; RDR 12 write sequence
1509 b,n perf_rdr_shift_out_U_leave
1514 sync ; RDR 13 write sequence
1518 b,n perf_rdr_shift_out_U_leave
1523 sync ; RDR 14 write sequence
1527 b,n perf_rdr_shift_out_U_leave
1532 sync ; RDR 15 write sequence
1536 b,n perf_rdr_shift_out_U_leave
1541 sync ; RDR 16 write sequence
1545 b,n perf_rdr_shift_out_U_leave
1550 sync ; RDR 17 write sequence
1554 b,n perf_rdr_shift_out_U_leave
1559 sync ; RDR 18 write sequence
1563 b,n perf_rdr_shift_out_U_leave
1568 sync ; RDR 19 write sequence
1572 b,n perf_rdr_shift_out_U_leave
1577 sync ; RDR 20 write sequence
1581 b,n perf_rdr_shift_out_U_leave
1586 sync ; RDR 21 write sequence
1590 b,n perf_rdr_shift_out_U_leave
1595 sync ; RDR 22 write sequence
1599 b,n perf_rdr_shift_out_U_leave
1604 sync ; RDR 23 write sequence
1608 b,n perf_rdr_shift_out_U_leave
1613 sync ; RDR 24 write sequence
1617 b,n perf_rdr_shift_out_U_leave
1622 sync ; RDR 25 write sequence
1626 b,n perf_rdr_shift_out_U_leave
1631 sync ; RDR 26 write sequence
1635 b,n perf_rdr_shift_out_U_leave
1640 sync ; RDR 27 write sequence
1644 b,n perf_rdr_shift_out_U_leave
1649 sync ; RDR 28 write sequence
1653 b,n perf_rdr_shift_out_U_leave
1658 sync ; RDR 29 write sequence
1662 b,n perf_rdr_shift_out_U_leave
1667 sync ; RDR 30 write sequence
1671 b,n perf_rdr_shift_out_U_leave
1676 sync ; RDR 31 write sequence
1680 b,n perf_rdr_shift_out_U_leave
1685 perf_rdr_shift_out_U_leave:
1688 MTDIAG_2 (23) ; restore DR2