2 * arch/powerpc/sysdev/uic.c
4 * IBM PowerPC 4xx Universal Interrupt Controller
6 * Copyright 2007 David Gibson <dwg@au1.ibm.com>, IBM Corporation.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/errno.h>
16 #include <linux/reboot.h>
17 #include <linux/slab.h>
18 #include <linux/stddef.h>
19 #include <linux/sched.h>
20 #include <linux/signal.h>
21 #include <linux/sysdev.h>
22 #include <linux/device.h>
23 #include <linux/bootmem.h>
24 #include <linux/spinlock.h>
25 #include <linux/irq.h>
26 #include <linux/interrupt.h>
32 #define NR_UIC_INTS 32
43 #define uic_irq_to_hw(virq) (irq_map[virq].hwirq)
45 struct uic *primary_uic;
53 /* The remapper for this UIC */
54 struct irq_host *irqhost;
56 /* For secondary UICs, the cascade interrupt's irqaction */
57 struct irqaction cascade;
59 /* The device node of the interrupt controller */
60 struct device_node *of_node;
63 static void uic_unmask_irq(unsigned int virq)
65 struct uic *uic = get_irq_chip_data(virq);
66 unsigned int src = uic_irq_to_hw(virq);
70 spin_lock_irqsave(&uic->lock, flags);
71 er = mfdcr(uic->dcrbase + UIC_ER);
72 er |= 1 << (31 - src);
73 mtdcr(uic->dcrbase + UIC_ER, er);
74 spin_unlock_irqrestore(&uic->lock, flags);
77 static void uic_mask_irq(unsigned int virq)
79 struct uic *uic = get_irq_chip_data(virq);
80 unsigned int src = uic_irq_to_hw(virq);
84 spin_lock_irqsave(&uic->lock, flags);
85 er = mfdcr(uic->dcrbase + UIC_ER);
86 er &= ~(1 << (31 - src));
87 mtdcr(uic->dcrbase + UIC_ER, er);
88 spin_unlock_irqrestore(&uic->lock, flags);
91 static void uic_ack_irq(unsigned int virq)
93 struct uic *uic = get_irq_chip_data(virq);
94 unsigned int src = uic_irq_to_hw(virq);
97 spin_lock_irqsave(&uic->lock, flags);
98 mtdcr(uic->dcrbase + UIC_SR, 1 << (31-src));
99 spin_unlock_irqrestore(&uic->lock, flags);
102 static int uic_set_irq_type(unsigned int virq, unsigned int flow_type)
104 struct uic *uic = get_irq_chip_data(virq);
105 unsigned int src = uic_irq_to_hw(virq);
106 struct irq_desc *desc = get_irq_desc(virq);
108 int trigger, polarity;
111 switch (flow_type & IRQ_TYPE_SENSE_MASK) {
116 case IRQ_TYPE_EDGE_RISING:
117 trigger = 1; polarity = 1;
119 case IRQ_TYPE_EDGE_FALLING:
120 trigger = 1; polarity = 0;
122 case IRQ_TYPE_LEVEL_HIGH:
123 trigger = 0; polarity = 1;
125 case IRQ_TYPE_LEVEL_LOW:
126 trigger = 0; polarity = 0;
132 mask = ~(1 << (31 - src));
134 spin_lock_irqsave(&uic->lock, flags);
135 tr = mfdcr(uic->dcrbase + UIC_TR);
136 pr = mfdcr(uic->dcrbase + UIC_PR);
137 tr = (tr & mask) | (trigger << (31-src));
138 pr = (pr & mask) | (polarity << (31-src));
140 mtdcr(uic->dcrbase + UIC_PR, pr);
141 mtdcr(uic->dcrbase + UIC_TR, tr);
143 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
144 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
146 desc->status |= IRQ_LEVEL;
148 spin_unlock_irqrestore(&uic->lock, flags);
153 static struct irq_chip uic_irq_chip = {
155 .unmask = uic_unmask_irq,
156 .mask = uic_mask_irq,
157 /* .mask_ack = uic_mask_irq_and_ack, */
159 .set_type = uic_set_irq_type,
162 static int uic_host_match(struct irq_host *h, struct device_node *node)
164 struct uic *uic = h->host_data;
165 return uic->of_node == node;
168 static int uic_host_map(struct irq_host *h, unsigned int virq,
171 struct uic *uic = h->host_data;
173 set_irq_chip_data(virq, uic);
174 /* Despite the name, handle_level_irq() works for both level
175 * and edge irqs on UIC. FIXME: check this is correct */
176 set_irq_chip_and_handler(virq, &uic_irq_chip, handle_level_irq);
178 /* Set default irq type */
179 set_irq_type(virq, IRQ_TYPE_NONE);
184 static int uic_host_xlate(struct irq_host *h, struct device_node *ct,
185 u32 *intspec, unsigned int intsize,
186 irq_hw_number_t *out_hwirq, unsigned int *out_type)
189 /* UIC intspecs must have 2 cells */
190 BUG_ON(intsize != 2);
191 *out_hwirq = intspec[0];
192 *out_type = intspec[1];
196 static struct irq_host_ops uic_host_ops = {
197 .match = uic_host_match,
199 .xlate = uic_host_xlate,
202 irqreturn_t uic_cascade(int virq, void *data)
204 struct uic *uic = data;
209 msr = mfdcr(uic->dcrbase + UIC_MSR);
212 subvirq = irq_linear_revmap(uic->irqhost, src);
213 generic_handle_irq(subvirq);
218 static struct uic * __init uic_init_one(struct device_node *node)
221 const u32 *indexp, *dcrreg;
224 BUG_ON(! of_device_is_compatible(node, "ibm,uic"));
226 uic = alloc_bootmem(sizeof(*uic));
228 return NULL; /* FIXME: panic? */
230 memset(uic, 0, sizeof(*uic));
231 spin_lock_init(&uic->lock);
232 uic->of_node = of_node_get(node);
233 indexp = of_get_property(node, "cell-index", &len);
234 if (!indexp || (len != sizeof(u32))) {
235 printk(KERN_ERR "uic: Device node %s has missing or invalid "
236 "cell-index property\n", node->full_name);
239 uic->index = *indexp;
241 dcrreg = of_get_property(node, "dcr-reg", &len);
242 if (!dcrreg || (len != 2*sizeof(u32))) {
243 printk(KERN_ERR "uic: Device node %s has missing or invalid "
244 "dcr-reg property\n", node->full_name);
247 uic->dcrbase = *dcrreg;
249 uic->irqhost = irq_alloc_host(IRQ_HOST_MAP_LINEAR, NR_UIC_INTS,
251 if (! uic->irqhost) {
253 return NULL; /* FIXME: panic? */
256 uic->irqhost->host_data = uic;
258 /* Start with all interrupts disabled, level and non-critical */
259 mtdcr(uic->dcrbase + UIC_ER, 0);
260 mtdcr(uic->dcrbase + UIC_CR, 0);
261 mtdcr(uic->dcrbase + UIC_TR, 0);
262 /* Clear any pending interrupts, in case the firmware left some */
263 mtdcr(uic->dcrbase + UIC_SR, 0xffffffff);
265 printk ("UIC%d (%d IRQ sources) at DCR 0x%x\n", uic->index,
266 NR_UIC_INTS, uic->dcrbase);
271 void __init uic_init_tree(void)
273 struct device_node *np;
275 const u32 *interrupts;
277 /* First locate and initialize the top-level UIC */
279 np = of_find_compatible_node(NULL, NULL, "ibm,uic");
281 interrupts = of_get_property(np, "interrupts", NULL);
285 np = of_find_compatible_node(np, NULL, "ibm,uic");
288 BUG_ON(!np); /* uic_init_tree() assumes there's a UIC as the
289 * top-level interrupt controller */
290 primary_uic = uic_init_one(np);
292 panic("Unable to initialize primary UIC %s\n", np->full_name);
294 irq_set_default_host(primary_uic->irqhost);
297 /* The scan again for cascaded UICs */
298 np = of_find_compatible_node(NULL, NULL, "ibm,uic");
300 interrupts = of_get_property(np, "interrupts", NULL);
306 uic = uic_init_one(np);
308 panic("Unable to initialize a secondary UIC %s\n",
311 cascade_virq = irq_of_parse_and_map(np, 0);
313 uic->cascade.handler = uic_cascade;
314 uic->cascade.name = "UIC cascade";
315 uic->cascade.dev_id = uic;
317 ret = setup_irq(cascade_virq, &uic->cascade);
319 printk(KERN_ERR "Failed to setup_irq(%d) for "
320 "UIC%d cascade\n", cascade_virq,
323 /* FIXME: setup critical cascade?? */
326 np = of_find_compatible_node(np, NULL, "ibm,uic");
330 /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
331 unsigned int uic_get_irq(void)
336 BUG_ON(! primary_uic);
338 msr = mfdcr(primary_uic->dcrbase + UIC_MSR);
341 return irq_linear_revmap(primary_uic->irqhost, src);