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   1 /*******************************************************************************
   2 *
   3 *      "swarm_cs4297a.c" --  Cirrus Logic-Crystal CS4297a linux audio driver.
   4 *
   5 *      Copyright (C) 2001  Broadcom Corporation.
   6 *      Copyright (C) 2000,2001  Cirrus Logic Corp.
   7 *            -- adapted from drivers by Thomas Sailer,
   8 *            -- but don't bug him; Problems should go to:
   9 *            -- tom woller (twoller@crystal.cirrus.com) or
  10 *               (audio@crystal.cirrus.com).
  11 *            -- adapted from cs4281 PCI driver for cs4297a on
  12 *               BCM1250 Synchronous Serial interface
  13 *               (Kip Walker, Broadcom Corp.)
  14 *      Copyright (C) 2004  Maciej W. Rozycki
  15 *      Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
  16 *
  17 *      This program is free software; you can redistribute it and/or modify
  18 *      it under the terms of the GNU General Public License as published by
  19 *      the Free Software Foundation; either version 2 of the License, or
  20 *      (at your option) any later version.
  21 *
  22 *      This program is distributed in the hope that it will be useful,
  23 *      but WITHOUT ANY WARRANTY; without even the implied warranty of
  24 *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25 *      GNU General Public License for more details.
  26 *
  27 *      You should have received a copy of the GNU General Public License
  28 *      along with this program; if not, write to the Free Software
  29 *      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  30 *
  31 * Module command line parameters:
  32 *   none
  33 *
  34 *  Supported devices:
  35 *  /dev/dsp    standard /dev/dsp device, (mostly) OSS compatible
  36 *  /dev/mixer  standard /dev/mixer device, (mostly) OSS compatible
  37 *  /dev/midi   simple MIDI UART interface, no ioctl
  38 *
  39 * Modification History
  40 * 08/20/00 trw - silence and no stopping DAC until release
  41 * 08/23/00 trw - added CS_DBG statements, fix interrupt hang issue on DAC stop.
  42 * 09/18/00 trw - added 16bit only record with conversion
  43 * 09/24/00 trw - added Enhanced Full duplex (separate simultaneous
  44 *                capture/playback rates)
  45 * 10/03/00 trw - fixed mmap (fixed GRECORD and the XMMS mmap test plugin
  46 *                libOSSm.so)
  47 * 10/11/00 trw - modified for 2.4.0-test9 kernel enhancements (NR_MAP removal)
  48 * 11/03/00 trw - fixed interrupt loss/stutter, added debug.
  49 * 11/10/00 bkz - added __devinit to cs4297a_hw_init()
  50 * 11/10/00 trw - fixed SMP and capture spinlock hang.
  51 * 12/04/00 trw - cleaned up CSDEBUG flags and added "defaultorder" moduleparm.
  52 * 12/05/00 trw - fixed polling (myth2), and added underrun swptr fix.
  53 * 12/08/00 trw - added PM support.
  54 * 12/14/00 trw - added wrapper code, builds under 2.4.0, 2.2.17-20, 2.2.17-8
  55 *                (RH/Dell base), 2.2.18, 2.2.12.  cleaned up code mods by ident.
  56 * 12/19/00 trw - added PM support for 2.2 base (apm_callback). other PM cleanup.
  57 * 12/21/00 trw - added fractional "defaultorder" inputs. if >100 then use
  58 *                defaultorder-100 as power of 2 for the buffer size. example:
  59 *                106 = 2^(106-100) = 2^6 = 64 bytes for the buffer size.
  60 *
  61 *******************************************************************************/
  62
  63 #include <linux/list.h>
  64 #include <linux/module.h>
  65 #include <linux/string.h>
  66 #include <linux/ioport.h>
  67 #include <linux/sched.h>
  68 #include <linux/delay.h>
  69 #include <linux/sound.h>
  70 #include <linux/slab.h>
  71 #include <linux/soundcard.h>
  72 #include <linux/ac97_codec.h>
  73 #include <linux/pci.h>
  74 #include <linux/bitops.h>
  75 #include <linux/interrupt.h>
  76 #include <linux/init.h>
  77 #include <linux/poll.h>
  78 #include <linux/smp_lock.h>
  79 #include <linux/mutex.h>
  80 #include <linux/kernel.h>
  81
  82 #include <asm/byteorder.h>
  83 #include <asm/dma.h>
  84 #include <asm/io.h>
  85 #include <asm/uaccess.h>
  86
  87 #include <asm/sibyte/sb1250_regs.h>
  88 #include <asm/sibyte/sb1250_int.h>
  89 #include <asm/sibyte/sb1250_dma.h>
  90 #include <asm/sibyte/sb1250_scd.h>
  91 #include <asm/sibyte/sb1250_syncser.h>
  92 #include <asm/sibyte/sb1250_mac.h>
  93 #include <asm/sibyte/sb1250.h>
  94
  95 struct cs4297a_state;
  96
  97 static void stop_dac(struct cs4297a_state *s);
  98 static void stop_adc(struct cs4297a_state *s);
  99 static void start_dac(struct cs4297a_state *s);
 100 static void start_adc(struct cs4297a_state *s);
 101 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
 102
 103 // ---------------------------------------------------------------------
 104
 105 #define CS4297a_MAGIC           0xf00beef1
 106
 107 // buffer order determines the size of the dma buffer for the driver.
 108 // under Linux, a smaller buffer allows more responsiveness from many of the
 109 // applications (e.g. games).  A larger buffer allows some of the apps (esound)
 110 // to not underrun the dma buffer as easily.  As default, use 32k (order=3)
 111 // rather than 64k as some of the games work more responsively.
 112 // log base 2( buff sz = 32k).
 113
 114 //static unsigned long defaultorder = 3;
 115 //MODULE_PARM(defaultorder, "i");
 116
 117 //
 118 // Turn on/off debugging compilation by commenting out "#define CSDEBUG"
 119 //
 120 #define CSDEBUG 0
 121 #if CSDEBUG
 122 #define CSDEBUG_INTERFACE 1
 123 #else
 124 #undef CSDEBUG_INTERFACE
 125 #endif
 126 //
 127 // cs_debugmask areas
 128 //
 129 #define CS_INIT         0x00000001      // initialization and probe functions
 130 #define CS_ERROR        0x00000002      // tmp debugging bit placeholder
 131 #define CS_INTERRUPT    0x00000004      // interrupt handler (separate from all other)
 132 #define CS_FUNCTION     0x00000008      // enter/leave functions
 133 #define CS_WAVE_WRITE   0x00000010      // write information for wave
 134 #define CS_WAVE_READ    0x00000020      // read information for wave
 135 #define CS_AC97         0x00000040      // AC97 register access
 136 #define CS_DESCR        0x00000080      // descriptor management
 137 #define CS_OPEN         0x00000400      // all open functions in the driver
 138 #define CS_RELEASE      0x00000800      // all release functions in the driver
 139 #define CS_PARMS        0x00001000      // functional and operational parameters
 140 #define CS_IOCTL        0x00002000      // ioctl (non-mixer)
 141 #define CS_TMP          0x10000000      // tmp debug mask bit
 142
 143 //
 144 // CSDEBUG is usual mode is set to 1, then use the
 145 // cs_debuglevel and cs_debugmask to turn on or off debugging.
 146 // Debug level of 1 has been defined to be kernel errors and info
 147 // that should be printed on any released driver.
 148 //
 149 #if CSDEBUG
 150 #define CS_DBGOUT(mask,level,x) if((cs_debuglevel >= (level)) && ((mask) & cs_debugmask) ) {x;}
 151 #else
 152 #define CS_DBGOUT(mask,level,x)
 153 #endif
 154
 155 #if CSDEBUG
 156 static unsigned long cs_debuglevel = 4; // levels range from 1-9
 157 static unsigned long cs_debugmask = CS_INIT /*| CS_IOCTL*/;
 158 module_param(cs_debuglevel, int, 0);
 159 module_param(cs_debugmask, int, 0);
 160 #endif
 161 #define CS_TRUE         1
 162 #define CS_FALSE        0
 163
 164 #define CS_TYPE_ADC 0
 165 #define CS_TYPE_DAC 1
 166
 167 #define SER_BASE    (A_SER_BASE_1 + KSEG1)
 168 #define SS_CSR(t)   (SER_BASE+t)
 169 #define SS_TXTBL(t) (SER_BASE+R_SER_TX_TABLE_BASE+(t*8))
 170 #define SS_RXTBL(t) (SER_BASE+R_SER_RX_TABLE_BASE+(t*8))
 171
 172 #define FRAME_BYTES            32
 173 #define FRAME_SAMPLE_BYTES      4
 174
 175 /* Should this be variable? */
 176 #define SAMPLE_BUF_SIZE        (16*1024)
 177 #define SAMPLE_FRAME_COUNT     (SAMPLE_BUF_SIZE / FRAME_SAMPLE_BYTES)
 178 /* The driver can explode/shrink the frames to/from a smaller sample
 179    buffer */
 180 #define DMA_BLOAT_FACTOR       1
 181 #define DMA_DESCR              (SAMPLE_FRAME_COUNT / DMA_BLOAT_FACTOR)
 182 #define DMA_BUF_SIZE           (DMA_DESCR * FRAME_BYTES)
 183
 184 /* Use the maxmium count (255 == 5.1 ms between interrupts) */
 185 #define DMA_INT_CNT            ((1 << S_DMA_INT_PKTCNT) - 1)
 186
 187 /* Figure this out: how many TX DMAs ahead to schedule a reg access */
 188 #define REG_LATENCY            150
 189
 190 #define FRAME_TX_US             20
 191
 192 #define SERDMA_NEXTBUF(d,f) (((d)->f+1) % (d)->ringsz)
 193
 194 static const char invalid_magic[] =
 195     KERN_CRIT "cs4297a: invalid magic value\n";
 196
 197 #define VALIDATE_STATE(s)                          \
 198 ({                                                 \
 199         if (!(s) || (s)->magic != CS4297a_MAGIC) { \
 200                 printk(invalid_magic);             \
 201                 return -ENXIO;                     \
 202         }                                          \
 203 })
 204
 205 struct list_head cs4297a_devs = { &cs4297a_devs, &cs4297a_devs };
 206
 207 typedef struct serdma_descr_s {
 208         u64 descr_a;
 209         u64 descr_b;
 210 } serdma_descr_t;
 211
 212 typedef unsigned long paddr_t;
 213
 214 typedef struct serdma_s {
 215         unsigned         ringsz;
 216         serdma_descr_t  *descrtab;
 217         serdma_descr_t  *descrtab_end;
 218         paddr_t          descrtab_phys;
 219
 220         serdma_descr_t  *descr_add;
 221         serdma_descr_t  *descr_rem;
 222
 223         u64  *dma_buf;           // buffer for DMA contents (frames)
 224         paddr_t          dma_buf_phys;
 225         u16  *sample_buf;               // tmp buffer for sample conversions
 226         u16  *sb_swptr;
 227         u16  *sb_hwptr;
 228         u16  *sb_end;
 229
 230         dma_addr_t dmaaddr;
 231 //        unsigned buforder;    // Log base 2 of 'dma_buf' size in bytes..
 232         unsigned numfrag;       // # of 'fragments' in the buffer.
 233         unsigned fragshift;     // Log base 2 of fragment size.
 234         unsigned hwptr, swptr;
 235         unsigned total_bytes;   // # bytes process since open.
 236         unsigned blocks;        // last returned blocks value GETOPTR
 237         unsigned wakeup;        // interrupt occurred on block
 238         int count;
 239         unsigned underrun;      // underrun flag
 240         unsigned error; // over/underrun
 241         wait_queue_head_t wait;
 242         wait_queue_head_t reg_wait;
 243         // redundant, but makes calculations easier
 244         unsigned fragsize;      // 2**fragshift..
 245         unsigned sbufsz;        // 2**buforder.
 246         unsigned fragsamples;
 247         // OSS stuff
 248         unsigned mapped:1;      // Buffer mapped in cs4297a_mmap()?
 249         unsigned ready:1;       // prog_dmabuf_dac()/adc() successful?
 250         unsigned endcleared:1;
 251         unsigned type:1;        // adc or dac buffer (CS_TYPE_XXX)
 252         unsigned ossfragshift;
 253         int ossmaxfrags;
 254         unsigned subdivision;
 255 } serdma_t;
 256
 257 struct cs4297a_state {
 258         // magic
 259         unsigned int magic;
 260
 261         struct list_head list;
 262
 263         // soundcore stuff
 264         int dev_audio;
 265         int dev_mixer;
 266
 267         // hardware resources
 268         unsigned int irq;
 269
 270         struct {
 271                 unsigned int rx_ovrrn; /* FIFO */
 272                 unsigned int rx_overflow; /* staging buffer */
 273                 unsigned int tx_underrun;
 274                 unsigned int rx_bad;
 275                 unsigned int rx_good;
 276         } stats;
 277
 278         // mixer registers
 279         struct {
 280                 unsigned short vol[10];
 281                 unsigned int recsrc;
 282                 unsigned int modcnt;
 283                 unsigned short micpreamp;
 284         } mix;
 285
 286         // wave stuff
 287         struct properties {
 288                 unsigned fmt;
 289                 unsigned fmt_original;  // original requested format
 290                 unsigned channels;
 291                 unsigned rate;
 292         } prop_dac, prop_adc;
 293         unsigned conversion:1;  // conversion from 16 to 8 bit in progress
 294         unsigned ena;
 295         spinlock_t lock;
 296         struct mutex open_mutex;
 297         struct mutex open_sem_adc;
 298         struct mutex open_sem_dac;
 299         mode_t open_mode;
 300         wait_queue_head_t open_wait;
 301         wait_queue_head_t open_wait_adc;
 302         wait_queue_head_t open_wait_dac;
 303
 304         dma_addr_t dmaaddr_sample_buf;
 305         unsigned buforder_sample_buf;   // Log base 2 of 'dma_buf' size in bytes..
 306
 307         serdma_t dma_dac, dma_adc;
 308
 309         volatile u16 read_value;
 310         volatile u16 read_reg;
 311         volatile u64 reg_request;
 312 };
 313
 314 #if 1
 315 #define prog_codec(a,b)
 316 #define dealloc_dmabuf(a,b);
 317 #endif
 318
 319 static int prog_dmabuf_adc(struct cs4297a_state *s)
 320 {
 321         s->dma_adc.ready = 1;
 322         return 0;
 323 }
 324
 325
 326 static int prog_dmabuf_dac(struct cs4297a_state *s)
 327 {
 328         s->dma_dac.ready = 1;
 329         return 0;
 330 }
 331
 332 static void clear_advance(void *buf, unsigned bsize, unsigned bptr,
 333                           unsigned len, unsigned char c)
 334 {
 335         if (bptr + len > bsize) {
 336                 unsigned x = bsize - bptr;
 337                 memset(((char *) buf) + bptr, c, x);
 338                 bptr = 0;
 339                 len -= x;
 340         }
 341         CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO
 342                 "cs4297a: clear_advance(): memset %d at 0x%.8x for %d size \n",
 343                         (unsigned)c, (unsigned)((char *) buf) + bptr, len));
 344         memset(((char *) buf) + bptr, c, len);
 345 }
 346
 347 #if CSDEBUG
 348
 349 // DEBUG ROUTINES
 350
 351 #define SOUND_MIXER_CS_GETDBGLEVEL      _SIOWR('M',120, int)
 352 #define SOUND_MIXER_CS_SETDBGLEVEL      _SIOWR('M',121, int)
 353 #define SOUND_MIXER_CS_GETDBGMASK       _SIOWR('M',122, int)
 354 #define SOUND_MIXER_CS_SETDBGMASK       _SIOWR('M',123, int)
 355
 356 static void cs_printioctl(unsigned int x)
 357 {
 358         unsigned int i;
 359         unsigned char vidx;
 360         // Index of mixtable1[] member is Device ID
 361         // and must be <= SOUND_MIXER_NRDEVICES.
 362         // Value of array member is index into s->mix.vol[]
 363         static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
 364                 [SOUND_MIXER_PCM] = 1,  // voice
 365                 [SOUND_MIXER_LINE1] = 2,        // AUX
 366                 [SOUND_MIXER_CD] = 3,   // CD
 367                 [SOUND_MIXER_LINE] = 4, // Line
 368                 [SOUND_MIXER_SYNTH] = 5,        // FM
 369                 [SOUND_MIXER_MIC] = 6,  // Mic
 370                 [SOUND_MIXER_SPEAKER] = 7,      // Speaker
 371                 [SOUND_MIXER_RECLEV] = 8,       // Recording level
 372                 [SOUND_MIXER_VOLUME] = 9        // Master Volume
 373         };
 374
 375         switch (x) {
 376         case SOUND_MIXER_CS_GETDBGMASK:
 377                 CS_DBGOUT(CS_IOCTL, 4,
 378                           printk("SOUND_MIXER_CS_GETDBGMASK:\n"));
 379                 break;
 380         case SOUND_MIXER_CS_GETDBGLEVEL:
 381                 CS_DBGOUT(CS_IOCTL, 4,
 382                           printk("SOUND_MIXER_CS_GETDBGLEVEL:\n"));
 383                 break;
 384         case SOUND_MIXER_CS_SETDBGMASK:
 385                 CS_DBGOUT(CS_IOCTL, 4,
 386                           printk("SOUND_MIXER_CS_SETDBGMASK:\n"));
 387                 break;
 388         case SOUND_MIXER_CS_SETDBGLEVEL:
 389                 CS_DBGOUT(CS_IOCTL, 4,
 390                           printk("SOUND_MIXER_CS_SETDBGLEVEL:\n"));
 391                 break;
 392         case OSS_GETVERSION:
 393                 CS_DBGOUT(CS_IOCTL, 4, printk("OSS_GETVERSION:\n"));
 394                 break;
 395         case SNDCTL_DSP_SYNC:
 396                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SYNC:\n"));
 397                 break;
 398         case SNDCTL_DSP_SETDUPLEX:
 399                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETDUPLEX:\n"));
 400                 break;
 401         case SNDCTL_DSP_GETCAPS:
 402                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETCAPS:\n"));
 403                 break;
 404         case SNDCTL_DSP_RESET:
 405                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_RESET:\n"));
 406                 break;
 407         case SNDCTL_DSP_SPEED:
 408                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SPEED:\n"));
 409                 break;
 410         case SNDCTL_DSP_STEREO:
 411                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_STEREO:\n"));
 412                 break;
 413         case SNDCTL_DSP_CHANNELS:
 414                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_CHANNELS:\n"));
 415                 break;
 416         case SNDCTL_DSP_GETFMTS:
 417                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETFMTS:\n"));
 418                 break;
 419         case SNDCTL_DSP_SETFMT:
 420                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETFMT:\n"));
 421                 break;
 422         case SNDCTL_DSP_POST:
 423                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_POST:\n"));
 424                 break;
 425         case SNDCTL_DSP_GETTRIGGER:
 426                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETTRIGGER:\n"));
 427                 break;
 428         case SNDCTL_DSP_SETTRIGGER:
 429                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETTRIGGER:\n"));
 430                 break;
 431         case SNDCTL_DSP_GETOSPACE:
 432                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOSPACE:\n"));
 433                 break;
 434         case SNDCTL_DSP_GETISPACE:
 435                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETISPACE:\n"));
 436                 break;
 437         case SNDCTL_DSP_NONBLOCK:
 438                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_NONBLOCK:\n"));
 439                 break;
 440         case SNDCTL_DSP_GETODELAY:
 441                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETODELAY:\n"));
 442                 break;
 443         case SNDCTL_DSP_GETIPTR:
 444                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETIPTR:\n"));
 445                 break;
 446         case SNDCTL_DSP_GETOPTR:
 447                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOPTR:\n"));
 448                 break;
 449         case SNDCTL_DSP_GETBLKSIZE:
 450                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETBLKSIZE:\n"));
 451                 break;
 452         case SNDCTL_DSP_SETFRAGMENT:
 453                 CS_DBGOUT(CS_IOCTL, 4,
 454                           printk("SNDCTL_DSP_SETFRAGMENT:\n"));
 455                 break;
 456         case SNDCTL_DSP_SUBDIVIDE:
 457                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SUBDIVIDE:\n"));
 458                 break;
 459         case SOUND_PCM_READ_RATE:
 460                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_RATE:\n"));
 461                 break;
 462         case SOUND_PCM_READ_CHANNELS:
 463                 CS_DBGOUT(CS_IOCTL, 4,
 464                           printk("SOUND_PCM_READ_CHANNELS:\n"));
 465                 break;
 466         case SOUND_PCM_READ_BITS:
 467                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_BITS:\n"));
 468                 break;
 469         case SOUND_PCM_WRITE_FILTER:
 470                 CS_DBGOUT(CS_IOCTL, 4,
 471                           printk("SOUND_PCM_WRITE_FILTER:\n"));
 472                 break;
 473         case SNDCTL_DSP_SETSYNCRO:
 474                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETSYNCRO:\n"));
 475                 break;
 476         case SOUND_PCM_READ_FILTER:
 477                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_FILTER:\n"));
 478                 break;
 479         case SOUND_MIXER_PRIVATE1:
 480                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE1:\n"));
 481                 break;
 482         case SOUND_MIXER_PRIVATE2:
 483                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE2:\n"));
 484                 break;
 485         case SOUND_MIXER_PRIVATE3:
 486                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE3:\n"));
 487                 break;
 488         case SOUND_MIXER_PRIVATE4:
 489                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE4:\n"));
 490                 break;
 491         case SOUND_MIXER_PRIVATE5:
 492                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE5:\n"));
 493                 break;
 494         case SOUND_MIXER_INFO:
 495                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_INFO:\n"));
 496                 break;
 497         case SOUND_OLD_MIXER_INFO:
 498                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_OLD_MIXER_INFO:\n"));
 499                 break;
 500
 501         default:
 502                 switch (_IOC_NR(x)) {
 503                 case SOUND_MIXER_VOLUME:
 504                         CS_DBGOUT(CS_IOCTL, 4,
 505                                   printk("SOUND_MIXER_VOLUME:\n"));
 506                         break;
 507                 case SOUND_MIXER_SPEAKER:
 508                         CS_DBGOUT(CS_IOCTL, 4,
 509                                   printk("SOUND_MIXER_SPEAKER:\n"));
 510                         break;
 511                 case SOUND_MIXER_RECLEV:
 512                         CS_DBGOUT(CS_IOCTL, 4,
 513                                   printk("SOUND_MIXER_RECLEV:\n"));
 514                         break;
 515                 case SOUND_MIXER_MIC:
 516                         CS_DBGOUT(CS_IOCTL, 4,
 517                                   printk("SOUND_MIXER_MIC:\n"));
 518                         break;
 519                 case SOUND_MIXER_SYNTH:
 520                         CS_DBGOUT(CS_IOCTL, 4,
 521                                   printk("SOUND_MIXER_SYNTH:\n"));
 522                         break;
 523                 case SOUND_MIXER_RECSRC:
 524                         CS_DBGOUT(CS_IOCTL, 4,
 525                                   printk("SOUND_MIXER_RECSRC:\n"));
 526                         break;
 527                 case SOUND_MIXER_DEVMASK:
 528                         CS_DBGOUT(CS_IOCTL, 4,
 529                                   printk("SOUND_MIXER_DEVMASK:\n"));
 530                         break;
 531                 case SOUND_MIXER_RECMASK:
 532                         CS_DBGOUT(CS_IOCTL, 4,
 533                                   printk("SOUND_MIXER_RECMASK:\n"));
 534                         break;
 535                 case SOUND_MIXER_STEREODEVS:
 536                         CS_DBGOUT(CS_IOCTL, 4,
 537                                   printk("SOUND_MIXER_STEREODEVS:\n"));
 538                         break;
 539                 case SOUND_MIXER_CAPS:
 540                         CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_CAPS:\n"));
 541                         break;
 542                 default:
 543                         i = _IOC_NR(x);
 544                         if (i >= SOUND_MIXER_NRDEVICES
 545                             || !(vidx = mixtable1[i])) {
 546                                 CS_DBGOUT(CS_IOCTL, 4, printk
 547                                         ("UNKNOWN IOCTL: 0x%.8x NR=%d\n",
 548                                                 x, i));
 549                         } else {
 550                                 CS_DBGOUT(CS_IOCTL, 4, printk
 551                                         ("SOUND_MIXER_IOCTL AC9x: 0x%.8x NR=%d\n",
 552                                                 x, i));
 553                         }
 554                         break;
 555                 }
 556         }
 557 }
 558 #endif
 559
 560
 561 static int ser_init(struct cs4297a_state *s)
 562 {
 563         int i;
 564
 565         CS_DBGOUT(CS_INIT, 2,
 566                   printk(KERN_INFO "cs4297a: Setting up serial parameters\n"));
 567
 568         __raw_writeq(M_SYNCSER_CMD_RX_RESET | M_SYNCSER_CMD_TX_RESET, SS_CSR(R_SER_CMD));
 569
 570         __raw_writeq(M_SYNCSER_MSB_FIRST, SS_CSR(R_SER_MODE));
 571         __raw_writeq(32, SS_CSR(R_SER_MINFRM_SZ));
 572         __raw_writeq(32, SS_CSR(R_SER_MAXFRM_SZ));
 573
 574         __raw_writeq(1, SS_CSR(R_SER_TX_RD_THRSH));
 575         __raw_writeq(4, SS_CSR(R_SER_TX_WR_THRSH));
 576         __raw_writeq(8, SS_CSR(R_SER_RX_RD_THRSH));
 577
 578         /* This looks good from experimentation */
 579         __raw_writeq((M_SYNCSER_TXSYNC_INT | V_SYNCSER_TXSYNC_DLY(0) | M_SYNCSER_TXCLK_EXT |
 580                M_SYNCSER_RXSYNC_INT | V_SYNCSER_RXSYNC_DLY(1) | M_SYNCSER_RXCLK_EXT | M_SYNCSER_RXSYNC_EDGE),
 581               SS_CSR(R_SER_LINE_MODE));
 582
 583         /* This looks good from experimentation */
 584         __raw_writeq(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE,
 585               SS_TXTBL(0));
 586         __raw_writeq(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
 587               SS_TXTBL(1));
 588         __raw_writeq(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
 589               SS_TXTBL(2));
 590         __raw_writeq(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE |
 591               M_SYNCSER_SEQ_STROBE | M_SYNCSER_SEQ_LAST, SS_TXTBL(3));
 592
 593         __raw_writeq(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE,
 594               SS_RXTBL(0));
 595         __raw_writeq(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
 596               SS_RXTBL(1));
 597         __raw_writeq(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
 598               SS_RXTBL(2));
 599         __raw_writeq(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE |
 600               M_SYNCSER_SEQ_LAST, SS_RXTBL(3));
 601
 602         for (i=4; i<16; i++) {
 603                 /* Just in case... */
 604                 __raw_writeq(M_SYNCSER_SEQ_LAST, SS_TXTBL(i));
 605                 __raw_writeq(M_SYNCSER_SEQ_LAST, SS_RXTBL(i));
 606         }
 607
 608         return 0;
 609 }
 610
 611 static int init_serdma(serdma_t *dma)
 612 {
 613         CS_DBGOUT(CS_INIT, 2,
 614                   printk(KERN_ERR "cs4297a: desc - %d sbufsize - %d dbufsize - %d\n",
 615                          DMA_DESCR, SAMPLE_BUF_SIZE, DMA_BUF_SIZE));
 616
 617         /* Descriptors */
 618         dma->ringsz = DMA_DESCR;
 619         dma->descrtab = kzalloc(dma->ringsz * sizeof(serdma_descr_t), GFP_KERNEL);
 620         if (!dma->descrtab) {
 621                 printk(KERN_ERR "cs4297a: kzalloc descrtab failed\n");
 622                 return -1;
 623         }
 624         dma->descrtab_end = dma->descrtab + dma->ringsz;
 625         /* XXX bloddy mess, use proper DMA API here ...  */
 626         dma->descrtab_phys = CPHYSADDR((long)dma->descrtab);
 627         dma->descr_add = dma->descr_rem = dma->descrtab;
 628
 629         /* Frame buffer area */
 630         dma->dma_buf = kzalloc(DMA_BUF_SIZE, GFP_KERNEL);
 631         if (!dma->dma_buf) {
 632                 printk(KERN_ERR "cs4297a: kzalloc dma_buf failed\n");
 633                 kfree(dma->descrtab);
 634                 return -1;
 635         }
 636         dma->dma_buf_phys = CPHYSADDR((long)dma->dma_buf);
 637
 638         /* Samples buffer area */
 639         dma->sbufsz = SAMPLE_BUF_SIZE;
 640         dma->sample_buf = kmalloc(dma->sbufsz, GFP_KERNEL);
 641         if (!dma->sample_buf) {
 642                 printk(KERN_ERR "cs4297a: kmalloc sample_buf failed\n");
 643                 kfree(dma->descrtab);
 644                 kfree(dma->dma_buf);
 645                 return -1;
 646         }
 647         dma->sb_swptr = dma->sb_hwptr = dma->sample_buf;
 648         dma->sb_end = (u16 *)((void *)dma->sample_buf + dma->sbufsz);
 649         dma->fragsize = dma->sbufsz >> 1;
 650
 651         CS_DBGOUT(CS_INIT, 4,
 652                   printk(KERN_ERR "cs4297a: descrtab - %08x dma_buf - %x sample_buf - %x\n",
 653                          (int)dma->descrtab, (int)dma->dma_buf,
 654                          (int)dma->sample_buf));
 655
 656         return 0;
 657 }
 658
 659 static int dma_init(struct cs4297a_state *s)
 660 {
 661         int i;
 662
 663         CS_DBGOUT(CS_INIT, 2,
 664                   printk(KERN_INFO "cs4297a: Setting up DMA\n"));
 665
 666         if (init_serdma(&s->dma_adc) ||
 667             init_serdma(&s->dma_dac))
 668                 return -1;
 669
 670         if (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_RX))||
 671             __raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) {
 672                 panic("DMA state corrupted?!");
 673         }
 674
 675         /* Initialize now - the descr/buffer pairings will never
 676            change... */
 677         for (i=0; i<DMA_DESCR; i++) {
 678                 s->dma_dac.descrtab[i].descr_a = M_DMA_SERRX_SOP | V_DMA_DSCRA_A_SIZE(1) |
 679                         (s->dma_dac.dma_buf_phys + i*FRAME_BYTES);
 680                 s->dma_dac.descrtab[i].descr_b = V_DMA_DSCRB_PKT_SIZE(FRAME_BYTES);
 681                 s->dma_adc.descrtab[i].descr_a = V_DMA_DSCRA_A_SIZE(1) |
 682                         (s->dma_adc.dma_buf_phys + i*FRAME_BYTES);
 683                 s->dma_adc.descrtab[i].descr_b = 0;
 684         }
 685
 686         __raw_writeq((M_DMA_EOP_INT_EN | V_DMA_INT_PKTCNT(DMA_INT_CNT) |
 687                V_DMA_RINGSZ(DMA_DESCR) | M_DMA_TDX_EN),
 688               SS_CSR(R_SER_DMA_CONFIG0_RX));
 689         __raw_writeq(M_DMA_L2CA, SS_CSR(R_SER_DMA_CONFIG1_RX));
 690         __raw_writeq(s->dma_adc.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_RX));
 691
 692         __raw_writeq(V_DMA_RINGSZ(DMA_DESCR), SS_CSR(R_SER_DMA_CONFIG0_TX));
 693         __raw_writeq(M_DMA_L2CA | M_DMA_NO_DSCR_UPDT, SS_CSR(R_SER_DMA_CONFIG1_TX));
 694         __raw_writeq(s->dma_dac.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_TX));
 695
 696         /* Prep the receive DMA descriptor ring */
 697         __raw_writeq(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
 698
 699         __raw_writeq(M_SYNCSER_DMA_RX_EN | M_SYNCSER_DMA_TX_EN, SS_CSR(R_SER_DMA_ENABLE));
 700
 701         __raw_writeq((M_SYNCSER_RX_SYNC_ERR | M_SYNCSER_RX_OVERRUN | M_SYNCSER_RX_EOP_COUNT),
 702               SS_CSR(R_SER_INT_MASK));
 703
 704         /* Enable the rx/tx; let the codec warm up to the sync and
 705            start sending good frames before the receive FIFO is
 706            enabled */
 707         __raw_writeq(M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD));
 708         udelay(1000);
 709         __raw_writeq(M_SYNCSER_CMD_RX_EN | M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD));
 710
 711         /* XXXKW is this magic? (the "1" part) */
 712         while ((__raw_readq(SS_CSR(R_SER_STATUS)) & 0xf1) != 1)
 713                 ;
 714
 715         CS_DBGOUT(CS_INIT, 4,
 716                   printk(KERN_INFO "cs4297a: status: %08x\n",
 717                          (unsigned int)(__raw_readq(SS_CSR(R_SER_STATUS)) & 0xffffffff)));
 718
 719         return 0;
 720 }
 721
 722 static int serdma_reg_access(struct cs4297a_state *s, u64 data)
 723 {
 724         serdma_t *d = &s->dma_dac;
 725         u64 *data_p;
 726         unsigned swptr;
 727         unsigned long flags;
 728         serdma_descr_t *descr;
 729
 730         if (s->reg_request) {
 731                 printk(KERN_ERR "cs4297a: attempt to issue multiple reg_access\n");
 732                 return -1;
 733         }
 734
 735         if (s->ena & FMODE_WRITE) {
 736                 /* Since a writer has the DSP open, we have to mux the
 737                    request in */
 738                 s->reg_request = data;
 739                 interruptible_sleep_on(&s->dma_dac.reg_wait);
 740                 /* XXXKW how can I deal with the starvation case where
 741                    the opener isn't writing? */
 742         } else {
 743                 /* Be safe when changing ring pointers */
 744                 spin_lock_irqsave(&s->lock, flags);
 745                 if (d->hwptr != d->swptr) {
 746                         printk(KERN_ERR "cs4297a: reg access found bookkeeping error (hw/sw = %d/%d\n",
 747                                d->hwptr, d->swptr);
 748                         spin_unlock_irqrestore(&s->lock, flags);
 749                         return -1;
 750                 }
 751                 swptr = d->swptr;
 752                 d->hwptr = d->swptr = (d->swptr + 1) % d->ringsz;
 753                 spin_unlock_irqrestore(&s->lock, flags);
 754
 755                 descr = &d->descrtab[swptr];
 756                 data_p = &d->dma_buf[swptr * 4];
 757                 *data_p = cpu_to_be64(data);
 758                 __raw_writeq(1, SS_CSR(R_SER_DMA_DSCR_COUNT_TX));
 759                 CS_DBGOUT(CS_DESCR, 4,
 760                           printk(KERN_INFO "cs4297a: add_tx  %p (%x -> %x)\n",
 761                                  data_p, swptr, d->hwptr));
 762         }
 763
 764         CS_DBGOUT(CS_FUNCTION, 6,
 765                   printk(KERN_INFO "cs4297a: serdma_reg_access()-\n"));
 766
 767         return 0;
 768 }
 769
 770 //****************************************************************************
 771 // "cs4297a_read_ac97" -- Reads an AC97 register
 772 //****************************************************************************
 773 static int cs4297a_read_ac97(struct cs4297a_state *s, u32 offset,
 774                             u32 * value)
 775 {
 776         CS_DBGOUT(CS_AC97, 1,
 777                   printk(KERN_INFO "cs4297a: read reg %2x\n", offset));
 778         if (serdma_reg_access(s, (0xCLL << 60) | (1LL << 47) | ((u64)(offset & 0x7F) << 40)))
 779                 return -1;
 780
 781         interruptible_sleep_on(&s->dma_adc.reg_wait);
 782         *value = s->read_value;
 783         CS_DBGOUT(CS_AC97, 2,
 784                   printk(KERN_INFO "cs4297a: rdr reg %x -> %x\n", s->read_reg, s->read_value));
 785
 786         return 0;
 787 }
 788
 789
 790 //****************************************************************************
 791 // "cs4297a_write_ac97()"-- writes an AC97 register
 792 //****************************************************************************
 793 static int cs4297a_write_ac97(struct cs4297a_state *s, u32 offset,
 794                              u32 value)
 795 {
 796         CS_DBGOUT(CS_AC97, 1,
 797                   printk(KERN_INFO "cs4297a: write reg %2x -> %04x\n", offset, value));
 798         return (serdma_reg_access(s, (0xELL << 60) | ((u64)(offset & 0x7F) << 40) | ((value & 0xffff) << 12)));
 799 }
 800
 801 static void stop_dac(struct cs4297a_state *s)
 802 {
 803         unsigned long flags;
 804
 805         CS_DBGOUT(CS_WAVE_WRITE, 3, printk(KERN_INFO "cs4297a: stop_dac():\n"));
 806         spin_lock_irqsave(&s->lock, flags);
 807         s->ena &= ~FMODE_WRITE;
 808 #if 0
 809         /* XXXKW what do I really want here?  My theory for now is
 810            that I just flip the "ena" bit, and the interrupt handler
 811            will stop processing the xmit channel */
 812         __raw_writeq((s->ena & FMODE_READ) ? M_SYNCSER_DMA_RX_EN : 0,
 813               SS_CSR(R_SER_DMA_ENABLE));
 814 #endif
 815
 816         spin_unlock_irqrestore(&s->lock, flags);
 817 }
 818
 819
 820 static void start_dac(struct cs4297a_state *s)
 821 {
 822         unsigned long flags;
 823
 824         CS_DBGOUT(CS_FUNCTION, 3, printk(KERN_INFO "cs4297a: start_dac()+\n"));
 825         spin_lock_irqsave(&s->lock, flags);
 826         if (!(s->ena & FMODE_WRITE) && (s->dma_dac.mapped ||
 827                                         (s->dma_dac.count > 0
 828                                         && s->dma_dac.ready))) {
 829                 s->ena |= FMODE_WRITE;
 830                 /* XXXKW what do I really want here?  My theory for
 831                    now is that I just flip the "ena" bit, and the
 832                    interrupt handler will start processing the xmit
 833                    channel */
 834
 835                 CS_DBGOUT(CS_WAVE_WRITE | CS_PARMS, 8, printk(KERN_INFO
 836                         "cs4297a: start_dac(): start dma\n"));
 837
 838         }
 839         spin_unlock_irqrestore(&s->lock, flags);
 840         CS_DBGOUT(CS_FUNCTION, 3,
 841                   printk(KERN_INFO "cs4297a: start_dac()-\n"));
 842 }
 843
 844
 845 static void stop_adc(struct cs4297a_state *s)
 846 {
 847         unsigned long flags;
 848
 849         CS_DBGOUT(CS_FUNCTION, 3,
 850                   printk(KERN_INFO "cs4297a: stop_adc()+\n"));
 851
 852         spin_lock_irqsave(&s->lock, flags);
 853         s->ena &= ~FMODE_READ;
 854
 855         if (s->conversion == 1) {
 856                 s->conversion = 0;
 857                 s->prop_adc.fmt = s->prop_adc.fmt_original;
 858         }
 859         /* Nothing to do really, I need to keep the DMA going
 860            XXXKW when do I get here, and is there more I should do? */
 861         spin_unlock_irqrestore(&s->lock, flags);
 862         CS_DBGOUT(CS_FUNCTION, 3,
 863                   printk(KERN_INFO "cs4297a: stop_adc()-\n"));
 864 }
 865
 866
 867 static void start_adc(struct cs4297a_state *s)
 868 {
 869         unsigned long flags;
 870
 871         CS_DBGOUT(CS_FUNCTION, 2,
 872                   printk(KERN_INFO "cs4297a: start_adc()+\n"));
 873
 874         if (!(s->ena & FMODE_READ) &&
 875             (s->dma_adc.mapped || s->dma_adc.count <=
 876              (signed) (s->dma_adc.sbufsz - 2 * s->dma_adc.fragsize))
 877             && s->dma_adc.ready) {
 878                 if (s->prop_adc.fmt & AFMT_S8 || s->prop_adc.fmt & AFMT_U8) {
 879                         //
 880                         // now only use 16 bit capture, due to truncation issue
 881                         // in the chip, noticable distortion occurs.
 882                         // allocate buffer and then convert from 16 bit to
 883                         // 8 bit for the user buffer.
 884                         //
 885                         s->prop_adc.fmt_original = s->prop_adc.fmt;
 886                         if (s->prop_adc.fmt & AFMT_S8) {
 887                                 s->prop_adc.fmt &= ~AFMT_S8;
 888                                 s->prop_adc.fmt |= AFMT_S16_LE;
 889                         }
 890                         if (s->prop_adc.fmt & AFMT_U8) {
 891                                 s->prop_adc.fmt &= ~AFMT_U8;
 892                                 s->prop_adc.fmt |= AFMT_U16_LE;
 893                         }
 894                         //
 895                         // prog_dmabuf_adc performs a stop_adc() but that is
 896                         // ok since we really haven't started the DMA yet.
 897                         //
 898                         prog_codec(s, CS_TYPE_ADC);
 899
 900                         prog_dmabuf_adc(s);
 901                         s->conversion = 1;
 902                 }
 903                 spin_lock_irqsave(&s->lock, flags);
 904                 s->ena |= FMODE_READ;
 905                 /* Nothing to do really, I am probably already
 906                    DMAing...  XXXKW when do I get here, and is there
 907                    more I should do? */
 908                 spin_unlock_irqrestore(&s->lock, flags);
 909
 910                 CS_DBGOUT(CS_PARMS, 6, printk(KERN_INFO
 911                          "cs4297a: start_adc(): start adc\n"));
 912         }
 913         CS_DBGOUT(CS_FUNCTION, 2,
 914                   printk(KERN_INFO "cs4297a: start_adc()-\n"));
 915
 916 }
 917
 918
 919 // call with spinlock held!
 920 static void cs4297a_update_ptr(struct cs4297a_state *s, int intflag)
 921 {
 922         int good_diff, diff, diff2;
 923         u64 *data_p, data;
 924         u32 *s_ptr;
 925         unsigned hwptr;
 926         u32 status;
 927         serdma_t *d;
 928         serdma_descr_t *descr;
 929
 930         // update ADC pointer
 931         status = intflag ? __raw_readq(SS_CSR(R_SER_STATUS)) : 0;
 932
 933         if ((s->ena & FMODE_READ) || (status & (M_SYNCSER_RX_EOP_COUNT))) {
 934                 d = &s->dma_adc;
 935                 hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
 936                                      d->descrtab_phys) / sizeof(serdma_descr_t));
 937
 938                 if (s->ena & FMODE_READ) {
 939                         CS_DBGOUT(CS_FUNCTION, 2,
 940                                   printk(KERN_INFO "cs4297a: upd_rcv sw->hw->hw %x/%x/%x (int-%d)n",
 941                                          d->swptr, d->hwptr, hwptr, intflag));
 942                         /* Number of DMA buffers available for software: */
 943                         diff2 = diff = (d->ringsz + hwptr - d->hwptr) % d->ringsz;
 944                         d->hwptr = hwptr;
 945                         good_diff = 0;
 946                         s_ptr = (u32 *)&(d->dma_buf[d->swptr*4]);
 947                         descr = &d->descrtab[d->swptr];
 948                         while (diff2--) {
 949                                 u64 data = be64_to_cpu(*(u64 *)s_ptr);
 950                                 u64 descr_a;
 951                                 u16 left, right;
 952                                 descr_a = descr->descr_a;
 953                                 descr->descr_a &= ~M_DMA_SERRX_SOP;
 954                                 if ((descr_a & M_DMA_DSCRA_A_ADDR) != CPHYSADDR((long)s_ptr)) {
 955                                         printk(KERN_ERR "cs4297a: RX Bad address (read)\n");
 956                                 }
 957                                 if (((data & 0x9800000000000000) != 0x9800000000000000) ||
 958                                     (!(descr_a & M_DMA_SERRX_SOP)) ||
 959                                     (G_DMA_DSCRB_PKT_SIZE(descr->descr_b) != FRAME_BYTES)) {
 960                                         s->stats.rx_bad++;
 961                                         printk(KERN_DEBUG "cs4297a: RX Bad attributes (read)\n");
 962                                         continue;
 963                                 }
 964                                 s->stats.rx_good++;
 965                                 if ((data >> 61) == 7) {
 966                                         s->read_value = (data >> 12) & 0xffff;
 967                                         s->read_reg = (data >> 40) & 0x7f;
 968                                         wake_up(&d->reg_wait);
 969                                 }
 970                                 if (d->count && (d->sb_hwptr == d->sb_swptr)) {
 971                                         s->stats.rx_overflow++;
 972                                         printk(KERN_DEBUG "cs4297a: RX overflow\n");
 973                                         continue;
 974                                 }
 975                                 good_diff++;
 976                                 left = ((be32_to_cpu(s_ptr[1]) & 0xff) << 8) |
 977                                        ((be32_to_cpu(s_ptr[2]) >> 24) & 0xff);
 978                                 right = (be32_to_cpu(s_ptr[2]) >> 4) & 0xffff;
 979                                 *d->sb_hwptr++ = cpu_to_be16(left);
 980                                 *d->sb_hwptr++ = cpu_to_be16(right);
 981                                 if (d->sb_hwptr == d->sb_end)
 982                                         d->sb_hwptr = d->sample_buf;
 983                                 descr++;
 984                                 if (descr == d->descrtab_end) {
 985                                         descr = d->descrtab;
 986                                         s_ptr = (u32 *)s->dma_adc.dma_buf;
 987                                 } else {
 988                                         s_ptr += 8;
 989                                 }
 990                         }
 991                         d->total_bytes += good_diff * FRAME_SAMPLE_BYTES;
 992                         d->count += good_diff * FRAME_SAMPLE_BYTES;
 993                         if (d->count > d->sbufsz) {
 994                                 printk(KERN_ERR "cs4297a: bogus receive overflow!!\n");
 995                         }
 996                         d->swptr = (d->swptr + diff) % d->ringsz;
 997                         __raw_writeq(diff, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
 998                         if (d->mapped) {
 999                                 if (d->count >= (signed) d->fragsize)
1000                                         wake_up(&d->wait);
1001                         } else {
1002                                 if (d->count > 0) {
1003                                         CS_DBGOUT(CS_WAVE_READ, 4,
1004                                                   printk(KERN_INFO
1005                                                          "cs4297a: update count -> %d\n", d->count));
1006                                         wake_up(&d->wait);
1007                                 }
1008                         }
1009                 } else {
1010                         /* Receive is going even if no one is
1011                            listening (for register accesses and to
1012                            avoid FIFO overrun) */
1013                         diff2 = diff = (hwptr + d->ringsz - d->hwptr) % d->ringsz;
1014                         if (!diff) {
1015                                 printk(KERN_ERR "cs4297a: RX full or empty?\n");
1016                         }
1017
1018                         descr = &d->descrtab[d->swptr];
1019                         data_p = &d->dma_buf[d->swptr*4];
1020
1021                         /* Force this to happen at least once; I got
1022                            here because of an interrupt, so there must
1023                            be a buffer to process. */
1024                         do {
1025                                 data = be64_to_cpu(*data_p);
1026                                 if ((descr->descr_a & M_DMA_DSCRA_A_ADDR) != CPHYSADDR((long)data_p)) {
1027                                         printk(KERN_ERR "cs4297a: RX Bad address %d (%llx %lx)\n", d->swptr,
1028                                                (long long)(descr->descr_a & M_DMA_DSCRA_A_ADDR),
1029                                                (long)CPHYSADDR((long)data_p));
1030                                 }
1031                                 if (!(data & (1LL << 63)) ||
1032                                     !(descr->descr_a & M_DMA_SERRX_SOP) ||
1033                                     (G_DMA_DSCRB_PKT_SIZE(descr->descr_b) != FRAME_BYTES)) {
1034                                         s->stats.rx_bad++;
1035                                         printk(KERN_DEBUG "cs4297a: RX Bad attributes\n");
1036                                 } else {
1037                                         s->stats.rx_good++;
1038                                         if ((data >> 61) == 7) {
1039                                                 s->read_value = (data >> 12) & 0xffff;
1040                                                 s->read_reg = (data >> 40) & 0x7f;
1041                                                 wake_up(&d->reg_wait);
1042                                         }
1043                                 }
1044                                 descr->descr_a &= ~M_DMA_SERRX_SOP;
1045                                 descr++;
1046                                 d->swptr++;
1047                                 data_p += 4;
1048                                 if (descr == d->descrtab_end) {
1049                                         descr = d->descrtab;
1050                                         d->swptr = 0;
1051                                         data_p = d->dma_buf;
1052                                 }
1053                                 __raw_writeq(1, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
1054                         } while (--diff);
1055                         d->hwptr = hwptr;
1056
1057                         CS_DBGOUT(CS_DESCR, 6,
1058                                   printk(KERN_INFO "cs4297a: hw/sw %x/%x\n", d->hwptr, d->swptr));
1059                 }
1060
1061                 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
1062                         "cs4297a: cs4297a_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n",
1063                                 (unsigned)s, d->hwptr,
1064                                 d->total_bytes, d->count));
1065         }
1066
1067         /* XXXKW worry about s->reg_request -- there is a starvation
1068            case if s->ena has FMODE_WRITE on, but the client isn't
1069            doing writes */
1070
1071         // update DAC pointer
1072         //
1073         // check for end of buffer, means that we are going to wait for another interrupt
1074         // to allow silence to fill the fifos on the part, to keep pops down to a minimum.
1075         //
1076         if (s->ena & FMODE_WRITE) {
1077                 serdma_t *d = &s->dma_dac;
1078                 hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1079                                      d->descrtab_phys) / sizeof(serdma_descr_t));
1080                 diff = (d->ringsz + hwptr - d->hwptr) % d->ringsz;
1081                 CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO
1082                                                    "cs4297a: cs4297a_update_ptr(): hw/hw/sw %x/%x/%x diff %d count %d\n",
1083                                                    d->hwptr, hwptr, d->swptr, diff, d->count));
1084                 d->hwptr = hwptr;
1085                 /* XXXKW stereo? conversion? Just assume 2 16-bit samples for now */
1086                 d->total_bytes += diff * FRAME_SAMPLE_BYTES;
1087                 if (d->mapped) {
1088                         d->count += diff * FRAME_SAMPLE_BYTES;
1089                         if (d->count >= d->fragsize) {
1090                                 d->wakeup = 1;
1091                                 wake_up(&d->wait);
1092                                 if (d->count > d->sbufsz)
1093                                         d->count &= d->sbufsz - 1;
1094                         }
1095                 } else {
1096                         d->count -= diff * FRAME_SAMPLE_BYTES;
1097                         if (d->count <= 0) {
1098                                 //
1099                                 // fill with silence, and do not shut down the DAC.
1100                                 // Continue to play silence until the _release.
1101                                 //
1102                                 CS_DBGOUT(CS_WAVE_WRITE, 6, printk(KERN_INFO
1103                                         "cs4297a: cs4297a_update_ptr(): memset %d at 0x%.8x for %d size \n",
1104                                                 (unsigned)(s->prop_dac.fmt &
1105                                                 (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
1106                                                 (unsigned)d->dma_buf,
1107                                                 d->ringsz));
1108                                 memset(d->dma_buf, 0, d->ringsz * FRAME_BYTES);
1109                                 if (d->count < 0) {
1110                                         d->underrun = 1;
1111                                         s->stats.tx_underrun++;
1112                                         d->count = 0;
1113                                         CS_DBGOUT(CS_ERROR, 9, printk(KERN_INFO
1114                                          "cs4297a: cs4297a_update_ptr(): underrun\n"));
1115                                 }
1116                         } else if (d->count <=
1117                                    (signed) d->fragsize
1118                                    && !d->endcleared) {
1119                           /* XXXKW what is this for? */
1120                                 clear_advance(d->dma_buf,
1121                                               d->sbufsz,
1122                                               d->swptr,
1123                                               d->fragsize,
1124                                               0);
1125                                 d->endcleared = 1;
1126                         }
1127                         if ( (d->count <= (signed) d->sbufsz/2) || intflag)
1128                         {
1129                                 CS_DBGOUT(CS_WAVE_WRITE, 4,
1130                                           printk(KERN_INFO
1131                                                  "cs4297a: update count -> %d\n", d->count));
1132                                 wake_up(&d->wait);
1133                         }
1134                 }
1135                 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
1136                         "cs4297a: cs4297a_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n",
1137                                 (unsigned) s, d->hwptr,
1138                                 d->total_bytes, d->count));
1139         }
1140 }
1141
1142 static int mixer_ioctl(struct cs4297a_state *s, unsigned int cmd,
1143                        unsigned long arg)
1144 {
1145         // Index to mixer_src[] is value of AC97 Input Mux Select Reg.
1146         // Value of array member is recording source Device ID Mask.
1147         static const unsigned int mixer_src[8] = {
1148                 SOUND_MASK_MIC, SOUND_MASK_CD, 0, SOUND_MASK_LINE1,
1149                 SOUND_MASK_LINE, SOUND_MASK_VOLUME, 0, 0
1150         };
1151
1152         // Index of mixtable1[] member is Device ID
1153         // and must be <= SOUND_MIXER_NRDEVICES.
1154         // Value of array member is index into s->mix.vol[]
1155         static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
1156                 [SOUND_MIXER_PCM] = 1,  // voice
1157                 [SOUND_MIXER_LINE1] = 2,        // AUX
1158                 [SOUND_MIXER_CD] = 3,   // CD
1159                 [SOUND_MIXER_LINE] = 4, // Line
1160                 [SOUND_MIXER_SYNTH] = 5,        // FM
1161                 [SOUND_MIXER_MIC] = 6,  // Mic
1162                 [SOUND_MIXER_SPEAKER] = 7,      // Speaker
1163                 [SOUND_MIXER_RECLEV] = 8,       // Recording level
1164                 [SOUND_MIXER_VOLUME] = 9        // Master Volume
1165         };
1166
1167         static const unsigned mixreg[] = {
1168                 AC97_PCMOUT_VOL,
1169                 AC97_AUX_VOL,
1170                 AC97_CD_VOL,
1171                 AC97_LINEIN_VOL
1172         };
1173         unsigned char l, r, rl, rr, vidx;
1174         unsigned char attentbl[11] =
1175             { 63, 42, 26, 17, 14, 11, 8, 6, 4, 2, 0 };
1176         unsigned temp1;
1177         int i, val;
1178
1179         VALIDATE_STATE(s);
1180         CS_DBGOUT(CS_FUNCTION, 4, printk(KERN_INFO
1181                  "cs4297a: mixer_ioctl(): s=0x%.8x cmd=0x%.8x\n",
1182                          (unsigned) s, cmd));
1183 #if CSDEBUG
1184         cs_printioctl(cmd);
1185 #endif
1186 #if CSDEBUG_INTERFACE
1187
1188         if ((cmd == SOUND_MIXER_CS_GETDBGMASK) ||
1189             (cmd == SOUND_MIXER_CS_SETDBGMASK) ||
1190             (cmd == SOUND_MIXER_CS_GETDBGLEVEL) ||
1191             (cmd == SOUND_MIXER_CS_SETDBGLEVEL))
1192         {
1193                 switch (cmd) {
1194
1195                 case SOUND_MIXER_CS_GETDBGMASK:
1196                         return put_user(cs_debugmask,
1197                                         (unsigned long *) arg);
1198
1199                 case SOUND_MIXER_CS_GETDBGLEVEL:
1200                         return put_user(cs_debuglevel,
1201                                         (unsigned long *) arg);
1202
1203                 case SOUND_MIXER_CS_SETDBGMASK:
1204                         if (get_user(val, (unsigned long *) arg))
1205                                 return -EFAULT;
1206                         cs_debugmask = val;
1207                         return 0;
1208
1209                 case SOUND_MIXER_CS_SETDBGLEVEL:
1210                         if (get_user(val, (unsigned long *) arg))
1211                                 return -EFAULT;
1212                         cs_debuglevel = val;
1213                         return 0;
1214                 default:
1215                         CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO
1216                                 "cs4297a: mixer_ioctl(): ERROR unknown debug cmd\n"));
1217                         return 0;
1218                 }
1219         }
1220 #endif
1221
1222         if (cmd == SOUND_MIXER_PRIVATE1) {
1223                 return -EINVAL;
1224         }
1225         if (cmd == SOUND_MIXER_PRIVATE2) {
1226                 // enable/disable/query spatializer
1227                 if (get_user(val, (int *) arg))
1228                         return -EFAULT;
1229                 if (val != -1) {
1230                         temp1 = (val & 0x3f) >> 2;
1231                         cs4297a_write_ac97(s, AC97_3D_CONTROL, temp1);
1232                         cs4297a_read_ac97(s, AC97_GENERAL_PURPOSE,
1233                                          &temp1);
1234                         cs4297a_write_ac97(s, AC97_GENERAL_PURPOSE,
1235                                           temp1 | 0x2000);
1236                 }
1237                 cs4297a_read_ac97(s, AC97_3D_CONTROL, &temp1);
1238                 return put_user((temp1 << 2) | 3, (int *) arg);
1239         }
1240         if (cmd == SOUND_MIXER_INFO) {
1241                 mixer_info info;
1242                 memset(&info, 0, sizeof(info));
1243                 strlcpy(info.id, "CS4297a", sizeof(info.id));
1244                 strlcpy(info.name, "Crystal CS4297a", sizeof(info.name));
1245                 info.modify_counter = s->mix.modcnt;
1246                 if (copy_to_user((void *) arg, &info, sizeof(info)))
1247                         return -EFAULT;
1248                 return 0;
1249         }
1250         if (cmd == SOUND_OLD_MIXER_INFO) {
1251                 _old_mixer_info info;
1252                 memset(&info, 0, sizeof(info));
1253                 strlcpy(info.id, "CS4297a", sizeof(info.id));
1254                 strlcpy(info.name, "Crystal CS4297a", sizeof(info.name));
1255                 if (copy_to_user((void *) arg, &info, sizeof(info)))
1256                         return -EFAULT;
1257                 return 0;
1258         }
1259         if (cmd == OSS_GETVERSION)
1260                 return put_user(SOUND_VERSION, (int *) arg);
1261
1262         if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int))
1263                 return -EINVAL;
1264
1265         // If ioctl has only the SIOC_READ bit(bit 31)
1266         // on, process the only-read commands.
1267         if (_SIOC_DIR(cmd) == _SIOC_READ) {
1268                 switch (_IOC_NR(cmd)) {
1269                 case SOUND_MIXER_RECSRC:        // Arg contains a bit for each recording source
1270                         cs4297a_read_ac97(s, AC97_RECORD_SELECT,
1271                                          &temp1);
1272                         return put_user(mixer_src[temp1 & 7], (int *) arg);
1273
1274                 case SOUND_MIXER_DEVMASK:       // Arg contains a bit for each supported device
1275                         return put_user(SOUND_MASK_PCM | SOUND_MASK_LINE |
1276                                         SOUND_MASK_VOLUME | SOUND_MASK_RECLEV,
1277                                         (int *) arg);
1278
1279                 case SOUND_MIXER_RECMASK:       // Arg contains a bit for each supported recording source
1280                         return put_user(SOUND_MASK_LINE | SOUND_MASK_VOLUME,
1281                                         (int *) arg);
1282
1283                 case SOUND_MIXER_STEREODEVS:    // Mixer channels supporting stereo
1284                         return put_user(SOUND_MASK_PCM | SOUND_MASK_LINE |
1285                                         SOUND_MASK_VOLUME | SOUND_MASK_RECLEV,
1286                                         (int *) arg);
1287
1288                 case SOUND_MIXER_CAPS:
1289                         return put_user(SOUND_CAP_EXCL_INPUT, (int *) arg);
1290
1291                 default:
1292                         i = _IOC_NR(cmd);
1293                         if (i >= SOUND_MIXER_NRDEVICES
1294                             || !(vidx = mixtable1[i]))
1295                                 return -EINVAL;
1296                         return put_user(s->mix.vol[vidx - 1], (int *) arg);
1297                 }
1298         }
1299         // If ioctl doesn't have both the SIOC_READ and
1300         // the SIOC_WRITE bit set, return invalid.
1301         if (_SIOC_DIR(cmd) != (_SIOC_READ | _SIOC_WRITE))
1302                 return -EINVAL;
1303
1304         // Increment the count of volume writes.
1305         s->mix.modcnt++;
1306
1307         // Isolate the command; it must be a write.
1308         switch (_IOC_NR(cmd)) {
1309
1310         case SOUND_MIXER_RECSRC:        // Arg contains a bit for each recording source
1311                 if (get_user(val, (int *) arg))
1312                         return -EFAULT;
1313                 i = hweight32(val);     // i = # bits on in val.
1314                 if (i != 1)     // One & only 1 bit must be on.
1315                         return 0;
1316                 for (i = 0; i < sizeof(mixer_src) / sizeof(int); i++) {
1317                         if (val == mixer_src[i]) {
1318                                 temp1 = (i << 8) | i;
1319                                 cs4297a_write_ac97(s,
1320                                                   AC97_RECORD_SELECT,
1321                                                   temp1);
1322                                 return 0;
1323                         }
1324                 }
1325                 return 0;
1326
1327         case SOUND_MIXER_VOLUME:
1328                 if (get_user(val, (int *) arg))
1329                         return -EFAULT;
1330                 l = val & 0xff;
1331                 if (l > 100)
1332                         l = 100;        // Max soundcard.h vol is 100.
1333                 if (l < 6) {
1334                         rl = 63;
1335                         l = 0;
1336                 } else
1337                         rl = attentbl[(10 * l) / 100];  // Convert 0-100 vol to 63-0 atten.
1338
1339                 r = (val >> 8) & 0xff;
1340                 if (r > 100)
1341                         r = 100;        // Max right volume is 100, too
1342                 if (r < 6) {
1343                         rr = 63;
1344                         r = 0;
1345                 } else
1346                         rr = attentbl[(10 * r) / 100];  // Convert volume to attenuation.
1347
1348                 if ((rl > 60) && (rr > 60))     // If both l & r are 'low',
1349                         temp1 = 0x8000; //  turn on the mute bit.
1350                 else
1351                         temp1 = 0;
1352
1353                 temp1 |= (rl << 8) | rr;
1354
1355                 cs4297a_write_ac97(s, AC97_MASTER_VOL_STEREO, temp1);
1356                 cs4297a_write_ac97(s, AC97_PHONE_VOL, temp1);
1357
1358 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1359                 s->mix.vol[8] = ((unsigned int) r << 8) | l;
1360 #else
1361                 s->mix.vol[8] = val;
1362 #endif
1363                 return put_user(s->mix.vol[8], (int *) arg);
1364
1365         case SOUND_MIXER_SPEAKER:
1366                 if (get_user(val, (int *) arg))
1367                         return -EFAULT;
1368                 l = val & 0xff;
1369                 if (l > 100)
1370                         l = 100;
1371                 if (l < 3) {
1372                         rl = 0;
1373                         l = 0;
1374                 } else {
1375                         rl = (l * 2 - 5) / 13;  // Convert 0-100 range to 0-15.
1376                         l = (rl * 13 + 5) / 2;
1377                 }
1378
1379                 if (rl < 3) {
1380                         temp1 = 0x8000;
1381                         rl = 0;
1382                 } else
1383                         temp1 = 0;
1384                 rl = 15 - rl;   // Convert volume to attenuation.
1385                 temp1 |= rl << 1;
1386                 cs4297a_write_ac97(s, AC97_PCBEEP_VOL, temp1);
1387
1388 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1389                 s->mix.vol[6] = l << 8;
1390 #else
1391                 s->mix.vol[6] = val;
1392 #endif
1393                 return put_user(s->mix.vol[6], (int *) arg);
1394
1395         case SOUND_MIXER_RECLEV:
1396                 if (get_user(val, (int *) arg))
1397                         return -EFAULT;
1398                 l = val & 0xff;
1399                 if (l > 100)
1400                         l = 100;
1401                 r = (val >> 8) & 0xff;
1402                 if (r > 100)
1403                         r = 100;
1404                 rl = (l * 2 - 5) / 13;  // Convert 0-100 scale to 0-15.
1405                 rr = (r * 2 - 5) / 13;
1406                 if (rl < 3 && rr < 3)
1407                         temp1 = 0x8000;
1408                 else
1409                         temp1 = 0;
1410
1411                 temp1 = temp1 | (rl << 8) | rr;
1412                 cs4297a_write_ac97(s, AC97_RECORD_GAIN, temp1);
1413
1414 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1415                 s->mix.vol[7] = ((unsigned int) r << 8) | l;
1416 #else
1417                 s->mix.vol[7] = val;
1418 #endif
1419                 return put_user(s->mix.vol[7], (int *) arg);
1420
1421         case SOUND_MIXER_MIC:
1422                 if (get_user(val, (int *) arg))
1423                         return -EFAULT;
1424                 l = val & 0xff;
1425                 if (l > 100)
1426                         l = 100;
1427                 if (l < 1) {
1428                         l = 0;
1429                         rl = 0;
1430                 } else {
1431                         rl = ((unsigned) l * 5 - 4) / 16;       // Convert 0-100 range to 0-31.
1432                         l = (rl * 16 + 4) / 5;
1433                 }
1434                 cs4297a_read_ac97(s, AC97_MIC_VOL, &temp1);
1435                 temp1 &= 0x40;  // Isolate 20db gain bit.
1436                 if (rl < 3) {
1437                         temp1 |= 0x8000;
1438                         rl = 0;
1439                 }
1440                 rl = 31 - rl;   // Convert volume to attenuation.
1441                 temp1 |= rl;
1442                 cs4297a_write_ac97(s, AC97_MIC_VOL, temp1);
1443
1444 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1445                 s->mix.vol[5] = val << 8;
1446 #else
1447                 s->mix.vol[5] = val;
1448 #endif
1449                 return put_user(s->mix.vol[5], (int *) arg);
1450
1451
1452         case SOUND_MIXER_SYNTH:
1453                 if (get_user(val, (int *) arg))
1454                         return -EFAULT;
1455                 l = val & 0xff;
1456                 if (l > 100)
1457                         l = 100;
1458                 if (get_user(val, (int *) arg))
1459                         return -EFAULT;
1460                 r = (val >> 8) & 0xff;
1461                 if (r > 100)
1462                         r = 100;
1463                 rl = (l * 2 - 11) / 3;  // Convert 0-100 range to 0-63.
1464                 rr = (r * 2 - 11) / 3;
1465                 if (rl < 3)     // If l is low, turn on
1466                         temp1 = 0x0080; //  the mute bit.
1467                 else
1468                         temp1 = 0;
1469
1470                 rl = 63 - rl;   // Convert vol to attenuation.
1471 //              writel(temp1 | rl, s->pBA0 + FMLVC);
1472                 if (rr < 3)     //  If rr is low, turn on
1473                         temp1 = 0x0080; //   the mute bit.
1474                 else
1475                         temp1 = 0;
1476                 rr = 63 - rr;   // Convert vol to attenuation.
1477 //              writel(temp1 | rr, s->pBA0 + FMRVC);
1478
1479 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1480                 s->mix.vol[4] = (r << 8) | l;
1481 #else
1482                 s->mix.vol[4] = val;
1483 #endif
1484                 return put_user(s->mix.vol[4], (int *) arg);
1485
1486
1487         default:
1488                 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
1489                         "cs4297a: mixer_ioctl(): default\n"));
1490
1491                 i = _IOC_NR(cmd);
1492                 if (i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i]))
1493                         return -EINVAL;
1494                 if (get_user(val, (int *) arg))
1495                         return -EFAULT;
1496                 l = val & 0xff;
1497                 if (l > 100)
1498                         l = 100;
1499                 if (l < 1) {
1500                         l = 0;
1501                         rl = 31;
1502                 } else
1503                         rl = (attentbl[(l * 10) / 100]) >> 1;
1504
1505                 r = (val >> 8) & 0xff;
1506                 if (r > 100)
1507                         r = 100;
1508                 if (r < 1) {
1509                         r = 0;
1510                         rr = 31;
1511                 } else
1512                         rr = (attentbl[(r * 10) / 100]) >> 1;
1513                 if ((rl > 30) && (rr > 30))
1514                         temp1 = 0x8000;
1515                 else
1516                         temp1 = 0;
1517                 temp1 = temp1 | (rl << 8) | rr;
1518                 cs4297a_write_ac97(s, mixreg[vidx - 1], temp1);
1519
1520 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1521                 s->mix.vol[vidx - 1] = ((unsigned int) r << 8) | l;
1522 #else
1523                 s->mix.vol[vidx - 1] = val;
1524 #endif
1525                 return put_user(s->mix.vol[vidx - 1], (int *) arg);
1526         }
1527 }
1528
1529
1530 // ---------------------------------------------------------------------
1531
1532 static int cs4297a_open_mixdev(struct inode *inode, struct file *file)
1533 {
1534         int minor = iminor(inode);
1535         struct cs4297a_state *s=NULL;
1536         struct list_head *entry;
1537
1538         CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4,
1539                   printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()+\n"));
1540
1541         list_for_each(entry, &cs4297a_devs)
1542         {
1543                 s = list_entry(entry, struct cs4297a_state, list);
1544                 if(s->dev_mixer == minor)
1545                         break;
1546         }
1547         if (!s)
1548         {
1549                 CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2,
1550                         printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()- -ENODEV\n"));
1551                 return -ENODEV;
1552         }
1553         VALIDATE_STATE(s);
1554         file->private_data = s;
1555
1556         CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4,
1557                   printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()- 0\n"));
1558
1559         return nonseekable_open(inode, file);
1560 }
1561
1562
1563 static int cs4297a_release_mixdev(struct inode *inode, struct file *file)
1564 {
1565         struct cs4297a_state *s =
1566             (struct cs4297a_state *) file->private_data;
1567
1568         VALIDATE_STATE(s);
1569         return 0;
1570 }
1571
1572
1573 static int cs4297a_ioctl_mixdev(struct inode *inode, struct file *file,
1574                                unsigned int cmd, unsigned long arg)
1575 {
1576         return mixer_ioctl((struct cs4297a_state *) file->private_data, cmd,
1577                            arg);
1578 }
1579
1580
1581 // ******************************************************************************************
1582 //   Mixer file operations struct.
1583 // ******************************************************************************************
1584 static /*const */ struct file_operations cs4297a_mixer_fops = {
1585         .owner          = THIS_MODULE,
1586         .llseek         = no_llseek,
1587         .ioctl          = cs4297a_ioctl_mixdev,
1588         .open           = cs4297a_open_mixdev,
1589         .release        = cs4297a_release_mixdev,
1590 };
1591
1592 // ---------------------------------------------------------------------
1593
1594
1595 static int drain_adc(struct cs4297a_state *s, int nonblock)
1596 {
1597         /* This routine serves no purpose currently - any samples
1598            sitting in the receive queue will just be processed by the
1599            background consumer.  This would be different if DMA
1600            actually stopped when there were no clients. */
1601         return 0;
1602 }
1603
1604 static int drain_dac(struct cs4297a_state *s, int nonblock)
1605 {
1606         DECLARE_WAITQUEUE(wait, current);
1607         unsigned long flags;
1608         unsigned hwptr;
1609         unsigned tmo;
1610         int count;
1611
1612         if (s->dma_dac.mapped)
1613                 return 0;
1614         if (nonblock)
1615                 return -EBUSY;
1616         add_wait_queue(&s->dma_dac.wait, &wait);
1617         while ((count = __raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) ||
1618                (s->dma_dac.count > 0)) {
1619                 if (!signal_pending(current)) {
1620                         set_current_state(TASK_INTERRUPTIBLE);
1621                         /* XXXKW is this calculation working? */
1622                         tmo = ((count * FRAME_TX_US) * HZ) / 1000000;
1623                         schedule_timeout(tmo + 1);
1624                 } else {
1625                         /* XXXKW do I care if there is a signal pending? */
1626                 }
1627         }
1628         spin_lock_irqsave(&s->lock, flags);
1629         /* Reset the bookkeeping */
1630         hwptr = (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1631                        s->dma_dac.descrtab_phys) / sizeof(serdma_descr_t));
1632         s->dma_dac.hwptr = s->dma_dac.swptr = hwptr;
1633         spin_unlock_irqrestore(&s->lock, flags);
1634         remove_wait_queue(&s->dma_dac.wait, &wait);
1635         current->state = TASK_RUNNING;
1636         return 0;
1637 }
1638
1639
1640 // ---------------------------------------------------------------------
1641
1642 static ssize_t cs4297a_read(struct file *file, char *buffer, size_t count,
1643                            loff_t * ppos)
1644 {
1645         struct cs4297a_state *s =
1646             (struct cs4297a_state *) file->private_data;
1647         ssize_t ret;
1648         unsigned long flags;
1649         int cnt, count_fr, cnt_by;
1650         unsigned copied = 0;
1651
1652         CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
1653                   printk(KERN_INFO "cs4297a: cs4297a_read()+ %d \n", count));
1654
1655         VALIDATE_STATE(s);
1656         if (s->dma_adc.mapped)
1657                 return -ENXIO;
1658         if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1659                 return ret;
1660         if (!access_ok(VERIFY_WRITE, buffer, count))
1661                 return -EFAULT;
1662         ret = 0;
1663 //
1664 // "count" is the amount of bytes to read (from app), is decremented each loop
1665 //      by the amount of bytes that have been returned to the user buffer.
1666 // "cnt" is the running total of each read from the buffer (changes each loop)
1667 // "buffer" points to the app's buffer
1668 // "ret" keeps a running total of the amount of bytes that have been copied
1669 //      to the user buffer.
1670 // "copied" is the total bytes copied into the user buffer for each loop.
1671 //
1672         while (count > 0) {
1673                 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
1674                         "_read() count>0 count=%d .count=%d .swptr=%d .hwptr=%d \n",
1675                                 count, s->dma_adc.count,
1676                                 s->dma_adc.swptr, s->dma_adc.hwptr));
1677                 spin_lock_irqsave(&s->lock, flags);
1678
1679                 /* cnt will be the number of available samples (16-bit
1680                    stereo); it starts out as the maxmimum consequetive
1681                    samples */
1682                 cnt = (s->dma_adc.sb_end - s->dma_adc.sb_swptr) / 2;
1683                 count_fr = s->dma_adc.count / FRAME_SAMPLE_BYTES;
1684
1685                 // dma_adc.count is the current total bytes that have not been read.
1686                 // if the amount of unread bytes from the current sw pointer to the
1687                 // end of the buffer is greater than the current total bytes that
1688                 // have not been read, then set the "cnt" (unread bytes) to the
1689                 // amount of unread bytes.
1690
1691                 if (count_fr < cnt)
1692                         cnt = count_fr;
1693                 cnt_by = cnt * FRAME_SAMPLE_BYTES;
1694                 spin_unlock_irqrestore(&s->lock, flags);
1695                 //
1696                 // if we are converting from 8/16 then we need to copy
1697                 // twice the number of 16 bit bytes then 8 bit bytes.
1698                 //
1699                 if (s->conversion) {
1700                         if (cnt_by > (count * 2)) {
1701                                 cnt = (count * 2) / FRAME_SAMPLE_BYTES;
1702                                 cnt_by = count * 2;
1703                         }
1704                 } else {
1705                         if (cnt_by > count) {
1706                                 cnt = count / FRAME_SAMPLE_BYTES;
1707                                 cnt_by = count;
1708                         }
1709                 }
1710                 //
1711                 // "cnt" NOW is the smaller of the amount that will be read,
1712                 // and the amount that is requested in this read (or partial).
1713                 // if there are no bytes in the buffer to read, then start the
1714                 // ADC and wait for the interrupt handler to wake us up.
1715                 //
1716                 if (cnt <= 0) {
1717
1718                         // start up the dma engine and then continue back to the top of
1719                         // the loop when wake up occurs.
1720                         start_adc(s);
1721                         if (file->f_flags & O_NONBLOCK)
1722                                 return ret ? ret : -EAGAIN;
1723                         interruptible_sleep_on(&s->dma_adc.wait);
1724                         if (signal_pending(current))
1725                                 return ret ? ret : -ERESTARTSYS;
1726                         continue;
1727                 }
1728                 // there are bytes in the buffer to read.
1729                 // copy from the hw buffer over to the user buffer.
1730                 // user buffer is designated by "buffer"
1731                 // virtual address to copy from is dma_buf+swptr
1732                 // the "cnt" is the number of bytes to read.
1733
1734                 CS_DBGOUT(CS_WAVE_READ, 2, printk(KERN_INFO
1735                         "_read() copy_to cnt=%d count=%d ", cnt_by, count));
1736                 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
1737                          " .sbufsz=%d .count=%d buffer=0x%.8x ret=%d\n",
1738                                  s->dma_adc.sbufsz, s->dma_adc.count,
1739                                  (unsigned) buffer, ret));
1740
1741                 if (copy_to_user (buffer, ((void *)s->dma_adc.sb_swptr), cnt_by))
1742                         return ret ? ret : -EFAULT;
1743                 copied = cnt_by;
1744
1745                 /* Return the descriptors */
1746                 spin_lock_irqsave(&s->lock, flags);
1747                 CS_DBGOUT(CS_FUNCTION, 2,
1748                           printk(KERN_INFO "cs4297a: upd_rcv sw->hw %x/%x\n", s->dma_adc.swptr, s->dma_adc.hwptr));
1749                 s->dma_adc.count -= cnt_by;
1750                 s->dma_adc.sb_swptr += cnt * 2;
1751                 if (s->dma_adc.sb_swptr == s->dma_adc.sb_end)
1752                         s->dma_adc.sb_swptr = s->dma_adc.sample_buf;
1753                 spin_unlock_irqrestore(&s->lock, flags);
1754                 count -= copied;
1755                 buffer += copied;
1756                 ret += copied;
1757                 start_adc(s);
1758         }
1759         CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
1760                   printk(KERN_INFO "cs4297a: cs4297a_read()- %d\n", ret));
1761         return ret;
1762 }
1763
1764
1765 static ssize_t cs4297a_write(struct file *file, const char *buffer,
1766                             size_t count, loff_t * ppos)
1767 {
1768         struct cs4297a_state *s =
1769             (struct cs4297a_state *) file->private_data;
1770         ssize_t ret;
1771         unsigned long flags;
1772         unsigned swptr, hwptr;
1773         int cnt;
1774
1775         CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
1776                   printk(KERN_INFO "cs4297a: cs4297a_write()+ count=%d\n",
1777                          count));
1778         VALIDATE_STATE(s);
1779
1780         if (s->dma_dac.mapped)
1781                 return -ENXIO;
1782         if (!s->dma_dac.ready && (ret = prog_dmabuf_dac(s)))
1783                 return ret;
1784         if (!access_ok(VERIFY_READ, buffer, count))
1785                 return -EFAULT;
1786         ret = 0;
1787         while (count > 0) {
1788                 serdma_t *d = &s->dma_dac;
1789                 int copy_cnt;
1790                 u32 *s_tmpl;
1791                 u32 *t_tmpl;
1792                 u32 left, right;
1793                 int swap = (s->prop_dac.fmt == AFMT_S16_LE) || (s->prop_dac.fmt == AFMT_U16_LE);
1794
1795                 /* XXXXXX this is broken for BLOAT_FACTOR */
1796                 spin_lock_irqsave(&s->lock, flags);
1797                 if (d->count < 0) {
1798                         d->count = 0;
1799                         d->swptr = d->hwptr;
1800                 }
1801                 if (d->underrun) {
1802                         d->underrun = 0;
1803                         hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1804                                              d->descrtab_phys) / sizeof(serdma_descr_t));
1805                         d->swptr = d->hwptr = hwptr;
1806                 }
1807                 swptr = d->swptr;
1808                 cnt = d->sbufsz - (swptr * FRAME_SAMPLE_BYTES);
1809                 /* Will this write fill up the buffer? */
1810                 if (d->count + cnt > d->sbufsz)
1811                         cnt = d->sbufsz - d->count;
1812                 spin_unlock_irqrestore(&s->lock, flags);
1813                 if (cnt > count)
1814                         cnt = count;
1815                 if (cnt <= 0) {
1816                         start_dac(s);
1817                         if (file->f_flags & O_NONBLOCK)
1818                                 return ret ? ret : -EAGAIN;
1819                         interruptible_sleep_on(&d->wait);
1820                         if (signal_pending(current))
1821                                 return ret ? ret : -ERESTARTSYS;
1822                         continue;
1823                 }
1824                 if (copy_from_user(d->sample_buf, buffer, cnt))
1825                         return ret ? ret : -EFAULT;
1826
1827                 copy_cnt = cnt;
1828                 s_tmpl = (u32 *)d->sample_buf;
1829                 t_tmpl = (u32 *)(d->dma_buf + (swptr * 4));
1830
1831                 /* XXXKW assuming 16-bit stereo! */
1832                 do {
1833                         u32 tmp;
1834
1835                         t_tmpl[0] = cpu_to_be32(0x98000000);
1836
1837                         tmp = be32_to_cpu(s_tmpl[0]);
1838                         left = tmp & 0xffff;
1839                         right = tmp >> 16;
1840                         if (swap) {
1841                                 left = swab16(left);
1842                                 right = swab16(right);
1843                         }
1844                         t_tmpl[1] = cpu_to_be32(left >> 8);
1845                         t_tmpl[2] = cpu_to_be32(((left & 0xff) << 24) |
1846                                                 (right << 4));
1847
1848                         s_tmpl++;
1849                         t_tmpl += 8;
1850                         copy_cnt -= 4;
1851                 } while (copy_cnt);
1852
1853                 /* Mux in any pending read/write accesses */
1854                 if (s->reg_request) {
1855                         *(u64 *)(d->dma_buf + (swptr * 4)) |=
1856                                 cpu_to_be64(s->reg_request);
1857                         s->reg_request = 0;
1858                         wake_up(&s->dma_dac.reg_wait);
1859                 }
1860
1861                 CS_DBGOUT(CS_WAVE_WRITE, 4,
1862                           printk(KERN_INFO
1863                                  "cs4297a: copy in %d to swptr %x\n", cnt, swptr));
1864
1865                 swptr = (swptr + (cnt/FRAME_SAMPLE_BYTES)) % d->ringsz;
1866                 __raw_writeq(cnt/FRAME_SAMPLE_BYTES, SS_CSR(R_SER_DMA_DSCR_COUNT_TX));
1867                 spin_lock_irqsave(&s->lock, flags);
1868                 d->swptr = swptr;
1869                 d->count += cnt;
1870                 d->endcleared = 0;
1871                 spin_unlock_irqrestore(&s->lock, flags);
1872                 count -= cnt;
1873                 buffer += cnt;
1874                 ret += cnt;
1875                 start_dac(s);
1876         }
1877         CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
1878                   printk(KERN_INFO "cs4297a: cs4297a_write()- %d\n", ret));
1879         return ret;
1880 }
1881
1882
1883 static unsigned int cs4297a_poll(struct file *file,
1884                                 struct poll_table_struct *wait)
1885 {
1886         struct cs4297a_state *s =
1887             (struct cs4297a_state *) file->private_data;
1888         unsigned long flags;
1889         unsigned int mask = 0;
1890
1891         CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1892                   printk(KERN_INFO "cs4297a: cs4297a_poll()+\n"));
1893         VALIDATE_STATE(s);
1894         if (file->f_mode & FMODE_WRITE) {
1895                 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1896                           printk(KERN_INFO
1897                                  "cs4297a: cs4297a_poll() wait on FMODE_WRITE\n"));
1898                 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
1899                         return 0;
1900                 poll_wait(file, &s->dma_dac.wait, wait);
1901         }
1902         if (file->f_mode & FMODE_READ) {
1903                 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1904                           printk(KERN_INFO
1905                                  "cs4297a: cs4297a_poll() wait on FMODE_READ\n"));
1906                 if(!s->dma_dac.ready && prog_dmabuf_adc(s))
1907                         return 0;
1908                 poll_wait(file, &s->dma_adc.wait, wait);
1909         }
1910         spin_lock_irqsave(&s->lock, flags);
1911         cs4297a_update_ptr(s,CS_FALSE);
1912         if (file->f_mode & FMODE_WRITE) {
1913                 if (s->dma_dac.mapped) {
1914                         if (s->dma_dac.count >=
1915                             (signed) s->dma_dac.fragsize) {
1916                                 if (s->dma_dac.wakeup)
1917                                         mask |= POLLOUT | POLLWRNORM;
1918                                 else
1919                                         mask = 0;
1920                                 s->dma_dac.wakeup = 0;
1921                         }
1922                 } else {
1923                         if ((signed) (s->dma_dac.sbufsz/2) >= s->dma_dac.count)
1924                                 mask |= POLLOUT | POLLWRNORM;
1925                 }
1926         } else if (file->f_mode & FMODE_READ) {
1927                 if (s->dma_adc.mapped) {
1928                         if (s->dma_adc.count >= (signed) s->dma_adc.fragsize)
1929                                 mask |= POLLIN | POLLRDNORM;
1930                 } else {
1931                         if (s->dma_adc.count > 0)
1932                                 mask |= POLLIN | POLLRDNORM;
1933                 }
1934         }
1935         spin_unlock_irqrestore(&s->lock, flags);
1936         CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1937                   printk(KERN_INFO "cs4297a: cs4297a_poll()- 0x%.8x\n",
1938                          mask));
1939         return mask;
1940 }
1941
1942
1943 static int cs4297a_mmap(struct file *file, struct vm_area_struct *vma)
1944 {
1945         /* XXXKW currently no mmap support */
1946         return -EINVAL;
1947         return 0;
1948 }
1949
1950
1951 static int cs4297a_ioctl(struct inode *inode, struct file *file,
1952                         unsigned int cmd, unsigned long arg)
1953 {
1954         struct cs4297a_state *s =
1955             (struct cs4297a_state *) file->private_data;
1956         unsigned long flags;
1957         audio_buf_info abinfo;
1958         count_info cinfo;
1959         int val, mapped, ret;
1960
1961         CS_DBGOUT(CS_FUNCTION|CS_IOCTL, 4, printk(KERN_INFO
1962                  "cs4297a: cs4297a_ioctl(): file=0x%.8x cmd=0x%.8x\n",
1963                          (unsigned) file, cmd));
1964 #if CSDEBUG
1965         cs_printioctl(cmd);
1966 #endif
1967         VALIDATE_STATE(s);
1968         mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1969             ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1970         switch (cmd) {
1971         case OSS_GETVERSION:
1972                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
1973                         "cs4297a: cs4297a_ioctl(): SOUND_VERSION=0x%.8x\n",
1974                                  SOUND_VERSION));
1975                 return put_user(SOUND_VERSION, (int *) arg);
1976
1977         case SNDCTL_DSP_SYNC:
1978                 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
1979                          "cs4297a: cs4297a_ioctl(): DSP_SYNC\n"));
1980                 if (file->f_mode & FMODE_WRITE)
1981                         return drain_dac(s,
1982                                          0 /*file->f_flags & O_NONBLOCK */
1983                                          );
1984                 return 0;
1985
1986         case SNDCTL_DSP_SETDUPLEX:
1987                 return 0;
1988
1989         case SNDCTL_DSP_GETCAPS:
1990                 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
1991                                 DSP_CAP_TRIGGER | DSP_CAP_MMAP,
1992                                 (int *) arg);
1993
1994         case SNDCTL_DSP_RESET:
1995                 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
1996                          "cs4297a: cs4297a_ioctl(): DSP_RESET\n"));
1997                 if (file->f_mode & FMODE_WRITE) {
1998                         stop_dac(s);
1999                         synchronize_irq(s->irq);
2000                         s->dma_dac.count = s->dma_dac.total_bytes =
2001                                 s->dma_dac.blocks = s->dma_dac.wakeup = 0;
2002                         s->dma_dac.swptr = s->dma_dac.hwptr =
2003                                 (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
2004                                        s->dma_dac.descrtab_phys) / sizeof(serdma_descr_t));
2005                 }
2006                 if (file->f_mode & FMODE_READ) {
2007                         stop_adc(s);
2008                         synchronize_irq(s->irq);
2009                         s->dma_adc.count = s->dma_adc.total_bytes =
2010                                 s->dma_adc.blocks = s->dma_dac.wakeup = 0;
2011                         s->dma_adc.swptr = s->dma_adc.hwptr =
2012                                 (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
2013                                        s->dma_adc.descrtab_phys) / sizeof(serdma_descr_t));
2014                 }
2015                 return 0;
2016
2017         case SNDCTL_DSP_SPEED:
2018                 if (get_user(val, (int *) arg))
2019                         return -EFAULT;
2020                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2021                          "cs4297a: cs4297a_ioctl(): DSP_SPEED val=%d -> 48000\n", val));
2022                 val = 48000;
2023                 return put_user(val, (int *) arg);
2024
2025         case SNDCTL_DSP_STEREO:
2026                 if (get_user(val, (int *) arg))
2027                         return -EFAULT;
2028                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2029                          "cs4297a: cs4297a_ioctl(): DSP_STEREO val=%d\n", val));
2030                 if (file->f_mode & FMODE_READ) {
2031                         stop_adc(s);
2032                         s->dma_adc.ready = 0;
2033                         s->prop_adc.channels = val ? 2 : 1;
2034                 }
2035                 if (file->f_mode & FMODE_WRITE) {
2036                         stop_dac(s);
2037                         s->dma_dac.ready = 0;
2038                         s->prop_dac.channels = val ? 2 : 1;
2039                 }
2040                 return 0;
2041
2042         case SNDCTL_DSP_CHANNELS:
2043                 if (get_user(val, (int *) arg))
2044                         return -EFAULT;
2045                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2046                          "cs4297a: cs4297a_ioctl(): DSP_CHANNELS val=%d\n",
2047                                  val));
2048                 if (val != 0) {
2049                         if (file->f_mode & FMODE_READ) {
2050                                 stop_adc(s);
2051                                 s->dma_adc.ready = 0;
2052                                 if (val >= 2)
2053                                         s->prop_adc.channels = 2;
2054                                 else
2055                                         s->prop_adc.channels = 1;
2056                         }
2057                         if (file->f_mode & FMODE_WRITE) {
2058                                 stop_dac(s);
2059                                 s->dma_dac.ready = 0;
2060                                 if (val >= 2)
2061                                         s->prop_dac.channels = 2;
2062                                 else
2063                                         s->prop_dac.channels = 1;
2064                         }
2065                 }
2066
2067                 if (file->f_mode & FMODE_WRITE)
2068                         val = s->prop_dac.channels;
2069                 else if (file->f_mode & FMODE_READ)
2070                         val = s->prop_adc.channels;
2071
2072                 return put_user(val, (int *) arg);
2073
2074         case SNDCTL_DSP_GETFMTS:        // Returns a mask
2075                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2076                         "cs4297a: cs4297a_ioctl(): DSP_GETFMT val=0x%.8x\n",
2077                                  AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
2078                                  AFMT_U8));
2079                 return put_user(AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
2080                                 AFMT_U8, (int *) arg);
2081
2082         case SNDCTL_DSP_SETFMT:
2083                 if (get_user(val, (int *) arg))
2084                         return -EFAULT;
2085                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2086                          "cs4297a: cs4297a_ioctl(): DSP_SETFMT val=0x%.8x\n",
2087                                  val));
2088                 if (val != AFMT_QUERY) {
2089                         if (file->f_mode & FMODE_READ) {
2090                                 stop_adc(s);
2091                                 s->dma_adc.ready = 0;
2092                                 if (val != AFMT_S16_LE
2093                                     && val != AFMT_U16_LE && val != AFMT_S8
2094                                     && val != AFMT_U8)
2095                                         val = AFMT_U8;
2096                                 s->prop_adc.fmt = val;
2097                                 s->prop_adc.fmt_original = s->prop_adc.fmt;
2098                         }
2099                         if (file->f_mode & FMODE_WRITE) {
2100                                 stop_dac(s);
2101                                 s->dma_dac.ready = 0;
2102                                 if (val != AFMT_S16_LE
2103                                     && val != AFMT_U16_LE && val != AFMT_S8
2104                                     && val != AFMT_U8)
2105                                         val = AFMT_U8;
2106                                 s->prop_dac.fmt = val;
2107                                 s->prop_dac.fmt_original = s->prop_dac.fmt;
2108                         }
2109                 } else {
2110                         if (file->f_mode & FMODE_WRITE)
2111                                 val = s->prop_dac.fmt_original;
2112                         else if (file->f_mode & FMODE_READ)
2113                                 val = s->prop_adc.fmt_original;
2114                 }
2115                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2116                   "cs4297a: cs4297a_ioctl(): DSP_SETFMT return val=0x%.8x\n",
2117                         val));
2118                 return put_user(val, (int *) arg);
2119
2120         case SNDCTL_DSP_POST:
2121                 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
2122                          "cs4297a: cs4297a_ioctl(): DSP_POST\n"));
2123                 return 0;
2124
2125         case SNDCTL_DSP_GETTRIGGER:
2126                 val = 0;
2127                 if (file->f_mode & s->ena & FMODE_READ)
2128                         val |= PCM_ENABLE_INPUT;
2129                 if (file->f_mode & s->ena & FMODE_WRITE)
2130                         val |= PCM_ENABLE_OUTPUT;
2131                 return put_user(val, (int *) arg);
2132
2133         case SNDCTL_DSP_SETTRIGGER:
2134                 if (get_user(val, (int *) arg))
2135                         return -EFAULT;
2136                 if (file->f_mode & FMODE_READ) {
2137                         if (val & PCM_ENABLE_INPUT) {
2138                                 if (!s->dma_adc.ready
2139                                     && (ret = prog_dmabuf_adc(s)))
2140                                         return ret;
2141                                 start_adc(s);
2142                         } else
2143                                 stop_adc(s);
2144                 }
2145                 if (file->f_mode & FMODE_WRITE) {
2146                         if (val & PCM_ENABLE_OUTPUT) {
2147                                 if (!s->dma_dac.ready
2148                                     && (ret = prog_dmabuf_dac(s)))
2149                                         return ret;
2150                                 start_dac(s);
2151                         } else
2152                                 stop_dac(s);
2153                 }
2154                 return 0;
2155
2156         case SNDCTL_DSP_GETOSPACE:
2157                 if (!(file->f_mode & FMODE_WRITE))
2158                         return -EINVAL;
2159                 if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s)))
2160                         return val;
2161                 spin_lock_irqsave(&s->lock, flags);
2162                 cs4297a_update_ptr(s,CS_FALSE);
2163                 abinfo.fragsize = s->dma_dac.fragsize;
2164                 if (s->dma_dac.mapped)
2165                         abinfo.bytes = s->dma_dac.sbufsz;
2166                 else
2167                         abinfo.bytes =
2168                             s->dma_dac.sbufsz - s->dma_dac.count;
2169                 abinfo.fragstotal = s->dma_dac.numfrag;
2170                 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
2171                 CS_DBGOUT(CS_FUNCTION | CS_PARMS, 4, printk(KERN_INFO
2172                         "cs4297a: cs4297a_ioctl(): GETOSPACE .fragsize=%d .bytes=%d .fragstotal=%d .fragments=%d\n",
2173                                 abinfo.fragsize,abinfo.bytes,abinfo.fragstotal,
2174                                 abinfo.fragments));
2175                 spin_unlock_irqrestore(&s->lock, flags);
2176                 return copy_to_user((void *) arg, &abinfo,
2177                                     sizeof(abinfo)) ? -EFAULT : 0;
2178
2179         case SNDCTL_DSP_GETISPACE:
2180                 if (!(file->f_mode & FMODE_READ))
2181                         return -EINVAL;
2182                 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)))
2183                         return val;
2184                 spin_lock_irqsave(&s->lock, flags);
2185                 cs4297a_update_ptr(s,CS_FALSE);
2186                 if (s->conversion) {
2187                         abinfo.fragsize = s->dma_adc.fragsize / 2;
2188                         abinfo.bytes = s->dma_adc.count / 2;
2189                         abinfo.fragstotal = s->dma_adc.numfrag;
2190                         abinfo.fragments =
2191                             abinfo.bytes >> (s->dma_adc.fragshift - 1);
2192                 } else {
2193                         abinfo.fragsize = s->dma_adc.fragsize;
2194                         abinfo.bytes = s->dma_adc.count;
2195                         abinfo.fragstotal = s->dma_adc.numfrag;
2196                         abinfo.fragments =
2197                             abinfo.bytes >> s->dma_adc.fragshift;
2198                 }
2199                 spin_unlock_irqrestore(&s->lock, flags);
2200                 return copy_to_user((void *) arg, &abinfo,
2201                                     sizeof(abinfo)) ? -EFAULT : 0;
2202
2203         case SNDCTL_DSP_NONBLOCK:
2204                 file->f_flags |= O_NONBLOCK;
2205                 return 0;
2206
2207         case SNDCTL_DSP_GETODELAY:
2208                 if (!(file->f_mode & FMODE_WRITE))
2209                         return -EINVAL;
2210                 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
2211                         return 0;
2212                 spin_lock_irqsave(&s->lock, flags);
2213                 cs4297a_update_ptr(s,CS_FALSE);
2214                 val = s->dma_dac.count;
2215                 spin_unlock_irqrestore(&s->lock, flags);
2216                 return put_user(val, (int *) arg);
2217
2218         case SNDCTL_DSP_GETIPTR:
2219                 if (!(file->f_mode & FMODE_READ))
2220                         return -EINVAL;
2221                 if(!s->dma_adc.ready && prog_dmabuf_adc(s))
2222                         return 0;
2223                 spin_lock_irqsave(&s->lock, flags);
2224                 cs4297a_update_ptr(s,CS_FALSE);
2225                 cinfo.bytes = s->dma_adc.total_bytes;
2226                 if (s->dma_adc.mapped) {
2227                         cinfo.blocks =
2228                             (cinfo.bytes >> s->dma_adc.fragshift) -
2229                             s->dma_adc.blocks;
2230                         s->dma_adc.blocks =
2231                             cinfo.bytes >> s->dma_adc.fragshift;
2232                 } else {
2233                         if (s->conversion) {
2234                                 cinfo.blocks =
2235                                     s->dma_adc.count /
2236                                     2 >> (s->dma_adc.fragshift - 1);
2237                         } else
2238                                 cinfo.blocks =
2239                                     s->dma_adc.count >> s->dma_adc.
2240                                     fragshift;
2241                 }
2242                 if (s->conversion)
2243                         cinfo.ptr = s->dma_adc.hwptr / 2;
2244                 else
2245                         cinfo.ptr = s->dma_adc.hwptr;
2246                 if (s->dma_adc.mapped)
2247                         s->dma_adc.count &= s->dma_adc.fragsize - 1;
2248                 spin_unlock_irqrestore(&s->lock, flags);
2249                 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
2250
2251         case SNDCTL_DSP_GETOPTR:
2252                 if (!(file->f_mode & FMODE_WRITE))
2253                         return -EINVAL;
2254                 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
2255                         return 0;
2256                 spin_lock_irqsave(&s->lock, flags);
2257                 cs4297a_update_ptr(s,CS_FALSE);
2258                 cinfo.bytes = s->dma_dac.total_bytes;
2259                 if (s->dma_dac.mapped) {
2260                         cinfo.blocks =
2261                             (cinfo.bytes >> s->dma_dac.fragshift) -
2262                             s->dma_dac.blocks;
2263                         s->dma_dac.blocks =
2264                             cinfo.bytes >> s->dma_dac.fragshift;
2265                 } else {
2266                         cinfo.blocks =
2267                             s->dma_dac.count >> s->dma_dac.fragshift;
2268                 }
2269                 cinfo.ptr = s->dma_dac.hwptr;
2270                 if (s->dma_dac.mapped)
2271                         s->dma_dac.count &= s->dma_dac.fragsize - 1;
2272                 spin_unlock_irqrestore(&s->lock, flags);
2273                 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
2274
2275         case SNDCTL_DSP_GETBLKSIZE:
2276                 if (file->f_mode & FMODE_WRITE) {
2277                         if ((val = prog_dmabuf_dac(s)))
2278                                 return val;
2279                         return put_user(s->dma_dac.fragsize, (int *) arg);
2280                 }
2281                 if ((val = prog_dmabuf_adc(s)))
2282                         return val;
2283                 if (s->conversion)
2284                         return put_user(s->dma_adc.fragsize / 2,
2285                                         (int *) arg);
2286                 else
2287                         return put_user(s->dma_adc.fragsize, (int *) arg);
2288
2289         case SNDCTL_DSP_SETFRAGMENT:
2290                 if (get_user(val, (int *) arg))
2291                         return -EFAULT;
2292                 return 0;       // Say OK, but do nothing.
2293
2294         case SNDCTL_DSP_SUBDIVIDE:
2295                 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision)
2296                     || (file->f_mode & FMODE_WRITE
2297                         && s->dma_dac.subdivision)) return -EINVAL;
2298                 if (get_user(val, (int *) arg))
2299                         return -EFAULT;
2300                 if (val != 1 && val != 2 && val != 4)
2301                         return -EINVAL;
2302                 if (file->f_mode & FMODE_READ)
2303                         s->dma_adc.subdivision = val;
2304                 else if (file->f_mode & FMODE_WRITE)
2305                         s->dma_dac.subdivision = val;
2306                 return 0;
2307
2308         case SOUND_PCM_READ_RATE:
2309                 if (file->f_mode & FMODE_READ)
2310                         return put_user(s->prop_adc.rate, (int *) arg);
2311                 else if (file->f_mode & FMODE_WRITE)
2312                         return put_user(s->prop_dac.rate, (int *) arg);
2313
2314         case SOUND_PCM_READ_CHANNELS:
2315                 if (file->f_mode & FMODE_READ)
2316                         return put_user(s->prop_adc.channels, (int *) arg);
2317                 else if (file->f_mode & FMODE_WRITE)
2318                         return put_user(s->prop_dac.channels, (int *) arg);
2319
2320         case SOUND_PCM_READ_BITS:
2321                 if (file->f_mode & FMODE_READ)
2322                         return
2323                             put_user(
2324                                      (s->prop_adc.
2325                                       fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
2326                                      (int *) arg);
2327                 else if (file->f_mode & FMODE_WRITE)
2328                         return
2329                             put_user(
2330                                      (s->prop_dac.
2331                                       fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
2332                                      (int *) arg);
2333
2334         case SOUND_PCM_WRITE_FILTER:
2335         case SNDCTL_DSP_SETSYNCRO:
2336         case SOUND_PCM_READ_FILTER:
2337                 return -EINVAL;
2338         }
2339         return mixer_ioctl(s, cmd, arg);
2340 }
2341
2342
2343 static int cs4297a_release(struct inode *inode, struct file *file)
2344 {
2345         struct cs4297a_state *s =
2346             (struct cs4297a_state *) file->private_data;
2347
2348         CS_DBGOUT(CS_FUNCTION | CS_RELEASE, 2, printk(KERN_INFO
2349                  "cs4297a: cs4297a_release(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n",
2350                          (unsigned) inode, (unsigned) file, file->f_mode));
2351         VALIDATE_STATE(s);
2352
2353         if (file->f_mode & FMODE_WRITE) {
2354                 drain_dac(s, file->f_flags & O_NONBLOCK);
2355                 mutex_lock(&s->open_sem_dac);
2356                 stop_dac(s);
2357                 dealloc_dmabuf(s, &s->dma_dac);
2358                 s->open_mode &= ~FMODE_WRITE;
2359                 mutex_unlock(&s->open_sem_dac);
2360                 wake_up(&s->open_wait_dac);
2361         }
2362         if (file->f_mode & FMODE_READ) {
2363                 drain_adc(s, file->f_flags & O_NONBLOCK);
2364                 mutex_lock(&s->open_sem_adc);
2365                 stop_adc(s);
2366                 dealloc_dmabuf(s, &s->dma_adc);
2367                 s->open_mode &= ~FMODE_READ;
2368                 mutex_unlock(&s->open_sem_adc);
2369                 wake_up(&s->open_wait_adc);
2370         }
2371         return 0;
2372 }
2373
2374 static int cs4297a_open(struct inode *inode, struct file *file)
2375 {
2376         int minor = iminor(inode);
2377         struct cs4297a_state *s=NULL;
2378         struct list_head *entry;
2379
2380         CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
2381                 "cs4297a: cs4297a_open(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n",
2382                         (unsigned) inode, (unsigned) file, file->f_mode));
2383         CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
2384                 "cs4297a: status = %08x\n", (int)__raw_readq(SS_CSR(R_SER_STATUS_DEBUG))));
2385
2386         list_for_each(entry, &cs4297a_devs)
2387         {
2388                 s = list_entry(entry, struct cs4297a_state, list);
2389
2390                 if (!((s->dev_audio ^ minor) & ~0xf))
2391                         break;
2392         }
2393         if (entry == &cs4297a_devs)
2394                 return -ENODEV;
2395         if (!s) {
2396                 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
2397                         "cs4297a: cs4297a_open(): Error - unable to find audio state struct\n"));
2398                 return -ENODEV;
2399         }
2400         VALIDATE_STATE(s);
2401         file->private_data = s;
2402
2403         // wait for device to become free
2404         if (!(file->f_mode & (FMODE_WRITE | FMODE_READ))) {
2405                 CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2, printk(KERN_INFO
2406                          "cs4297a: cs4297a_open(): Error - must open READ and/or WRITE\n"));
2407                 return -ENODEV;
2408         }
2409         if (file->f_mode & FMODE_WRITE) {
2410                 if (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX)) != 0) {
2411                         printk(KERN_ERR "cs4297a: TX pipe needs to drain\n");
2412                         while (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX)))
2413                                 ;
2414                 }
2415
2416                 mutex_lock(&s->open_sem_dac);
2417                 while (s->open_mode & FMODE_WRITE) {
2418                         if (file->f_flags & O_NONBLOCK) {
2419                                 mutex_unlock(&s->open_sem_dac);
2420                                 return -EBUSY;
2421                         }
2422                         mutex_unlock(&s->open_sem_dac);
2423                         interruptible_sleep_on(&s->open_wait_dac);
2424
2425                         if (signal_pending(current)) {
2426                                 printk("open - sig pending\n");
2427                                 return -ERESTARTSYS;
2428                         }
2429                         mutex_lock(&s->open_sem_dac);
2430                 }
2431         }
2432         if (file->f_mode & FMODE_READ) {
2433                 mutex_lock(&s->open_sem_adc);
2434                 while (s->open_mode & FMODE_READ) {
2435                         if (file->f_flags & O_NONBLOCK) {
2436                                 mutex_unlock(&s->open_sem_adc);
2437                                 return -EBUSY;
2438                         }
2439                         mutex_unlock(&s->open_sem_adc);
2440                         interruptible_sleep_on(&s->open_wait_adc);
2441
2442                         if (signal_pending(current)) {
2443                                 printk("open - sig pending\n");
2444                                 return -ERESTARTSYS;
2445                         }
2446                         mutex_lock(&s->open_sem_adc);
2447                 }
2448         }
2449         s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
2450         if (file->f_mode & FMODE_READ) {
2451                 s->prop_adc.fmt = AFMT_S16_BE;
2452                 s->prop_adc.fmt_original = s->prop_adc.fmt;
2453                 s->prop_adc.channels = 2;
2454                 s->prop_adc.rate = 48000;
2455                 s->conversion = 0;
2456                 s->ena &= ~FMODE_READ;
2457                 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
2458                     s->dma_adc.subdivision = 0;
2459                 mutex_unlock(&s->open_sem_adc);
2460
2461                 if (prog_dmabuf_adc(s)) {
2462                         CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
2463                                 "cs4297a: adc Program dmabufs failed.\n"));
2464                         cs4297a_release(inode, file);
2465                         return -ENOMEM;
2466                 }
2467         }
2468         if (file->f_mode & FMODE_WRITE) {
2469                 s->prop_dac.fmt = AFMT_S16_BE;
2470                 s->prop_dac.fmt_original = s->prop_dac.fmt;
2471                 s->prop_dac.channels = 2;
2472                 s->prop_dac.rate = 48000;
2473                 s->conversion = 0;
2474                 s->ena &= ~FMODE_WRITE;
2475                 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
2476                     s->dma_dac.subdivision = 0;
2477                 mutex_unlock(&s->open_sem_dac);
2478
2479                 if (prog_dmabuf_dac(s)) {
2480                         CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
2481                                 "cs4297a: dac Program dmabufs failed.\n"));
2482                         cs4297a_release(inode, file);
2483                         return -ENOMEM;
2484                 }
2485         }
2486         CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2,
2487                   printk(KERN_INFO "cs4297a: cs4297a_open()- 0\n"));
2488         return nonseekable_open(inode, file);
2489 }
2490
2491
2492 // ******************************************************************************************
2493 //   Wave (audio) file operations struct.
2494 // ******************************************************************************************
2495 static /*const */ struct file_operations cs4297a_audio_fops = {
2496         .owner          = THIS_MODULE,
2497         .llseek         = no_llseek,
2498         .read           = cs4297a_read,
2499         .write          = cs4297a_write,
2500         .poll           = cs4297a_poll,
2501         .ioctl          = cs4297a_ioctl,
2502         .mmap           = cs4297a_mmap,
2503         .open           = cs4297a_open,
2504         .release        = cs4297a_release,
2505 };
2506
2507 static void cs4297a_interrupt(int irq, void *dev_id)
2508 {
2509         struct cs4297a_state *s = (struct cs4297a_state *) dev_id;
2510         u32 status;
2511
2512         status = __raw_readq(SS_CSR(R_SER_STATUS_DEBUG));
2513
2514         CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO
2515                  "cs4297a: cs4297a_interrupt() HISR=0x%.8x\n", status));
2516
2517 #if 0
2518         /* XXXKW what check *should* be done here? */
2519         if (!(status & (M_SYNCSER_RX_EOP_COUNT | M_SYNCSER_RX_OVERRUN | M_SYNCSER_RX_SYNC_ERR))) {
2520                 status = __raw_readq(SS_CSR(R_SER_STATUS));
2521                 printk(KERN_ERR "cs4297a: unexpected interrupt (status %08x)\n", status);
2522                 return;
2523         }
2524 #endif
2525
2526         if (status & M_SYNCSER_RX_SYNC_ERR) {
2527                 status = __raw_readq(SS_CSR(R_SER_STATUS));
2528                 printk(KERN_ERR "cs4297a: rx sync error (status %08x)\n", status);
2529                 return;
2530         }
2531
2532         if (status & M_SYNCSER_RX_OVERRUN) {
2533                 int newptr, i;
2534                 s->stats.rx_ovrrn++;
2535                 printk(KERN_ERR "cs4297a: receive FIFO overrun\n");
2536
2537                 /* Fix things up: get the receive descriptor pool
2538                    clean and give them back to the hardware */
2539                 while (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_RX)))
2540                         ;
2541                 newptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
2542                                      s->dma_adc.descrtab_phys) / sizeof(serdma_descr_t));
2543                 for (i=0; i<DMA_DESCR; i++) {
2544                         s->dma_adc.descrtab[i].descr_a &= ~M_DMA_SERRX_SOP;
2545                 }
2546                 s->dma_adc.swptr = s->dma_adc.hwptr = newptr;
2547                 s->dma_adc.count = 0;
2548                 s->dma_adc.sb_swptr = s->dma_adc.sb_hwptr = s->dma_adc.sample_buf;
2549                 __raw_writeq(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
2550         }
2551
2552         spin_lock(&s->lock);
2553         cs4297a_update_ptr(s,CS_TRUE);
2554         spin_unlock(&s->lock);
2555
2556         CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO
2557                   "cs4297a: cs4297a_interrupt()-\n"));
2558 }
2559
2560 #if 0
2561 static struct initvol {
2562         int mixch;
2563         int vol;
2564 } initvol[] __initdata = {
2565
2566         {SOUND_MIXER_WRITE_VOLUME, 0x4040},
2567         {SOUND_MIXER_WRITE_PCM, 0x4040},
2568         {SOUND_MIXER_WRITE_SYNTH, 0x4040},
2569         {SOUND_MIXER_WRITE_CD, 0x4040},
2570         {SOUND_MIXER_WRITE_LINE, 0x4040},
2571         {SOUND_MIXER_WRITE_LINE1, 0x4040},
2572         {SOUND_MIXER_WRITE_RECLEV, 0x0000},
2573         {SOUND_MIXER_WRITE_SPEAKER, 0x4040},
2574         {SOUND_MIXER_WRITE_MIC, 0x0000}
2575 };
2576 #endif
2577
2578 static int __init cs4297a_init(void)
2579 {
2580         struct cs4297a_state *s;
2581         u32 pwr, id;
2582         mm_segment_t fs;
2583         int rval;
2584 #ifndef CONFIG_BCM_CS4297A_CSWARM
2585         u64 cfg;
2586         int mdio_val;
2587 #endif
2588
2589         CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO
2590                 "cs4297a: cs4297a_init_module()+ \n"));
2591
2592 #ifndef CONFIG_BCM_CS4297A_CSWARM
2593         mdio_val = __raw_readq(KSEG1 + A_MAC_REGISTER(2, R_MAC_MDIO)) &
2594                 (M_MAC_MDIO_DIR|M_MAC_MDIO_OUT);
2595
2596         /* Check syscfg for synchronous serial on port 1 */
2597         cfg = __raw_readq(KSEG1 + A_SCD_SYSTEM_CFG);
2598         if (!(cfg & M_SYS_SER1_ENABLE)) {
2599                 __raw_writeq(cfg | M_SYS_SER1_ENABLE, KSEG1+A_SCD_SYSTEM_CFG);
2600                 cfg = __raw_readq(KSEG1 + A_SCD_SYSTEM_CFG);
2601                 if (!(cfg & M_SYS_SER1_ENABLE)) {
2602                   printk(KERN_INFO "cs4297a: serial port 1 not configured for synchronous operation\n");
2603                   return -1;
2604                 }
2605
2606                 printk(KERN_INFO "cs4297a: serial port 1 switching to synchronous operation\n");
2607
2608                 /* Force the codec (on SWARM) to reset by clearing
2609                    GENO, preserving MDIO (no effect on CSWARM) */
2610                 __raw_writeq(mdio_val, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO));
2611                 udelay(10);
2612         }
2613
2614         /* Now set GENO */
2615         __raw_writeq(mdio_val | M_MAC_GENC, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO));
2616         /* Give the codec some time to finish resetting (start the bit clock) */
2617         udelay(100);
2618 #endif
2619
2620         if (!(s = kzalloc(sizeof(struct cs4297a_state), GFP_KERNEL))) {
2621                 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
2622                       "cs4297a: probe() no memory for state struct.\n"));
2623                 return -1;
2624         }
2625         s->magic = CS4297a_MAGIC;
2626         init_waitqueue_head(&s->dma_adc.wait);
2627         init_waitqueue_head(&s->dma_dac.wait);
2628         init_waitqueue_head(&s->dma_adc.reg_wait);
2629         init_waitqueue_head(&s->dma_dac.reg_wait);
2630         init_waitqueue_head(&s->open_wait);
2631         init_waitqueue_head(&s->open_wait_adc);
2632         init_waitqueue_head(&s->open_wait_dac);
2633         mutex_init(&s->open_sem_adc);
2634         mutex_init(&s->open_sem_dac);
2635         spin_lock_init(&s->lock);
2636
2637         s->irq = K_INT_SER_1;
2638
2639         if (request_irq
2640             (s->irq, cs4297a_interrupt, 0, "Crystal CS4297a", s)) {
2641                 CS_DBGOUT(CS_INIT | CS_ERROR, 1,
2642                           printk(KERN_ERR "cs4297a: irq %u in use\n", s->irq));
2643                 goto err_irq;
2644         }
2645         if ((s->dev_audio = register_sound_dsp(&cs4297a_audio_fops, -1)) <
2646             0) {
2647                 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
2648                          "cs4297a: probe() register_sound_dsp() failed.\n"));
2649                 goto err_dev1;
2650         }
2651         if ((s->dev_mixer = register_sound_mixer(&cs4297a_mixer_fops, -1)) <
2652             0) {
2653                 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
2654                          "cs4297a: probe() register_sound_mixer() failed.\n"));
2655                 goto err_dev2;
2656         }
2657
2658         if (ser_init(s) || dma_init(s)) {
2659                 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
2660                          "cs4297a: ser_init failed.\n"));
2661                 goto err_dev3;
2662         }
2663
2664         do {
2665                 udelay(4000);
2666                 rval = cs4297a_read_ac97(s, AC97_POWER_CONTROL, &pwr);
2667         } while (!rval && (pwr != 0xf));
2668
2669         if (!rval) {
2670                 char *sb1250_duart_present;
2671
2672                 fs = get_fs();
2673                 set_fs(KERNEL_DS);
2674 #if 0
2675                 val = SOUND_MASK_LINE;
2676                 mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long) &val);
2677                 for (i = 0; i < ARRAY_SIZE(initvol); i++) {
2678                         val = initvol[i].vol;
2679                         mixer_ioctl(s, initvol[i].mixch, (unsigned long) &val);
2680                 }
2681 //                cs4297a_write_ac97(s, 0x18, 0x0808);
2682 #else
2683                 //                cs4297a_write_ac97(s, 0x5e, 0x180);
2684                 cs4297a_write_ac97(s, 0x02, 0x0808);
2685                 cs4297a_write_ac97(s, 0x18, 0x0808);
2686 #endif
2687                 set_fs(fs);
2688
2689                 list_add(&s->list, &cs4297a_devs);
2690
2691                 cs4297a_read_ac97(s, AC97_VENDOR_ID1, &id);
2692
2693                 sb1250_duart_present = symbol_get(sb1250_duart_present);
2694                 if (sb1250_duart_present)
2695                         sb1250_duart_present[1] = 0;
2696
2697                 printk(KERN_INFO "cs4297a: initialized (vendor id = %x)\n", id);
2698
2699                 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
2700                           printk(KERN_INFO "cs4297a: cs4297a_init_module()-\n"));
2701
2702                 return 0;
2703         }
2704
2705  err_dev3:
2706         unregister_sound_mixer(s->dev_mixer);
2707  err_dev2:
2708         unregister_sound_dsp(s->dev_audio);
2709  err_dev1:
2710         free_irq(s->irq, s);
2711  err_irq:
2712         kfree(s);
2713
2714         printk(KERN_INFO "cs4297a: initialization failed\n");
2715
2716         return -1;
2717 }
2718
2719 static void __exit cs4297a_cleanup(void)
2720 {
2721         /*
2722           XXXKW
2723            disable_irq, free_irq
2724            drain DMA queue
2725            disable DMA
2726            disable TX/RX
2727            free memory
2728         */
2729         CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
2730                   printk(KERN_INFO "cs4297a: cleanup_cs4297a() finished\n"));
2731 }
2732
2733 // ---------------------------------------------------------------------
2734
2735 MODULE_AUTHOR("Kip Walker, Broadcom Corp.");
2736 MODULE_DESCRIPTION("Cirrus Logic CS4297a Driver for Broadcom SWARM board");
2737
2738 // ---------------------------------------------------------------------
2739
2740 module_init(cs4297a_init);
2741 module_exit(cs4297a_cleanup);