2 * arch/s390/kernel/entry64.S
3 * S390 low-level entry points.
5 * Copyright (C) IBM Corp. 1999,2006
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
7 * Hartmut Penner (hp@de.ibm.com),
8 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
9 * Heiko Carstens <heiko.carstens@de.ibm.com>
12 #include <linux/sys.h>
13 #include <linux/linkage.h>
14 #include <linux/init.h>
15 #include <asm/cache.h>
16 #include <asm/lowcore.h>
17 #include <asm/errno.h>
18 #include <asm/ptrace.h>
19 #include <asm/thread_info.h>
20 #include <asm/asm-offsets.h>
21 #include <asm/unistd.h>
25 * Stack layout for the system_call stack entry.
26 * The first few entries are identical to the user_regs_struct.
28 SP_PTREGS = STACK_FRAME_OVERHEAD
29 SP_ARGS = STACK_FRAME_OVERHEAD + __PT_ARGS
30 SP_PSW = STACK_FRAME_OVERHEAD + __PT_PSW
31 SP_R0 = STACK_FRAME_OVERHEAD + __PT_GPRS
32 SP_R1 = STACK_FRAME_OVERHEAD + __PT_GPRS + 8
33 SP_R2 = STACK_FRAME_OVERHEAD + __PT_GPRS + 16
34 SP_R3 = STACK_FRAME_OVERHEAD + __PT_GPRS + 24
35 SP_R4 = STACK_FRAME_OVERHEAD + __PT_GPRS + 32
36 SP_R5 = STACK_FRAME_OVERHEAD + __PT_GPRS + 40
37 SP_R6 = STACK_FRAME_OVERHEAD + __PT_GPRS + 48
38 SP_R7 = STACK_FRAME_OVERHEAD + __PT_GPRS + 56
39 SP_R8 = STACK_FRAME_OVERHEAD + __PT_GPRS + 64
40 SP_R9 = STACK_FRAME_OVERHEAD + __PT_GPRS + 72
41 SP_R10 = STACK_FRAME_OVERHEAD + __PT_GPRS + 80
42 SP_R11 = STACK_FRAME_OVERHEAD + __PT_GPRS + 88
43 SP_R12 = STACK_FRAME_OVERHEAD + __PT_GPRS + 96
44 SP_R13 = STACK_FRAME_OVERHEAD + __PT_GPRS + 104
45 SP_R14 = STACK_FRAME_OVERHEAD + __PT_GPRS + 112
46 SP_R15 = STACK_FRAME_OVERHEAD + __PT_GPRS + 120
47 SP_ORIG_R2 = STACK_FRAME_OVERHEAD + __PT_ORIG_GPR2
48 SP_ILC = STACK_FRAME_OVERHEAD + __PT_ILC
49 SP_SVCNR = STACK_FRAME_OVERHEAD + __PT_SVCNR
50 SP_SIZE = STACK_FRAME_OVERHEAD + __PT_SIZE
52 STACK_SHIFT = PAGE_SHIFT + THREAD_ORDER
53 STACK_SIZE = 1 << STACK_SHIFT
55 _TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
56 _TIF_MCCK_PENDING | _TIF_RESTART_SVC | _TIF_SINGLE_STEP )
57 _TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
59 _TIF_SYSCALL = (_TIF_SYSCALL_TRACE>>8 | _TIF_SYSCALL_AUDIT>>8 | \
60 _TIF_SECCOMP>>8 | _TIF_SYSCALL_FTRACE>>8)
62 #define BASED(name) name-system_call(%r13)
64 #ifdef CONFIG_TRACE_IRQFLAGS
67 brasl %r14,trace_hardirqs_on_caller
72 brasl %r14,trace_hardirqs_off_caller
75 .macro TRACE_IRQS_CHECK
77 tm SP_PSW(%r15),0x03 # irqs enabled?
79 brasl %r14,trace_hardirqs_on_caller
81 0: brasl %r14,trace_hardirqs_off_caller
86 #define TRACE_IRQS_OFF
87 #define TRACE_IRQS_CHECK
91 .macro LOCKDEP_SYS_EXIT
92 tm SP_PSW+1(%r15),0x01 # returning to user ?
94 brasl %r14,lockdep_sys_exit
98 #define LOCKDEP_SYS_EXIT
101 .macro UPDATE_VTIME lc_from,lc_to,lc_sum
109 * Register usage in interrupt handlers:
110 * R9 - pointer to current task structure
111 * R13 - pointer to literal pool
112 * R14 - return register for function calls
113 * R15 - kernel stack pointer
116 .macro SAVE_ALL_BASE savearea
117 stmg %r12,%r15,\savearea
118 larl %r13,system_call
121 .macro SAVE_ALL_SVC psworg,savearea
123 lg %r15,__LC_KERNEL_STACK # problem state -> load ksp
126 .macro SAVE_ALL_SYNC psworg,savearea
128 tm \psworg+1,0x01 # test problem state bit
129 jz 2f # skip stack setup save
130 lg %r15,__LC_KERNEL_STACK # problem state -> load ksp
131 #ifdef CONFIG_CHECK_STACK
133 2: tml %r15,STACK_SIZE - CONFIG_STACK_GUARD
140 .macro SAVE_ALL_ASYNC psworg,savearea
142 tm \psworg+1,0x01 # test problem state bit
143 jnz 1f # from user -> load kernel stack
144 clc \psworg+8(8),BASED(.Lcritical_end)
146 clc \psworg+8(8),BASED(.Lcritical_start)
148 brasl %r14,cleanup_critical
149 tm 1(%r12),0x01 # retest problem state after cleanup
151 0: lg %r14,__LC_ASYNC_STACK # are we already on the async. stack ?
153 srag %r14,%r14,STACK_SHIFT
155 1: lg %r15,__LC_ASYNC_STACK # load async stack
156 #ifdef CONFIG_CHECK_STACK
158 2: tml %r15,STACK_SIZE - CONFIG_STACK_GUARD
165 .macro CREATE_STACK_FRAME psworg,savearea
166 aghi %r15,-SP_SIZE # make room for registers & psw
167 mvc SP_PSW(16,%r15),0(%r12) # move user PSW to stack
168 stg %r2,SP_ORIG_R2(%r15) # store original content of gpr 2
169 icm %r12,3,__LC_SVC_ILC
170 stmg %r0,%r11,SP_R0(%r15) # store gprs %r0-%r11 to kernel stack
171 st %r12,SP_SVCNR(%r15)
172 mvc SP_R12(32,%r15),\savearea # move %r12-%r15 to stack
174 stg %r12,__SF_BACKCHAIN(%r15)
177 .macro RESTORE_ALL psworg,sync
178 mvc \psworg(16),SP_PSW(%r15) # move user PSW to lowcore
180 ni \psworg+1,0xfd # clear wait state bit
182 lg %r14,__LC_VDSO_PER_CPU
183 lmg %r0,%r13,SP_R0(%r15) # load gprs 0-13 of user
185 mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
186 lmg %r14,%r15,SP_R14(%r15) # load grps 14-15 of user
187 lpswe \psworg # back to caller
191 * Scheduler resume function, called by switch_to
192 * gpr2 = (task_struct *) prev
193 * gpr3 = (task_struct *) next
199 tm __THREAD_per+4(%r3),0xe8 # is the new process using per ?
200 jz __switch_to_noper # if not we're fine
201 stctg %c9,%c11,__SF_EMPTY(%r15)# We are using per stuff
202 clc __THREAD_per(24,%r3),__SF_EMPTY(%r15)
203 je __switch_to_noper # we got away without bashing TLB's
204 lctlg %c9,%c11,__THREAD_per(%r3) # Nope we didn't
206 lg %r4,__THREAD_info(%r2) # get thread_info of prev
207 tm __TI_flags+7(%r4),_TIF_MCCK_PENDING # machine check pending?
208 jz __switch_to_no_mcck
209 ni __TI_flags+7(%r4),255-_TIF_MCCK_PENDING # clear flag in prev
210 lg %r4,__THREAD_info(%r3) # get thread_info of next
211 oi __TI_flags+7(%r4),_TIF_MCCK_PENDING # set it in next
213 stmg %r6,%r15,__SF_GPRS(%r15)# store __switch_to registers of prev task
214 stg %r15,__THREAD_ksp(%r2) # store kernel stack to prev->tss.ksp
215 lg %r15,__THREAD_ksp(%r3) # load kernel stack from next->tss.ksp
216 lmg %r6,%r15,__SF_GPRS(%r15)# load __switch_to registers of next task
217 stg %r3,__LC_CURRENT # __LC_CURRENT = current task struct
218 lctl %c4,%c4,__TASK_pid(%r3) # load pid to control reg. 4
219 lg %r3,__THREAD_info(%r3) # load thread_info from task struct
220 stg %r3,__LC_THREAD_INFO
222 stg %r3,__LC_KERNEL_STACK # __LC_KERNEL_STACK = new kernel stack
227 * SVC interrupt handler routine. System calls are synchronous events and
228 * are executed with interrupts enabled.
233 stpt __LC_SYNC_ENTER_TIMER
235 SAVE_ALL_BASE __LC_SAVE_AREA
236 SAVE_ALL_SVC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
237 CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA
238 llgh %r7,__LC_SVC_INT_CODE # get svc number from lowcore
240 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
242 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
244 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
246 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
247 ltgr %r7,%r7 # test for svc 0
249 # svc 0: system call number in %r1
250 cl %r1,BASED(.Lnr_syscalls)
252 lgfr %r7,%r1 # clear high word in r1
254 mvc SP_ARGS(8,%r15),SP_R7(%r15)
256 sth %r7,SP_SVCNR(%r15)
257 sllg %r7,%r7,2 # svc number * 4
258 larl %r10,sys_call_table
260 tm __TI_flags+5(%r9),(_TIF_31BIT>>16) # running in 31 bit mode ?
262 larl %r10,sys_call_table_emu # use 31 bit emulation system calls
265 tm __TI_flags+6(%r9),_TIF_SYSCALL
266 lgf %r8,0(%r7,%r10) # load address of system call routine
268 basr %r14,%r8 # call sys_xxxx
269 stg %r2,SP_R2(%r15) # store return value (change R2 on stack)
272 tm __TI_flags+7(%r9),_TIF_WORK_SVC
273 jnz sysc_work # there is work to do (signals etc.)
275 #ifdef CONFIG_TRACE_IRQFLAGS
276 larl %r1,sysc_restore_trace_psw
283 RESTORE_ALL __LC_RETURN_PSW,1
286 #ifdef CONFIG_TRACE_IRQFLAGS
288 .globl sysc_restore_trace_psw
289 sysc_restore_trace_psw:
290 .quad 0, sysc_restore_trace
294 # recheck if there is more work to do
297 tm __TI_flags+7(%r9),_TIF_WORK_SVC
298 jz sysc_restore # there is no work to do
300 # One of the work bits is on. Find out which one.
303 tm SP_PSW+1(%r15),0x01 # returning to user ?
305 tm __TI_flags+7(%r9),_TIF_MCCK_PENDING
307 tm __TI_flags+7(%r9),_TIF_NEED_RESCHED
309 tm __TI_flags+7(%r9),_TIF_SIGPENDING
311 tm __TI_flags+7(%r9),_TIF_NOTIFY_RESUME
312 jnz sysc_notify_resume
313 tm __TI_flags+7(%r9),_TIF_RESTART_SVC
315 tm __TI_flags+7(%r9),_TIF_SINGLE_STEP
321 # _TIF_NEED_RESCHED is set, call schedule
324 larl %r14,sysc_work_loop
325 jg schedule # return point is sysc_return
328 # _TIF_MCCK_PENDING is set, call handler
331 larl %r14,sysc_work_loop
332 jg s390_handle_mcck # TIF bit will be cleared by handler
335 # _TIF_SIGPENDING is set, call do_signal
338 ni __TI_flags+7(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP
339 la %r2,SP_PTREGS(%r15) # load pt_regs
340 brasl %r14,do_signal # call do_signal
341 tm __TI_flags+7(%r9),_TIF_RESTART_SVC
343 tm __TI_flags+7(%r9),_TIF_SINGLE_STEP
348 # _TIF_NOTIFY_RESUME is set, call do_notify_resume
351 la %r2,SP_PTREGS(%r15) # load pt_regs
352 larl %r14,sysc_work_loop
353 jg do_notify_resume # call do_notify_resume
356 # _TIF_RESTART_SVC is set, set up registers and restart svc
359 ni __TI_flags+7(%r9),255-_TIF_RESTART_SVC # clear TIF_RESTART_SVC
360 lg %r7,SP_R2(%r15) # load new svc number
361 mvc SP_R2(8,%r15),SP_ORIG_R2(%r15) # restore first argument
362 lmg %r2,%r6,SP_R2(%r15) # load svc arguments
363 j sysc_do_restart # restart svc
366 # _TIF_SINGLE_STEP is set, call do_single_step
369 ni __TI_flags+7(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP
370 xc SP_SVCNR(2,%r15),SP_SVCNR(%r15) # clear svc number
371 la %r2,SP_PTREGS(%r15) # address of register-save area
372 larl %r14,sysc_return # load adr. of system return
373 jg do_single_step # branch to do_sigtrap
376 # call tracehook_report_syscall_entry/tracehook_report_syscall_exit before
377 # and after the system call
380 la %r2,SP_PTREGS(%r15) # load pt_regs
384 brasl %r14,do_syscall_trace_enter
388 sllg %r7,%r2,2 # svc number *4
391 lmg %r3,%r6,SP_R3(%r15)
392 lg %r2,SP_ORIG_R2(%r15)
393 basr %r14,%r8 # call sys_xxx
394 stg %r2,SP_R2(%r15) # store return value
396 tm __TI_flags+6(%r9),_TIF_SYSCALL
398 la %r2,SP_PTREGS(%r15) # load pt_regs
399 larl %r14,sysc_return # return point is sysc_return
400 jg do_syscall_trace_exit
403 # a new process exits the kernel with ret_from_fork
407 lg %r13,__LC_SVC_NEW_PSW+8
408 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
409 tm SP_PSW+1(%r15),0x01 # forking a kernel thread ?
411 stg %r15,SP_R15(%r15) # store stack pointer for new kthread
412 0: brasl %r14,schedule_tail
414 stosm 24(%r15),0x03 # reenable interrupts
418 # kernel_execve function needs to deal with pt_regs that is not
423 stmg %r12,%r15,96(%r15)
426 stg %r14,__SF_BACKCHAIN(%r15)
427 la %r12,SP_PTREGS(%r15)
428 xc 0(__PT_SIZE,%r12),0(%r12)
434 lmg %r12,%r15,96(%r15)
437 0: stnsm __SF_EMPTY(%r15),0xfc # disable interrupts
438 lg %r15,__LC_KERNEL_STACK # load ksp
439 aghi %r15,-SP_SIZE # make room for registers & psw
440 lg %r13,__LC_SVC_NEW_PSW+8
441 lg %r9,__LC_THREAD_INFO
442 mvc SP_PTREGS(__PT_SIZE,%r15),0(%r12) # copy pt_regs
443 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
444 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
445 brasl %r14,execve_tail
449 * Program check handler routine
452 .globl pgm_check_handler
455 * First we need to check for a special case:
456 * Single stepping an instruction that disables the PER event mask will
457 * cause a PER event AFTER the mask has been set. Example: SVC or LPSW.
458 * For a single stepped SVC the program check handler gets control after
459 * the SVC new PSW has been loaded. But we want to execute the SVC first and
460 * then handle the PER event. Therefore we update the SVC old PSW to point
461 * to the pgm_check_handler and branch to the SVC handler after we checked
462 * if we have to load the kernel stack register.
463 * For every other possible cause for PER event without the PER mask set
464 * we just ignore the PER event (FIXME: is there anything we have to do
467 stpt __LC_SYNC_ENTER_TIMER
468 SAVE_ALL_BASE __LC_SAVE_AREA
469 tm __LC_PGM_INT_CODE+1,0x80 # check whether we got a per exception
470 jnz pgm_per # got per exception -> special case
471 SAVE_ALL_SYNC __LC_PGM_OLD_PSW,__LC_SAVE_AREA
472 CREATE_STACK_FRAME __LC_PGM_OLD_PSW,__LC_SAVE_AREA
473 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
475 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
476 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
477 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
479 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
480 mvc SP_ARGS(8,%r15),__LC_LAST_BREAK
482 lgf %r3,__LC_PGM_ILC # load program interruption code
487 larl %r1,pgm_check_table
488 lg %r1,0(%r8,%r1) # load address of handler routine
489 la %r2,SP_PTREGS(%r15) # address of register-save area
490 larl %r14,sysc_return
491 br %r1 # branch to interrupt-handler
494 # handle per exception
497 tm __LC_PGM_OLD_PSW,0x40 # test if per event recording is on
498 jnz pgm_per_std # ok, normal per event from user space
499 # ok its one of the special cases, now we need to find out which one
500 clc __LC_PGM_OLD_PSW(16),__LC_SVC_NEW_PSW
502 # no interesting special case, ignore PER event
503 lmg %r12,%r15,__LC_SAVE_AREA
504 lpswe __LC_PGM_OLD_PSW
507 # Normal per exception
510 SAVE_ALL_SYNC __LC_PGM_OLD_PSW,__LC_SAVE_AREA
511 CREATE_STACK_FRAME __LC_PGM_OLD_PSW,__LC_SAVE_AREA
512 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
514 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
515 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
516 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
518 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
520 lg %r1,__TI_task(%r9)
521 tm SP_PSW+1(%r15),0x01 # kernel per event ?
523 mvc __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID
524 mvc __THREAD_per+__PER_address(8,%r1),__LC_PER_ADDRESS
525 mvc __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID
526 oi __TI_flags+7(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP
527 lgf %r3,__LC_PGM_ILC # load program interruption code
529 ngr %r8,%r3 # clear per-event-bit and ilc
534 # it was a single stepped SVC that is causing all the trouble
537 SAVE_ALL_SYNC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
538 CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA
539 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
540 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
541 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
542 llgh %r7,__LC_SVC_INT_CODE # get svc number from lowcore
543 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
544 lg %r1,__TI_task(%r9)
545 mvc __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID
546 mvc __THREAD_per+__PER_address(8,%r1),__LC_PER_ADDRESS
547 mvc __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID
548 oi __TI_flags+7(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP
550 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
554 # per was called from kernel, must be kprobes
557 xc SP_SVCNR(2,%r15),SP_SVCNR(%r15) # clear svc number
558 la %r2,SP_PTREGS(%r15) # address of register-save area
559 larl %r14,sysc_restore # load adr. of system ret, no work
560 jg do_single_step # branch to do_single_step
563 * IO interrupt handler routine
565 .globl io_int_handler
568 stpt __LC_ASYNC_ENTER_TIMER
569 SAVE_ALL_BASE __LC_SAVE_AREA+32
570 SAVE_ALL_ASYNC __LC_IO_OLD_PSW,__LC_SAVE_AREA+32
571 CREATE_STACK_FRAME __LC_IO_OLD_PSW,__LC_SAVE_AREA+32
572 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
574 UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
575 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
576 mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
578 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
580 la %r2,SP_PTREGS(%r15) # address of register-save area
581 brasl %r14,do_IRQ # call standard irq handler
583 tm __TI_flags+7(%r9),_TIF_WORK_INT
584 jnz io_work # there is work to do (signals etc.)
586 #ifdef CONFIG_TRACE_IRQFLAGS
587 larl %r1,io_restore_trace_psw
594 RESTORE_ALL __LC_RETURN_PSW,0
597 #ifdef CONFIG_TRACE_IRQFLAGS
599 .globl io_restore_trace_psw
600 io_restore_trace_psw:
601 .quad 0, io_restore_trace
605 # There is work todo, we need to check if we return to userspace, then
606 # check, if we are in SIE, if yes leave it
609 tm SP_PSW+1(%r15),0x01 # returning to user ?
610 #ifndef CONFIG_PREEMPT
611 #if defined(CONFIG_KVM) || defined(CONFIG_KVM_MODULE)
612 jnz io_work_user # yes -> no need to check for SIE
613 la %r1, BASED(sie_opcode) # we return to kernel here
614 lg %r2, SP_PSW+8(%r15)
615 clc 0(2,%r1), 0(%r2) # is current instruction = SIE?
616 jne io_restore # no-> return to kernel
617 lg %r1, SP_PSW+8(%r15) # yes-> add 4 bytes to leave SIE
619 stg %r1, SP_PSW+8(%r15)
620 j io_restore # return to kernel
622 jno io_restore # no-> skip resched & signal
625 jnz io_work_user # yes -> do resched & signal
626 #if defined(CONFIG_KVM) || defined(CONFIG_KVM_MODULE)
627 la %r1, BASED(sie_opcode)
628 lg %r2, SP_PSW+8(%r15)
629 clc 0(2,%r1), 0(%r2) # is current instruction = SIE?
630 jne 0f # no -> leave PSW alone
631 lg %r1, SP_PSW+8(%r15) # yes-> add 4 bytes to leave SIE
633 stg %r1, SP_PSW+8(%r15)
636 # check for preemptive scheduling
637 icm %r0,15,__TI_precount(%r9)
638 jnz io_restore # preemption is disabled
639 # switch to kernel stack
642 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
643 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
646 tm __TI_flags+7(%r9),_TIF_NEED_RESCHED
648 larl %r14,io_resume_loop
649 jg preempt_schedule_irq
653 lg %r1,__LC_KERNEL_STACK
655 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
656 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
659 # One of the work bits is on. Find out which one.
660 # Checked are: _TIF_SIGPENDING, _TIF_RESTORE_SIGPENDING, _TIF_NEED_RESCHED
661 # and _TIF_MCCK_PENDING
664 tm __TI_flags+7(%r9),_TIF_MCCK_PENDING
666 tm __TI_flags+7(%r9),_TIF_NEED_RESCHED
668 tm __TI_flags+7(%r9),_TIF_SIGPENDING
670 tm __TI_flags+7(%r9),_TIF_NOTIFY_RESUME
675 #if defined(CONFIG_KVM) || defined(CONFIG_KVM_MODULE)
681 # _TIF_MCCK_PENDING is set, call handler
684 brasl %r14,s390_handle_mcck # TIF bit will be cleared by handler
688 # _TIF_NEED_RESCHED is set, call schedule
692 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
693 brasl %r14,schedule # call scheduler
694 stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts
696 tm __TI_flags+7(%r9),_TIF_WORK_INT
697 jz io_restore # there is no work to do
701 # _TIF_SIGPENDING or is set, call do_signal
705 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
706 la %r2,SP_PTREGS(%r15) # load pt_regs
707 brasl %r14,do_signal # call do_signal
708 stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts
713 # _TIF_NOTIFY_RESUME or is set, call do_notify_resume
717 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
718 la %r2,SP_PTREGS(%r15) # load pt_regs
719 brasl %r14,do_notify_resume # call do_notify_resume
720 stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts
725 * External interrupt handler routine
727 .globl ext_int_handler
730 stpt __LC_ASYNC_ENTER_TIMER
731 SAVE_ALL_BASE __LC_SAVE_AREA+32
732 SAVE_ALL_ASYNC __LC_EXT_OLD_PSW,__LC_SAVE_AREA+32
733 CREATE_STACK_FRAME __LC_EXT_OLD_PSW,__LC_SAVE_AREA+32
734 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
736 UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
737 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
738 mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
740 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
742 la %r2,SP_PTREGS(%r15) # address of register-save area
743 llgh %r3,__LC_EXT_INT_CODE # get interruption code
750 * Machine check handler routines
752 .globl mcck_int_handler
755 la %r1,4095 # revalidate r1
756 spt __LC_CPU_TIMER_SAVE_AREA-4095(%r1) # revalidate cpu timer
757 lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# revalidate gprs
758 SAVE_ALL_BASE __LC_SAVE_AREA+64
759 la %r12,__LC_MCK_OLD_PSW
760 tm __LC_MCCK_CODE,0x80 # system damage?
761 jo mcck_int_main # yes -> rest of mcck code invalid
763 mvc __LC_SAVE_AREA+104(8),__LC_ASYNC_ENTER_TIMER
764 mvc __LC_ASYNC_ENTER_TIMER(8),__LC_CPU_TIMER_SAVE_AREA-4095(%r14)
765 tm __LC_MCCK_CODE+5,0x02 # stored cpu timer value valid?
767 la %r14,__LC_SYNC_ENTER_TIMER
768 clc 0(8,%r14),__LC_ASYNC_ENTER_TIMER
770 la %r14,__LC_ASYNC_ENTER_TIMER
771 0: clc 0(8,%r14),__LC_EXIT_TIMER
773 la %r14,__LC_EXIT_TIMER
774 0: clc 0(8,%r14),__LC_LAST_UPDATE_TIMER
776 la %r14,__LC_LAST_UPDATE_TIMER
778 mvc __LC_ASYNC_ENTER_TIMER(8),0(%r14)
779 1: tm __LC_MCCK_CODE+2,0x09 # mwp + ia of old psw valid?
780 jno mcck_int_main # no -> skip cleanup critical
781 tm __LC_MCK_OLD_PSW+1,0x01 # test problem state bit
782 jnz mcck_int_main # from user -> load kernel stack
783 clc __LC_MCK_OLD_PSW+8(8),BASED(.Lcritical_end)
785 clc __LC_MCK_OLD_PSW+8(8),BASED(.Lcritical_start)
787 brasl %r14,cleanup_critical
789 lg %r14,__LC_PANIC_STACK # are we already on the panic stack?
791 srag %r14,%r14,PAGE_SHIFT
793 lg %r15,__LC_PANIC_STACK # load panic stack
794 0: CREATE_STACK_FRAME __LC_MCK_OLD_PSW,__LC_SAVE_AREA+64
795 tm __LC_MCCK_CODE+2,0x08 # mwp of old psw valid?
796 jno mcck_no_vtime # no -> no timer update
797 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
799 UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
800 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
801 mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
803 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
804 la %r2,SP_PTREGS(%r15) # load pt_regs
805 brasl %r14,s390_do_machine_check
806 tm SP_PSW+1(%r15),0x01 # returning to user ?
808 lg %r1,__LC_KERNEL_STACK # switch to kernel stack
810 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
811 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
813 stosm __SF_EMPTY(%r15),0x04 # turn dat on
814 tm __TI_flags+7(%r9),_TIF_MCCK_PENDING
817 brasl %r14,s390_handle_mcck
820 mvc __LC_RETURN_MCCK_PSW(16),SP_PSW(%r15) # move return PSW
821 ni __LC_RETURN_MCCK_PSW+1,0xfd # clear wait state bit
822 lmg %r0,%r15,SP_R0(%r15) # load gprs 0-15
823 mvc __LC_ASYNC_ENTER_TIMER(8),__LC_SAVE_AREA+104
824 tm __LC_RETURN_MCCK_PSW+1,0x01 # returning to user ?
827 0: lpswe __LC_RETURN_MCCK_PSW # back to caller
830 * Restart interruption handler, kick starter for additional CPUs
834 .globl restart_int_handler
838 spt restart_vtime-restart_base(%r1)
839 stck __LC_LAST_UPDATE_CLOCK
840 mvc __LC_LAST_UPDATE_TIMER(8),restart_vtime-restart_base(%r1)
841 mvc __LC_EXIT_TIMER(8),restart_vtime-restart_base(%r1)
842 lg %r15,__LC_SAVE_AREA+120 # load ksp
843 lghi %r10,__LC_CREGS_SAVE_AREA
844 lctlg %c0,%c15,0(%r10) # get new ctl regs
845 lghi %r10,__LC_AREGS_SAVE_AREA
847 lmg %r6,%r15,__SF_GPRS(%r15) # load registers from clone
848 lg %r1,__LC_THREAD_INFO
849 mvc __LC_USER_TIMER(8),__TI_user_timer(%r1)
850 mvc __LC_SYSTEM_TIMER(8),__TI_system_timer(%r1)
851 xc __LC_STEAL_TIMER(8),__LC_STEAL_TIMER
852 stosm __SF_EMPTY(%r15),0x04 # now we can turn dat on
856 .long 0x7fffffff,0xffffffff
860 * If we do not run with SMP enabled, let the new CPU crash ...
862 .globl restart_int_handler
866 lpswe restart_crash-restart_base(%r1)
869 .long 0x000a0000,0x00000000,0x00000000,0x00000000
873 #ifdef CONFIG_CHECK_STACK
875 * The synchronous or the asynchronous stack overflowed. We are dead.
876 * No need to properly save the registers, we are going to panic anyway.
877 * Setup a pt_regs so that show_trace can provide a good call trace.
880 lg %r15,__LC_PANIC_STACK # change to panic stack
882 mvc SP_PSW(16,%r15),0(%r12) # move user PSW to stack
883 stmg %r0,%r11,SP_R0(%r15) # store gprs %r0-%r11 to kernel stack
884 la %r1,__LC_SAVE_AREA
885 chi %r12,__LC_SVC_OLD_PSW
887 chi %r12,__LC_PGM_OLD_PSW
889 la %r1,__LC_SAVE_AREA+32
890 0: mvc SP_R12(32,%r15),0(%r1) # move %r12-%r15 to stack
891 mvc SP_ARGS(8,%r15),__LC_LAST_BREAK
892 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) # clear back chain
893 la %r2,SP_PTREGS(%r15) # load pt_regs
894 jg kernel_stack_overflow
897 cleanup_table_system_call:
898 .quad system_call, sysc_do_svc
899 cleanup_table_sysc_return:
900 .quad sysc_return, sysc_leave
901 cleanup_table_sysc_leave:
902 .quad sysc_leave, sysc_done
903 cleanup_table_sysc_work_loop:
904 .quad sysc_work_loop, sysc_work_done
905 cleanup_table_io_return:
906 .quad io_return, io_leave
907 cleanup_table_io_leave:
908 .quad io_leave, io_done
909 cleanup_table_io_work_loop:
910 .quad io_work_loop, io_work_done
913 clc 8(8,%r12),BASED(cleanup_table_system_call)
915 clc 8(8,%r12),BASED(cleanup_table_system_call+8)
916 jl cleanup_system_call
918 clc 8(8,%r12),BASED(cleanup_table_sysc_return)
920 clc 8(8,%r12),BASED(cleanup_table_sysc_return+8)
921 jl cleanup_sysc_return
923 clc 8(8,%r12),BASED(cleanup_table_sysc_leave)
925 clc 8(8,%r12),BASED(cleanup_table_sysc_leave+8)
926 jl cleanup_sysc_leave
928 clc 8(8,%r12),BASED(cleanup_table_sysc_work_loop)
930 clc 8(8,%r12),BASED(cleanup_table_sysc_work_loop+8)
931 jl cleanup_sysc_return
933 clc 8(8,%r12),BASED(cleanup_table_io_return)
935 clc 8(8,%r12),BASED(cleanup_table_io_return+8)
938 clc 8(8,%r12),BASED(cleanup_table_io_leave)
940 clc 8(8,%r12),BASED(cleanup_table_io_leave+8)
943 clc 8(8,%r12),BASED(cleanup_table_io_work_loop)
945 clc 8(8,%r12),BASED(cleanup_table_io_work_loop+8)
951 mvc __LC_RETURN_PSW(16),0(%r12)
952 cghi %r12,__LC_MCK_OLD_PSW
954 la %r12,__LC_SAVE_AREA+32
956 0: la %r12,__LC_SAVE_AREA+64
958 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+8)
960 mvc __LC_SYNC_ENTER_TIMER(8),__LC_ASYNC_ENTER_TIMER
961 0: clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+16)
963 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn)
965 mvc __LC_SAVE_AREA(32),0(%r12)
967 stg %r12,__LC_SAVE_AREA+96 # argh
968 SAVE_ALL_SYNC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
969 CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA
970 lg %r12,__LC_SAVE_AREA+96 # argh
972 llgh %r7,__LC_SVC_INT_CODE
974 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+24)
976 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
978 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+32)
980 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
982 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
983 mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_system_call+8)
984 la %r12,__LC_RETURN_PSW
986 cleanup_system_call_insn:
994 mvc __LC_RETURN_PSW(8),0(%r12)
995 mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_sysc_return)
996 la %r12,__LC_RETURN_PSW
1000 clc 8(8,%r12),BASED(cleanup_sysc_leave_insn)
1002 clc 8(8,%r12),BASED(cleanup_sysc_leave_insn+8)
1004 mvc __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER
1005 0: mvc __LC_RETURN_PSW(16),SP_PSW(%r15)
1006 cghi %r12,__LC_MCK_OLD_PSW
1008 mvc __LC_SAVE_AREA+64(32),SP_R12(%r15)
1010 1: mvc __LC_SAVE_AREA+32(32),SP_R12(%r15)
1011 2: lmg %r0,%r11,SP_R0(%r15)
1012 lg %r15,SP_R15(%r15)
1013 3: la %r12,__LC_RETURN_PSW
1015 cleanup_sysc_leave_insn:
1017 .quad sysc_done - 16
1020 mvc __LC_RETURN_PSW(8),0(%r12)
1021 mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_io_work_loop)
1022 la %r12,__LC_RETURN_PSW
1026 clc 8(8,%r12),BASED(cleanup_io_leave_insn)
1028 clc 8(8,%r12),BASED(cleanup_io_leave_insn+8)
1030 mvc __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER
1031 0: mvc __LC_RETURN_PSW(16),SP_PSW(%r15)
1032 cghi %r12,__LC_MCK_OLD_PSW
1034 mvc __LC_SAVE_AREA+64(32),SP_R12(%r15)
1036 1: mvc __LC_SAVE_AREA+32(32),SP_R12(%r15)
1037 2: lmg %r0,%r11,SP_R0(%r15)
1038 lg %r15,SP_R15(%r15)
1039 3: la %r12,__LC_RETURN_PSW
1041 cleanup_io_leave_insn:
1050 .Lnr_syscalls: .long NR_syscalls
1051 .L0x0130: .short 0x130
1052 .L0x0140: .short 0x140
1053 .L0x0150: .short 0x150
1054 .L0x0160: .short 0x160
1055 .L0x0170: .short 0x170
1057 .quad __critical_start
1059 .quad __critical_end
1061 .section .rodata, "a"
1062 #define SYSCALL(esa,esame,emu) .long esame
1063 .globl sys_call_table
1065 #include "syscalls.S"
1068 #ifdef CONFIG_COMPAT
1070 #define SYSCALL(esa,esame,emu) .long emu
1072 #include "syscalls.S"