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[linux-2.6] / arch / mips / sibyte / sb1250 / irq.c
1 /*
2  * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * as published by the Free Software Foundation; either version 2
7  * of the License, or (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
17  */
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/linkage.h>
21 #include <linux/interrupt.h>
22 #include <linux/spinlock.h>
23 #include <linux/smp.h>
24 #include <linux/mm.h>
25 #include <linux/slab.h>
26 #include <linux/kernel_stat.h>
27
28 #include <asm/errno.h>
29 #include <asm/signal.h>
30 #include <asm/system.h>
31 #include <asm/io.h>
32
33 #include <asm/sibyte/sb1250_regs.h>
34 #include <asm/sibyte/sb1250_int.h>
35 #include <asm/sibyte/sb1250_uart.h>
36 #include <asm/sibyte/sb1250_scd.h>
37 #include <asm/sibyte/sb1250.h>
38
39 /*
40  * These are the routines that handle all the low level interrupt stuff.
41  * Actions handled here are: initialization of the interrupt map, requesting of
42  * interrupt lines by handlers, dispatching if interrupts to handlers, probing
43  * for interrupt lines
44  */
45
46
47 static void end_sb1250_irq(unsigned int irq);
48 static void enable_sb1250_irq(unsigned int irq);
49 static void disable_sb1250_irq(unsigned int irq);
50 static void ack_sb1250_irq(unsigned int irq);
51 #ifdef CONFIG_SMP
52 static void sb1250_set_affinity(unsigned int irq, cpumask_t mask);
53 #endif
54
55 #ifdef CONFIG_SIBYTE_HAS_LDT
56 extern unsigned long ldt_eoi_space;
57 #endif
58
59 #ifdef CONFIG_KGDB
60 static int kgdb_irq;
61
62 /* Default to UART1 */
63 int kgdb_port = 1;
64 #ifdef CONFIG_SIBYTE_SB1250_DUART
65 extern char sb1250_duart_present[];
66 #endif
67 #endif
68
69 static struct irq_chip sb1250_irq_type = {
70         .typename = "SB1250-IMR",
71         .ack = ack_sb1250_irq,
72         .mask = disable_sb1250_irq,
73         .mask_ack = ack_sb1250_irq,
74         .unmask = enable_sb1250_irq,
75         .end = end_sb1250_irq,
76 #ifdef CONFIG_SMP
77         .set_affinity = sb1250_set_affinity
78 #endif
79 };
80
81 /* Store the CPU id (not the logical number) */
82 int sb1250_irq_owner[SB1250_NR_IRQS];
83
84 DEFINE_SPINLOCK(sb1250_imr_lock);
85
86 void sb1250_mask_irq(int cpu, int irq)
87 {
88         unsigned long flags;
89         u64 cur_ints;
90
91         spin_lock_irqsave(&sb1250_imr_lock, flags);
92         cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
93                                         R_IMR_INTERRUPT_MASK));
94         cur_ints |= (((u64) 1) << irq);
95         ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
96                                         R_IMR_INTERRUPT_MASK));
97         spin_unlock_irqrestore(&sb1250_imr_lock, flags);
98 }
99
100 void sb1250_unmask_irq(int cpu, int irq)
101 {
102         unsigned long flags;
103         u64 cur_ints;
104
105         spin_lock_irqsave(&sb1250_imr_lock, flags);
106         cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
107                                         R_IMR_INTERRUPT_MASK));
108         cur_ints &= ~(((u64) 1) << irq);
109         ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
110                                         R_IMR_INTERRUPT_MASK));
111         spin_unlock_irqrestore(&sb1250_imr_lock, flags);
112 }
113
114 #ifdef CONFIG_SMP
115 static void sb1250_set_affinity(unsigned int irq, cpumask_t mask)
116 {
117         int i = 0, old_cpu, cpu, int_on;
118         u64 cur_ints;
119         struct irq_desc *desc = irq_desc + irq;
120         unsigned long flags;
121
122         i = first_cpu(mask);
123
124         if (cpus_weight(mask) > 1) {
125                 printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq);
126                 return;
127         }
128
129         /* Convert logical CPU to physical CPU */
130         cpu = cpu_logical_map(i);
131
132         /* Protect against other affinity changers and IMR manipulation */
133         spin_lock_irqsave(&desc->lock, flags);
134         spin_lock(&sb1250_imr_lock);
135
136         /* Swizzle each CPU's IMR (but leave the IP selection alone) */
137         old_cpu = sb1250_irq_owner[irq];
138         cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) +
139                                         R_IMR_INTERRUPT_MASK));
140         int_on = !(cur_ints & (((u64) 1) << irq));
141         if (int_on) {
142                 /* If it was on, mask it */
143                 cur_ints |= (((u64) 1) << irq);
144                 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +
145                                         R_IMR_INTERRUPT_MASK));
146         }
147         sb1250_irq_owner[irq] = cpu;
148         if (int_on) {
149                 /* unmask for the new CPU */
150                 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
151                                         R_IMR_INTERRUPT_MASK));
152                 cur_ints &= ~(((u64) 1) << irq);
153                 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
154                                         R_IMR_INTERRUPT_MASK));
155         }
156         spin_unlock(&sb1250_imr_lock);
157         spin_unlock_irqrestore(&desc->lock, flags);
158 }
159 #endif
160
161 /*****************************************************************************/
162
163 static void disable_sb1250_irq(unsigned int irq)
164 {
165         sb1250_mask_irq(sb1250_irq_owner[irq], irq);
166 }
167
168 static void enable_sb1250_irq(unsigned int irq)
169 {
170         sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
171 }
172
173
174 static void ack_sb1250_irq(unsigned int irq)
175 {
176 #ifdef CONFIG_SIBYTE_HAS_LDT
177         u64 pending;
178
179         /*
180          * If the interrupt was an HT interrupt, now is the time to
181          * clear it.  NOTE: we assume the HT bridge was set up to
182          * deliver the interrupts to all CPUs (which makes affinity
183          * changing easier for us)
184          */
185         pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
186                                                     R_IMR_LDT_INTERRUPT)));
187         pending &= ((u64)1 << (irq));
188         if (pending) {
189                 int i;
190                 for (i=0; i<NR_CPUS; i++) {
191                         int cpu;
192 #ifdef CONFIG_SMP
193                         cpu = cpu_logical_map(i);
194 #else
195                         cpu = i;
196 #endif
197                         /*
198                          * Clear for all CPUs so an affinity switch
199                          * doesn't find an old status
200                          */
201                         __raw_writeq(pending,
202                                      IOADDR(A_IMR_REGISTER(cpu,
203                                                 R_IMR_LDT_INTERRUPT_CLR)));
204                 }
205
206                 /*
207                  * Generate EOI.  For Pass 1 parts, EOI is a nop.  For
208                  * Pass 2, the LDT world may be edge-triggered, but
209                  * this EOI shouldn't hurt.  If they are
210                  * level-sensitive, the EOI is required.
211                  */
212                 *(uint32_t *)(ldt_eoi_space+(irq<<16)+(7<<2)) = 0;
213         }
214 #endif
215         sb1250_mask_irq(sb1250_irq_owner[irq], irq);
216 }
217
218
219 static void end_sb1250_irq(unsigned int irq)
220 {
221         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
222                 sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
223         }
224 }
225
226
227 void __init init_sb1250_irqs(void)
228 {
229         int i;
230
231         for (i = 0; i < SB1250_NR_IRQS; i++) {
232                 set_irq_chip(i, &sb1250_irq_type);
233                 sb1250_irq_owner[i] = 0;
234         }
235 }
236
237
238 static irqreturn_t  sb1250_dummy_handler(int irq, void *dev_id)
239 {
240         return IRQ_NONE;
241 }
242
243 static struct irqaction sb1250_dummy_action = {
244         .handler = sb1250_dummy_handler,
245         .flags   = 0,
246         .mask    = CPU_MASK_NONE,
247         .name    = "sb1250-private",
248         .next    = NULL,
249         .dev_id  = 0
250 };
251
252 int sb1250_steal_irq(int irq)
253 {
254         struct irq_desc *desc = irq_desc + irq;
255         unsigned long flags;
256         int retval = 0;
257
258         if (irq >= SB1250_NR_IRQS)
259                 return -EINVAL;
260
261         spin_lock_irqsave(&desc->lock,flags);
262         /* Don't allow sharing at all for these */
263         if (desc->action != NULL)
264                 retval = -EBUSY;
265         else {
266                 desc->action = &sb1250_dummy_action;
267                 desc->depth = 0;
268         }
269         spin_unlock_irqrestore(&desc->lock,flags);
270         return 0;
271 }
272
273 /*
274  *  arch_init_irq is called early in the boot sequence from init/main.c via
275  *  init_IRQ.  It is responsible for setting up the interrupt mapper and
276  *  installing the handler that will be responsible for dispatching interrupts
277  *  to the "right" place.
278  */
279 /*
280  * For now, map all interrupts to IP[2].  We could save
281  * some cycles by parceling out system interrupts to different
282  * IP lines, but keep it simple for bringup.  We'll also direct
283  * all interrupts to a single CPU; we should probably route
284  * PCI and LDT to one cpu and everything else to the other
285  * to balance the load a bit.
286  *
287  * On the second cpu, everything is set to IP5, which is
288  * ignored, EXCEPT the mailbox interrupt.  That one is
289  * set to IP[2] so it is handled.  This is needed so we
290  * can do cross-cpu function calls, as requred by SMP
291  */
292
293 #define IMR_IP2_VAL     K_INT_MAP_I0
294 #define IMR_IP3_VAL     K_INT_MAP_I1
295 #define IMR_IP4_VAL     K_INT_MAP_I2
296 #define IMR_IP5_VAL     K_INT_MAP_I3
297 #define IMR_IP6_VAL     K_INT_MAP_I4
298
299 void __init arch_init_irq(void)
300 {
301
302         unsigned int i;
303         u64 tmp;
304         unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
305                 STATUSF_IP1 | STATUSF_IP0;
306
307         /* Default everything to IP2 */
308         for (i = 0; i < SB1250_NR_IRQS; i++) {  /* was I0 */
309                 __raw_writeq(IMR_IP2_VAL,
310                              IOADDR(A_IMR_REGISTER(0,
311                                                    R_IMR_INTERRUPT_MAP_BASE) +
312                                     (i << 3)));
313                 __raw_writeq(IMR_IP2_VAL,
314                              IOADDR(A_IMR_REGISTER(1,
315                                                    R_IMR_INTERRUPT_MAP_BASE) +
316                                     (i << 3)));
317         }
318
319         init_sb1250_irqs();
320
321         /*
322          * Map the high 16 bits of the mailbox registers to IP[3], for
323          * inter-cpu messages
324          */
325         /* Was I1 */
326         __raw_writeq(IMR_IP3_VAL,
327                      IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
328                             (K_INT_MBOX_0 << 3)));
329         __raw_writeq(IMR_IP3_VAL,
330                      IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
331                             (K_INT_MBOX_0 << 3)));
332
333         /* Clear the mailboxes.  The firmware may leave them dirty */
334         __raw_writeq(0xffffffffffffffffULL,
335                      IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
336         __raw_writeq(0xffffffffffffffffULL,
337                      IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
338
339         /* Mask everything except the mailbox registers for both cpus */
340         tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
341         __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
342         __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
343
344         sb1250_steal_irq(K_INT_MBOX_0);
345
346         /*
347          * Note that the timer interrupts are also mapped, but this is
348          * done in sb1250_time_init().  Also, the profiling driver
349          * does its own management of IP7.
350          */
351
352 #ifdef CONFIG_KGDB
353         imask |= STATUSF_IP6;
354 #endif
355         /* Enable necessary IPs, disable the rest */
356         change_c0_status(ST0_IM, imask);
357
358 #ifdef CONFIG_KGDB
359         if (kgdb_flag) {
360                 kgdb_irq = K_INT_UART_0 + kgdb_port;
361
362 #ifdef CONFIG_SIBYTE_SB1250_DUART
363                 sb1250_duart_present[kgdb_port] = 0;
364 #endif
365                 /* Setup uart 1 settings, mapper */
366                 __raw_writeq(M_DUART_IMR_BRK,
367                              IOADDR(A_DUART_IMRREG(kgdb_port)));
368
369                 sb1250_steal_irq(kgdb_irq);
370                 __raw_writeq(IMR_IP6_VAL,
371                              IOADDR(A_IMR_REGISTER(0,
372                                                    R_IMR_INTERRUPT_MAP_BASE) +
373                                     (kgdb_irq << 3)));
374                 sb1250_unmask_irq(0, kgdb_irq);
375         }
376 #endif
377 }
378
379 #ifdef CONFIG_KGDB
380
381 #include <linux/delay.h>
382
383 #define duart_out(reg, val)     csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
384 #define duart_in(reg)           csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
385
386 static void sb1250_kgdb_interrupt(void)
387 {
388         /*
389          * Clear break-change status (allow some time for the remote
390          * host to stop the break, since we would see another
391          * interrupt on the end-of-break too)
392          */
393         kstat_this_cpu.irqs[kgdb_irq]++;
394         mdelay(500);
395         duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT |
396                                 M_DUART_RX_EN | M_DUART_TX_EN);
397         set_async_breakpoint(&get_irq_regs()->cp0_epc);
398 }
399
400 #endif  /* CONFIG_KGDB */
401
402 extern void sb1250_timer_interrupt(void);
403 extern void sb1250_mailbox_interrupt(void);
404
405 asmlinkage void plat_irq_dispatch(void)
406 {
407         unsigned int pending;
408
409 #ifdef CONFIG_SIBYTE_SB1250_PROF
410         /* Set compare to count to silence count/compare timer interrupts */
411         write_c0_compare(read_c0_count());
412 #endif
413
414         /*
415          * What a pain. We have to be really careful saving the upper 32 bits
416          * of any * register across function calls if we don't want them
417          * trashed--since were running in -o32, the calling routing never saves
418          * the full 64 bits of a register across a function call.  Being the
419          * interrupt handler, we're guaranteed that interrupts are disabled
420          * during this code so we don't have to worry about random interrupts
421          * blasting the high 32 bits.
422          */
423
424         pending = read_c0_cause() & read_c0_status();
425
426 #ifdef CONFIG_SIBYTE_SB1250_PROF
427         if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */
428                 sbprof_cpu_intr();
429         else
430 #endif
431
432         if (pending & CAUSEF_IP4)
433                 sb1250_timer_interrupt();
434
435 #ifdef CONFIG_SMP
436         else if (pending & CAUSEF_IP3)
437                 sb1250_mailbox_interrupt();
438 #endif
439
440 #ifdef CONFIG_KGDB
441         else if (pending & CAUSEF_IP6)                  /* KGDB (uart 1) */
442                 sb1250_kgdb_interrupt();
443 #endif
444
445         else if (pending & CAUSEF_IP2) {
446                 unsigned long long mask;
447
448                 /*
449                  * Default...we've hit an IP[2] interrupt, which means we've
450                  * got to check the 1250 interrupt registers to figure out what
451                  * to do.  Need to detect which CPU we're on, now that
452                  * smp_affinity is supported.
453                  */
454                 mask = __raw_readq(IOADDR(A_IMR_REGISTER(smp_processor_id(),
455                                               R_IMR_INTERRUPT_STATUS_BASE)));
456                 if (mask)
457                         do_IRQ(fls64(mask) - 1);
458                 else
459                         spurious_interrupt();
460         } else
461                 spurious_interrupt();
462 }