Pull button into test branch
[linux-2.6] / arch / x86_64 / kernel / nmi.c
1 /*
2  *  linux/arch/x86_64/nmi.c
3  *
4  *  NMI watchdog support on APIC systems
5  *
6  *  Started by Ingo Molnar <mingo@redhat.com>
7  *
8  *  Fixes:
9  *  Mikael Pettersson   : AMD K7 support for local APIC NMI watchdog.
10  *  Mikael Pettersson   : Power Management for local APIC NMI watchdog.
11  *  Pavel Machek and
12  *  Mikael Pettersson   : PM converted to driver model. Disable/enable API.
13  */
14
15 #include <linux/nmi.h>
16 #include <linux/mm.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/sysdev.h>
21 #include <linux/sysctl.h>
22 #include <linux/kprobes.h>
23 #include <linux/cpumask.h>
24
25 #include <asm/smp.h>
26 #include <asm/nmi.h>
27 #include <asm/proto.h>
28 #include <asm/kdebug.h>
29 #include <asm/mce.h>
30 #include <asm/intel_arch_perfmon.h>
31
32 int unknown_nmi_panic;
33 int nmi_watchdog_enabled;
34 int panic_on_unrecovered_nmi;
35
36 /* perfctr_nmi_owner tracks the ownership of the perfctr registers:
37  * evtsel_nmi_owner tracks the ownership of the event selection
38  * - different performance counters/ event selection may be reserved for
39  *   different subsystems this reservation system just tries to coordinate
40  *   things a little
41  */
42 static DEFINE_PER_CPU(unsigned, perfctr_nmi_owner);
43 static DEFINE_PER_CPU(unsigned, evntsel_nmi_owner[2]);
44
45 static cpumask_t backtrace_mask = CPU_MASK_NONE;
46
47 /* this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
48  * offset from MSR_P4_BSU_ESCR0.  It will be the max for all platforms (for now)
49  */
50 #define NMI_MAX_COUNTER_BITS 66
51
52 /* nmi_active:
53  * >0: the lapic NMI watchdog is active, but can be disabled
54  * <0: the lapic NMI watchdog has not been set up, and cannot
55  *     be enabled
56  *  0: the lapic NMI watchdog is disabled, but can be enabled
57  */
58 atomic_t nmi_active = ATOMIC_INIT(0);           /* oprofile uses this */
59 int panic_on_timeout;
60
61 unsigned int nmi_watchdog = NMI_DEFAULT;
62 static unsigned int nmi_hz = HZ;
63
64 struct nmi_watchdog_ctlblk {
65         int enabled;
66         u64 check_bit;
67         unsigned int cccr_msr;
68         unsigned int perfctr_msr;  /* the MSR to reset in NMI handler */
69         unsigned int evntsel_msr;  /* the MSR to select the events to handle */
70 };
71 static DEFINE_PER_CPU(struct nmi_watchdog_ctlblk, nmi_watchdog_ctlblk);
72
73 /* local prototypes */
74 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu);
75
76 /* converts an msr to an appropriate reservation bit */
77 static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
78 {
79         /* returns the bit offset of the performance counter register */
80         switch (boot_cpu_data.x86_vendor) {
81         case X86_VENDOR_AMD:
82                 return (msr - MSR_K7_PERFCTR0);
83         case X86_VENDOR_INTEL:
84                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
85                         return (msr - MSR_ARCH_PERFMON_PERFCTR0);
86                 else
87                         return (msr - MSR_P4_BPU_PERFCTR0);
88         }
89         return 0;
90 }
91
92 /* converts an msr to an appropriate reservation bit */
93 static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
94 {
95         /* returns the bit offset of the event selection register */
96         switch (boot_cpu_data.x86_vendor) {
97         case X86_VENDOR_AMD:
98                 return (msr - MSR_K7_EVNTSEL0);
99         case X86_VENDOR_INTEL:
100                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
101                         return (msr - MSR_ARCH_PERFMON_EVENTSEL0);
102                 else
103                         return (msr - MSR_P4_BSU_ESCR0);
104         }
105         return 0;
106 }
107
108 /* checks for a bit availability (hack for oprofile) */
109 int avail_to_resrv_perfctr_nmi_bit(unsigned int counter)
110 {
111         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
112
113         return (!test_bit(counter, &__get_cpu_var(perfctr_nmi_owner)));
114 }
115
116 /* checks the an msr for availability */
117 int avail_to_resrv_perfctr_nmi(unsigned int msr)
118 {
119         unsigned int counter;
120
121         counter = nmi_perfctr_msr_to_bit(msr);
122         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
123
124         return (!test_bit(counter, &__get_cpu_var(perfctr_nmi_owner)));
125 }
126
127 int reserve_perfctr_nmi(unsigned int msr)
128 {
129         unsigned int counter;
130
131         counter = nmi_perfctr_msr_to_bit(msr);
132         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
133
134         if (!test_and_set_bit(counter, &__get_cpu_var(perfctr_nmi_owner)))
135                 return 1;
136         return 0;
137 }
138
139 void release_perfctr_nmi(unsigned int msr)
140 {
141         unsigned int counter;
142
143         counter = nmi_perfctr_msr_to_bit(msr);
144         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
145
146         clear_bit(counter, &__get_cpu_var(perfctr_nmi_owner));
147 }
148
149 int reserve_evntsel_nmi(unsigned int msr)
150 {
151         unsigned int counter;
152
153         counter = nmi_evntsel_msr_to_bit(msr);
154         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
155
156         if (!test_and_set_bit(counter, &__get_cpu_var(evntsel_nmi_owner)))
157                 return 1;
158         return 0;
159 }
160
161 void release_evntsel_nmi(unsigned int msr)
162 {
163         unsigned int counter;
164
165         counter = nmi_evntsel_msr_to_bit(msr);
166         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
167
168         clear_bit(counter, &__get_cpu_var(evntsel_nmi_owner));
169 }
170
171 static __cpuinit inline int nmi_known_cpu(void)
172 {
173         switch (boot_cpu_data.x86_vendor) {
174         case X86_VENDOR_AMD:
175                 return boot_cpu_data.x86 == 15;
176         case X86_VENDOR_INTEL:
177                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
178                         return 1;
179                 else
180                         return (boot_cpu_data.x86 == 15);
181         }
182         return 0;
183 }
184
185 /* Run after command line and cpu_init init, but before all other checks */
186 void nmi_watchdog_default(void)
187 {
188         if (nmi_watchdog != NMI_DEFAULT)
189                 return;
190         if (nmi_known_cpu())
191                 nmi_watchdog = NMI_LOCAL_APIC;
192         else
193                 nmi_watchdog = NMI_IO_APIC;
194 }
195
196 static int endflag __initdata = 0;
197
198 #ifdef CONFIG_SMP
199 /* The performance counters used by NMI_LOCAL_APIC don't trigger when
200  * the CPU is idle. To make sure the NMI watchdog really ticks on all
201  * CPUs during the test make them busy.
202  */
203 static __init void nmi_cpu_busy(void *data)
204 {
205         local_irq_enable_in_hardirq();
206         /* Intentionally don't use cpu_relax here. This is
207            to make sure that the performance counter really ticks,
208            even if there is a simulator or similar that catches the
209            pause instruction. On a real HT machine this is fine because
210            all other CPUs are busy with "useless" delay loops and don't
211            care if they get somewhat less cycles. */
212         while (endflag == 0)
213                 mb();
214 }
215 #endif
216
217 int __init check_nmi_watchdog (void)
218 {
219         int *counts;
220         int cpu;
221
222         if ((nmi_watchdog == NMI_NONE) || (nmi_watchdog == NMI_DEFAULT))
223                 return 0;
224
225         if (!atomic_read(&nmi_active))
226                 return 0;
227
228         counts = kmalloc(NR_CPUS * sizeof(int), GFP_KERNEL);
229         if (!counts)
230                 return -1;
231
232         printk(KERN_INFO "testing NMI watchdog ... ");
233
234 #ifdef CONFIG_SMP
235         if (nmi_watchdog == NMI_LOCAL_APIC)
236                 smp_call_function(nmi_cpu_busy, (void *)&endflag, 0, 0);
237 #endif
238
239         for (cpu = 0; cpu < NR_CPUS; cpu++)
240                 counts[cpu] = cpu_pda(cpu)->__nmi_count;
241         local_irq_enable();
242         mdelay((10*1000)/nmi_hz); // wait 10 ticks
243
244         for_each_online_cpu(cpu) {
245                 if (!per_cpu(nmi_watchdog_ctlblk, cpu).enabled)
246                         continue;
247                 if (cpu_pda(cpu)->__nmi_count - counts[cpu] <= 5) {
248                         printk("CPU#%d: NMI appears to be stuck (%d->%d)!\n",
249                                cpu,
250                                counts[cpu],
251                                cpu_pda(cpu)->__nmi_count);
252                         per_cpu(nmi_watchdog_ctlblk, cpu).enabled = 0;
253                         atomic_dec(&nmi_active);
254                 }
255         }
256         if (!atomic_read(&nmi_active)) {
257                 kfree(counts);
258                 atomic_set(&nmi_active, -1);
259                 endflag = 1;
260                 return -1;
261         }
262         endflag = 1;
263         printk("OK.\n");
264
265         /* now that we know it works we can reduce NMI frequency to
266            something more reasonable; makes a difference in some configs */
267         if (nmi_watchdog == NMI_LOCAL_APIC) {
268                 struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
269
270                 nmi_hz = 1;
271                 /*
272                  * On Intel CPUs with ARCH_PERFMON only 32 bits in the counter
273                  * are writable, with higher bits sign extending from bit 31.
274                  * So, we can only program the counter with 31 bit values and
275                  * 32nd bit should be 1, for 33.. to be 1.
276                  * Find the appropriate nmi_hz
277                  */
278                 if (wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0 &&
279                         ((u64)cpu_khz * 1000) > 0x7fffffffULL) {
280                         nmi_hz = ((u64)cpu_khz * 1000) / 0x7fffffffUL + 1;
281                 }
282         }
283
284         kfree(counts);
285         return 0;
286 }
287
288 int __init setup_nmi_watchdog(char *str)
289 {
290         int nmi;
291
292         if (!strncmp(str,"panic",5)) {
293                 panic_on_timeout = 1;
294                 str = strchr(str, ',');
295                 if (!str)
296                         return 1;
297                 ++str;
298         }
299
300         get_option(&str, &nmi);
301
302         if ((nmi >= NMI_INVALID) || (nmi < NMI_NONE))
303                 return 0;
304
305         if ((nmi == NMI_LOCAL_APIC) && (nmi_known_cpu() == 0))
306                 return 0;  /* no lapic support */
307         nmi_watchdog = nmi;
308         return 1;
309 }
310
311 __setup("nmi_watchdog=", setup_nmi_watchdog);
312
313 static void disable_lapic_nmi_watchdog(void)
314 {
315         BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
316
317         if (atomic_read(&nmi_active) <= 0)
318                 return;
319
320         on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
321
322         BUG_ON(atomic_read(&nmi_active) != 0);
323 }
324
325 static void enable_lapic_nmi_watchdog(void)
326 {
327         BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
328
329         /* are we already enabled */
330         if (atomic_read(&nmi_active) != 0)
331                 return;
332
333         /* are we lapic aware */
334         if (nmi_known_cpu() <= 0)
335                 return;
336
337         on_each_cpu(setup_apic_nmi_watchdog, NULL, 0, 1);
338         touch_nmi_watchdog();
339 }
340
341 void disable_timer_nmi_watchdog(void)
342 {
343         BUG_ON(nmi_watchdog != NMI_IO_APIC);
344
345         if (atomic_read(&nmi_active) <= 0)
346                 return;
347
348         disable_irq(0);
349         on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
350
351         BUG_ON(atomic_read(&nmi_active) != 0);
352 }
353
354 void enable_timer_nmi_watchdog(void)
355 {
356         BUG_ON(nmi_watchdog != NMI_IO_APIC);
357
358         if (atomic_read(&nmi_active) == 0) {
359                 touch_nmi_watchdog();
360                 on_each_cpu(setup_apic_nmi_watchdog, NULL, 0, 1);
361                 enable_irq(0);
362         }
363 }
364
365 #ifdef CONFIG_PM
366
367 static int nmi_pm_active; /* nmi_active before suspend */
368
369 static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state)
370 {
371         /* only CPU0 goes here, other CPUs should be offline */
372         nmi_pm_active = atomic_read(&nmi_active);
373         stop_apic_nmi_watchdog(NULL);
374         BUG_ON(atomic_read(&nmi_active) != 0);
375         return 0;
376 }
377
378 static int lapic_nmi_resume(struct sys_device *dev)
379 {
380         /* only CPU0 goes here, other CPUs should be offline */
381         if (nmi_pm_active > 0) {
382                 setup_apic_nmi_watchdog(NULL);
383                 touch_nmi_watchdog();
384         }
385         return 0;
386 }
387
388 static struct sysdev_class nmi_sysclass = {
389         set_kset_name("lapic_nmi"),
390         .resume         = lapic_nmi_resume,
391         .suspend        = lapic_nmi_suspend,
392 };
393
394 static struct sys_device device_lapic_nmi = {
395         .id             = 0,
396         .cls    = &nmi_sysclass,
397 };
398
399 static int __init init_lapic_nmi_sysfs(void)
400 {
401         int error;
402
403         /* should really be a BUG_ON but b/c this is an
404          * init call, it just doesn't work.  -dcz
405          */
406         if (nmi_watchdog != NMI_LOCAL_APIC)
407                 return 0;
408
409         if ( atomic_read(&nmi_active) < 0 )
410                 return 0;
411
412         error = sysdev_class_register(&nmi_sysclass);
413         if (!error)
414                 error = sysdev_register(&device_lapic_nmi);
415         return error;
416 }
417 /* must come after the local APIC's device_initcall() */
418 late_initcall(init_lapic_nmi_sysfs);
419
420 #endif  /* CONFIG_PM */
421
422 /*
423  * Activate the NMI watchdog via the local APIC.
424  * Original code written by Keith Owens.
425  */
426
427 /* Note that these events don't tick when the CPU idles. This means
428    the frequency varies with CPU load. */
429
430 #define K7_EVNTSEL_ENABLE       (1 << 22)
431 #define K7_EVNTSEL_INT          (1 << 20)
432 #define K7_EVNTSEL_OS           (1 << 17)
433 #define K7_EVNTSEL_USR          (1 << 16)
434 #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING    0x76
435 #define K7_NMI_EVENT            K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
436
437 static int setup_k7_watchdog(void)
438 {
439         unsigned int perfctr_msr, evntsel_msr;
440         unsigned int evntsel;
441         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
442
443         perfctr_msr = MSR_K7_PERFCTR0;
444         evntsel_msr = MSR_K7_EVNTSEL0;
445         if (!reserve_perfctr_nmi(perfctr_msr))
446                 goto fail;
447
448         if (!reserve_evntsel_nmi(evntsel_msr))
449                 goto fail1;
450
451         /* Simulator may not support it */
452         if (checking_wrmsrl(evntsel_msr, 0UL))
453                 goto fail2;
454         wrmsrl(perfctr_msr, 0UL);
455
456         evntsel = K7_EVNTSEL_INT
457                 | K7_EVNTSEL_OS
458                 | K7_EVNTSEL_USR
459                 | K7_NMI_EVENT;
460
461         /* setup the timer */
462         wrmsr(evntsel_msr, evntsel, 0);
463         wrmsrl(perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
464         apic_write(APIC_LVTPC, APIC_DM_NMI);
465         evntsel |= K7_EVNTSEL_ENABLE;
466         wrmsr(evntsel_msr, evntsel, 0);
467
468         wd->perfctr_msr = perfctr_msr;
469         wd->evntsel_msr = evntsel_msr;
470         wd->cccr_msr = 0;  //unused
471         wd->check_bit = 1ULL<<63;
472         return 1;
473 fail2:
474         release_evntsel_nmi(evntsel_msr);
475 fail1:
476         release_perfctr_nmi(perfctr_msr);
477 fail:
478         return 0;
479 }
480
481 static void stop_k7_watchdog(void)
482 {
483         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
484
485         wrmsr(wd->evntsel_msr, 0, 0);
486
487         release_evntsel_nmi(wd->evntsel_msr);
488         release_perfctr_nmi(wd->perfctr_msr);
489 }
490
491 /* Note that these events don't tick when the CPU idles. This means
492    the frequency varies with CPU load. */
493
494 #define MSR_P4_MISC_ENABLE_PERF_AVAIL   (1<<7)
495 #define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
496 #define P4_ESCR_OS              (1<<3)
497 #define P4_ESCR_USR             (1<<2)
498 #define P4_CCCR_OVF_PMI0        (1<<26)
499 #define P4_CCCR_OVF_PMI1        (1<<27)
500 #define P4_CCCR_THRESHOLD(N)    ((N)<<20)
501 #define P4_CCCR_COMPLEMENT      (1<<19)
502 #define P4_CCCR_COMPARE         (1<<18)
503 #define P4_CCCR_REQUIRED        (3<<16)
504 #define P4_CCCR_ESCR_SELECT(N)  ((N)<<13)
505 #define P4_CCCR_ENABLE          (1<<12)
506 #define P4_CCCR_OVF             (1<<31)
507 /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
508    CRU_ESCR0 (with any non-null event selector) through a complemented
509    max threshold. [IA32-Vol3, Section 14.9.9] */
510
511 static int setup_p4_watchdog(void)
512 {
513         unsigned int perfctr_msr, evntsel_msr, cccr_msr;
514         unsigned int evntsel, cccr_val;
515         unsigned int misc_enable, dummy;
516         unsigned int ht_num;
517         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
518
519         rdmsr(MSR_IA32_MISC_ENABLE, misc_enable, dummy);
520         if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
521                 return 0;
522
523 #ifdef CONFIG_SMP
524         /* detect which hyperthread we are on */
525         if (smp_num_siblings == 2) {
526                 unsigned int ebx, apicid;
527
528                 ebx = cpuid_ebx(1);
529                 apicid = (ebx >> 24) & 0xff;
530                 ht_num = apicid & 1;
531         } else
532 #endif
533                 ht_num = 0;
534
535         /* performance counters are shared resources
536          * assign each hyperthread its own set
537          * (re-use the ESCR0 register, seems safe
538          * and keeps the cccr_val the same)
539          */
540         if (!ht_num) {
541                 /* logical cpu 0 */
542                 perfctr_msr = MSR_P4_IQ_PERFCTR0;
543                 evntsel_msr = MSR_P4_CRU_ESCR0;
544                 cccr_msr = MSR_P4_IQ_CCCR0;
545                 cccr_val = P4_CCCR_OVF_PMI0 | P4_CCCR_ESCR_SELECT(4);
546         } else {
547                 /* logical cpu 1 */
548                 perfctr_msr = MSR_P4_IQ_PERFCTR1;
549                 evntsel_msr = MSR_P4_CRU_ESCR0;
550                 cccr_msr = MSR_P4_IQ_CCCR1;
551                 cccr_val = P4_CCCR_OVF_PMI1 | P4_CCCR_ESCR_SELECT(4);
552         }
553
554         if (!reserve_perfctr_nmi(perfctr_msr))
555                 goto fail;
556
557         if (!reserve_evntsel_nmi(evntsel_msr))
558                 goto fail1;
559
560         evntsel = P4_ESCR_EVENT_SELECT(0x3F)
561                 | P4_ESCR_OS
562                 | P4_ESCR_USR;
563
564         cccr_val |= P4_CCCR_THRESHOLD(15)
565                  | P4_CCCR_COMPLEMENT
566                  | P4_CCCR_COMPARE
567                  | P4_CCCR_REQUIRED;
568
569         wrmsr(evntsel_msr, evntsel, 0);
570         wrmsr(cccr_msr, cccr_val, 0);
571         wrmsrl(perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
572         apic_write(APIC_LVTPC, APIC_DM_NMI);
573         cccr_val |= P4_CCCR_ENABLE;
574         wrmsr(cccr_msr, cccr_val, 0);
575
576         wd->perfctr_msr = perfctr_msr;
577         wd->evntsel_msr = evntsel_msr;
578         wd->cccr_msr = cccr_msr;
579         wd->check_bit = 1ULL<<39;
580         return 1;
581 fail1:
582         release_perfctr_nmi(perfctr_msr);
583 fail:
584         return 0;
585 }
586
587 static void stop_p4_watchdog(void)
588 {
589         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
590
591         wrmsr(wd->cccr_msr, 0, 0);
592         wrmsr(wd->evntsel_msr, 0, 0);
593
594         release_evntsel_nmi(wd->evntsel_msr);
595         release_perfctr_nmi(wd->perfctr_msr);
596 }
597
598 #define ARCH_PERFMON_NMI_EVENT_SEL      ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL
599 #define ARCH_PERFMON_NMI_EVENT_UMASK    ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK
600
601 static int setup_intel_arch_watchdog(void)
602 {
603         unsigned int ebx;
604         union cpuid10_eax eax;
605         unsigned int unused;
606         unsigned int perfctr_msr, evntsel_msr;
607         unsigned int evntsel;
608         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
609
610         /*
611          * Check whether the Architectural PerfMon supports
612          * Unhalted Core Cycles Event or not.
613          * NOTE: Corresponding bit = 0 in ebx indicates event present.
614          */
615         cpuid(10, &(eax.full), &ebx, &unused, &unused);
616         if ((eax.split.mask_length < (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX+1)) ||
617             (ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
618                 goto fail;
619
620         perfctr_msr = MSR_ARCH_PERFMON_PERFCTR0;
621         evntsel_msr = MSR_ARCH_PERFMON_EVENTSEL0;
622
623         if (!reserve_perfctr_nmi(perfctr_msr))
624                 goto fail;
625
626         if (!reserve_evntsel_nmi(evntsel_msr))
627                 goto fail1;
628
629         wrmsrl(perfctr_msr, 0UL);
630
631         evntsel = ARCH_PERFMON_EVENTSEL_INT
632                 | ARCH_PERFMON_EVENTSEL_OS
633                 | ARCH_PERFMON_EVENTSEL_USR
634                 | ARCH_PERFMON_NMI_EVENT_SEL
635                 | ARCH_PERFMON_NMI_EVENT_UMASK;
636
637         /* setup the timer */
638         wrmsr(evntsel_msr, evntsel, 0);
639         wrmsrl(perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
640
641         apic_write(APIC_LVTPC, APIC_DM_NMI);
642         evntsel |= ARCH_PERFMON_EVENTSEL0_ENABLE;
643         wrmsr(evntsel_msr, evntsel, 0);
644
645         wd->perfctr_msr = perfctr_msr;
646         wd->evntsel_msr = evntsel_msr;
647         wd->cccr_msr = 0;  //unused
648         wd->check_bit = 1ULL << (eax.split.bit_width - 1);
649         return 1;
650 fail1:
651         release_perfctr_nmi(perfctr_msr);
652 fail:
653         return 0;
654 }
655
656 static void stop_intel_arch_watchdog(void)
657 {
658         unsigned int ebx;
659         union cpuid10_eax eax;
660         unsigned int unused;
661         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
662
663         /*
664          * Check whether the Architectural PerfMon supports
665          * Unhalted Core Cycles Event or not.
666          * NOTE: Corresponding bit = 0 in ebx indicates event present.
667          */
668         cpuid(10, &(eax.full), &ebx, &unused, &unused);
669         if ((eax.split.mask_length < (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX+1)) ||
670             (ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
671                 return;
672
673         wrmsr(wd->evntsel_msr, 0, 0);
674
675         release_evntsel_nmi(wd->evntsel_msr);
676         release_perfctr_nmi(wd->perfctr_msr);
677 }
678
679 void setup_apic_nmi_watchdog(void *unused)
680 {
681         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
682
683         /* only support LOCAL and IO APICs for now */
684         if ((nmi_watchdog != NMI_LOCAL_APIC) &&
685             (nmi_watchdog != NMI_IO_APIC))
686                 return;
687
688         if (wd->enabled == 1)
689                 return;
690
691         /* cheap hack to support suspend/resume */
692         /* if cpu0 is not active neither should the other cpus */
693         if ((smp_processor_id() != 0) && (atomic_read(&nmi_active) <= 0))
694                 return;
695
696         if (nmi_watchdog == NMI_LOCAL_APIC) {
697                 switch (boot_cpu_data.x86_vendor) {
698                 case X86_VENDOR_AMD:
699                         if (strstr(boot_cpu_data.x86_model_id, "Screwdriver"))
700                                 return;
701                         if (!setup_k7_watchdog())
702                                 return;
703                         break;
704                 case X86_VENDOR_INTEL:
705                         if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
706                                 if (!setup_intel_arch_watchdog())
707                                         return;
708                                 break;
709                         }
710                         if (!setup_p4_watchdog())
711                                 return;
712                         break;
713                 default:
714                         return;
715                 }
716         }
717         wd->enabled = 1;
718         atomic_inc(&nmi_active);
719 }
720
721 void stop_apic_nmi_watchdog(void *unused)
722 {
723         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
724
725         /* only support LOCAL and IO APICs for now */
726         if ((nmi_watchdog != NMI_LOCAL_APIC) &&
727             (nmi_watchdog != NMI_IO_APIC))
728                 return;
729
730         if (wd->enabled == 0)
731                 return;
732
733         if (nmi_watchdog == NMI_LOCAL_APIC) {
734                 switch (boot_cpu_data.x86_vendor) {
735                 case X86_VENDOR_AMD:
736                         if (strstr(boot_cpu_data.x86_model_id, "Screwdriver"))
737                                 return;
738                         stop_k7_watchdog();
739                         break;
740                 case X86_VENDOR_INTEL:
741                         if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
742                                 stop_intel_arch_watchdog();
743                                 break;
744                         }
745                         stop_p4_watchdog();
746                         break;
747                 default:
748                         return;
749                 }
750         }
751         wd->enabled = 0;
752         atomic_dec(&nmi_active);
753 }
754
755 /*
756  * the best way to detect whether a CPU has a 'hard lockup' problem
757  * is to check it's local APIC timer IRQ counts. If they are not
758  * changing then that CPU has some problem.
759  *
760  * as these watchdog NMI IRQs are generated on every CPU, we only
761  * have to check the current processor.
762  */
763
764 static DEFINE_PER_CPU(unsigned, last_irq_sum);
765 static DEFINE_PER_CPU(local_t, alert_counter);
766 static DEFINE_PER_CPU(int, nmi_touch);
767
768 void touch_nmi_watchdog (void)
769 {
770         if (nmi_watchdog > 0) {
771                 unsigned cpu;
772
773                 /*
774                  * Tell other CPUs to reset their alert counters. We cannot
775                  * do it ourselves because the alert count increase is not
776                  * atomic.
777                  */
778                 for_each_present_cpu (cpu)
779                         per_cpu(nmi_touch, cpu) = 1;
780         }
781
782         touch_softlockup_watchdog();
783 }
784
785 int __kprobes nmi_watchdog_tick(struct pt_regs * regs, unsigned reason)
786 {
787         int sum;
788         int touched = 0;
789         int cpu = smp_processor_id();
790         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
791         u64 dummy;
792         int rc=0;
793
794         /* check for other users first */
795         if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT)
796                         == NOTIFY_STOP) {
797                 rc = 1;
798                 touched = 1;
799         }
800
801         sum = read_pda(apic_timer_irqs);
802         if (__get_cpu_var(nmi_touch)) {
803                 __get_cpu_var(nmi_touch) = 0;
804                 touched = 1;
805         }
806
807         if (cpu_isset(cpu, backtrace_mask)) {
808                 static DEFINE_SPINLOCK(lock);   /* Serialise the printks */
809
810                 spin_lock(&lock);
811                 printk("NMI backtrace for cpu %d\n", cpu);
812                 dump_stack();
813                 spin_unlock(&lock);
814                 cpu_clear(cpu, backtrace_mask);
815         }
816
817 #ifdef CONFIG_X86_MCE
818         /* Could check oops_in_progress here too, but it's safer
819            not too */
820         if (atomic_read(&mce_entry) > 0)
821                 touched = 1;
822 #endif
823         /* if the apic timer isn't firing, this cpu isn't doing much */
824         if (!touched && __get_cpu_var(last_irq_sum) == sum) {
825                 /*
826                  * Ayiee, looks like this CPU is stuck ...
827                  * wait a few IRQs (5 seconds) before doing the oops ...
828                  */
829                 local_inc(&__get_cpu_var(alert_counter));
830                 if (local_read(&__get_cpu_var(alert_counter)) == 5*nmi_hz)
831                         die_nmi("NMI Watchdog detected LOCKUP on CPU %d\n", regs,
832                                 panic_on_timeout);
833         } else {
834                 __get_cpu_var(last_irq_sum) = sum;
835                 local_set(&__get_cpu_var(alert_counter), 0);
836         }
837
838         /* see if the nmi watchdog went off */
839         if (wd->enabled) {
840                 if (nmi_watchdog == NMI_LOCAL_APIC) {
841                         rdmsrl(wd->perfctr_msr, dummy);
842                         if (dummy & wd->check_bit){
843                                 /* this wasn't a watchdog timer interrupt */
844                                 goto done;
845                         }
846
847                         /* only Intel uses the cccr msr */
848                         if (wd->cccr_msr != 0) {
849                                 /*
850                                  * P4 quirks:
851                                  * - An overflown perfctr will assert its interrupt
852                                  *   until the OVF flag in its CCCR is cleared.
853                                  * - LVTPC is masked on interrupt and must be
854                                  *   unmasked by the LVTPC handler.
855                                  */
856                                 rdmsrl(wd->cccr_msr, dummy);
857                                 dummy &= ~P4_CCCR_OVF;
858                                 wrmsrl(wd->cccr_msr, dummy);
859                                 apic_write(APIC_LVTPC, APIC_DM_NMI);
860                         } else if (wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0) {
861                                 /*
862                                  * ArchPerfom/Core Duo needs to re-unmask
863                                  * the apic vector
864                                  */
865                                 apic_write(APIC_LVTPC, APIC_DM_NMI);
866                         }
867                         /* start the cycle over again */
868                         wrmsrl(wd->perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
869                         rc = 1;
870                 } else  if (nmi_watchdog == NMI_IO_APIC) {
871                         /* don't know how to accurately check for this.
872                          * just assume it was a watchdog timer interrupt
873                          * This matches the old behaviour.
874                          */
875                         rc = 1;
876                 } else
877                         printk(KERN_WARNING "Unknown enabled NMI hardware?!\n");
878         }
879 done:
880         return rc;
881 }
882
883 asmlinkage __kprobes void do_nmi(struct pt_regs * regs, long error_code)
884 {
885         nmi_enter();
886         add_pda(__nmi_count,1);
887         default_do_nmi(regs);
888         nmi_exit();
889 }
890
891 int do_nmi_callback(struct pt_regs * regs, int cpu)
892 {
893 #ifdef CONFIG_SYSCTL
894         if (unknown_nmi_panic)
895                 return unknown_nmi_panic_callback(regs, cpu);
896 #endif
897         return 0;
898 }
899
900 #ifdef CONFIG_SYSCTL
901
902 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu)
903 {
904         unsigned char reason = get_nmi_reason();
905         char buf[64];
906
907         sprintf(buf, "NMI received for unknown reason %02x\n", reason);
908         die_nmi(buf, regs, 1);  /* Always panic here */
909         return 0;
910 }
911
912 /*
913  * proc handler for /proc/sys/kernel/nmi
914  */
915 int proc_nmi_enabled(struct ctl_table *table, int write, struct file *file,
916                         void __user *buffer, size_t *length, loff_t *ppos)
917 {
918         int old_state;
919
920         nmi_watchdog_enabled = (atomic_read(&nmi_active) > 0) ? 1 : 0;
921         old_state = nmi_watchdog_enabled;
922         proc_dointvec(table, write, file, buffer, length, ppos);
923         if (!!old_state == !!nmi_watchdog_enabled)
924                 return 0;
925
926         if (atomic_read(&nmi_active) < 0) {
927                 printk( KERN_WARNING "NMI watchdog is permanently disabled\n");
928                 return -EIO;
929         }
930
931         /* if nmi_watchdog is not set yet, then set it */
932         nmi_watchdog_default();
933
934         if (nmi_watchdog == NMI_LOCAL_APIC) {
935                 if (nmi_watchdog_enabled)
936                         enable_lapic_nmi_watchdog();
937                 else
938                         disable_lapic_nmi_watchdog();
939         } else {
940                 printk( KERN_WARNING
941                         "NMI watchdog doesn't know what hardware to touch\n");
942                 return -EIO;
943         }
944         return 0;
945 }
946
947 #endif
948
949 void __trigger_all_cpu_backtrace(void)
950 {
951         int i;
952
953         backtrace_mask = cpu_online_map;
954         /* Wait for up to 10 seconds for all CPUs to do the backtrace */
955         for (i = 0; i < 10 * 1000; i++) {
956                 if (cpus_empty(backtrace_mask))
957                         break;
958                 mdelay(1);
959         }
960 }
961
962 EXPORT_SYMBOL(nmi_active);
963 EXPORT_SYMBOL(nmi_watchdog);
964 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi);
965 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);
966 EXPORT_SYMBOL(reserve_perfctr_nmi);
967 EXPORT_SYMBOL(release_perfctr_nmi);
968 EXPORT_SYMBOL(reserve_evntsel_nmi);
969 EXPORT_SYMBOL(release_evntsel_nmi);
970 EXPORT_SYMBOL(disable_timer_nmi_watchdog);
971 EXPORT_SYMBOL(enable_timer_nmi_watchdog);
972 EXPORT_SYMBOL(touch_nmi_watchdog);