Pull acpica into release branch
[linux-2.6] / drivers / infiniband / hw / ipath / ipath_init_chip.c
1 /*
2  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include <linux/pci.h>
34 #include <linux/netdevice.h>
35 #include <linux/vmalloc.h>
36
37 #include "ipath_kernel.h"
38 #include "ips_common.h"
39
40 /*
41  * min buffers we want to have per port, after driver
42  */
43 #define IPATH_MIN_USER_PORT_BUFCNT 8
44
45 /*
46  * Number of ports we are configured to use (to allow for more pio
47  * buffers per port, etc.)  Zero means use chip value.
48  */
49 static ushort ipath_cfgports;
50
51 module_param_named(cfgports, ipath_cfgports, ushort, S_IRUGO);
52 MODULE_PARM_DESC(cfgports, "Set max number of ports to use");
53
54 /*
55  * Number of buffers reserved for driver (layered drivers and SMA
56  * send).  Reserved at end of buffer list.   Initialized based on
57  * number of PIO buffers if not set via module interface.
58  * The problem with this is that it's global, but we'll use different
59  * numbers for different chip types.  So the default value is not
60  * very useful.  I've redefined it for the 1.3 release so that it's
61  * zero unless set by the user to something else, in which case we
62  * try to respect it.
63  */
64 static ushort ipath_kpiobufs;
65
66 static int ipath_set_kpiobufs(const char *val, struct kernel_param *kp);
67
68 module_param_call(kpiobufs, ipath_set_kpiobufs, param_get_ushort,
69                   &ipath_kpiobufs, S_IWUSR | S_IRUGO);
70 MODULE_PARM_DESC(kpiobufs, "Set number of PIO buffers for driver");
71
72 /**
73  * create_port0_egr - allocate the eager TID buffers
74  * @dd: the infinipath device
75  *
76  * This code is now quite different for user and kernel, because
77  * the kernel uses skb's, for the accelerated network performance.
78  * This is the kernel (port0) version.
79  *
80  * Allocate the eager TID buffers and program them into infinipath.
81  * We use the network layer alloc_skb() allocator to allocate the
82  * memory, and either use the buffers as is for things like SMA
83  * packets, or pass the buffers up to the ipath layered driver and
84  * thence the network layer, replacing them as we do so (see
85  * ipath_rcv_layer()).
86  */
87 static int create_port0_egr(struct ipath_devdata *dd)
88 {
89         unsigned e, egrcnt;
90         struct sk_buff **skbs;
91         int ret;
92
93         egrcnt = dd->ipath_rcvegrcnt;
94
95         skbs = vmalloc(sizeof(*dd->ipath_port0_skbs) * egrcnt);
96         if (skbs == NULL) {
97                 ipath_dev_err(dd, "allocation error for eager TID "
98                               "skb array\n");
99                 ret = -ENOMEM;
100                 goto bail;
101         }
102         for (e = 0; e < egrcnt; e++) {
103                 /*
104                  * This is a bit tricky in that we allocate extra
105                  * space for 2 bytes of the 14 byte ethernet header.
106                  * These two bytes are passed in the ipath header so
107                  * the rest of the data is word aligned.  We allocate
108                  * 4 bytes so that the data buffer stays word aligned.
109                  * See ipath_kreceive() for more details.
110                  */
111                 skbs[e] = ipath_alloc_skb(dd, GFP_KERNEL);
112                 if (!skbs[e]) {
113                         ipath_dev_err(dd, "SKB allocation error for "
114                                       "eager TID %u\n", e);
115                         while (e != 0)
116                                 dev_kfree_skb(skbs[--e]);
117                         ret = -ENOMEM;
118                         goto bail;
119                 }
120         }
121         /*
122          * After loop above, so we can test non-NULL to see if ready
123          * to use at receive, etc.
124          */
125         dd->ipath_port0_skbs = skbs;
126
127         for (e = 0; e < egrcnt; e++) {
128                 unsigned long phys =
129                         virt_to_phys(dd->ipath_port0_skbs[e]->data);
130                 dd->ipath_f_put_tid(dd, e + (u64 __iomem *)
131                                     ((char __iomem *) dd->ipath_kregbase +
132                                      dd->ipath_rcvegrbase), 0, phys);
133         }
134
135         ret = 0;
136
137 bail:
138         return ret;
139 }
140
141 static int bringup_link(struct ipath_devdata *dd)
142 {
143         u64 val, ibc;
144         int ret = 0;
145
146         /* hold IBC in reset */
147         dd->ipath_control &= ~INFINIPATH_C_LINKENABLE;
148         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
149                          dd->ipath_control);
150
151         /*
152          * Note that prior to try 14 or 15 of IB, the credit scaling
153          * wasn't working, because it was swapped for writes with the
154          * 1 bit default linkstate field
155          */
156
157         /* ignore pbc and align word */
158         val = dd->ipath_piosize2k - 2 * sizeof(u32);
159         /*
160          * for ICRC, which we only send in diag test pkt mode, and we
161          * don't need to worry about that for mtu
162          */
163         val += 1;
164         /*
165          * Set the IBC maxpktlength to the size of our pio buffers the
166          * maxpktlength is in words.  This is *not* the IB data MTU.
167          */
168         ibc = (val / sizeof(u32)) << INFINIPATH_IBCC_MAXPKTLEN_SHIFT;
169         /* in KB */
170         ibc |= 0x5ULL << INFINIPATH_IBCC_FLOWCTRLWATERMARK_SHIFT;
171         /*
172          * How often flowctrl sent.  More or less in usecs; balance against
173          * watermark value, so that in theory senders always get a flow
174          * control update in time to not let the IB link go idle.
175          */
176         ibc |= 0x3ULL << INFINIPATH_IBCC_FLOWCTRLPERIOD_SHIFT;
177         /* max error tolerance */
178         ibc |= 0xfULL << INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT;
179         /* use "real" buffer space for */
180         ibc |= 4ULL << INFINIPATH_IBCC_CREDITSCALE_SHIFT;
181         /* IB credit flow control. */
182         ibc |= 0xfULL << INFINIPATH_IBCC_OVERRUNTHRESHOLD_SHIFT;
183         /* initially come up waiting for TS1, without sending anything. */
184         dd->ipath_ibcctrl = ibc;
185         /*
186          * Want to start out with both LINKCMD and LINKINITCMD in NOP
187          * (0 and 0).  Don't put linkinitcmd in ipath_ibcctrl, want that
188          * to stay a NOP
189          */
190         ibc |= INFINIPATH_IBCC_LINKINITCMD_DISABLE <<
191                 INFINIPATH_IBCC_LINKINITCMD_SHIFT;
192         ipath_cdbg(VERBOSE, "Writing 0x%llx to ibcctrl\n",
193                    (unsigned long long) ibc);
194         ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl, ibc);
195
196         // be sure chip saw it
197         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
198
199         ret = dd->ipath_f_bringup_serdes(dd);
200
201         if (ret)
202                 dev_info(&dd->pcidev->dev, "Could not initialize SerDes, "
203                          "not usable\n");
204         else {
205                 /* enable IBC */
206                 dd->ipath_control |= INFINIPATH_C_LINKENABLE;
207                 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
208                                  dd->ipath_control);
209         }
210
211         return ret;
212 }
213
214 static int init_chip_first(struct ipath_devdata *dd,
215                            struct ipath_portdata **pdp)
216 {
217         struct ipath_portdata *pd = NULL;
218         int ret = 0;
219         u64 val;
220
221         /*
222          * skip cfgports stuff because we are not allocating memory,
223          * and we don't want problems if the portcnt changed due to
224          * cfgports.  We do still check and report a difference, if
225          * not same (should be impossible).
226          */
227         dd->ipath_portcnt =
228                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt);
229         if (!ipath_cfgports)
230                 dd->ipath_cfgports = dd->ipath_portcnt;
231         else if (ipath_cfgports <= dd->ipath_portcnt) {
232                 dd->ipath_cfgports = ipath_cfgports;
233                 ipath_dbg("Configured to use %u ports out of %u in chip\n",
234                           dd->ipath_cfgports, dd->ipath_portcnt);
235         } else {
236                 dd->ipath_cfgports = dd->ipath_portcnt;
237                 ipath_dbg("Tried to configured to use %u ports; chip "
238                           "only supports %u\n", ipath_cfgports,
239                           dd->ipath_portcnt);
240         }
241         dd->ipath_pd = kzalloc(sizeof(*dd->ipath_pd) * dd->ipath_cfgports,
242                                GFP_KERNEL);
243
244         if (!dd->ipath_pd) {
245                 ipath_dev_err(dd, "Unable to allocate portdata array, "
246                               "failing\n");
247                 ret = -ENOMEM;
248                 goto done;
249         }
250
251         dd->ipath_lastegrheads = kzalloc(sizeof(*dd->ipath_lastegrheads)
252                                          * dd->ipath_cfgports,
253                                          GFP_KERNEL);
254         dd->ipath_lastrcvhdrqtails =
255                 kzalloc(sizeof(*dd->ipath_lastrcvhdrqtails)
256                         * dd->ipath_cfgports, GFP_KERNEL);
257
258         if (!dd->ipath_lastegrheads || !dd->ipath_lastrcvhdrqtails) {
259                 ipath_dev_err(dd, "Unable to allocate head arrays, "
260                               "failing\n");
261                 ret = -ENOMEM;
262                 goto done;
263         }
264
265         dd->ipath_pd[0] = kzalloc(sizeof(*pd), GFP_KERNEL);
266
267         if (!dd->ipath_pd[0]) {
268                 ipath_dev_err(dd, "Unable to allocate portdata for port "
269                               "0, failing\n");
270                 ret = -ENOMEM;
271                 goto done;
272         }
273         pd = dd->ipath_pd[0];
274         pd->port_dd = dd;
275         pd->port_port = 0;
276         pd->port_cnt = 1;
277         /* The port 0 pkey table is used by the layer interface. */
278         pd->port_pkeys[0] = IPS_DEFAULT_P_KEY;
279         dd->ipath_rcvtidcnt =
280                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
281         dd->ipath_rcvtidbase =
282                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
283         dd->ipath_rcvegrcnt =
284                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
285         dd->ipath_rcvegrbase =
286                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
287         dd->ipath_palign =
288                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign);
289         dd->ipath_piobufbase =
290                 ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufbase);
291         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiosize);
292         dd->ipath_piosize2k = val & ~0U;
293         dd->ipath_piosize4k = val >> 32;
294         dd->ipath_ibmtu = 4096; /* default to largest legal MTU */
295         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufcnt);
296         dd->ipath_piobcnt2k = val & ~0U;
297         dd->ipath_piobcnt4k = val >> 32;
298         dd->ipath_pio2kbase =
299                 (u32 __iomem *) (((char __iomem *) dd->ipath_kregbase) +
300                                  (dd->ipath_piobufbase & 0xffffffff));
301         if (dd->ipath_piobcnt4k) {
302                 dd->ipath_pio4kbase = (u32 __iomem *)
303                         (((char __iomem *) dd->ipath_kregbase) +
304                          (dd->ipath_piobufbase >> 32));
305                 /*
306                  * 4K buffers take 2 pages; we use roundup just to be
307                  * paranoid; we calculate it once here, rather than on
308                  * ever buf allocate
309                  */
310                 dd->ipath_4kalign = ALIGN(dd->ipath_piosize4k,
311                                           dd->ipath_palign);
312                 ipath_dbg("%u 2k(%x) piobufs @ %p, %u 4k(%x) @ %p "
313                           "(%x aligned)\n",
314                           dd->ipath_piobcnt2k, dd->ipath_piosize2k,
315                           dd->ipath_pio2kbase, dd->ipath_piobcnt4k,
316                           dd->ipath_piosize4k, dd->ipath_pio4kbase,
317                           dd->ipath_4kalign);
318         }
319         else ipath_dbg("%u 2k piobufs @ %p\n",
320                        dd->ipath_piobcnt2k, dd->ipath_pio2kbase);
321
322         spin_lock_init(&dd->ipath_tid_lock);
323
324 done:
325         *pdp = pd;
326         return ret;
327 }
328
329 /**
330  * init_chip_reset - re-initialize after a reset, or enable
331  * @dd: the infinipath device
332  * @pdp: output for port data
333  *
334  * sanity check at least some of the values after reset, and
335  * ensure no receive or transmit (explictly, in case reset
336  * failed
337  */
338 static int init_chip_reset(struct ipath_devdata *dd,
339                            struct ipath_portdata **pdp)
340 {
341         struct ipath_portdata *pd;
342         u32 rtmp;
343
344         *pdp = pd = dd->ipath_pd[0];
345         /* ensure chip does no sends or receives while we re-initialize */
346         dd->ipath_control = dd->ipath_sendctrl = dd->ipath_rcvctrl = 0U;
347         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl, 0);
348         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, 0);
349         ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0);
350
351         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt);
352         if (dd->ipath_portcnt != rtmp)
353                 dev_info(&dd->pcidev->dev, "portcnt was %u before "
354                          "reset, now %u, using original\n",
355                          dd->ipath_portcnt, rtmp);
356         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
357         if (rtmp != dd->ipath_rcvtidcnt)
358                 dev_info(&dd->pcidev->dev, "tidcnt was %u before "
359                          "reset, now %u, using original\n",
360                          dd->ipath_rcvtidcnt, rtmp);
361         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
362         if (rtmp != dd->ipath_rcvtidbase)
363                 dev_info(&dd->pcidev->dev, "tidbase was %u before "
364                          "reset, now %u, using original\n",
365                          dd->ipath_rcvtidbase, rtmp);
366         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
367         if (rtmp != dd->ipath_rcvegrcnt)
368                 dev_info(&dd->pcidev->dev, "egrcnt was %u before "
369                          "reset, now %u, using original\n",
370                          dd->ipath_rcvegrcnt, rtmp);
371         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
372         if (rtmp != dd->ipath_rcvegrbase)
373                 dev_info(&dd->pcidev->dev, "egrbase was %u before "
374                          "reset, now %u, using original\n",
375                          dd->ipath_rcvegrbase, rtmp);
376
377         return 0;
378 }
379
380 static int init_pioavailregs(struct ipath_devdata *dd)
381 {
382         int ret;
383
384         dd->ipath_pioavailregs_dma = dma_alloc_coherent(
385                 &dd->pcidev->dev, PAGE_SIZE, &dd->ipath_pioavailregs_phys,
386                 GFP_KERNEL);
387         if (!dd->ipath_pioavailregs_dma) {
388                 ipath_dev_err(dd, "failed to allocate PIOavail reg area "
389                               "in memory\n");
390                 ret = -ENOMEM;
391                 goto done;
392         }
393
394         /*
395          * we really want L2 cache aligned, but for current CPUs of
396          * interest, they are the same.
397          */
398         dd->ipath_statusp = (u64 *)
399                 ((char *)dd->ipath_pioavailregs_dma +
400                  ((2 * L1_CACHE_BYTES +
401                    dd->ipath_pioavregs * sizeof(u64)) & ~L1_CACHE_BYTES));
402         /* copy the current value now that it's really allocated */
403         *dd->ipath_statusp = dd->_ipath_status;
404         /*
405          * setup buffer to hold freeze msg, accessible to apps,
406          * following statusp
407          */
408         dd->ipath_freezemsg = (char *)&dd->ipath_statusp[1];
409         /* and its length */
410         dd->ipath_freezelen = L1_CACHE_BYTES - sizeof(dd->ipath_statusp[0]);
411
412         if (dd->ipath_unit * 64 > (IPATH_PORT0_RCVHDRTAIL_SIZE - 64)) {
413                 ipath_dev_err(dd, "unit %u too large for port 0 "
414                               "rcvhdrtail buffer size\n", dd->ipath_unit);
415                 ret = -ENODEV;
416         }
417         else
418                 ret = 0;
419
420         /* so we can get current tail in ipath_kreceive(), per chip */
421         dd->ipath_hdrqtailptr = &ipath_port0_rcvhdrtail[
422                 dd->ipath_unit * (64 / sizeof(*ipath_port0_rcvhdrtail))];
423 done:
424         return ret;
425 }
426
427 /**
428  * init_shadow_tids - allocate the shadow TID array
429  * @dd: the infinipath device
430  *
431  * allocate the shadow TID array, so we can ipath_munlock previous
432  * entries.  It may make more sense to move the pageshadow to the
433  * port data structure, so we only allocate memory for ports actually
434  * in use, since we at 8k per port, now.
435  */
436 static void init_shadow_tids(struct ipath_devdata *dd)
437 {
438         dd->ipath_pageshadow = (struct page **)
439                 vmalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt *
440                         sizeof(struct page *));
441         if (!dd->ipath_pageshadow)
442                 ipath_dev_err(dd, "failed to allocate shadow page * "
443                               "array, no expected sends!\n");
444         else
445                 memset(dd->ipath_pageshadow, 0,
446                        dd->ipath_cfgports * dd->ipath_rcvtidcnt *
447                        sizeof(struct page *));
448 }
449
450 static void enable_chip(struct ipath_devdata *dd,
451                         struct ipath_portdata *pd, int reinit)
452 {
453         u32 val;
454         int i;
455
456         if (!reinit) {
457                 init_waitqueue_head(&ipath_sma_state_wait);
458         }
459         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
460                          dd->ipath_rcvctrl);
461
462         /* Enable PIO send, and update of PIOavail regs to memory. */
463         dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE |
464                 INFINIPATH_S_PIOBUFAVAILUPD;
465         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
466                          dd->ipath_sendctrl);
467
468         /*
469          * enable port 0 receive, and receive interrupt.  other ports
470          * done as user opens and inits them.
471          */
472         dd->ipath_rcvctrl = INFINIPATH_R_TAILUPD |
473                 (1ULL << INFINIPATH_R_PORTENABLE_SHIFT) |
474                 (1ULL << INFINIPATH_R_INTRAVAIL_SHIFT);
475         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
476                          dd->ipath_rcvctrl);
477
478         /*
479          * now ready for use.  this should be cleared whenever we
480          * detect a reset, or initiate one.
481          */
482         dd->ipath_flags |= IPATH_INITTED;
483
484         /*
485          * init our shadow copies of head from tail values, and write
486          * head values to match.
487          */
488         val = ipath_read_ureg32(dd, ur_rcvegrindextail, 0);
489         (void)ipath_write_ureg(dd, ur_rcvegrindexhead, val, 0);
490         dd->ipath_port0head = ipath_read_ureg32(dd, ur_rcvhdrtail, 0);
491
492         /* Initialize so we interrupt on next packet received */
493         (void)ipath_write_ureg(dd, ur_rcvhdrhead,
494                                dd->ipath_rhdrhead_intr_off |
495                                dd->ipath_port0head, 0);
496
497         /*
498          * by now pioavail updates to memory should have occurred, so
499          * copy them into our working/shadow registers; this is in
500          * case something went wrong with abort, but mostly to get the
501          * initial values of the generation bit correct.
502          */
503         for (i = 0; i < dd->ipath_pioavregs; i++) {
504                 __le64 val;
505
506                 /*
507                  * Chip Errata bug 6641; even and odd qwords>3 are swapped.
508                  */
509                 if (i > 3) {
510                         if (i & 1)
511                                 val = dd->ipath_pioavailregs_dma[i - 1];
512                         else
513                                 val = dd->ipath_pioavailregs_dma[i + 1];
514                 }
515                 else
516                         val = dd->ipath_pioavailregs_dma[i];
517                 dd->ipath_pioavailshadow[i] = le64_to_cpu(val);
518         }
519         /* can get counters, stats, etc. */
520         dd->ipath_flags |= IPATH_PRESENT;
521 }
522
523 static int init_housekeeping(struct ipath_devdata *dd,
524                              struct ipath_portdata **pdp, int reinit)
525 {
526         char boardn[32];
527         int ret = 0;
528
529         /*
530          * have to clear shadow copies of registers at init that are
531          * not otherwise set here, or all kinds of bizarre things
532          * happen with driver on chip reset
533          */
534         dd->ipath_rcvhdrsize = 0;
535
536         /*
537          * Don't clear ipath_flags as 8bit mode was set before
538          * entering this func. However, we do set the linkstate to
539          * unknown, so we can watch for a transition.
540          * PRESENT is set because we want register reads to work,
541          * and the kernel infrastructure saw it in config space;
542          * We clear it if we have failures.
543          */
544         dd->ipath_flags |= IPATH_LINKUNK | IPATH_PRESENT;
545         dd->ipath_flags &= ~(IPATH_LINKACTIVE | IPATH_LINKARMED |
546                              IPATH_LINKDOWN | IPATH_LINKINIT);
547
548         ipath_cdbg(VERBOSE, "Try to read spc chip revision\n");
549         dd->ipath_revision =
550                 ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
551
552         /*
553          * set up fundamental info we need to use the chip; we assume
554          * if the revision reg and these regs are OK, we don't need to
555          * special case the rest
556          */
557         dd->ipath_sregbase =
558                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_sendregbase);
559         dd->ipath_cregbase =
560                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_counterregbase);
561         dd->ipath_uregbase =
562                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_userregbase);
563         ipath_cdbg(VERBOSE, "ipath_kregbase %p, sendbase %x usrbase %x, "
564                    "cntrbase %x\n", dd->ipath_kregbase, dd->ipath_sregbase,
565                    dd->ipath_uregbase, dd->ipath_cregbase);
566         if ((dd->ipath_revision & 0xffffffff) == 0xffffffff
567             || (dd->ipath_sregbase & 0xffffffff) == 0xffffffff
568             || (dd->ipath_cregbase & 0xffffffff) == 0xffffffff
569             || (dd->ipath_uregbase & 0xffffffff) == 0xffffffff) {
570                 ipath_dev_err(dd, "Register read failures from chip, "
571                               "giving up initialization\n");
572                 dd->ipath_flags &= ~IPATH_PRESENT;
573                 ret = -ENODEV;
574                 goto done;
575         }
576
577         /* clear the initial reset flag, in case first driver load */
578         ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear,
579                          INFINIPATH_E_RESET);
580
581         if (reinit)
582                 ret = init_chip_reset(dd, pdp);
583         else
584                 ret = init_chip_first(dd, pdp);
585
586         if (ret)
587                 goto done;
588
589         ipath_cdbg(VERBOSE, "Revision %llx (PCI %x), %u ports, %u tids, "
590                    "%u egrtids\n", (unsigned long long) dd->ipath_revision,
591                    dd->ipath_pcirev, dd->ipath_portcnt, dd->ipath_rcvtidcnt,
592                    dd->ipath_rcvegrcnt);
593
594         if (((dd->ipath_revision >> INFINIPATH_R_SOFTWARE_SHIFT) &
595              INFINIPATH_R_SOFTWARE_MASK) != IPATH_CHIP_SWVERSION) {
596                 ipath_dev_err(dd, "Driver only handles version %d, "
597                               "chip swversion is %d (%llx), failng\n",
598                               IPATH_CHIP_SWVERSION,
599                               (int)(dd->ipath_revision >>
600                                     INFINIPATH_R_SOFTWARE_SHIFT) &
601                               INFINIPATH_R_SOFTWARE_MASK,
602                               (unsigned long long) dd->ipath_revision);
603                 ret = -ENOSYS;
604                 goto done;
605         }
606         dd->ipath_majrev = (u8) ((dd->ipath_revision >>
607                                   INFINIPATH_R_CHIPREVMAJOR_SHIFT) &
608                                  INFINIPATH_R_CHIPREVMAJOR_MASK);
609         dd->ipath_minrev = (u8) ((dd->ipath_revision >>
610                                   INFINIPATH_R_CHIPREVMINOR_SHIFT) &
611                                  INFINIPATH_R_CHIPREVMINOR_MASK);
612         dd->ipath_boardrev = (u8) ((dd->ipath_revision >>
613                                     INFINIPATH_R_BOARDID_SHIFT) &
614                                    INFINIPATH_R_BOARDID_MASK);
615
616         ret = dd->ipath_f_get_boardname(dd, boardn, sizeof boardn);
617
618         snprintf(dd->ipath_boardversion, sizeof(dd->ipath_boardversion),
619                  "Driver %u.%u, %s, InfiniPath%u %u.%u, PCI %u, "
620                  "SW Compat %u\n",
621                  IPATH_CHIP_VERS_MAJ, IPATH_CHIP_VERS_MIN, boardn,
622                  (unsigned)(dd->ipath_revision >> INFINIPATH_R_ARCH_SHIFT) &
623                  INFINIPATH_R_ARCH_MASK,
624                  dd->ipath_majrev, dd->ipath_minrev, dd->ipath_pcirev,
625                  (unsigned)(dd->ipath_revision >>
626                             INFINIPATH_R_SOFTWARE_SHIFT) &
627                  INFINIPATH_R_SOFTWARE_MASK);
628
629         ipath_dbg("%s", dd->ipath_boardversion);
630
631 done:
632         return ret;
633 }
634
635
636 /**
637  * ipath_init_chip - do the actual initialization sequence on the chip
638  * @dd: the infinipath device
639  * @reinit: reinitializing, so don't allocate new memory
640  *
641  * Do the actual initialization sequence on the chip.  This is done
642  * both from the init routine called from the PCI infrastructure, and
643  * when we reset the chip, or detect that it was reset internally,
644  * or it's administratively re-enabled.
645  *
646  * Memory allocation here and in called routines is only done in
647  * the first case (reinit == 0).  We have to be careful, because even
648  * without memory allocation, we need to re-write all the chip registers
649  * TIDs, etc. after the reset or enable has completed.
650  */
651 int ipath_init_chip(struct ipath_devdata *dd, int reinit)
652 {
653         int ret = 0, i;
654         u32 val32, kpiobufs;
655         u64 val, atmp;
656         struct ipath_portdata *pd = NULL; /* keep gcc4 happy */
657
658         ret = init_housekeeping(dd, &pd, reinit);
659         if (ret)
660                 goto done;
661
662         /*
663          * we ignore most issues after reporting them, but have to specially
664          * handle hardware-disabled chips.
665          */
666         if (ret == 2) {
667                 /* unique error, known to ipath_init_one */
668                 ret = -EPERM;
669                 goto done;
670         }
671
672         /*
673          * We could bump this to allow for full rcvegrcnt + rcvtidcnt,
674          * but then it no longer nicely fits power of two, and since
675          * we now use routines that backend onto __get_free_pages, the
676          * rest would be wasted.
677          */
678         dd->ipath_rcvhdrcnt = dd->ipath_rcvegrcnt;
679         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrcnt,
680                          dd->ipath_rcvhdrcnt);
681
682         /*
683          * Set up the shadow copies of the piobufavail registers,
684          * which we compare against the chip registers for now, and
685          * the in memory DMA'ed copies of the registers.  This has to
686          * be done early, before we calculate lastport, etc.
687          */
688         val = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
689         /*
690          * calc number of pioavail registers, and save it; we have 2
691          * bits per buffer.
692          */
693         dd->ipath_pioavregs = ALIGN(val, sizeof(u64) * BITS_PER_BYTE / 2)
694                 / (sizeof(u64) * BITS_PER_BYTE / 2);
695         if (ipath_kpiobufs == 0) {
696                 /* not set by user, or set explictly to default  */
697                 if ((dd->ipath_piobcnt2k + dd->ipath_piobcnt4k) > 128)
698                         kpiobufs = 32;
699                 else
700                         kpiobufs = 16;
701         }
702         else
703                 kpiobufs = ipath_kpiobufs;
704
705         if (kpiobufs >
706             (dd->ipath_piobcnt2k + dd->ipath_piobcnt4k -
707              (dd->ipath_cfgports * IPATH_MIN_USER_PORT_BUFCNT))) {
708                 i = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k -
709                         (dd->ipath_cfgports * IPATH_MIN_USER_PORT_BUFCNT);
710                 if (i < 0)
711                         i = 0;
712                 dev_info(&dd->pcidev->dev, "Allocating %d PIO bufs for "
713                          "kernel leaves too few for %d user ports "
714                          "(%d each); using %u\n", kpiobufs,
715                          dd->ipath_cfgports - 1,
716                          IPATH_MIN_USER_PORT_BUFCNT, i);
717                 /*
718                  * shouldn't change ipath_kpiobufs, because could be
719                  * different for different devices...
720                  */
721                 kpiobufs = i;
722         }
723         dd->ipath_lastport_piobuf =
724                 dd->ipath_piobcnt2k + dd->ipath_piobcnt4k - kpiobufs;
725         dd->ipath_pbufsport = dd->ipath_cfgports > 1
726                 ? dd->ipath_lastport_piobuf / (dd->ipath_cfgports - 1)
727                 : 0;
728         val32 = dd->ipath_lastport_piobuf -
729                 (dd->ipath_pbufsport * (dd->ipath_cfgports - 1));
730         if (val32 > 0) {
731                 ipath_dbg("allocating %u pbufs/port leaves %u unused, "
732                           "add to kernel\n", dd->ipath_pbufsport, val32);
733                 dd->ipath_lastport_piobuf -= val32;
734                 ipath_dbg("%u pbufs/port leaves %u unused, add to kernel\n",
735                           dd->ipath_pbufsport, val32);
736         }
737         dd->ipath_lastpioindex = dd->ipath_lastport_piobuf;
738         ipath_cdbg(VERBOSE, "%d PIO bufs for kernel out of %d total %u "
739                    "each for %u user ports\n", kpiobufs,
740                    dd->ipath_piobcnt2k + dd->ipath_piobcnt4k,
741                    dd->ipath_pbufsport, dd->ipath_cfgports - 1);
742
743         dd->ipath_f_early_init(dd);
744
745         /* early_init sets rcvhdrentsize and rcvhdrsize, so this must be
746          * done after early_init */
747         dd->ipath_hdrqlast =
748                 dd->ipath_rcvhdrentsize * (dd->ipath_rcvhdrcnt - 1);
749         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrentsize,
750                          dd->ipath_rcvhdrentsize);
751         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize,
752                          dd->ipath_rcvhdrsize);
753
754         if (!reinit) {
755                 ret = init_pioavailregs(dd);
756                 init_shadow_tids(dd);
757                 if (ret)
758                         goto done;
759         }
760
761         (void)ipath_write_kreg(dd, dd->ipath_kregs->kr_sendpioavailaddr,
762                                dd->ipath_pioavailregs_phys);
763         /*
764          * this is to detect s/w errors, which the h/w works around by
765          * ignoring the low 6 bits of address, if it wasn't aligned.
766          */
767         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpioavailaddr);
768         if (val != dd->ipath_pioavailregs_phys) {
769                 ipath_dev_err(dd, "Catastrophic software error, "
770                               "SendPIOAvailAddr written as %lx, "
771                               "read back as %llx\n",
772                               (unsigned long) dd->ipath_pioavailregs_phys,
773                               (unsigned long long) val);
774                 ret = -EINVAL;
775                 goto done;
776         }
777
778         val = ipath_port0_rcvhdrtail_dma + dd->ipath_unit * 64;
779
780         /* verify that the alignment requirement was met */
781         ipath_write_kreg_port(dd, dd->ipath_kregs->kr_rcvhdrtailaddr,
782                               0, val);
783         atmp = ipath_read_kreg64_port(
784                 dd, dd->ipath_kregs->kr_rcvhdrtailaddr, 0);
785         if (val != atmp) {
786                 ipath_dev_err(dd, "Catastrophic software error, "
787                               "RcvHdrTailAddr0 written as %llx, "
788                               "read back as %llx from %x\n",
789                               (unsigned long long) val,
790                               (unsigned long long) atmp,
791                               dd->ipath_kregs->kr_rcvhdrtailaddr);
792                 ret = -EINVAL;
793                 goto done;
794         }
795
796         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvbthqp, IPATH_KD_QP);
797
798         /*
799          * make sure we are not in freeze, and PIO send enabled, so
800          * writes to pbc happen
801          */
802         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, 0ULL);
803         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
804                          ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED);
805         ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0ULL);
806         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
807                          INFINIPATH_S_PIOENABLE);
808
809         /*
810          * before error clears, since we expect serdes pll errors during
811          * this, the first time after reset
812          */
813         if (bringup_link(dd)) {
814                 dev_info(&dd->pcidev->dev, "Failed to bringup IB link\n");
815                 ret = -ENETDOWN;
816                 goto done;
817         }
818
819         /*
820          * clear any "expected" hwerrs from reset and/or initialization
821          * clear any that aren't enabled (at least this once), and then
822          * set the enable mask
823          */
824         dd->ipath_f_init_hwerrors(dd);
825         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
826                          ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED);
827         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
828                          dd->ipath_hwerrmask);
829
830         dd->ipath_maskederrs = dd->ipath_ignorederrs;
831         /* clear all */
832         ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL);
833         /* enable errors that are masked, at least this first time. */
834         ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
835                          ~dd->ipath_maskederrs);
836         /* clear any interrups up to this point (ints still not enabled) */
837         ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL);
838
839         ipath_stats.sps_lid[dd->ipath_unit] = dd->ipath_lid;
840
841         /*
842          * Set up the port 0 (kernel) rcvhdr q and egr TIDs.  If doing
843          * re-init, the simplest way to handle this is to free
844          * existing, and re-allocate.
845          */
846         if (reinit)
847                 ipath_free_pddata(dd, 0, 0);
848         dd->ipath_f_tidtemplate(dd);
849         ret = ipath_create_rcvhdrq(dd, pd);
850         if (!ret)
851                 ret = create_port0_egr(dd);
852         if (ret)
853                 ipath_dev_err(dd, "failed to allocate port 0 (kernel) "
854                               "rcvhdrq and/or egr bufs\n");
855         else
856                 enable_chip(dd, pd, reinit);
857
858         /*
859          * cause retrigger of pending interrupts ignored during init,
860          * even if we had errors
861          */
862         ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, 0ULL);
863
864         if(!dd->ipath_stats_timer_active) {
865                 /*
866                  * first init, or after an admin disable/enable
867                  * set up stats retrieval timer, even if we had errors
868                  * in last portion of setup
869                  */
870                 init_timer(&dd->ipath_stats_timer);
871                 dd->ipath_stats_timer.function = ipath_get_faststats;
872                 dd->ipath_stats_timer.data = (unsigned long) dd;
873                 /* every 5 seconds; */
874                 dd->ipath_stats_timer.expires = jiffies + 5 * HZ;
875                 /* takes ~16 seconds to overflow at full IB 4x bandwdith */
876                 add_timer(&dd->ipath_stats_timer);
877                 dd->ipath_stats_timer_active = 1;
878         }
879
880 done:
881         if (!ret) {
882                 *dd->ipath_statusp |= IPATH_STATUS_CHIP_PRESENT;
883                 if (!dd->ipath_f_intrsetup(dd)) {
884                         /* now we can enable all interrupts from the chip */
885                         ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask,
886                                          -1LL);
887                         /* force re-interrupt of any pending interrupts. */
888                         ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear,
889                                          0ULL);
890                         /* chip is usable; mark it as initialized */
891                         *dd->ipath_statusp |= IPATH_STATUS_INITTED;
892                 } else
893                         ipath_dev_err(dd, "No interrupts enabled, couldn't "
894                                       "setup interrupt address\n");
895
896                 if (dd->ipath_cfgports > ipath_stats.sps_nports)
897                         /*
898                          * sps_nports is a global, so, we set it to
899                          * the highest number of ports of any of the
900                          * chips we find; we never decrement it, at
901                          * least for now.  Since this might have changed
902                          * over disable/enable or prior to reset, always
903                          * do the check and potentially adjust.
904                          */
905                         ipath_stats.sps_nports = dd->ipath_cfgports;
906         } else
907                 ipath_dbg("Failed (%d) to initialize chip\n", ret);
908
909         /* if ret is non-zero, we probably should do some cleanup
910            here... */
911         return ret;
912 }
913
914 static int ipath_set_kpiobufs(const char *str, struct kernel_param *kp)
915 {
916         struct ipath_devdata *dd;
917         unsigned long flags;
918         unsigned short val;
919         int ret;
920
921         ret = ipath_parse_ushort(str, &val);
922
923         spin_lock_irqsave(&ipath_devs_lock, flags);
924
925         if (ret < 0)
926                 goto bail;
927
928         if (val == 0) {
929                 ret = -EINVAL;
930                 goto bail;
931         }
932
933         list_for_each_entry(dd, &ipath_dev_list, ipath_list) {
934                 if (dd->ipath_kregbase)
935                         continue;
936                 if (val > (dd->ipath_piobcnt2k + dd->ipath_piobcnt4k -
937                            (dd->ipath_cfgports *
938                             IPATH_MIN_USER_PORT_BUFCNT)))
939                 {
940                         ipath_dev_err(
941                                 dd,
942                                 "Allocating %d PIO bufs for kernel leaves "
943                                 "too few for %d user ports (%d each)\n",
944                                 val, dd->ipath_cfgports - 1,
945                                 IPATH_MIN_USER_PORT_BUFCNT);
946                         ret = -EINVAL;
947                         goto bail;
948                 }
949                 dd->ipath_lastport_piobuf =
950                         dd->ipath_piobcnt2k + dd->ipath_piobcnt4k - val;
951         }
952
953         ret = 0;
954 bail:
955         spin_unlock_irqrestore(&ipath_devs_lock, flags);
956
957         return ret;
958 }