git.oblomov.eu Git - linux-2.6/blob - drivers/char/drm/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /**************************************************************************
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  **************************************************************************/
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 /* General customization:
  34  */
  35
  36 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  37
  38 #define DRIVER_NAME             "i915"
  39 #define DRIVER_DESC             "Intel Graphics"
  40 #define DRIVER_DATE             "20040405"
  41
  42 /* Interface history:
  43  *
  44  * 1.1: Original.
  45  */
  46 #define DRIVER_MAJOR            1
  47 #define DRIVER_MINOR            1
  48 #define DRIVER_PATCHLEVEL       0
  49
  50 /* We use our own dma mechanisms, not the drm template code.  However,
  51  * the shared IRQ code is useful to us:
  52  */
  53 #define __HAVE_PM               1
  54
  55 typedef struct _drm_i915_ring_buffer {
  56         int tail_mask;
  57         unsigned long Start;
  58         unsigned long End;
  59         unsigned long Size;
  60         u8 *virtual_start;
  61         int head;
  62         int tail;
  63         int space;
  64         drm_local_map_t map;
  65 } drm_i915_ring_buffer_t;
  66
  67 struct mem_block {
  68         struct mem_block *next;
  69         struct mem_block *prev;
  70         int start;
  71         int size;
  72         DRMFILE filp;           /* 0: free, -1: heap, other: real files */
  73 };
  74
  75 typedef struct drm_i915_private {
  76         drm_local_map_t *sarea;
  77         drm_local_map_t *mmio_map;
  78
  79         drm_i915_sarea_t *sarea_priv;
  80         drm_i915_ring_buffer_t ring;
  81
  82         drm_dma_handle_t *status_page_dmah;
  83         void *hw_status_page;
  84         dma_addr_t dma_status_page;
  85         unsigned long counter;
  86
  87         int back_offset;
  88         int front_offset;
  89         int current_page;
  90         int page_flipping;
  91         int use_mi_batchbuffer_start;
  92
  93         wait_queue_head_t irq_queue;
  94         atomic_t irq_received;
  95         atomic_t irq_emitted;
  96
  97         int tex_lru_log_granularity;
  98         int allow_batchbuffer;
  99         struct mem_block *agp_heap;
 100 } drm_i915_private_t;
 101
 102 extern drm_ioctl_desc_t i915_ioctls[];
 103 extern int i915_max_ioctl;
 104
 105                                 /* i915_dma.c */
 106 extern void i915_kernel_lost_context(drm_device_t * dev);
 107 extern void i915_driver_pretakedown(drm_device_t * dev);
 108 extern void i915_driver_prerelease(drm_device_t * dev, DRMFILE filp);
 109 extern int i915_driver_device_is_agp(drm_device_t * dev);
 110
 111 /* i915_irq.c */
 112 extern int i915_irq_emit(DRM_IOCTL_ARGS);
 113 extern int i915_irq_wait(DRM_IOCTL_ARGS);
 114
 115 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
 116 extern void i915_driver_irq_preinstall(drm_device_t * dev);
 117 extern void i915_driver_irq_postinstall(drm_device_t * dev);
 118 extern void i915_driver_irq_uninstall(drm_device_t * dev);
 119
 120 /* i915_mem.c */
 121 extern int i915_mem_alloc(DRM_IOCTL_ARGS);
 122 extern int i915_mem_free(DRM_IOCTL_ARGS);
 123 extern int i915_mem_init_heap(DRM_IOCTL_ARGS);
 124 extern void i915_mem_takedown(struct mem_block **heap);
 125 extern void i915_mem_release(drm_device_t * dev,
 126                              DRMFILE filp, struct mem_block *heap);
 127
 128 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
 129                               unsigned long arg);
 130
 131 #define I915_READ(reg)          DRM_READ32(dev_priv->mmio_map, reg)
 132 #define I915_WRITE(reg,val)     DRM_WRITE32(dev_priv->mmio_map, reg, val)
 133 #define I915_READ16(reg)        DRM_READ16(dev_priv->mmio_map, reg)
 134 #define I915_WRITE16(reg,val)   DRM_WRITE16(dev_priv->mmio_map, reg, val)
 135
 136 #define I915_VERBOSE 0
 137
 138 #define RING_LOCALS     unsigned int outring, ringmask, outcount; \
 139                         volatile char *virt;
 140
 141 #define BEGIN_LP_RING(n) do {                           \
 142         if (I915_VERBOSE)                               \
 143                 DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n",  \
 144                           n, __FUNCTION__);             \
 145         if (dev_priv->ring.space < n*4)                 \
 146                 i915_wait_ring(dev, n*4, __FUNCTION__);         \
 147         outcount = 0;                                   \
 148         outring = dev_priv->ring.tail;                  \
 149         ringmask = dev_priv->ring.tail_mask;            \
 150         virt = dev_priv->ring.virtual_start;            \
 151 } while (0)
 152
 153 #define OUT_RING(n) do {                                        \
 154         if (I915_VERBOSE) DRM_DEBUG("   OUT_RING %x\n", (int)(n));      \
 155         *(volatile unsigned int *)(virt + outring) = n;         \
 156         outcount++;                                             \
 157         outring += 4;                                           \
 158         outring &= ringmask;                                    \
 159 } while (0)
 160
 161 #define ADVANCE_LP_RING() do {                                          \
 162         if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring);   \
 163         dev_priv->ring.tail = outring;                                  \
 164         dev_priv->ring.space -= outcount * 4;                           \
 165         I915_WRITE(LP_RING + RING_TAIL, outring);                       \
 166 } while(0)
 167
 168 extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
 169
 170 #define GFX_OP_USER_INTERRUPT           ((0<<29)|(2<<23))
 171 #define GFX_OP_BREAKPOINT_INTERRUPT     ((0<<29)|(1<<23))
 172 #define CMD_REPORT_HEAD                 (7<<23)
 173 #define CMD_STORE_DWORD_IDX             ((0x21<<23) | 0x1)
 174 #define CMD_OP_BATCH_BUFFER  ((0x0<<29)|(0x30<<23)|0x1)
 175
 176 #define INST_PARSER_CLIENT   0x00000000
 177 #define INST_OP_FLUSH        0x02000000
 178 #define INST_FLUSH_MAP_CACHE 0x00000001
 179
 180 #define BB1_START_ADDR_MASK   (~0x7)
 181 #define BB1_PROTECTED         (1<<0)
 182 #define BB1_UNPROTECTED       (0<<0)
 183 #define BB2_END_ADDR_MASK     (~0x7)
 184
 185 #define I915REG_HWSTAM          0x02098
 186 #define I915REG_INT_IDENTITY_R  0x020a4
 187 #define I915REG_INT_MASK_R      0x020a8
 188 #define I915REG_INT_ENABLE_R    0x020a0
 189
 190 #define SRX_INDEX               0x3c4
 191 #define SRX_DATA                0x3c5
 192 #define SR01                    1
 193 #define SR01_SCREEN_OFF         (1<<5)
 194
 195 #define PPCR                    0x61204
 196 #define PPCR_ON                 (1<<0)
 197
 198 #define ADPA                    0x61100
 199 #define ADPA_DPMS_MASK          (~(3<<10))
 200 #define ADPA_DPMS_ON            (0<<10)
 201 #define ADPA_DPMS_SUSPEND       (1<<10)
 202 #define ADPA_DPMS_STANDBY       (2<<10)
 203 #define ADPA_DPMS_OFF           (3<<10)
 204
 205 #define NOPID                   0x2094
 206 #define LP_RING                 0x2030
 207 #define HP_RING                 0x2040
 208 #define RING_TAIL               0x00
 209 #define TAIL_ADDR               0x001FFFF8
 210 #define RING_HEAD               0x04
 211 #define HEAD_WRAP_COUNT         0xFFE00000
 212 #define HEAD_WRAP_ONE           0x00200000
 213 #define HEAD_ADDR               0x001FFFFC
 214 #define RING_START              0x08
 215 #define START_ADDR              0x0xFFFFF000
 216 #define RING_LEN                0x0C
 217 #define RING_NR_PAGES           0x001FF000
 218 #define RING_REPORT_MASK        0x00000006
 219 #define RING_REPORT_64K         0x00000002
 220 #define RING_REPORT_128K        0x00000004
 221 #define RING_NO_REPORT          0x00000000
 222 #define RING_VALID_MASK         0x00000001
 223 #define RING_VALID              0x00000001
 224 #define RING_INVALID            0x00000000
 225
 226 #define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
 227 #define SC_UPDATE_SCISSOR       (0x1<<1)
 228 #define SC_ENABLE_MASK          (0x1<<0)
 229 #define SC_ENABLE               (0x1<<0)
 230
 231 #define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
 232 #define SCI_YMIN_MASK      (0xffff<<16)
 233 #define SCI_XMIN_MASK      (0xffff<<0)
 234 #define SCI_YMAX_MASK      (0xffff<<16)
 235 #define SCI_XMAX_MASK      (0xffff<<0)
 236
 237 #define GFX_OP_SCISSOR_ENABLE    ((0x3<<29)|(0x1c<<24)|(0x10<<19))
 238 #define GFX_OP_SCISSOR_RECT      ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
 239 #define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
 240 #define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
 241 #define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
 242 #define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
 243 #define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
 244
 245 #define MI_BATCH_BUFFER         ((0x30<<23)|1)
 246 #define MI_BATCH_BUFFER_START   (0x31<<23)
 247 #define MI_BATCH_BUFFER_END     (0xA<<23)
 248 #define MI_BATCH_NON_SECURE     (1)
 249
 250 #define MI_WAIT_FOR_EVENT       ((0x3<<23))
 251 #define MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
 252 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
 253
 254 #define MI_LOAD_SCAN_LINES_INCL  ((0x12<<23))
 255
 256 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
 257 #define ASYNC_FLIP                (1<<22)
 258
 259 #define CMD_OP_DESTBUFFER_INFO   ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
 260
 261 #endif