sh: Fix up fpu emu build.
[linux-2.6] / arch / sh / kernel / traps_32.c
1 /*
2  * 'traps.c' handles hardware traps and faults after we have saved some
3  * state in 'entry.S'.
4  *
5  *  SuperH version: Copyright (C) 1999 Niibe Yutaka
6  *                  Copyright (C) 2000 Philipp Rumpf
7  *                  Copyright (C) 2000 David Howells
8  *                  Copyright (C) 2002 - 2007 Paul Mundt
9  *
10  * This file is subject to the terms and conditions of the GNU General Public
11  * License.  See the file "COPYING" in the main directory of this archive
12  * for more details.
13  */
14 #include <linux/kernel.h>
15 #include <linux/ptrace.h>
16 #include <linux/init.h>
17 #include <linux/spinlock.h>
18 #include <linux/module.h>
19 #include <linux/kallsyms.h>
20 #include <linux/io.h>
21 #include <linux/bug.h>
22 #include <linux/debug_locks.h>
23 #include <linux/kdebug.h>
24 #include <linux/kexec.h>
25 #include <linux/limits.h>
26 #include <asm/system.h>
27 #include <asm/uaccess.h>
28 #include <asm/fpu.h>
29 #include <asm/kprobes.h>
30
31 #ifdef CONFIG_SH_KGDB
32 #include <asm/kgdb.h>
33 #define CHK_REMOTE_DEBUG(regs)                  \
34 {                                               \
35         if (kgdb_debug_hook && !user_mode(regs))\
36                 (*kgdb_debug_hook)(regs);       \
37 }
38 #else
39 #define CHK_REMOTE_DEBUG(regs)
40 #endif
41
42 #ifdef CONFIG_CPU_SH2
43 # define TRAP_RESERVED_INST     4
44 # define TRAP_ILLEGAL_SLOT_INST 6
45 # define TRAP_ADDRESS_ERROR     9
46 # ifdef CONFIG_CPU_SH2A
47 #  define TRAP_FPU_ERROR        13
48 #  define TRAP_DIVZERO_ERROR    17
49 #  define TRAP_DIVOVF_ERROR     18
50 # endif
51 #else
52 #define TRAP_RESERVED_INST      12
53 #define TRAP_ILLEGAL_SLOT_INST  13
54 #endif
55
56 static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
57 {
58         unsigned long p;
59         int i;
60
61         printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
62
63         for (p = bottom & ~31; p < top; ) {
64                 printk("%04lx: ", p & 0xffff);
65
66                 for (i = 0; i < 8; i++, p += 4) {
67                         unsigned int val;
68
69                         if (p < bottom || p >= top)
70                                 printk("         ");
71                         else {
72                                 if (__get_user(val, (unsigned int __user *)p)) {
73                                         printk("\n");
74                                         return;
75                                 }
76                                 printk("%08x ", val);
77                         }
78                 }
79                 printk("\n");
80         }
81 }
82
83 static DEFINE_SPINLOCK(die_lock);
84
85 void die(const char * str, struct pt_regs * regs, long err)
86 {
87         static int die_counter;
88
89         oops_enter();
90
91         console_verbose();
92         spin_lock_irq(&die_lock);
93         bust_spinlocks(1);
94
95         printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
96
97         CHK_REMOTE_DEBUG(regs);
98         print_modules();
99         show_regs(regs);
100
101         printk("Process: %s (pid: %d, stack limit = %p)\n", current->comm,
102                         task_pid_nr(current), task_stack_page(current) + 1);
103
104         if (!user_mode(regs) || in_interrupt())
105                 dump_mem("Stack: ", regs->regs[15], THREAD_SIZE +
106                          (unsigned long)task_stack_page(current));
107
108         bust_spinlocks(0);
109         add_taint(TAINT_DIE);
110         spin_unlock_irq(&die_lock);
111
112         if (kexec_should_crash(current))
113                 crash_kexec(regs);
114
115         if (in_interrupt())
116                 panic("Fatal exception in interrupt");
117
118         if (panic_on_oops)
119                 panic("Fatal exception");
120
121         oops_exit();
122         do_exit(SIGSEGV);
123 }
124
125 static inline void die_if_kernel(const char *str, struct pt_regs *regs,
126                                  long err)
127 {
128         if (!user_mode(regs))
129                 die(str, regs, err);
130 }
131
132 /*
133  * try and fix up kernelspace address errors
134  * - userspace errors just cause EFAULT to be returned, resulting in SEGV
135  * - kernel/userspace interfaces cause a jump to an appropriate handler
136  * - other kernel errors are bad
137  * - return 0 if fixed-up, -EFAULT if non-fatal (to the kernel) fault
138  */
139 static int die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
140 {
141         if (!user_mode(regs)) {
142                 const struct exception_table_entry *fixup;
143                 fixup = search_exception_tables(regs->pc);
144                 if (fixup) {
145                         regs->pc = fixup->fixup;
146                         return 0;
147                 }
148                 die(str, regs, err);
149         }
150         return -EFAULT;
151 }
152
153 static inline void sign_extend(unsigned int count, unsigned char *dst)
154 {
155 #ifdef __LITTLE_ENDIAN__
156         if ((count == 1) && dst[0] & 0x80) {
157                 dst[1] = 0xff;
158                 dst[2] = 0xff;
159                 dst[3] = 0xff;
160         }
161         if ((count == 2) && dst[1] & 0x80) {
162                 dst[2] = 0xff;
163                 dst[3] = 0xff;
164         }
165 #else
166         if ((count == 1) && dst[3] & 0x80) {
167                 dst[2] = 0xff;
168                 dst[1] = 0xff;
169                 dst[0] = 0xff;
170         }
171         if ((count == 2) && dst[2] & 0x80) {
172                 dst[1] = 0xff;
173                 dst[0] = 0xff;
174         }
175 #endif
176 }
177
178 static struct mem_access user_mem_access = {
179         copy_from_user,
180         copy_to_user,
181 };
182
183 /*
184  * handle an instruction that does an unaligned memory access by emulating the
185  * desired behaviour
186  * - note that PC _may not_ point to the faulting instruction
187  *   (if that instruction is in a branch delay slot)
188  * - return 0 if emulation okay, -EFAULT on existential error
189  */
190 static int handle_unaligned_ins(opcode_t instruction, struct pt_regs *regs,
191                                 struct mem_access *ma)
192 {
193         int ret, index, count;
194         unsigned long *rm, *rn;
195         unsigned char *src, *dst;
196         unsigned char __user *srcu, *dstu;
197
198         index = (instruction>>8)&15;    /* 0x0F00 */
199         rn = &regs->regs[index];
200
201         index = (instruction>>4)&15;    /* 0x00F0 */
202         rm = &regs->regs[index];
203
204         count = 1<<(instruction&3);
205
206         ret = -EFAULT;
207         switch (instruction>>12) {
208         case 0: /* mov.[bwl] to/from memory via r0+rn */
209                 if (instruction & 8) {
210                         /* from memory */
211                         srcu = (unsigned char __user *)*rm;
212                         srcu += regs->regs[0];
213                         dst = (unsigned char *)rn;
214                         *(unsigned long *)dst = 0;
215
216 #if !defined(__LITTLE_ENDIAN__)
217                         dst += 4-count;
218 #endif
219                         if (ma->from(dst, srcu, count))
220                                 goto fetch_fault;
221
222                         sign_extend(count, dst);
223                 } else {
224                         /* to memory */
225                         src = (unsigned char *)rm;
226 #if !defined(__LITTLE_ENDIAN__)
227                         src += 4-count;
228 #endif
229                         dstu = (unsigned char __user *)*rn;
230                         dstu += regs->regs[0];
231
232                         if (ma->to(dstu, src, count))
233                                 goto fetch_fault;
234                 }
235                 ret = 0;
236                 break;
237
238         case 1: /* mov.l Rm,@(disp,Rn) */
239                 src = (unsigned char*) rm;
240                 dstu = (unsigned char __user *)*rn;
241                 dstu += (instruction&0x000F)<<2;
242
243                 if (ma->to(dstu, src, 4))
244                         goto fetch_fault;
245                 ret = 0;
246                 break;
247
248         case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
249                 if (instruction & 4)
250                         *rn -= count;
251                 src = (unsigned char*) rm;
252                 dstu = (unsigned char __user *)*rn;
253 #if !defined(__LITTLE_ENDIAN__)
254                 src += 4-count;
255 #endif
256                 if (ma->to(dstu, src, count))
257                         goto fetch_fault;
258                 ret = 0;
259                 break;
260
261         case 5: /* mov.l @(disp,Rm),Rn */
262                 srcu = (unsigned char __user *)*rm;
263                 srcu += (instruction & 0x000F) << 2;
264                 dst = (unsigned char *)rn;
265                 *(unsigned long *)dst = 0;
266
267                 if (ma->from(dst, srcu, 4))
268                         goto fetch_fault;
269                 ret = 0;
270                 break;
271
272         case 6: /* mov.[bwl] from memory, possibly with post-increment */
273                 srcu = (unsigned char __user *)*rm;
274                 if (instruction & 4)
275                         *rm += count;
276                 dst = (unsigned char*) rn;
277                 *(unsigned long*)dst = 0;
278
279 #if !defined(__LITTLE_ENDIAN__)
280                 dst += 4-count;
281 #endif
282                 if (ma->from(dst, srcu, count))
283                         goto fetch_fault;
284                 sign_extend(count, dst);
285                 ret = 0;
286                 break;
287
288         case 8:
289                 switch ((instruction&0xFF00)>>8) {
290                 case 0x81: /* mov.w R0,@(disp,Rn) */
291                         src = (unsigned char *) &regs->regs[0];
292 #if !defined(__LITTLE_ENDIAN__)
293                         src += 2;
294 #endif
295                         dstu = (unsigned char __user *)*rm; /* called Rn in the spec */
296                         dstu += (instruction & 0x000F) << 1;
297
298                         if (ma->to(dstu, src, 2))
299                                 goto fetch_fault;
300                         ret = 0;
301                         break;
302
303                 case 0x85: /* mov.w @(disp,Rm),R0 */
304                         srcu = (unsigned char __user *)*rm;
305                         srcu += (instruction & 0x000F) << 1;
306                         dst = (unsigned char *) &regs->regs[0];
307                         *(unsigned long *)dst = 0;
308
309 #if !defined(__LITTLE_ENDIAN__)
310                         dst += 2;
311 #endif
312                         if (ma->from(dst, srcu, 2))
313                                 goto fetch_fault;
314                         sign_extend(2, dst);
315                         ret = 0;
316                         break;
317                 }
318                 break;
319         }
320         return ret;
321
322  fetch_fault:
323         /* Argh. Address not only misaligned but also non-existent.
324          * Raise an EFAULT and see if it's trapped
325          */
326         return die_if_no_fixup("Fault in unaligned fixup", regs, 0);
327 }
328
329 /*
330  * emulate the instruction in the delay slot
331  * - fetches the instruction from PC+2
332  */
333 static inline int handle_delayslot(struct pt_regs *regs,
334                                    opcode_t old_instruction,
335                                    struct mem_access *ma)
336 {
337         opcode_t instruction;
338         void __user *addr = (void __user *)(regs->pc +
339                 instruction_size(old_instruction));
340
341         if (copy_from_user(&instruction, addr, sizeof(instruction))) {
342                 /* the instruction-fetch faulted */
343                 if (user_mode(regs))
344                         return -EFAULT;
345
346                 /* kernel */
347                 die("delay-slot-insn faulting in handle_unaligned_delayslot",
348                     regs, 0);
349         }
350
351         return handle_unaligned_ins(instruction, regs, ma);
352 }
353
354 /*
355  * handle an instruction that does an unaligned memory access
356  * - have to be careful of branch delay-slot instructions that fault
357  *  SH3:
358  *   - if the branch would be taken PC points to the branch
359  *   - if the branch would not be taken, PC points to delay-slot
360  *  SH4:
361  *   - PC always points to delayed branch
362  * - return 0 if handled, -EFAULT if failed (may not return if in kernel)
363  */
364
365 /* Macros to determine offset from current PC for branch instructions */
366 /* Explicit type coercion is used to force sign extension where needed */
367 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
368 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
369
370 /*
371  * XXX: SH-2A needs this too, but it needs an overhaul thanks to mixed 32-bit
372  * opcodes..
373  */
374
375 static int handle_unaligned_notify_count = 10;
376
377 int handle_unaligned_access(opcode_t instruction, struct pt_regs *regs,
378                             struct mem_access *ma)
379 {
380         u_int rm;
381         int ret, index;
382
383         index = (instruction>>8)&15;    /* 0x0F00 */
384         rm = regs->regs[index];
385
386         /* shout about the first ten userspace fixups */
387         if (user_mode(regs) && handle_unaligned_notify_count>0) {
388                 handle_unaligned_notify_count--;
389
390                 printk(KERN_NOTICE "Fixing up unaligned userspace access "
391                        "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
392                        current->comm, task_pid_nr(current),
393                        (void *)regs->pc, instruction);
394         }
395
396         ret = -EFAULT;
397         switch (instruction&0xF000) {
398         case 0x0000:
399                 if (instruction==0x000B) {
400                         /* rts */
401                         ret = handle_delayslot(regs, instruction, ma);
402                         if (ret==0)
403                                 regs->pc = regs->pr;
404                 }
405                 else if ((instruction&0x00FF)==0x0023) {
406                         /* braf @Rm */
407                         ret = handle_delayslot(regs, instruction, ma);
408                         if (ret==0)
409                                 regs->pc += rm + 4;
410                 }
411                 else if ((instruction&0x00FF)==0x0003) {
412                         /* bsrf @Rm */
413                         ret = handle_delayslot(regs, instruction, ma);
414                         if (ret==0) {
415                                 regs->pr = regs->pc + 4;
416                                 regs->pc += rm + 4;
417                         }
418                 }
419                 else {
420                         /* mov.[bwl] to/from memory via r0+rn */
421                         goto simple;
422                 }
423                 break;
424
425         case 0x1000: /* mov.l Rm,@(disp,Rn) */
426                 goto simple;
427
428         case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
429                 goto simple;
430
431         case 0x4000:
432                 if ((instruction&0x00FF)==0x002B) {
433                         /* jmp @Rm */
434                         ret = handle_delayslot(regs, instruction, ma);
435                         if (ret==0)
436                                 regs->pc = rm;
437                 }
438                 else if ((instruction&0x00FF)==0x000B) {
439                         /* jsr @Rm */
440                         ret = handle_delayslot(regs, instruction, ma);
441                         if (ret==0) {
442                                 regs->pr = regs->pc + 4;
443                                 regs->pc = rm;
444                         }
445                 }
446                 else {
447                         /* mov.[bwl] to/from memory via r0+rn */
448                         goto simple;
449                 }
450                 break;
451
452         case 0x5000: /* mov.l @(disp,Rm),Rn */
453                 goto simple;
454
455         case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
456                 goto simple;
457
458         case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
459                 switch (instruction&0x0F00) {
460                 case 0x0100: /* mov.w R0,@(disp,Rm) */
461                         goto simple;
462                 case 0x0500: /* mov.w @(disp,Rm),R0 */
463                         goto simple;
464                 case 0x0B00: /* bf   lab - no delayslot*/
465                         break;
466                 case 0x0F00: /* bf/s lab */
467                         ret = handle_delayslot(regs, instruction, ma);
468                         if (ret==0) {
469 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
470                                 if ((regs->sr & 0x00000001) != 0)
471                                         regs->pc += 4; /* next after slot */
472                                 else
473 #endif
474                                         regs->pc += SH_PC_8BIT_OFFSET(instruction);
475                         }
476                         break;
477                 case 0x0900: /* bt   lab - no delayslot */
478                         break;
479                 case 0x0D00: /* bt/s lab */
480                         ret = handle_delayslot(regs, instruction, ma);
481                         if (ret==0) {
482 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
483                                 if ((regs->sr & 0x00000001) == 0)
484                                         regs->pc += 4; /* next after slot */
485                                 else
486 #endif
487                                         regs->pc += SH_PC_8BIT_OFFSET(instruction);
488                         }
489                         break;
490                 }
491                 break;
492
493         case 0xA000: /* bra label */
494                 ret = handle_delayslot(regs, instruction, ma);
495                 if (ret==0)
496                         regs->pc += SH_PC_12BIT_OFFSET(instruction);
497                 break;
498
499         case 0xB000: /* bsr label */
500                 ret = handle_delayslot(regs, instruction, ma);
501                 if (ret==0) {
502                         regs->pr = regs->pc + 4;
503                         regs->pc += SH_PC_12BIT_OFFSET(instruction);
504                 }
505                 break;
506         }
507         return ret;
508
509         /* handle non-delay-slot instruction */
510  simple:
511         ret = handle_unaligned_ins(instruction, regs, ma);
512         if (ret==0)
513                 regs->pc += instruction_size(instruction);
514         return ret;
515 }
516
517 #ifdef CONFIG_CPU_HAS_SR_RB
518 #define lookup_exception_vector(x)      \
519         __asm__ __volatile__ ("stc r2_bank, %0\n\t" : "=r" ((x)))
520 #else
521 #define lookup_exception_vector(x)      \
522         __asm__ __volatile__ ("mov r4, %0\n\t" : "=r" ((x)))
523 #endif
524
525 /*
526  * Handle various address error exceptions:
527  *  - instruction address error:
528  *       misaligned PC
529  *       PC >= 0x80000000 in user mode
530  *  - data address error (read and write)
531  *       misaligned data access
532  *       access to >= 0x80000000 is user mode
533  * Unfortuntaly we can't distinguish between instruction address error
534  * and data address errors caused by read accesses.
535  */
536 asmlinkage void do_address_error(struct pt_regs *regs,
537                                  unsigned long writeaccess,
538                                  unsigned long address)
539 {
540         unsigned long error_code = 0;
541         mm_segment_t oldfs;
542         siginfo_t info;
543         opcode_t instruction;
544         int tmp;
545
546         /* Intentional ifdef */
547 #ifdef CONFIG_CPU_HAS_SR_RB
548         lookup_exception_vector(error_code);
549 #endif
550
551         oldfs = get_fs();
552
553         if (user_mode(regs)) {
554                 int si_code = BUS_ADRERR;
555
556                 local_irq_enable();
557
558                 /* bad PC is not something we can fix */
559                 if (regs->pc & 1) {
560                         si_code = BUS_ADRALN;
561                         goto uspace_segv;
562                 }
563
564                 set_fs(USER_DS);
565                 if (copy_from_user(&instruction, (void __user *)(regs->pc),
566                                    sizeof(instruction))) {
567                         /* Argh. Fault on the instruction itself.
568                            This should never happen non-SMP
569                         */
570                         set_fs(oldfs);
571                         goto uspace_segv;
572                 }
573
574                 tmp = handle_unaligned_access(instruction, regs,
575                                               &user_mem_access);
576                 set_fs(oldfs);
577
578                 if (tmp==0)
579                         return; /* sorted */
580 uspace_segv:
581                 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned "
582                        "access (PC %lx PR %lx)\n", current->comm, regs->pc,
583                        regs->pr);
584
585                 info.si_signo = SIGBUS;
586                 info.si_errno = 0;
587                 info.si_code = si_code;
588                 info.si_addr = (void __user *)address;
589                 force_sig_info(SIGBUS, &info, current);
590         } else {
591                 if (regs->pc & 1)
592                         die("unaligned program counter", regs, error_code);
593
594                 set_fs(KERNEL_DS);
595                 if (copy_from_user(&instruction, (void __user *)(regs->pc),
596                                    sizeof(instruction))) {
597                         /* Argh. Fault on the instruction itself.
598                            This should never happen non-SMP
599                         */
600                         set_fs(oldfs);
601                         die("insn faulting in do_address_error", regs, 0);
602                 }
603
604                 handle_unaligned_access(instruction, regs, &user_mem_access);
605                 set_fs(oldfs);
606         }
607 }
608
609 #ifdef CONFIG_SH_DSP
610 /*
611  *      SH-DSP support gerg@snapgear.com.
612  */
613 int is_dsp_inst(struct pt_regs *regs)
614 {
615         unsigned short inst = 0;
616
617         /*
618          * Safe guard if DSP mode is already enabled or we're lacking
619          * the DSP altogether.
620          */
621         if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
622                 return 0;
623
624         get_user(inst, ((unsigned short *) regs->pc));
625
626         inst &= 0xf000;
627
628         /* Check for any type of DSP or support instruction */
629         if ((inst == 0xf000) || (inst == 0x4000))
630                 return 1;
631
632         return 0;
633 }
634 #else
635 #define is_dsp_inst(regs)       (0)
636 #endif /* CONFIG_SH_DSP */
637
638 #ifdef CONFIG_CPU_SH2A
639 asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
640                                 unsigned long r6, unsigned long r7,
641                                 struct pt_regs __regs)
642 {
643         siginfo_t info;
644
645         switch (r4) {
646         case TRAP_DIVZERO_ERROR:
647                 info.si_code = FPE_INTDIV;
648                 break;
649         case TRAP_DIVOVF_ERROR:
650                 info.si_code = FPE_INTOVF;
651                 break;
652         }
653
654         force_sig_info(SIGFPE, &info, current);
655 }
656 #endif
657
658 asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
659                                 unsigned long r6, unsigned long r7,
660                                 struct pt_regs __regs)
661 {
662         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
663         unsigned long error_code;
664         struct task_struct *tsk = current;
665
666 #ifdef CONFIG_SH_FPU_EMU
667         unsigned short inst = 0;
668         int err;
669
670         get_user(inst, (unsigned short*)regs->pc);
671
672         err = do_fpu_inst(inst, regs);
673         if (!err) {
674                 regs->pc += instruction_size(inst);
675                 return;
676         }
677         /* not a FPU inst. */
678 #endif
679
680 #ifdef CONFIG_SH_DSP
681         /* Check if it's a DSP instruction */
682         if (is_dsp_inst(regs)) {
683                 /* Enable DSP mode, and restart instruction. */
684                 regs->sr |= SR_DSP;
685                 return;
686         }
687 #endif
688
689         lookup_exception_vector(error_code);
690
691         local_irq_enable();
692         CHK_REMOTE_DEBUG(regs);
693         force_sig(SIGILL, tsk);
694         die_if_no_fixup("reserved instruction", regs, error_code);
695 }
696
697 #ifdef CONFIG_SH_FPU_EMU
698 static int emulate_branch(unsigned short inst, struct pt_regs* regs)
699 {
700         /*
701          * bfs: 8fxx: PC+=d*2+4;
702          * bts: 8dxx: PC+=d*2+4;
703          * bra: axxx: PC+=D*2+4;
704          * bsr: bxxx: PC+=D*2+4  after PR=PC+4;
705          * braf:0x23: PC+=Rn*2+4;
706          * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
707          * jmp: 4x2b: PC=Rn;
708          * jsr: 4x0b: PC=Rn      after PR=PC+4;
709          * rts: 000b: PC=PR;
710          */
711         if ((inst & 0xfd00) == 0x8d00) {
712                 regs->pc += SH_PC_8BIT_OFFSET(inst);
713                 return 0;
714         }
715
716         if ((inst & 0xe000) == 0xa000) {
717                 regs->pc += SH_PC_12BIT_OFFSET(inst);
718                 return 0;
719         }
720
721         if ((inst & 0xf0df) == 0x0003) {
722                 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
723                 return 0;
724         }
725
726         if ((inst & 0xf0df) == 0x400b) {
727                 regs->pc = regs->regs[(inst & 0x0f00) >> 8];
728                 return 0;
729         }
730
731         if ((inst & 0xffff) == 0x000b) {
732                 regs->pc = regs->pr;
733                 return 0;
734         }
735
736         return 1;
737 }
738 #endif
739
740 asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
741                                 unsigned long r6, unsigned long r7,
742                                 struct pt_regs __regs)
743 {
744         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
745         unsigned long inst;
746         struct task_struct *tsk = current;
747
748         if (kprobe_handle_illslot(regs->pc) == 0)
749                 return;
750
751 #ifdef CONFIG_SH_FPU_EMU
752         get_user(inst, (unsigned short *)regs->pc + 1);
753         if (!do_fpu_inst(inst, regs)) {
754                 get_user(inst, (unsigned short *)regs->pc);
755                 if (!emulate_branch(inst, regs))
756                         return;
757                 /* fault in branch.*/
758         }
759         /* not a FPU inst. */
760 #endif
761
762         lookup_exception_vector(inst);
763
764         local_irq_enable();
765         CHK_REMOTE_DEBUG(regs);
766         force_sig(SIGILL, tsk);
767         die_if_no_fixup("illegal slot instruction", regs, inst);
768 }
769
770 asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
771                                    unsigned long r6, unsigned long r7,
772                                    struct pt_regs __regs)
773 {
774         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
775         long ex;
776
777         lookup_exception_vector(ex);
778         die_if_kernel("exception", regs, ex);
779 }
780
781 #if defined(CONFIG_SH_STANDARD_BIOS)
782 void *gdb_vbr_vector;
783
784 static inline void __init gdb_vbr_init(void)
785 {
786         register unsigned long vbr;
787
788         /*
789          * Read the old value of the VBR register to initialise
790          * the vector through which debug and BIOS traps are
791          * delegated by the Linux trap handler.
792          */
793         asm volatile("stc vbr, %0" : "=r" (vbr));
794
795         gdb_vbr_vector = (void *)(vbr + 0x100);
796         printk("Setting GDB trap vector to 0x%08lx\n",
797                (unsigned long)gdb_vbr_vector);
798 }
799 #endif
800
801 void __cpuinit per_cpu_trap_init(void)
802 {
803         extern void *vbr_base;
804
805 #ifdef CONFIG_SH_STANDARD_BIOS
806         if (raw_smp_processor_id() == 0)
807                 gdb_vbr_init();
808 #endif
809
810         /* NOTE: The VBR value should be at P1
811            (or P2, virtural "fixed" address space).
812            It's definitely should not in physical address.  */
813
814         asm volatile("ldc       %0, vbr"
815                      : /* no output */
816                      : "r" (&vbr_base)
817                      : "memory");
818 }
819
820 void *set_exception_table_vec(unsigned int vec, void *handler)
821 {
822         extern void *exception_handling_table[];
823         void *old_handler;
824
825         old_handler = exception_handling_table[vec];
826         exception_handling_table[vec] = handler;
827         return old_handler;
828 }
829
830 void __init trap_init(void)
831 {
832         set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
833         set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
834
835 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
836     defined(CONFIG_SH_FPU_EMU)
837         /*
838          * For SH-4 lacking an FPU, treat floating point instructions as
839          * reserved. They'll be handled in the math-emu case, or faulted on
840          * otherwise.
841          */
842         set_exception_table_evt(0x800, do_reserved_inst);
843         set_exception_table_evt(0x820, do_illegal_slot_inst);
844 #elif defined(CONFIG_SH_FPU)
845 #ifdef CONFIG_CPU_SUBTYPE_SHX3
846         set_exception_table_evt(0xd80, fpu_state_restore_trap_handler);
847         set_exception_table_evt(0xda0, fpu_state_restore_trap_handler);
848 #else
849         set_exception_table_evt(0x800, fpu_state_restore_trap_handler);
850         set_exception_table_evt(0x820, fpu_state_restore_trap_handler);
851 #endif
852 #endif
853
854 #ifdef CONFIG_CPU_SH2
855         set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler);
856 #endif
857 #ifdef CONFIG_CPU_SH2A
858         set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error);
859         set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error);
860 #ifdef CONFIG_SH_FPU
861         set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler);
862 #endif
863 #endif
864
865         /* Setup VBR for boot cpu */
866         per_cpu_trap_init();
867 }
868
869 void show_trace(struct task_struct *tsk, unsigned long *sp,
870                 struct pt_regs *regs)
871 {
872         unsigned long addr;
873
874         if (regs && user_mode(regs))
875                 return;
876
877         printk("\nCall trace: ");
878 #ifdef CONFIG_KALLSYMS
879         printk("\n");
880 #endif
881
882         while (!kstack_end(sp)) {
883                 addr = *sp++;
884                 if (kernel_text_address(addr))
885                         print_ip_sym(addr);
886         }
887
888         printk("\n");
889
890         if (!tsk)
891                 tsk = current;
892
893         debug_show_held_locks(tsk);
894 }
895
896 void show_stack(struct task_struct *tsk, unsigned long *sp)
897 {
898         unsigned long stack;
899
900         if (!tsk)
901                 tsk = current;
902         if (tsk == current)
903                 sp = (unsigned long *)current_stack_pointer;
904         else
905                 sp = (unsigned long *)tsk->thread.sp;
906
907         stack = (unsigned long)sp;
908         dump_mem("Stack: ", stack, THREAD_SIZE +
909                  (unsigned long)task_stack_page(tsk));
910         show_trace(tsk, sp, NULL);
911 }
912
913 void dump_stack(void)
914 {
915         show_stack(NULL, NULL);
916 }
917 EXPORT_SYMBOL(dump_stack);