2 * File: arch/blackfin/mach-common/ints-priority-sc.c
7 * Description: Set up the interrupt priorities
11 * 1999 D. Jeff Dionne <jeff@uclinux.org>
12 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
13 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
14 * 2003 Metrowerks/Motorola
15 * 2003 Bas Vermeulen <bas@buyways.nl>
16 * Copyright 2004-2007 Analog Devices Inc.
18 * Bugs: Enter bugs at http://blackfin.uclinux.org/
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, see the file COPYING, or write
32 * to the Free Software Foundation, Inc.,
33 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
36 #include <linux/module.h>
37 #include <linux/kernel_stat.h>
38 #include <linux/seq_file.h>
39 #include <linux/irq.h>
41 #include <linux/kgdb.h>
43 #include <asm/traps.h>
44 #include <asm/blackfin.h>
46 #include <asm/irq_handler.h>
49 # define BF537_GENERIC_ERROR_INT_DEMUX
51 # undef BF537_GENERIC_ERROR_INT_DEMUX
56 * - we have separated the physical Hardware interrupt from the
57 * levels that the LINUX kernel sees (see the description in irq.h)
61 unsigned long irq_flags = 0;
63 /* The number of spurious interrupts */
64 atomic_t num_spurious;
67 /* irq number for request_irq, available in mach-bf533/irq.h */
69 /* corresponding bit in the SIC_ISR register */
71 } ivg_table[NR_PERI_INTS];
74 /* position of first irq in ivg_table for given ivg */
77 } ivg7_13[IVG13 - IVG7 + 1];
79 static void search_IAR(void);
82 * Search SIC_IAR and fill tables with the irqvalues
83 * and their positions in the SIC_ISR register.
85 static void __init search_IAR(void)
87 unsigned ivg, irq_pos = 0;
88 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
91 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
93 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
94 int iar_shift = (irqn & 7) * 4;
97 bfin_read32((unsigned long *)SIC_IAR0 +
98 (irqn >> 3)) >> iar_shift)) {
99 ivg_table[irq_pos].irqno = IVG7 + irqn;
100 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
101 ivg7_13[ivg].istop++;
109 * This is for BF533 internal IRQs
112 static void ack_noop(unsigned int irq)
114 /* Dummy function. */
117 static void bfin_core_mask_irq(unsigned int irq)
119 irq_flags &= ~(1 << irq);
120 if (!irqs_disabled())
124 static void bfin_core_unmask_irq(unsigned int irq)
126 irq_flags |= 1 << irq;
128 * If interrupts are enabled, IMASK must contain the same value
129 * as irq_flags. Make sure that invariant holds. If interrupts
130 * are currently disabled we need not do anything; one of the
131 * callers will take care of setting IMASK to the proper value
132 * when reenabling interrupts.
133 * local_irq_enable just does "STI irq_flags", so it's exactly
136 if (!irqs_disabled())
141 static void bfin_internal_mask_irq(unsigned int irq)
144 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
145 ~(1 << (irq - (IRQ_CORETMR + 1))));
147 unsigned mask_bank, mask_bit;
148 mask_bank = (irq - (IRQ_CORETMR + 1)) / 32;
149 mask_bit = (irq - (IRQ_CORETMR + 1)) % 32;
150 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
156 static void bfin_internal_unmask_irq(unsigned int irq)
159 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
160 (1 << (irq - (IRQ_CORETMR + 1))));
162 unsigned mask_bank, mask_bit;
163 mask_bank = (irq - (IRQ_CORETMR + 1)) / 32;
164 mask_bit = (irq - (IRQ_CORETMR + 1)) % 32;
165 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
171 static struct irq_chip bfin_core_irqchip = {
173 .mask = bfin_core_mask_irq,
174 .unmask = bfin_core_unmask_irq,
177 static struct irq_chip bfin_internal_irqchip = {
179 .mask = bfin_internal_mask_irq,
180 .unmask = bfin_internal_unmask_irq,
183 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
184 static int error_int_mask;
186 static void bfin_generic_error_ack_irq(unsigned int irq)
191 static void bfin_generic_error_mask_irq(unsigned int irq)
193 error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
195 if (!error_int_mask) {
197 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
200 (IRQ_CORETMR + 1))));
206 static void bfin_generic_error_unmask_irq(unsigned int irq)
209 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | 1 <<
210 (IRQ_GENERIC_ERROR - (IRQ_CORETMR + 1)));
214 error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
217 static struct irq_chip bfin_generic_error_irqchip = {
218 .ack = bfin_generic_error_ack_irq,
219 .mask = bfin_generic_error_mask_irq,
220 .unmask = bfin_generic_error_unmask_irq,
223 static void bfin_demux_error_irq(unsigned int int_err_irq,
224 struct irq_desc *intb_desc)
230 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
231 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
235 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
236 irq = IRQ_SPORT0_ERROR;
237 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
238 irq = IRQ_SPORT1_ERROR;
239 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
241 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
243 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
245 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) &&
246 (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0))
247 irq = IRQ_UART0_ERROR;
248 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) &&
249 (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0))
250 irq = IRQ_UART1_ERROR;
253 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) {
254 struct irq_desc *desc = irq_desc + irq;
255 desc->handle_irq(irq, desc);
260 bfin_write_PPI_STATUS(PPI_ERR_MASK);
262 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
264 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
267 case IRQ_SPORT0_ERROR:
268 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
271 case IRQ_SPORT1_ERROR:
272 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
276 bfin_write_CAN_GIS(CAN_ERR_MASK);
280 bfin_write_SPI_STAT(SPI_ERR_MASK);
288 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
293 "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
294 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
295 __FUNCTION__, __FILE__, __LINE__);
298 #endif /* BF537_GENERIC_ERROR_INT_DEMUX */
300 #if defined(CONFIG_IRQCHIP_DEMUX_GPIO) && !defined(CONFIG_BF54x)
302 static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
303 static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
305 static void bfin_gpio_ack_irq(unsigned int irq)
307 u16 gpionr = irq - IRQ_PF0;
309 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
310 set_gpio_data(gpionr, 0);
315 static void bfin_gpio_mask_ack_irq(unsigned int irq)
317 u16 gpionr = irq - IRQ_PF0;
319 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
320 set_gpio_data(gpionr, 0);
324 set_gpio_maska(gpionr, 0);
328 static void bfin_gpio_mask_irq(unsigned int irq)
330 set_gpio_maska(irq - IRQ_PF0, 0);
334 static void bfin_gpio_unmask_irq(unsigned int irq)
336 set_gpio_maska(irq - IRQ_PF0, 1);
340 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
343 u16 gpionr = irq - IRQ_PF0;
345 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
346 ret = gpio_request(gpionr, NULL);
351 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
352 bfin_gpio_unmask_irq(irq);
357 static void bfin_gpio_irq_shutdown(unsigned int irq)
359 bfin_gpio_mask_irq(irq);
360 gpio_free(irq - IRQ_PF0);
361 gpio_enabled[gpio_bank(irq - IRQ_PF0)] &= ~gpio_bit(irq - IRQ_PF0);
364 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
368 u16 gpionr = irq - IRQ_PF0;
370 if (type == IRQ_TYPE_PROBE) {
371 /* only probe unenabled GPIO interrupt lines */
372 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
374 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
377 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
378 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
379 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
380 ret = gpio_request(gpionr, NULL);
385 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
387 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
391 set_gpio_dir(gpionr, 0);
392 set_gpio_inen(gpionr, 1);
394 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
395 gpio_edge_triggered[gpio_bank(gpionr)] |= gpio_bit(gpionr);
396 set_gpio_edge(gpionr, 1);
398 set_gpio_edge(gpionr, 0);
399 gpio_edge_triggered[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
402 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
403 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
404 set_gpio_both(gpionr, 1);
406 set_gpio_both(gpionr, 0);
408 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
409 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
411 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
415 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
416 set_irq_handler(irq, handle_edge_irq);
418 set_irq_handler(irq, handle_level_irq);
423 static struct irq_chip bfin_gpio_irqchip = {
424 .ack = bfin_gpio_ack_irq,
425 .mask = bfin_gpio_mask_irq,
426 .mask_ack = bfin_gpio_mask_ack_irq,
427 .unmask = bfin_gpio_unmask_irq,
428 .set_type = bfin_gpio_irq_type,
429 .startup = bfin_gpio_irq_startup,
430 .shutdown = bfin_gpio_irq_shutdown
433 static void bfin_demux_gpio_irq(unsigned int intb_irq,
434 struct irq_desc *intb_desc)
437 struct irq_desc *desc;
439 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += 16) {
440 int irq = IRQ_PF0 + i;
441 int flag_d = get_gpiop_data(i);
443 flag_d & (gpio_enabled[gpio_bank(i)] & get_gpiop_maska(i));
447 desc = irq_desc + irq;
448 desc->handle_irq(irq, desc);
456 #else /* CONFIG_IRQCHIP_DEMUX_GPIO */
458 #define NR_PINT_SYS_IRQS 4
459 #define NR_PINT_BITS 32
461 #define IRQ_NOT_AVAIL 0xFF
463 #define PINT_2_BANK(x) ((x) >> 5)
464 #define PINT_2_BIT(x) ((x) & 0x1F)
465 #define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
467 static unsigned char irq2pint_lut[NR_PINTS];
468 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
471 unsigned int mask_set;
472 unsigned int mask_clear;
473 unsigned int request;
475 unsigned int edge_set;
476 unsigned int edge_clear;
477 unsigned int invert_set;
478 unsigned int invert_clear;
479 unsigned int pinstate;
483 static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
484 (struct pin_int_t *)PINT0_MASK_SET,
485 (struct pin_int_t *)PINT1_MASK_SET,
486 (struct pin_int_t *)PINT2_MASK_SET,
487 (struct pin_int_t *)PINT3_MASK_SET,
490 unsigned short get_irq_base(u8 bank, u8 bmap)
495 if (bank < 2) { /*PA-PB */
496 irq_base = IRQ_PA0 + bmap * 16;
498 irq_base = IRQ_PC0 + bmap * 16;
505 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
506 void init_pint_lut(void)
508 u16 bank, bit, irq_base, bit_pos;
512 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
514 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
516 pint_assign = pint[bank]->assign;
518 for (bit = 0; bit < NR_PINT_BITS; bit++) {
520 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
522 irq_base = get_irq_base(bank, bmap);
524 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
525 bit_pos = bit + bank * NR_PINT_BITS;
527 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
528 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
536 static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
538 static void bfin_gpio_ack_irq(unsigned int irq)
540 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
542 pint[PINT_2_BANK(pint_val)]->request = PINT_BIT(pint_val);
546 static void bfin_gpio_mask_ack_irq(unsigned int irq)
548 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
549 u32 pintbit = PINT_BIT(pint_val);
550 u8 bank = PINT_2_BANK(pint_val);
552 pint[bank]->request = pintbit;
553 pint[bank]->mask_clear = pintbit;
557 static void bfin_gpio_mask_irq(unsigned int irq)
559 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
561 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
565 static void bfin_gpio_unmask_irq(unsigned int irq)
567 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
568 u32 pintbit = PINT_BIT(pint_val);
569 u8 bank = PINT_2_BANK(pint_val);
571 pint[bank]->request = pintbit;
572 pint[bank]->mask_set = pintbit;
576 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
579 u16 gpionr = irq - IRQ_PA0;
580 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
582 if (pint_val == IRQ_NOT_AVAIL)
585 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
586 ret = gpio_request(gpionr, NULL);
591 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
592 bfin_gpio_unmask_irq(irq);
597 static void bfin_gpio_irq_shutdown(unsigned int irq)
599 bfin_gpio_mask_irq(irq);
600 gpio_free(irq - IRQ_PA0);
601 gpio_enabled[gpio_bank(irq - IRQ_PA0)] &= ~gpio_bit(irq - IRQ_PA0);
604 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
608 u16 gpionr = irq - IRQ_PA0;
609 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
610 u32 pintbit = PINT_BIT(pint_val);
611 u8 bank = PINT_2_BANK(pint_val);
613 if (pint_val == IRQ_NOT_AVAIL)
616 if (type == IRQ_TYPE_PROBE) {
617 /* only probe unenabled GPIO interrupt lines */
618 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
620 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
623 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
624 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
625 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
626 ret = gpio_request(gpionr, NULL);
631 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
633 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
637 gpio_direction_input(gpionr);
639 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
640 pint[bank]->edge_set = pintbit;
642 pint[bank]->edge_clear = pintbit;
645 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
646 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
648 pint[bank]->invert_set = pintbit; /* high or rising edge denoted by zero */
650 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
651 pint[bank]->invert_set = pintbit;
653 pint[bank]->invert_set = pintbit;
657 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
658 set_irq_handler(irq, handle_edge_irq);
660 set_irq_handler(irq, handle_level_irq);
665 static struct irq_chip bfin_gpio_irqchip = {
666 .ack = bfin_gpio_ack_irq,
667 .mask = bfin_gpio_mask_irq,
668 .mask_ack = bfin_gpio_mask_ack_irq,
669 .unmask = bfin_gpio_unmask_irq,
670 .set_type = bfin_gpio_irq_type,
671 .startup = bfin_gpio_irq_startup,
672 .shutdown = bfin_gpio_irq_shutdown
675 static void bfin_demux_gpio_irq(unsigned int intb_irq,
676 struct irq_desc *intb_desc)
680 struct irq_desc *desc;
699 pint_val = bank * NR_PINT_BITS;
701 request = pint[bank]->request;
705 irq = pint2irq_lut[pint_val] + SYS_IRQS;
706 desc = irq_desc + irq;
707 desc->handle_irq(irq, desc);
714 #endif /* CONFIG_IRQCHIP_DEMUX_GPIO */
717 * This function should be called during kernel startup to initialize
718 * the BFin IRQ handling routines.
720 int __init init_arch_irq(void)
723 unsigned long ilat = 0;
724 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
726 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
727 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
728 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
729 bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
730 bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
731 bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
733 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
734 bfin_write_SIC_IWR(IWR_ENABLE_ALL);
742 bfin_write_EVT0(evt_emulation);
744 bfin_write_EVT2(evt_evt2);
745 bfin_write_EVT3(trap);
746 bfin_write_EVT5(evt_ivhw);
747 bfin_write_EVT6(evt_timer);
748 bfin_write_EVT7(evt_evt7);
749 bfin_write_EVT8(evt_evt8);
750 bfin_write_EVT9(evt_evt9);
751 bfin_write_EVT10(evt_evt10);
752 bfin_write_EVT11(evt_evt11);
753 bfin_write_EVT12(evt_evt12);
754 bfin_write_EVT13(evt_evt13);
755 bfin_write_EVT14(evt14_softirq);
756 bfin_write_EVT15(evt_system_call);
759 #if defined(CONFIG_IRQCHIP_DEMUX_GPIO) && defined(CONFIG_BF54x)
760 #ifdef CONFIG_PINTx_REASSIGN
761 pint[0]->assign = CONFIG_PINT0_ASSIGN;
762 pint[1]->assign = CONFIG_PINT1_ASSIGN;
763 pint[2]->assign = CONFIG_PINT2_ASSIGN;
764 pint[3]->assign = CONFIG_PINT3_ASSIGN;
766 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
770 for (irq = 0; irq <= SYS_IRQS; irq++) {
771 if (irq <= IRQ_CORETMR)
772 set_irq_chip(irq, &bfin_core_irqchip);
774 set_irq_chip(irq, &bfin_internal_irqchip);
775 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
776 if (irq != IRQ_GENERIC_ERROR) {
780 #ifdef CONFIG_IRQCHIP_DEMUX_GPIO
783 set_irq_chained_handler(irq,
784 bfin_demux_gpio_irq);
786 #if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
788 set_irq_chained_handler(irq,
789 bfin_demux_gpio_irq);
794 set_irq_chained_handler(irq,
795 bfin_demux_gpio_irq);
798 set_irq_chained_handler(irq,
799 bfin_demux_gpio_irq);
802 set_irq_chained_handler(irq,
803 bfin_demux_gpio_irq);
806 set_irq_chained_handler(irq,
807 bfin_demux_gpio_irq);
809 #endif /*CONFIG_BF54x */
812 set_irq_handler(irq, handle_simple_irq);
816 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
818 set_irq_handler(irq, bfin_demux_error_irq);
822 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
823 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++) {
824 set_irq_chip(irq, &bfin_generic_error_irqchip);
825 set_irq_handler(irq, handle_level_irq);
829 #ifdef CONFIG_IRQCHIP_DEMUX_GPIO
831 for (irq = IRQ_PF0; irq < NR_IRQS; irq++) {
833 for (irq = IRQ_PA0; irq < NR_IRQS; irq++) {
835 set_irq_chip(irq, &bfin_gpio_irqchip);
836 /* if configured as edge, then will be changed to do_edge_IRQ */
837 set_irq_handler(irq, handle_level_irq);
842 ilat = bfin_read_ILAT();
844 bfin_write_ILAT(ilat);
847 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
848 /* IMASK=xxx is equivalent to STI xx or irq_flags=xx,
852 /* Therefore it's better to setup IARs before interrupts enabled */
855 /* Enable interrupts IVG7-15 */
856 irq_flags = irq_flags | IMASK_IVG15 |
857 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
858 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
863 #ifdef CONFIG_DO_IRQ_L1
864 void do_irq(int vec, struct pt_regs *fp) __attribute__((l1_text));
867 void do_irq(int vec, struct pt_regs *fp)
869 if (vec == EVT_IVTMR_P) {
872 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
873 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
875 unsigned long sic_status[3];
878 sic_status[0] = bfin_read_SIC_ISR(0) & bfin_read_SIC_IMASK(0);
879 sic_status[1] = bfin_read_SIC_ISR(1) & bfin_read_SIC_IMASK(1);
880 sic_status[2] = bfin_read_SIC_ISR(2) & bfin_read_SIC_IMASK(2);
883 if (ivg >= ivg_stop) {
884 atomic_inc(&num_spurious);
887 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
891 unsigned long sic_status;
893 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
896 if (ivg >= ivg_stop) {
897 atomic_inc(&num_spurious);
899 } else if (sic_status & ivg->isrflag)
908 kgdb_process_breakpoint();