1 Every GPIO controller node must have #gpio-cells property defined,
2 this information will be used to translate gpio-specifiers.
4 On CPM1 devices, all ports are using slightly different register layouts.
5 Ports A, C and D are 16bit ports and Ports B and E are 32bit ports.
7 On CPM2 devices, all ports are 32bit ports and use a common register layout.
10 - compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
11 "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
12 "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
13 - #gpio-cells : Should be two. The first cell is the pin number and the
14 second cell is used to specify optional paramters (currently unused).
15 - gpio-controller : Marks the port as GPIO controller.
17 Example of three SOC GPIO banks defined as gpio-controller nodes:
19 CPM1_PIO_A: gpio-controller@950 {
21 compatible = "fsl,cpm1-pario-bank-a";
26 CPM1_PIO_B: gpio-controller@ab8 {
28 compatible = "fsl,cpm1-pario-bank-b";
33 CPM1_PIO_E: gpio-controller@ac8 {
35 compatible = "fsl,cpm1-pario-bank-e";