2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
9 #include <linux/delay.h>
12 qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump)
14 fw_dump->fw_major_version = htonl(ha->fw_major_version);
15 fw_dump->fw_minor_version = htonl(ha->fw_minor_version);
16 fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version);
17 fw_dump->fw_attributes = htonl(ha->fw_attributes);
19 fw_dump->vendor = htonl(ha->pdev->vendor);
20 fw_dump->device = htonl(ha->pdev->device);
21 fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor);
22 fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device);
26 qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr)
28 struct req_que *req = ha->req_q_map[0];
29 struct rsp_que *rsp = ha->rsp_q_map[0];
31 memcpy(ptr, req->ring, req->length *
35 ptr += req->length * sizeof(request_t);
36 memcpy(ptr, rsp->ring, rsp->length *
39 return ptr + (rsp->length * sizeof(response_t));
43 qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram,
44 uint32_t ram_dwords, void **nxt)
47 uint32_t cnt, stat, timer, dwords, idx;
49 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
50 dma_addr_t dump_dma = ha->gid_list_dma;
51 uint32_t *dump = (uint32_t *)ha->gid_list;
56 WRT_REG_WORD(®->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
57 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
59 dwords = GID_LIST_SIZE / 4;
60 for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
61 cnt += dwords, addr += dwords) {
62 if (cnt + dwords > ram_dwords)
63 dwords = ram_dwords - cnt;
65 WRT_REG_WORD(®->mailbox1, LSW(addr));
66 WRT_REG_WORD(®->mailbox8, MSW(addr));
68 WRT_REG_WORD(®->mailbox2, MSW(dump_dma));
69 WRT_REG_WORD(®->mailbox3, LSW(dump_dma));
70 WRT_REG_WORD(®->mailbox6, MSW(MSD(dump_dma)));
71 WRT_REG_WORD(®->mailbox7, LSW(MSD(dump_dma)));
73 WRT_REG_WORD(®->mailbox4, MSW(dwords));
74 WRT_REG_WORD(®->mailbox5, LSW(dwords));
75 WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT);
77 for (timer = 6000000; timer; timer--) {
78 /* Check for pending interrupts. */
79 stat = RD_REG_DWORD(®->host_status);
80 if (stat & HSRX_RISC_INT) {
83 if (stat == 0x1 || stat == 0x2 ||
84 stat == 0x10 || stat == 0x11) {
85 set_bit(MBX_INTERRUPT,
88 mb0 = RD_REG_WORD(®->mailbox0);
90 WRT_REG_DWORD(®->hccr,
92 RD_REG_DWORD(®->hccr);
96 /* Clear this intr; it wasn't a mailbox intr */
97 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT);
98 RD_REG_DWORD(®->hccr);
103 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
104 rval = mb0 & MBS_MASK;
105 for (idx = 0; idx < dwords; idx++)
106 ram[cnt + idx] = swab32(dump[idx]);
108 rval = QLA_FUNCTION_FAILED;
112 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
117 qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram,
118 uint32_t cram_size, void **nxt)
123 rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt);
124 if (rval != QLA_SUCCESS)
127 /* External Memory. */
128 return qla24xx_dump_ram(ha, 0x100000, *nxt,
129 ha->fw_memory_size - 0x100000 + 1, nxt);
133 qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
134 uint32_t count, uint32_t *buf)
136 uint32_t __iomem *dmp_reg;
138 WRT_REG_DWORD(®->iobase_addr, iobase);
139 dmp_reg = ®->iobase_window;
141 *buf++ = htonl(RD_REG_DWORD(dmp_reg++));
147 qla24xx_pause_risc(struct device_reg_24xx __iomem *reg)
149 int rval = QLA_SUCCESS;
152 if (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE)
155 WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE);
156 for (cnt = 30000; (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0 &&
157 rval == QLA_SUCCESS; cnt--) {
161 rval = QLA_FUNCTION_TIMEOUT;
168 qla24xx_soft_reset(struct qla_hw_data *ha)
170 int rval = QLA_SUCCESS;
173 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
176 WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
177 for (cnt = 0; cnt < 30000; cnt++) {
178 if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
184 WRT_REG_DWORD(®->ctrl_status,
185 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
186 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
189 /* Wait for firmware to complete NVRAM accesses. */
190 mb0 = (uint32_t) RD_REG_WORD(®->mailbox0);
191 for (cnt = 10000 ; cnt && mb0; cnt--) {
193 mb0 = (uint32_t) RD_REG_WORD(®->mailbox0);
197 /* Wait for soft-reset to complete. */
198 for (cnt = 0; cnt < 30000; cnt++) {
199 if ((RD_REG_DWORD(®->ctrl_status) &
200 CSRX_ISP_SOFT_RESET) == 0)
205 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET);
206 RD_REG_DWORD(®->hccr); /* PCI Posting. */
208 for (cnt = 30000; RD_REG_WORD(®->mailbox0) != 0 &&
209 rval == QLA_SUCCESS; cnt--) {
213 rval = QLA_FUNCTION_TIMEOUT;
220 qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint16_t *ram,
221 uint16_t ram_words, void **nxt)
224 uint32_t cnt, stat, timer, words, idx;
226 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
227 dma_addr_t dump_dma = ha->gid_list_dma;
228 uint16_t *dump = (uint16_t *)ha->gid_list;
233 WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED);
234 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
236 words = GID_LIST_SIZE / 2;
237 for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS;
238 cnt += words, addr += words) {
239 if (cnt + words > ram_words)
240 words = ram_words - cnt;
242 WRT_MAILBOX_REG(ha, reg, 1, LSW(addr));
243 WRT_MAILBOX_REG(ha, reg, 8, MSW(addr));
245 WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma));
246 WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma));
247 WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma)));
248 WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma)));
250 WRT_MAILBOX_REG(ha, reg, 4, words);
251 WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT);
253 for (timer = 6000000; timer; timer--) {
254 /* Check for pending interrupts. */
255 stat = RD_REG_DWORD(®->u.isp2300.host_status);
256 if (stat & HSR_RISC_INT) {
259 if (stat == 0x1 || stat == 0x2) {
260 set_bit(MBX_INTERRUPT,
263 mb0 = RD_MAILBOX_REG(ha, reg, 0);
265 /* Release mailbox registers. */
266 WRT_REG_WORD(®->semaphore, 0);
267 WRT_REG_WORD(®->hccr,
269 RD_REG_WORD(®->hccr);
271 } else if (stat == 0x10 || stat == 0x11) {
272 set_bit(MBX_INTERRUPT,
275 mb0 = RD_MAILBOX_REG(ha, reg, 0);
277 WRT_REG_WORD(®->hccr,
279 RD_REG_WORD(®->hccr);
283 /* clear this intr; it wasn't a mailbox intr */
284 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT);
285 RD_REG_WORD(®->hccr);
290 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
291 rval = mb0 & MBS_MASK;
292 for (idx = 0; idx < words; idx++)
293 ram[cnt + idx] = swab16(dump[idx]);
295 rval = QLA_FUNCTION_FAILED;
299 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
304 qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
307 uint16_t __iomem *dmp_reg = ®->u.isp2300.fb_cmd;
310 *buf++ = htons(RD_REG_WORD(dmp_reg++));
314 qla24xx_copy_eft(struct qla_hw_data *ha, void *ptr)
319 memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size));
320 return ptr + ntohl(ha->fw_dump->eft_size);
324 qla25xx_copy_fce(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
328 struct qla2xxx_fce_chain *fcec = ptr;
333 *last_chain = &fcec->type;
334 fcec->type = __constant_htonl(DUMP_CHAIN_FCE);
335 fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) +
336 fce_calc_size(ha->fce_bufs));
337 fcec->size = htonl(fce_calc_size(ha->fce_bufs));
338 fcec->addr_l = htonl(LSD(ha->fce_dma));
339 fcec->addr_h = htonl(MSD(ha->fce_dma));
341 iter_reg = fcec->eregs;
342 for (cnt = 0; cnt < 8; cnt++)
343 *iter_reg++ = htonl(ha->fce_mb[cnt]);
345 memcpy(iter_reg, ha->fce, ntohl(fcec->size));
351 qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
353 uint32_t cnt, que_idx;
355 struct qla2xxx_mq_chain *mq = ptr;
356 struct device_reg_25xxmq __iomem *reg;
362 *last_chain = &mq->type;
363 mq->type = __constant_htonl(DUMP_CHAIN_MQ);
364 mq->chain_size = __constant_htonl(sizeof(struct qla2xxx_mq_chain));
366 que_cnt = ha->max_req_queues > ha->max_rsp_queues ?
367 ha->max_req_queues : ha->max_rsp_queues;
368 mq->count = htonl(que_cnt);
369 for (cnt = 0; cnt < que_cnt; cnt++) {
370 reg = (struct device_reg_25xxmq *) ((void *)
371 ha->mqiobase + cnt * QLA_QUE_PAGE);
373 mq->qregs[que_idx] = htonl(RD_REG_DWORD(®->req_q_in));
374 mq->qregs[que_idx+1] = htonl(RD_REG_DWORD(®->req_q_out));
375 mq->qregs[que_idx+2] = htonl(RD_REG_DWORD(®->rsp_q_in));
376 mq->qregs[que_idx+3] = htonl(RD_REG_DWORD(®->rsp_q_out));
379 return ptr + sizeof(struct qla2xxx_mq_chain);
383 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
385 * @hardware_locked: Called with the hardware_lock
388 qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
392 struct qla_hw_data *ha = vha->hw;
393 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
394 uint16_t __iomem *dmp_reg;
396 struct qla2300_fw_dump *fw;
398 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
402 if (!hardware_locked)
403 spin_lock_irqsave(&ha->hardware_lock, flags);
406 qla_printk(KERN_WARNING, ha,
407 "No buffer available for dump!!!\n");
408 goto qla2300_fw_dump_failed;
412 qla_printk(KERN_WARNING, ha,
413 "Firmware has been previously dumped (%p) -- ignoring "
414 "request...\n", ha->fw_dump);
415 goto qla2300_fw_dump_failed;
417 fw = &ha->fw_dump->isp.isp23;
418 qla2xxx_prep_dump(ha, ha->fw_dump);
421 fw->hccr = htons(RD_REG_WORD(®->hccr));
424 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
425 if (IS_QLA2300(ha)) {
427 (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 &&
428 rval == QLA_SUCCESS; cnt--) {
432 rval = QLA_FUNCTION_TIMEOUT;
435 RD_REG_WORD(®->hccr); /* PCI Posting. */
439 if (rval == QLA_SUCCESS) {
440 dmp_reg = ®->flash_address;
441 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
442 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
444 dmp_reg = ®->u.isp2300.req_q_in;
445 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
446 fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
448 dmp_reg = ®->u.isp2300.mailbox0;
449 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
450 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
452 WRT_REG_WORD(®->ctrl_status, 0x40);
453 qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
455 WRT_REG_WORD(®->ctrl_status, 0x50);
456 qla2xxx_read_window(reg, 48, fw->dma_reg);
458 WRT_REG_WORD(®->ctrl_status, 0x00);
459 dmp_reg = ®->risc_hw;
460 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
461 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
463 WRT_REG_WORD(®->pcr, 0x2000);
464 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
466 WRT_REG_WORD(®->pcr, 0x2200);
467 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
469 WRT_REG_WORD(®->pcr, 0x2400);
470 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
472 WRT_REG_WORD(®->pcr, 0x2600);
473 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
475 WRT_REG_WORD(®->pcr, 0x2800);
476 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
478 WRT_REG_WORD(®->pcr, 0x2A00);
479 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
481 WRT_REG_WORD(®->pcr, 0x2C00);
482 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
484 WRT_REG_WORD(®->pcr, 0x2E00);
485 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
487 WRT_REG_WORD(®->ctrl_status, 0x10);
488 qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg);
490 WRT_REG_WORD(®->ctrl_status, 0x20);
491 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
493 WRT_REG_WORD(®->ctrl_status, 0x30);
494 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
497 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET);
498 for (cnt = 0; cnt < 30000; cnt++) {
499 if ((RD_REG_WORD(®->ctrl_status) &
500 CSR_ISP_SOFT_RESET) == 0)
507 if (!IS_QLA2300(ha)) {
508 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
509 rval == QLA_SUCCESS; cnt--) {
513 rval = QLA_FUNCTION_TIMEOUT;
518 if (rval == QLA_SUCCESS)
519 rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram,
520 sizeof(fw->risc_ram) / 2, &nxt);
522 /* Get stack SRAM. */
523 if (rval == QLA_SUCCESS)
524 rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram,
525 sizeof(fw->stack_ram) / 2, &nxt);
528 if (rval == QLA_SUCCESS)
529 rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram,
530 ha->fw_memory_size - 0x11000 + 1, &nxt);
532 if (rval == QLA_SUCCESS)
533 qla2xxx_copy_queues(ha, nxt);
535 if (rval != QLA_SUCCESS) {
536 qla_printk(KERN_WARNING, ha,
537 "Failed to dump firmware (%x)!!!\n", rval);
541 qla_printk(KERN_INFO, ha,
542 "Firmware dump saved to temp buffer (%ld/%p).\n",
543 base_vha->host_no, ha->fw_dump);
547 qla2300_fw_dump_failed:
548 if (!hardware_locked)
549 spin_unlock_irqrestore(&ha->hardware_lock, flags);
553 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
555 * @hardware_locked: Called with the hardware_lock
558 qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
562 uint16_t risc_address;
564 struct qla_hw_data *ha = vha->hw;
565 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
566 uint16_t __iomem *dmp_reg;
568 struct qla2100_fw_dump *fw;
569 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
575 if (!hardware_locked)
576 spin_lock_irqsave(&ha->hardware_lock, flags);
579 qla_printk(KERN_WARNING, ha,
580 "No buffer available for dump!!!\n");
581 goto qla2100_fw_dump_failed;
585 qla_printk(KERN_WARNING, ha,
586 "Firmware has been previously dumped (%p) -- ignoring "
587 "request...\n", ha->fw_dump);
588 goto qla2100_fw_dump_failed;
590 fw = &ha->fw_dump->isp.isp21;
591 qla2xxx_prep_dump(ha, ha->fw_dump);
594 fw->hccr = htons(RD_REG_WORD(®->hccr));
597 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
598 for (cnt = 30000; (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 &&
599 rval == QLA_SUCCESS; cnt--) {
603 rval = QLA_FUNCTION_TIMEOUT;
605 if (rval == QLA_SUCCESS) {
606 dmp_reg = ®->flash_address;
607 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
608 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
610 dmp_reg = ®->u.isp2100.mailbox0;
611 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
613 dmp_reg = ®->u_end.isp2200.mailbox8;
615 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
618 dmp_reg = ®->u.isp2100.unused_2[0];
619 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
620 fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
622 WRT_REG_WORD(®->ctrl_status, 0x00);
623 dmp_reg = ®->risc_hw;
624 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
625 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
627 WRT_REG_WORD(®->pcr, 0x2000);
628 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
630 WRT_REG_WORD(®->pcr, 0x2100);
631 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
633 WRT_REG_WORD(®->pcr, 0x2200);
634 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
636 WRT_REG_WORD(®->pcr, 0x2300);
637 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
639 WRT_REG_WORD(®->pcr, 0x2400);
640 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
642 WRT_REG_WORD(®->pcr, 0x2500);
643 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
645 WRT_REG_WORD(®->pcr, 0x2600);
646 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
648 WRT_REG_WORD(®->pcr, 0x2700);
649 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
651 WRT_REG_WORD(®->ctrl_status, 0x10);
652 qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg);
654 WRT_REG_WORD(®->ctrl_status, 0x20);
655 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
657 WRT_REG_WORD(®->ctrl_status, 0x30);
658 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
661 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET);
664 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
665 rval == QLA_SUCCESS; cnt--) {
669 rval = QLA_FUNCTION_TIMEOUT;
673 if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) &&
674 (RD_REG_WORD(®->mctr) & (BIT_1 | BIT_0)) != 0))) {
676 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
678 (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 &&
679 rval == QLA_SUCCESS; cnt--) {
683 rval = QLA_FUNCTION_TIMEOUT;
685 if (rval == QLA_SUCCESS) {
686 /* Set memory configuration and timing. */
688 WRT_REG_WORD(®->mctr, 0xf1);
690 WRT_REG_WORD(®->mctr, 0xf2);
691 RD_REG_WORD(®->mctr); /* PCI Posting. */
694 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC);
698 if (rval == QLA_SUCCESS) {
700 risc_address = 0x1000;
701 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
702 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
704 for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
705 cnt++, risc_address++) {
706 WRT_MAILBOX_REG(ha, reg, 1, risc_address);
707 WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT);
709 for (timer = 6000000; timer != 0; timer--) {
710 /* Check for pending interrupts. */
711 if (RD_REG_WORD(®->istatus) & ISR_RISC_INT) {
712 if (RD_REG_WORD(®->semaphore) & BIT_0) {
713 set_bit(MBX_INTERRUPT,
716 mb0 = RD_MAILBOX_REG(ha, reg, 0);
717 mb2 = RD_MAILBOX_REG(ha, reg, 2);
719 WRT_REG_WORD(®->semaphore, 0);
720 WRT_REG_WORD(®->hccr,
722 RD_REG_WORD(®->hccr);
725 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT);
726 RD_REG_WORD(®->hccr);
731 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
732 rval = mb0 & MBS_MASK;
733 fw->risc_ram[cnt] = htons(mb2);
735 rval = QLA_FUNCTION_FAILED;
739 if (rval == QLA_SUCCESS)
740 qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]);
742 if (rval != QLA_SUCCESS) {
743 qla_printk(KERN_WARNING, ha,
744 "Failed to dump firmware (%x)!!!\n", rval);
748 qla_printk(KERN_INFO, ha,
749 "Firmware dump saved to temp buffer (%ld/%p).\n",
750 base_vha->host_no, ha->fw_dump);
754 qla2100_fw_dump_failed:
755 if (!hardware_locked)
756 spin_unlock_irqrestore(&ha->hardware_lock, flags);
760 qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
764 uint32_t risc_address;
765 struct qla_hw_data *ha = vha->hw;
766 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
767 uint32_t __iomem *dmp_reg;
769 uint16_t __iomem *mbx_reg;
771 struct qla24xx_fw_dump *fw;
772 uint32_t ext_mem_cnt;
774 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
776 risc_address = ext_mem_cnt = 0;
779 if (!hardware_locked)
780 spin_lock_irqsave(&ha->hardware_lock, flags);
783 qla_printk(KERN_WARNING, ha,
784 "No buffer available for dump!!!\n");
785 goto qla24xx_fw_dump_failed;
789 qla_printk(KERN_WARNING, ha,
790 "Firmware has been previously dumped (%p) -- ignoring "
791 "request...\n", ha->fw_dump);
792 goto qla24xx_fw_dump_failed;
794 fw = &ha->fw_dump->isp.isp24;
795 qla2xxx_prep_dump(ha, ha->fw_dump);
797 fw->host_status = htonl(RD_REG_DWORD(®->host_status));
800 rval = qla24xx_pause_risc(reg);
801 if (rval != QLA_SUCCESS)
802 goto qla24xx_fw_dump_failed_0;
804 /* Host interface registers. */
805 dmp_reg = ®->flash_addr;
806 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
807 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
809 /* Disable interrupts. */
810 WRT_REG_DWORD(®->ictrl, 0);
811 RD_REG_DWORD(®->ictrl);
813 /* Shadow registers. */
814 WRT_REG_DWORD(®->iobase_addr, 0x0F70);
815 RD_REG_DWORD(®->iobase_addr);
816 WRT_REG_DWORD(®->iobase_select, 0xB0000000);
817 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata));
819 WRT_REG_DWORD(®->iobase_select, 0xB0100000);
820 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata));
822 WRT_REG_DWORD(®->iobase_select, 0xB0200000);
823 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata));
825 WRT_REG_DWORD(®->iobase_select, 0xB0300000);
826 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata));
828 WRT_REG_DWORD(®->iobase_select, 0xB0400000);
829 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata));
831 WRT_REG_DWORD(®->iobase_select, 0xB0500000);
832 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata));
834 WRT_REG_DWORD(®->iobase_select, 0xB0600000);
835 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata));
837 /* Mailbox registers. */
838 mbx_reg = ®->mailbox0;
839 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
840 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
842 /* Transfer sequence registers. */
843 iter_reg = fw->xseq_gp_reg;
844 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
845 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
846 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
847 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
848 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
849 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
850 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
851 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
853 qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg);
854 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
856 /* Receive sequence registers. */
857 iter_reg = fw->rseq_gp_reg;
858 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
859 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
860 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
861 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
862 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
863 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
864 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
865 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
867 qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg);
868 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
869 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
871 /* Command DMA registers. */
872 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
875 iter_reg = fw->req0_dma_reg;
876 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
877 dmp_reg = ®->iobase_q;
878 for (cnt = 0; cnt < 7; cnt++)
879 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
881 iter_reg = fw->resp0_dma_reg;
882 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
883 dmp_reg = ®->iobase_q;
884 for (cnt = 0; cnt < 7; cnt++)
885 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
887 iter_reg = fw->req1_dma_reg;
888 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
889 dmp_reg = ®->iobase_q;
890 for (cnt = 0; cnt < 7; cnt++)
891 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
893 /* Transmit DMA registers. */
894 iter_reg = fw->xmt0_dma_reg;
895 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
896 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
898 iter_reg = fw->xmt1_dma_reg;
899 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
900 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
902 iter_reg = fw->xmt2_dma_reg;
903 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
904 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
906 iter_reg = fw->xmt3_dma_reg;
907 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
908 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
910 iter_reg = fw->xmt4_dma_reg;
911 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
912 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
914 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
916 /* Receive DMA registers. */
917 iter_reg = fw->rcvt0_data_dma_reg;
918 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
919 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
921 iter_reg = fw->rcvt1_data_dma_reg;
922 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
923 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
925 /* RISC registers. */
926 iter_reg = fw->risc_gp_reg;
927 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
928 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
929 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
930 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
931 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
932 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
933 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
934 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
936 /* Local memory controller registers. */
937 iter_reg = fw->lmc_reg;
938 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
939 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
940 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
941 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
942 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
943 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
944 qla24xx_read_window(reg, 0x3060, 16, iter_reg);
946 /* Fibre Protocol Module registers. */
947 iter_reg = fw->fpm_hdw_reg;
948 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
949 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
950 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
951 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
952 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
953 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
954 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
955 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
956 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
957 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
958 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
959 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
961 /* Frame Buffer registers. */
962 iter_reg = fw->fb_hdw_reg;
963 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
964 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
965 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
966 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
967 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
968 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
969 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
970 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
971 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
972 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
973 qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
975 rval = qla24xx_soft_reset(ha);
976 if (rval != QLA_SUCCESS)
977 goto qla24xx_fw_dump_failed_0;
979 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
981 if (rval != QLA_SUCCESS)
982 goto qla24xx_fw_dump_failed_0;
984 nxt = qla2xxx_copy_queues(ha, nxt);
986 qla24xx_copy_eft(ha, nxt);
988 qla24xx_fw_dump_failed_0:
989 if (rval != QLA_SUCCESS) {
990 qla_printk(KERN_WARNING, ha,
991 "Failed to dump firmware (%x)!!!\n", rval);
995 qla_printk(KERN_INFO, ha,
996 "Firmware dump saved to temp buffer (%ld/%p).\n",
997 base_vha->host_no, ha->fw_dump);
1001 qla24xx_fw_dump_failed:
1002 if (!hardware_locked)
1003 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1007 qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1011 uint32_t risc_address;
1012 struct qla_hw_data *ha = vha->hw;
1013 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1014 uint32_t __iomem *dmp_reg;
1016 uint16_t __iomem *mbx_reg;
1017 unsigned long flags;
1018 struct qla25xx_fw_dump *fw;
1019 uint32_t ext_mem_cnt;
1020 void *nxt, *nxt_chain;
1021 uint32_t *last_chain = NULL;
1022 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1024 risc_address = ext_mem_cnt = 0;
1027 if (!hardware_locked)
1028 spin_lock_irqsave(&ha->hardware_lock, flags);
1031 qla_printk(KERN_WARNING, ha,
1032 "No buffer available for dump!!!\n");
1033 goto qla25xx_fw_dump_failed;
1036 if (ha->fw_dumped) {
1037 qla_printk(KERN_WARNING, ha,
1038 "Firmware has been previously dumped (%p) -- ignoring "
1039 "request...\n", ha->fw_dump);
1040 goto qla25xx_fw_dump_failed;
1042 fw = &ha->fw_dump->isp.isp25;
1043 qla2xxx_prep_dump(ha, ha->fw_dump);
1044 ha->fw_dump->version = __constant_htonl(2);
1046 fw->host_status = htonl(RD_REG_DWORD(®->host_status));
1049 rval = qla24xx_pause_risc(reg);
1050 if (rval != QLA_SUCCESS)
1051 goto qla25xx_fw_dump_failed_0;
1053 /* Host/Risc registers. */
1054 iter_reg = fw->host_risc_reg;
1055 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1056 qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1058 /* PCIe registers. */
1059 WRT_REG_DWORD(®->iobase_addr, 0x7C00);
1060 RD_REG_DWORD(®->iobase_addr);
1061 WRT_REG_DWORD(®->iobase_window, 0x01);
1062 dmp_reg = ®->iobase_c4;
1063 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1064 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1065 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1066 fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window));
1068 WRT_REG_DWORD(®->iobase_window, 0x00);
1069 RD_REG_DWORD(®->iobase_window);
1071 /* Host interface registers. */
1072 dmp_reg = ®->flash_addr;
1073 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1074 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1076 /* Disable interrupts. */
1077 WRT_REG_DWORD(®->ictrl, 0);
1078 RD_REG_DWORD(®->ictrl);
1080 /* Shadow registers. */
1081 WRT_REG_DWORD(®->iobase_addr, 0x0F70);
1082 RD_REG_DWORD(®->iobase_addr);
1083 WRT_REG_DWORD(®->iobase_select, 0xB0000000);
1084 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata));
1086 WRT_REG_DWORD(®->iobase_select, 0xB0100000);
1087 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata));
1089 WRT_REG_DWORD(®->iobase_select, 0xB0200000);
1090 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata));
1092 WRT_REG_DWORD(®->iobase_select, 0xB0300000);
1093 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata));
1095 WRT_REG_DWORD(®->iobase_select, 0xB0400000);
1096 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata));
1098 WRT_REG_DWORD(®->iobase_select, 0xB0500000);
1099 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata));
1101 WRT_REG_DWORD(®->iobase_select, 0xB0600000);
1102 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata));
1104 WRT_REG_DWORD(®->iobase_select, 0xB0700000);
1105 fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata));
1107 WRT_REG_DWORD(®->iobase_select, 0xB0800000);
1108 fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata));
1110 WRT_REG_DWORD(®->iobase_select, 0xB0900000);
1111 fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata));
1113 WRT_REG_DWORD(®->iobase_select, 0xB0A00000);
1114 fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata));
1116 /* RISC I/O register. */
1117 WRT_REG_DWORD(®->iobase_addr, 0x0010);
1118 fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window));
1120 /* Mailbox registers. */
1121 mbx_reg = ®->mailbox0;
1122 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1123 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1125 /* Transfer sequence registers. */
1126 iter_reg = fw->xseq_gp_reg;
1127 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1128 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1129 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1130 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1131 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1132 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1133 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1134 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1136 iter_reg = fw->xseq_0_reg;
1137 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1138 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1139 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1141 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1143 /* Receive sequence registers. */
1144 iter_reg = fw->rseq_gp_reg;
1145 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1146 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1147 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1148 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1149 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1150 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1151 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1152 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1154 iter_reg = fw->rseq_0_reg;
1155 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1156 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1158 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1159 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1161 /* Auxiliary sequence registers. */
1162 iter_reg = fw->aseq_gp_reg;
1163 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1164 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1165 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1166 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1167 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1168 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1169 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1170 qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1172 iter_reg = fw->aseq_0_reg;
1173 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1174 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1176 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1177 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1179 /* Command DMA registers. */
1180 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1183 iter_reg = fw->req0_dma_reg;
1184 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1185 dmp_reg = ®->iobase_q;
1186 for (cnt = 0; cnt < 7; cnt++)
1187 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1189 iter_reg = fw->resp0_dma_reg;
1190 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1191 dmp_reg = ®->iobase_q;
1192 for (cnt = 0; cnt < 7; cnt++)
1193 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1195 iter_reg = fw->req1_dma_reg;
1196 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1197 dmp_reg = ®->iobase_q;
1198 for (cnt = 0; cnt < 7; cnt++)
1199 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1201 /* Transmit DMA registers. */
1202 iter_reg = fw->xmt0_dma_reg;
1203 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1204 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1206 iter_reg = fw->xmt1_dma_reg;
1207 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1208 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1210 iter_reg = fw->xmt2_dma_reg;
1211 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1212 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1214 iter_reg = fw->xmt3_dma_reg;
1215 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1216 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1218 iter_reg = fw->xmt4_dma_reg;
1219 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1220 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1222 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1224 /* Receive DMA registers. */
1225 iter_reg = fw->rcvt0_data_dma_reg;
1226 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1227 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1229 iter_reg = fw->rcvt1_data_dma_reg;
1230 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1231 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1233 /* RISC registers. */
1234 iter_reg = fw->risc_gp_reg;
1235 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1236 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1237 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1238 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1239 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1240 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1241 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1242 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1244 /* Local memory controller registers. */
1245 iter_reg = fw->lmc_reg;
1246 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1247 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1248 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1249 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1250 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1251 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1252 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1253 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1255 /* Fibre Protocol Module registers. */
1256 iter_reg = fw->fpm_hdw_reg;
1257 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1258 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1259 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1260 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1261 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1262 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1263 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1264 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1265 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1266 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1267 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1268 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1270 /* Frame Buffer registers. */
1271 iter_reg = fw->fb_hdw_reg;
1272 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1273 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1274 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1275 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1276 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1277 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1278 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1279 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1280 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1281 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1282 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1283 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1285 /* Multi queue registers */
1286 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
1289 rval = qla24xx_soft_reset(ha);
1290 if (rval != QLA_SUCCESS)
1291 goto qla25xx_fw_dump_failed_0;
1293 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1295 if (rval != QLA_SUCCESS)
1296 goto qla25xx_fw_dump_failed_0;
1298 nxt = qla2xxx_copy_queues(ha, nxt);
1300 nxt = qla24xx_copy_eft(ha, nxt);
1302 /* Chain entries -- started with MQ. */
1303 qla25xx_copy_fce(ha, nxt_chain, &last_chain);
1305 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1306 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1309 qla25xx_fw_dump_failed_0:
1310 if (rval != QLA_SUCCESS) {
1311 qla_printk(KERN_WARNING, ha,
1312 "Failed to dump firmware (%x)!!!\n", rval);
1316 qla_printk(KERN_INFO, ha,
1317 "Firmware dump saved to temp buffer (%ld/%p).\n",
1318 base_vha->host_no, ha->fw_dump);
1322 qla25xx_fw_dump_failed:
1323 if (!hardware_locked)
1324 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1328 qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1332 uint32_t risc_address;
1333 struct qla_hw_data *ha = vha->hw;
1334 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1335 uint32_t __iomem *dmp_reg;
1337 uint16_t __iomem *mbx_reg;
1338 unsigned long flags;
1339 struct qla81xx_fw_dump *fw;
1340 uint32_t ext_mem_cnt;
1341 void *nxt, *nxt_chain;
1342 uint32_t *last_chain = NULL;
1343 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1345 risc_address = ext_mem_cnt = 0;
1348 if (!hardware_locked)
1349 spin_lock_irqsave(&ha->hardware_lock, flags);
1352 qla_printk(KERN_WARNING, ha,
1353 "No buffer available for dump!!!\n");
1354 goto qla81xx_fw_dump_failed;
1357 if (ha->fw_dumped) {
1358 qla_printk(KERN_WARNING, ha,
1359 "Firmware has been previously dumped (%p) -- ignoring "
1360 "request...\n", ha->fw_dump);
1361 goto qla81xx_fw_dump_failed;
1363 fw = &ha->fw_dump->isp.isp81;
1364 qla2xxx_prep_dump(ha, ha->fw_dump);
1366 fw->host_status = htonl(RD_REG_DWORD(®->host_status));
1369 rval = qla24xx_pause_risc(reg);
1370 if (rval != QLA_SUCCESS)
1371 goto qla81xx_fw_dump_failed_0;
1373 /* Host/Risc registers. */
1374 iter_reg = fw->host_risc_reg;
1375 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1376 qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1378 /* PCIe registers. */
1379 WRT_REG_DWORD(®->iobase_addr, 0x7C00);
1380 RD_REG_DWORD(®->iobase_addr);
1381 WRT_REG_DWORD(®->iobase_window, 0x01);
1382 dmp_reg = ®->iobase_c4;
1383 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1384 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1385 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1386 fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window));
1388 WRT_REG_DWORD(®->iobase_window, 0x00);
1389 RD_REG_DWORD(®->iobase_window);
1391 /* Host interface registers. */
1392 dmp_reg = ®->flash_addr;
1393 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1394 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1396 /* Disable interrupts. */
1397 WRT_REG_DWORD(®->ictrl, 0);
1398 RD_REG_DWORD(®->ictrl);
1400 /* Shadow registers. */
1401 WRT_REG_DWORD(®->iobase_addr, 0x0F70);
1402 RD_REG_DWORD(®->iobase_addr);
1403 WRT_REG_DWORD(®->iobase_select, 0xB0000000);
1404 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata));
1406 WRT_REG_DWORD(®->iobase_select, 0xB0100000);
1407 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata));
1409 WRT_REG_DWORD(®->iobase_select, 0xB0200000);
1410 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata));
1412 WRT_REG_DWORD(®->iobase_select, 0xB0300000);
1413 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata));
1415 WRT_REG_DWORD(®->iobase_select, 0xB0400000);
1416 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata));
1418 WRT_REG_DWORD(®->iobase_select, 0xB0500000);
1419 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata));
1421 WRT_REG_DWORD(®->iobase_select, 0xB0600000);
1422 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata));
1424 WRT_REG_DWORD(®->iobase_select, 0xB0700000);
1425 fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata));
1427 WRT_REG_DWORD(®->iobase_select, 0xB0800000);
1428 fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata));
1430 WRT_REG_DWORD(®->iobase_select, 0xB0900000);
1431 fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata));
1433 WRT_REG_DWORD(®->iobase_select, 0xB0A00000);
1434 fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata));
1436 /* RISC I/O register. */
1437 WRT_REG_DWORD(®->iobase_addr, 0x0010);
1438 fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window));
1440 /* Mailbox registers. */
1441 mbx_reg = ®->mailbox0;
1442 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1443 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1445 /* Transfer sequence registers. */
1446 iter_reg = fw->xseq_gp_reg;
1447 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1448 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1449 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1450 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1451 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1452 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1453 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1454 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1456 iter_reg = fw->xseq_0_reg;
1457 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1458 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1459 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1461 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1463 /* Receive sequence registers. */
1464 iter_reg = fw->rseq_gp_reg;
1465 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1466 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1467 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1468 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1469 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1470 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1471 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1472 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1474 iter_reg = fw->rseq_0_reg;
1475 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1476 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1478 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1479 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1481 /* Auxiliary sequence registers. */
1482 iter_reg = fw->aseq_gp_reg;
1483 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1484 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1485 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1486 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1487 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1488 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1489 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1490 qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1492 iter_reg = fw->aseq_0_reg;
1493 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1494 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1496 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1497 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1499 /* Command DMA registers. */
1500 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1503 iter_reg = fw->req0_dma_reg;
1504 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1505 dmp_reg = ®->iobase_q;
1506 for (cnt = 0; cnt < 7; cnt++)
1507 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1509 iter_reg = fw->resp0_dma_reg;
1510 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1511 dmp_reg = ®->iobase_q;
1512 for (cnt = 0; cnt < 7; cnt++)
1513 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1515 iter_reg = fw->req1_dma_reg;
1516 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1517 dmp_reg = ®->iobase_q;
1518 for (cnt = 0; cnt < 7; cnt++)
1519 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1521 /* Transmit DMA registers. */
1522 iter_reg = fw->xmt0_dma_reg;
1523 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1524 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1526 iter_reg = fw->xmt1_dma_reg;
1527 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1528 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1530 iter_reg = fw->xmt2_dma_reg;
1531 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1532 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1534 iter_reg = fw->xmt3_dma_reg;
1535 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1536 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1538 iter_reg = fw->xmt4_dma_reg;
1539 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1540 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1542 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1544 /* Receive DMA registers. */
1545 iter_reg = fw->rcvt0_data_dma_reg;
1546 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1547 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1549 iter_reg = fw->rcvt1_data_dma_reg;
1550 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1551 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1553 /* RISC registers. */
1554 iter_reg = fw->risc_gp_reg;
1555 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1556 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1557 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1558 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1559 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1560 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1561 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1562 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1564 /* Local memory controller registers. */
1565 iter_reg = fw->lmc_reg;
1566 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1567 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1568 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1569 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1570 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1571 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1572 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1573 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1575 /* Fibre Protocol Module registers. */
1576 iter_reg = fw->fpm_hdw_reg;
1577 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1578 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1579 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1580 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1581 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1582 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1583 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1584 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1585 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1586 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1587 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1588 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1589 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
1590 qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
1592 /* Frame Buffer registers. */
1593 iter_reg = fw->fb_hdw_reg;
1594 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1595 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1596 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1597 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1598 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1599 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1600 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1601 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1602 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1603 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1604 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1605 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
1606 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1608 /* Multi queue registers */
1609 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
1612 rval = qla24xx_soft_reset(ha);
1613 if (rval != QLA_SUCCESS)
1614 goto qla81xx_fw_dump_failed_0;
1616 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1618 if (rval != QLA_SUCCESS)
1619 goto qla81xx_fw_dump_failed_0;
1621 nxt = qla2xxx_copy_queues(ha, nxt);
1623 nxt = qla24xx_copy_eft(ha, nxt);
1625 /* Chain entries -- started with MQ. */
1626 qla25xx_copy_fce(ha, nxt_chain, &last_chain);
1628 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1629 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1632 qla81xx_fw_dump_failed_0:
1633 if (rval != QLA_SUCCESS) {
1634 qla_printk(KERN_WARNING, ha,
1635 "Failed to dump firmware (%x)!!!\n", rval);
1639 qla_printk(KERN_INFO, ha,
1640 "Firmware dump saved to temp buffer (%ld/%p).\n",
1641 base_vha->host_no, ha->fw_dump);
1645 qla81xx_fw_dump_failed:
1646 if (!hardware_locked)
1647 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1650 /****************************************************************************/
1651 /* Driver Debug Functions. */
1652 /****************************************************************************/
1655 qla2x00_dump_regs(scsi_qla_host_t *vha)
1658 struct qla_hw_data *ha = vha->hw;
1659 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1660 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
1661 uint16_t __iomem *mbx_reg;
1663 mbx_reg = IS_FWI2_CAPABLE(ha) ? ®24->mailbox0:
1664 MAILBOX_REG(ha, reg, 0);
1666 printk("Mailbox registers:\n");
1667 for (i = 0; i < 6; i++)
1668 printk("scsi(%ld): mbox %d 0x%04x \n", vha->host_no, i,
1669 RD_REG_WORD(mbx_reg++));
1674 qla2x00_dump_buffer(uint8_t * b, uint32_t size)
1679 printk(" 0 1 2 3 4 5 6 7 8 9 "
1680 "Ah Bh Ch Dh Eh Fh\n");
1681 printk("----------------------------------------"
1682 "----------------------\n");
1684 for (cnt = 0; cnt < size;) {
1686 printk("%02x",(uint32_t) c);