2 * include/asm-s390/spinlock.h
5 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
8 * Derived from "include/asm-i386/spinlock.h"
11 #ifndef __ASM_SPINLOCK_H
12 #define __ASM_SPINLOCK_H
16 * Grmph, take care of %&#! user space programs that include
17 * asm/spinlock.h. The diagnose is only available in kernel
21 #include <asm/lowcore.h>
22 #define __DIAG44_INSN "ex"
23 #define __DIAG44_OPERAND __LC_DIAG44_OPCODE
25 #define __DIAG44_INSN "#"
26 #define __DIAG44_OPERAND 0
28 #endif /* __s390x__ */
31 * Simple spin lock operations. There are two variants, one clears IRQ's
32 * on the local processor, one does not.
34 * We make no fairness assumptions. They have a cost.
38 volatile unsigned int lock;
40 unsigned int break_lock;
42 } __attribute__ ((aligned (4))) spinlock_t;
44 #define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 }
45 #define spin_lock_init(lp) do { (lp)->lock = 0; } while(0)
46 #define spin_unlock_wait(lp) do { barrier(); } while(((volatile spinlock_t *)(lp))->lock)
47 #define spin_is_locked(x) ((x)->lock != 0)
48 #define _raw_spin_lock_flags(lock, flags) _raw_spin_lock(lock)
50 extern inline void _raw_spin_lock(spinlock_t *lp)
53 unsigned int reg1, reg2;
54 __asm__ __volatile__(" bras %0,1f\n"
59 : "=&d" (reg1), "=&d" (reg2), "=m" (lp->lock)
60 : "a" (&lp->lock), "m" (lp->lock)
63 unsigned long reg1, reg2;
64 __asm__ __volatile__(" bras %1,1f\n"
65 "0: " __DIAG44_INSN " 0,%4\n"
69 : "=&d" (reg1), "=&d" (reg2), "=m" (lp->lock)
70 : "a" (&lp->lock), "i" (__DIAG44_OPERAND),
71 "m" (lp->lock) : "cc", "memory" );
72 #endif /* __s390x__ */
75 extern inline int _raw_spin_trylock(spinlock_t *lp)
80 __asm__ __volatile__(" basr %1,0\n"
82 : "=d" (result), "=&d" (reg), "=m" (lp->lock)
83 : "a" (&lp->lock), "m" (lp->lock), "0" (0)
88 extern inline void _raw_spin_unlock(spinlock_t *lp)
92 __asm__ __volatile__("cs %0,%3,0(%4)"
93 : "=d" (old), "=m" (lp->lock)
94 : "0" (lp->lock), "d" (0), "a" (lp)
99 * Read-write spinlocks, allowing multiple readers
100 * but only one writer.
102 * NOTE! it is quite common to have readers in interrupts
103 * but no interrupt writers. For those circumstances we
104 * can "mix" irq-safe locks - any writer needs to get a
105 * irq-safe write-lock, but readers can get non-irqsafe
109 volatile unsigned long lock;
110 volatile unsigned long owner_pc;
111 #ifdef CONFIG_PREEMPT
112 unsigned int break_lock;
116 #define RW_LOCK_UNLOCKED (rwlock_t) { 0, 0 }
118 #define rwlock_init(x) do { *(x) = RW_LOCK_UNLOCKED; } while(0)
121 * read_can_lock - would read_trylock() succeed?
122 * @lock: the rwlock in question.
124 #define read_can_lock(x) ((int)(x)->lock >= 0)
127 * write_can_lock - would write_trylock() succeed?
128 * @lock: the rwlock in question.
130 #define write_can_lock(x) ((x)->lock == 0)
133 #define _raw_read_lock(rw) \
134 asm volatile(" l 2,0(%1)\n" \
137 "1: la 2,0(2)\n" /* clear high (=write) bit */ \
138 " la 3,1(2)\n" /* one more reader */ \
139 " cs 2,3,0(%1)\n" /* try to write new value */ \
141 : "=m" ((rw)->lock) : "a" (&(rw)->lock), \
142 "m" ((rw)->lock) : "2", "3", "cc", "memory" )
143 #else /* __s390x__ */
144 #define _raw_read_lock(rw) \
145 asm volatile(" lg 2,0(%1)\n" \
147 "0: " __DIAG44_INSN " 0,%2\n" \
148 "1: nihh 2,0x7fff\n" /* clear high (=write) bit */ \
149 " la 3,1(2)\n" /* one more reader */ \
150 " csg 2,3,0(%1)\n" /* try to write new value */ \
152 : "=m" ((rw)->lock) \
153 : "a" (&(rw)->lock), "i" (__DIAG44_OPERAND), \
154 "m" ((rw)->lock) : "2", "3", "cc", "memory" )
155 #endif /* __s390x__ */
158 #define _raw_read_unlock(rw) \
159 asm volatile(" l 2,0(%1)\n" \
163 " ahi 3,-1\n" /* one less reader */ \
166 : "=m" ((rw)->lock) : "a" (&(rw)->lock), \
167 "m" ((rw)->lock) : "2", "3", "cc", "memory" )
168 #else /* __s390x__ */
169 #define _raw_read_unlock(rw) \
170 asm volatile(" lg 2,0(%1)\n" \
172 "0: " __DIAG44_INSN " 0,%2\n" \
174 " bctgr 3,0\n" /* one less reader */ \
177 : "=m" ((rw)->lock) \
178 : "a" (&(rw)->lock), "i" (__DIAG44_OPERAND), \
179 "m" ((rw)->lock) : "2", "3", "cc", "memory" )
180 #endif /* __s390x__ */
183 #define _raw_write_lock(rw) \
184 asm volatile(" lhi 3,1\n" \
185 " sll 3,31\n" /* new lock value = 0x80000000 */ \
188 "1: slr 2,2\n" /* old lock value must be 0 */ \
191 : "=m" ((rw)->lock) : "a" (&(rw)->lock), \
192 "m" ((rw)->lock) : "2", "3", "cc", "memory" )
193 #else /* __s390x__ */
194 #define _raw_write_lock(rw) \
195 asm volatile(" llihh 3,0x8000\n" /* new lock value = 0x80...0 */ \
197 "0: " __DIAG44_INSN " 0,%2\n" \
198 "1: slgr 2,2\n" /* old lock value must be 0 */ \
201 : "=m" ((rw)->lock) \
202 : "a" (&(rw)->lock), "i" (__DIAG44_OPERAND), \
203 "m" ((rw)->lock) : "2", "3", "cc", "memory" )
204 #endif /* __s390x__ */
207 #define _raw_write_unlock(rw) \
208 asm volatile(" slr 3,3\n" /* new lock value = 0 */ \
212 " sll 2,31\n" /* old lock value must be 0x80000000 */ \
215 : "=m" ((rw)->lock) : "a" (&(rw)->lock), \
216 "m" ((rw)->lock) : "2", "3", "cc", "memory" )
217 #else /* __s390x__ */
218 #define _raw_write_unlock(rw) \
219 asm volatile(" slgr 3,3\n" /* new lock value = 0 */ \
221 "0: " __DIAG44_INSN " 0,%2\n" \
222 "1: llihh 2,0x8000\n" /* old lock value must be 0x8..0 */\
225 : "=m" ((rw)->lock) \
226 : "a" (&(rw)->lock), "i" (__DIAG44_OPERAND), \
227 "m" ((rw)->lock) : "2", "3", "cc", "memory" )
228 #endif /* __s390x__ */
230 #define _raw_read_trylock(lock) generic_raw_read_trylock(lock)
232 extern inline int _raw_write_trylock(rwlock_t *rw)
234 unsigned long result, reg;
236 __asm__ __volatile__(
241 #else /* __s390x__ */
243 "0: csg %0,%1,0(%3)\n"
244 #endif /* __s390x__ */
245 : "=d" (result), "=&d" (reg), "=m" (rw->lock)
246 : "a" (&rw->lock), "m" (rw->lock), "0" (0UL)
251 #endif /* __ASM_SPINLOCK_H */