2 * linux/arch/ia64/kernel/irq_ia64.c
4 * Copyright (C) 1998-2001 Hewlett-Packard Co
5 * Stephane Eranian <eranian@hpl.hp.com>
6 * David Mosberger-Tang <davidm@hpl.hp.com>
8 * 6/10/99: Updated to bring in sync with x86 version to facilitate
9 * support for SMP and different interrupt controllers.
11 * 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
12 * PCI to vector allocation routine.
13 * 04/14/2004 Ashok Raj <ashok.raj@intel.com>
14 * Added CPU Hotplug handling for IPF.
17 #include <linux/module.h>
19 #include <linux/jiffies.h>
20 #include <linux/errno.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/ioport.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/slab.h>
26 #include <linux/ptrace.h>
27 #include <linux/random.h> /* for rand_initialize_irq() */
28 #include <linux/signal.h>
29 #include <linux/smp.h>
30 #include <linux/threads.h>
31 #include <linux/bitops.h>
32 #include <linux/irq.h>
34 #include <asm/delay.h>
35 #include <asm/intrinsics.h>
37 #include <asm/hw_irq.h>
38 #include <asm/machvec.h>
39 #include <asm/pgtable.h>
40 #include <asm/system.h>
41 #include <asm/tlbflush.h>
44 # include <asm/perfmon.h>
49 #define IRQ_VECTOR_UNASSIGNED (0)
51 #define IRQ_UNUSED (0)
55 /* These can be overridden in platform_irq_init */
56 int ia64_first_device_vector = IA64_DEF_FIRST_DEVICE_VECTOR;
57 int ia64_last_device_vector = IA64_DEF_LAST_DEVICE_VECTOR;
59 /* default base addr of IPI table */
60 void __iomem *ipi_base_addr = ((void __iomem *)
61 (__IA64_UNCACHED_OFFSET | IA64_IPI_DEFAULT_BASE_ADDR));
63 static cpumask_t vector_allocation_domain(int cpu);
66 * Legacy IRQ to IA-64 vector translation table.
68 __u8 isa_irq_to_vector_map[16] = {
69 /* 8259 IRQ translation, first 16 entries */
70 0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
71 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
73 EXPORT_SYMBOL(isa_irq_to_vector_map);
75 DEFINE_SPINLOCK(vector_lock);
77 struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
78 [0 ... NR_IRQS - 1] = {
79 .vector = IRQ_VECTOR_UNASSIGNED,
80 .domain = CPU_MASK_NONE
84 DEFINE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq) = {
85 [0 ... IA64_NUM_VECTORS - 1] = IA64_SPURIOUS_INT_VECTOR
88 static cpumask_t vector_table[IA64_MAX_DEVICE_VECTORS] = {
89 [0 ... IA64_MAX_DEVICE_VECTORS - 1] = CPU_MASK_NONE
92 static int irq_status[NR_IRQS] = {
93 [0 ... NR_IRQS -1] = IRQ_UNUSED
96 int check_irq_used(int irq)
98 if (irq_status[irq] == IRQ_USED)
104 static void reserve_irq(unsigned int irq)
108 spin_lock_irqsave(&vector_lock, flags);
109 irq_status[irq] = IRQ_RSVD;
110 spin_unlock_irqrestore(&vector_lock, flags);
113 static inline int find_unassigned_irq(void)
117 for (irq = IA64_FIRST_DEVICE_VECTOR; irq < NR_IRQS; irq++)
118 if (irq_status[irq] == IRQ_UNUSED)
123 static inline int find_unassigned_vector(cpumask_t domain)
128 cpus_and(mask, domain, cpu_online_map);
129 if (cpus_empty(mask))
132 for (pos = 0; pos < IA64_NUM_DEVICE_VECTORS; pos++) {
133 cpus_and(mask, domain, vector_table[pos]);
134 if (!cpus_empty(mask))
136 return IA64_FIRST_DEVICE_VECTOR + pos;
141 static int __bind_irq_vector(int irq, int vector, cpumask_t domain)
145 struct irq_cfg *cfg = &irq_cfg[irq];
147 cpus_and(mask, domain, cpu_online_map);
148 if (cpus_empty(mask))
150 if ((cfg->vector == vector) && cpus_equal(cfg->domain, domain))
152 if (cfg->vector != IRQ_VECTOR_UNASSIGNED)
154 for_each_cpu_mask(cpu, mask)
155 per_cpu(vector_irq, cpu)[vector] = irq;
156 cfg->vector = vector;
157 cfg->domain = domain;
158 irq_status[irq] = IRQ_USED;
159 pos = vector - IA64_FIRST_DEVICE_VECTOR;
160 cpus_or(vector_table[pos], vector_table[pos], domain);
164 int bind_irq_vector(int irq, int vector, cpumask_t domain)
169 spin_lock_irqsave(&vector_lock, flags);
170 ret = __bind_irq_vector(irq, vector, domain);
171 spin_unlock_irqrestore(&vector_lock, flags);
175 static void __clear_irq_vector(int irq)
177 int vector, cpu, pos;
180 struct irq_cfg *cfg = &irq_cfg[irq];
182 BUG_ON((unsigned)irq >= NR_IRQS);
183 BUG_ON(cfg->vector == IRQ_VECTOR_UNASSIGNED);
184 vector = cfg->vector;
185 domain = cfg->domain;
186 cpus_and(mask, cfg->domain, cpu_online_map);
187 for_each_cpu_mask(cpu, mask)
188 per_cpu(vector_irq, cpu)[vector] = IA64_SPURIOUS_INT_VECTOR;
189 cfg->vector = IRQ_VECTOR_UNASSIGNED;
190 cfg->domain = CPU_MASK_NONE;
191 irq_status[irq] = IRQ_UNUSED;
192 pos = vector - IA64_FIRST_DEVICE_VECTOR;
193 cpus_andnot(vector_table[pos], vector_table[pos], domain);
196 static void clear_irq_vector(int irq)
200 spin_lock_irqsave(&vector_lock, flags);
201 __clear_irq_vector(irq);
202 spin_unlock_irqrestore(&vector_lock, flags);
206 assign_irq_vector (int irq)
214 spin_lock_irqsave(&vector_lock, flags);
218 for_each_online_cpu(cpu) {
219 domain = vector_allocation_domain(cpu);
220 vector = find_unassigned_vector(domain);
226 BUG_ON(__bind_irq_vector(irq, vector, domain));
228 spin_unlock_irqrestore(&vector_lock, flags);
233 free_irq_vector (int vector)
235 if (vector < IA64_FIRST_DEVICE_VECTOR ||
236 vector > IA64_LAST_DEVICE_VECTOR)
238 clear_irq_vector(vector);
242 reserve_irq_vector (int vector)
244 if (vector < IA64_FIRST_DEVICE_VECTOR ||
245 vector > IA64_LAST_DEVICE_VECTOR)
247 return !!bind_irq_vector(vector, vector, CPU_MASK_ALL);
251 * Initialize vector_irq on a new cpu. This function must be called
252 * with vector_lock held.
254 void __setup_vector_irq(int cpu)
258 /* Clear vector_irq */
259 for (vector = 0; vector < IA64_NUM_VECTORS; ++vector)
260 per_cpu(vector_irq, cpu)[vector] = IA64_SPURIOUS_INT_VECTOR;
261 /* Mark the inuse vectors */
262 for (irq = 0; irq < NR_IRQS; ++irq) {
263 if (!cpu_isset(cpu, irq_cfg[irq].domain))
265 vector = irq_to_vector(irq);
266 per_cpu(vector_irq, cpu)[vector] = irq;
270 #if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG))
271 static enum vector_domain_type {
274 } vector_domain_type = VECTOR_DOMAIN_NONE;
276 static cpumask_t vector_allocation_domain(int cpu)
278 if (vector_domain_type == VECTOR_DOMAIN_PERCPU)
279 return cpumask_of_cpu(cpu);
283 static int __init parse_vector_domain(char *arg)
287 if (!strcmp(arg, "percpu")) {
288 vector_domain_type = VECTOR_DOMAIN_PERCPU;
293 early_param("vector", parse_vector_domain);
295 static cpumask_t vector_allocation_domain(int cpu)
302 void destroy_and_reserve_irq(unsigned int irq)
304 dynamic_irq_cleanup(irq);
306 clear_irq_vector(irq);
310 static int __reassign_irq_vector(int irq, int cpu)
312 struct irq_cfg *cfg = &irq_cfg[irq];
316 if (cfg->vector == IRQ_VECTOR_UNASSIGNED || !cpu_online(cpu))
318 if (cpu_isset(cpu, cfg->domain))
320 domain = vector_allocation_domain(cpu);
321 vector = find_unassigned_vector(domain);
324 __clear_irq_vector(irq);
325 BUG_ON(__bind_irq_vector(irq, vector, domain));
329 int reassign_irq_vector(int irq, int cpu)
334 spin_lock_irqsave(&vector_lock, flags);
335 ret = __reassign_irq_vector(irq, cpu);
336 spin_unlock_irqrestore(&vector_lock, flags);
341 * Dynamic irq allocate and deallocation for MSI
346 int irq, vector, cpu;
349 irq = vector = -ENOSPC;
350 spin_lock_irqsave(&vector_lock, flags);
351 for_each_online_cpu(cpu) {
352 domain = vector_allocation_domain(cpu);
353 vector = find_unassigned_vector(domain);
359 irq = find_unassigned_irq();
362 BUG_ON(__bind_irq_vector(irq, vector, domain));
364 spin_unlock_irqrestore(&vector_lock, flags);
366 dynamic_irq_init(irq);
370 void destroy_irq(unsigned int irq)
372 dynamic_irq_cleanup(irq);
373 clear_irq_vector(irq);
377 # define IS_RESCHEDULE(vec) (vec == IA64_IPI_RESCHEDULE)
378 # define IS_LOCAL_TLB_FLUSH(vec) (vec == IA64_IPI_LOCAL_TLB_FLUSH)
380 # define IS_RESCHEDULE(vec) (0)
381 # define IS_LOCAL_TLB_FLUSH(vec) (0)
384 * That's where the IVT branches when we get an external
385 * interrupt. This branches to the correct hardware IRQ handler via
389 ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
391 struct pt_regs *old_regs = set_irq_regs(regs);
392 unsigned long saved_tpr;
396 unsigned long bsp, sp;
399 * Note: if the interrupt happened while executing in
400 * the context switch routine (ia64_switch_to), we may
401 * get a spurious stack overflow here. This is
402 * because the register and the memory stack are not
403 * switched atomically.
405 bsp = ia64_getreg(_IA64_REG_AR_BSP);
406 sp = ia64_getreg(_IA64_REG_SP);
408 if ((sp - bsp) < 1024) {
409 static unsigned char count;
410 static long last_time;
412 if (jiffies - last_time > 5*HZ)
416 printk("ia64_handle_irq: DANGER: less than "
417 "1KB of free stack space!!\n"
418 "(bsp=0x%lx, sp=%lx)\n", bsp, sp);
422 #endif /* IRQ_DEBUG */
425 * Always set TPR to limit maximum interrupt nesting depth to
426 * 16 (without this, it would be ~240, which could easily lead
427 * to kernel stack overflows).
430 saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
432 while (vector != IA64_SPURIOUS_INT_VECTOR) {
433 if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
434 smp_local_flush_tlb();
435 kstat_this_cpu.irqs[vector]++;
436 } else if (unlikely(IS_RESCHEDULE(vector)))
437 kstat_this_cpu.irqs[vector]++;
439 ia64_setreg(_IA64_REG_CR_TPR, vector);
442 generic_handle_irq(local_vector_to_irq(vector));
445 * Disable interrupts and send EOI:
448 ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
451 vector = ia64_get_ivr();
454 * This must be done *after* the ia64_eoi(). For example, the keyboard softirq
455 * handler needs to be able to wait for further keyboard interrupts, which can't
456 * come through until ia64_eoi() has been done.
459 set_irq_regs(old_regs);
462 #ifdef CONFIG_HOTPLUG_CPU
464 * This function emulates a interrupt processing when a cpu is about to be
467 void ia64_process_pending_intr(void)
470 unsigned long saved_tpr;
471 extern unsigned int vectors_in_migration[NR_IRQS];
473 vector = ia64_get_ivr();
476 saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
480 * Perform normal interrupt style processing
482 while (vector != IA64_SPURIOUS_INT_VECTOR) {
483 if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
484 smp_local_flush_tlb();
485 kstat_this_cpu.irqs[vector]++;
486 } else if (unlikely(IS_RESCHEDULE(vector)))
487 kstat_this_cpu.irqs[vector]++;
489 struct pt_regs *old_regs = set_irq_regs(NULL);
491 ia64_setreg(_IA64_REG_CR_TPR, vector);
495 * Now try calling normal ia64_handle_irq as it would have got called
496 * from a real intr handler. Try passing null for pt_regs, hopefully
497 * it will work. I hope it works!.
498 * Probably could shared code.
500 vectors_in_migration[local_vector_to_irq(vector)]=0;
501 generic_handle_irq(local_vector_to_irq(vector));
502 set_irq_regs(old_regs);
505 * Disable interrupts and send EOI
508 ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
511 vector = ia64_get_ivr();
520 static irqreturn_t dummy_handler (int irq, void *dev_id)
524 extern irqreturn_t handle_IPI (int irq, void *dev_id);
526 static struct irqaction ipi_irqaction = {
527 .handler = handle_IPI,
528 .flags = IRQF_DISABLED,
532 static struct irqaction resched_irqaction = {
533 .handler = dummy_handler,
534 .flags = IRQF_DISABLED,
538 static struct irqaction tlb_irqaction = {
539 .handler = dummy_handler,
540 .flags = IRQF_DISABLED,
547 register_percpu_irq (ia64_vector vec, struct irqaction *action)
553 BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL));
554 desc = irq_desc + irq;
555 desc->status |= IRQ_PER_CPU;
556 desc->chip = &irq_type_ia64_lsapic;
558 setup_irq(irq, action);
564 register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
566 register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
567 register_percpu_irq(IA64_IPI_RESCHEDULE, &resched_irqaction);
568 register_percpu_irq(IA64_IPI_LOCAL_TLB_FLUSH, &tlb_irqaction);
570 #ifdef CONFIG_PERFMON
577 ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
579 void __iomem *ipi_addr;
580 unsigned long ipi_data;
581 unsigned long phys_cpu_id;
584 phys_cpu_id = cpu_physical_id(cpu);
586 phys_cpu_id = (ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff;
590 * cpu number is in 8bit ID and 8bit EID
593 ipi_data = (delivery_mode << 8) | (vector & 0xff);
594 ipi_addr = ipi_base_addr + ((phys_cpu_id << 4) | ((redirect & 1) << 3));
596 writeq(ipi_data, ipi_addr);