git.oblomov.eu Git - linux-2.6/blob - drivers/usb/gadget/omap_udc.c

   1 /*
   2  * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
   3  *
   4  * Copyright (C) 2004 Texas Instruments, Inc.
   5  * Copyright (C) 2004-2005 David Brownell
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 #undef  DEBUG
  23 #undef  VERBOSE
  24
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/ioport.h>
  28 #include <linux/types.h>
  29 #include <linux/errno.h>
  30 #include <linux/delay.h>
  31 #include <linux/slab.h>
  32 #include <linux/init.h>
  33 #include <linux/timer.h>
  34 #include <linux/list.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/proc_fs.h>
  37 #include <linux/mm.h>
  38 #include <linux/moduleparam.h>
  39 #include <linux/platform_device.h>
  40 #include <linux/usb/ch9.h>
  41 #include <linux/usb_gadget.h>
  42 #include <linux/usb/otg.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/clk.h>
  45
  46 #include <asm/byteorder.h>
  47 #include <asm/io.h>
  48 #include <asm/irq.h>
  49 #include <asm/system.h>
  50 #include <asm/unaligned.h>
  51 #include <asm/mach-types.h>
  52
  53 #include <asm/arch/dma.h>
  54 #include <asm/arch/usb.h>
  55
  56 #include "omap_udc.h"
  57
  58 #undef  USB_TRACE
  59
  60 /* bulk DMA seems to be behaving for both IN and OUT */
  61 #define USE_DMA
  62
  63 /* FIXME: OMAP2 currently has some problem in DMA mode */
  64 #ifdef CONFIG_ARCH_OMAP2
  65 #undef USE_DMA
  66 #endif
  67
  68 /* ISO too */
  69 #define USE_ISO
  70
  71 #define DRIVER_DESC     "OMAP UDC driver"
  72 #define DRIVER_VERSION  "4 October 2004"
  73
  74 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
  75
  76
  77 /*
  78  * The OMAP UDC needs _very_ early endpoint setup:  before enabling the
  79  * D+ pullup to allow enumeration.  That's too early for the gadget
  80  * framework to use from usb_endpoint_enable(), which happens after
  81  * enumeration as part of activating an interface.  (But if we add an
  82  * optional new "UDC not yet running" state to the gadget driver model,
  83  * even just during driver binding, the endpoint autoconfig logic is the
  84  * natural spot to manufacture new endpoints.)
  85  *
  86  * So instead of using endpoint enable calls to control the hardware setup,
  87  * this driver defines a "fifo mode" parameter.  It's used during driver
  88  * initialization to choose among a set of pre-defined endpoint configs.
  89  * See omap_udc_setup() for available modes, or to add others.  That code
  90  * lives in an init section, so use this driver as a module if you need
  91  * to change the fifo mode after the kernel boots.
  92  *
  93  * Gadget drivers normally ignore endpoints they don't care about, and
  94  * won't include them in configuration descriptors.  That means only
  95  * misbehaving hosts would even notice they exist.
  96  */
  97 #ifdef  USE_ISO
  98 static unsigned fifo_mode = 3;
  99 #else
 100 static unsigned fifo_mode = 0;
 101 #endif
 102
 103 /* "modprobe omap_udc fifo_mode=42", or else as a kernel
 104  * boot parameter "omap_udc:fifo_mode=42"
 105  */
 106 module_param (fifo_mode, uint, 0);
 107 MODULE_PARM_DESC (fifo_mode, "endpoint configuration");
 108
 109 #ifdef  USE_DMA
 110 static unsigned use_dma = 1;
 111
 112 /* "modprobe omap_udc use_dma=y", or else as a kernel
 113  * boot parameter "omap_udc:use_dma=y"
 114  */
 115 module_param (use_dma, bool, 0);
 116 MODULE_PARM_DESC (use_dma, "enable/disable DMA");
 117 #else   /* !USE_DMA */
 118
 119 /* save a bit of code */
 120 #define use_dma         0
 121 #endif  /* !USE_DMA */
 122
 123
 124 static const char driver_name [] = "omap_udc";
 125 static const char driver_desc [] = DRIVER_DESC;
 126
 127 /*-------------------------------------------------------------------------*/
 128
 129 /* there's a notion of "current endpoint" for modifying endpoint
 130  * state, and PIO access to its FIFO.
 131  */
 132
 133 static void use_ep(struct omap_ep *ep, u16 select)
 134 {
 135         u16     num = ep->bEndpointAddress & 0x0f;
 136
 137         if (ep->bEndpointAddress & USB_DIR_IN)
 138                 num |= UDC_EP_DIR;
 139         UDC_EP_NUM_REG = num | select;
 140         /* when select, MUST deselect later !! */
 141 }
 142
 143 static inline void deselect_ep(void)
 144 {
 145         UDC_EP_NUM_REG &= ~UDC_EP_SEL;
 146         /* 6 wait states before TX will happen */
 147 }
 148
 149 static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
 150
 151 /*-------------------------------------------------------------------------*/
 152
 153 static int omap_ep_enable(struct usb_ep *_ep,
 154                 const struct usb_endpoint_descriptor *desc)
 155 {
 156         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 157         struct omap_udc *udc;
 158         unsigned long   flags;
 159         u16             maxp;
 160
 161         /* catch various bogus parameters */
 162         if (!_ep || !desc || ep->desc
 163                         || desc->bDescriptorType != USB_DT_ENDPOINT
 164                         || ep->bEndpointAddress != desc->bEndpointAddress
 165                         || ep->maxpacket < le16_to_cpu
 166                                                 (desc->wMaxPacketSize)) {
 167                 DBG("%s, bad ep or descriptor\n", __FUNCTION__);
 168                 return -EINVAL;
 169         }
 170         maxp = le16_to_cpu (desc->wMaxPacketSize);
 171         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 172                                 && maxp != ep->maxpacket)
 173                         || le16_to_cpu(desc->wMaxPacketSize) > ep->maxpacket
 174                         || !desc->wMaxPacketSize) {
 175                 DBG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name);
 176                 return -ERANGE;
 177         }
 178
 179 #ifdef  USE_ISO
 180         if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
 181                                 && desc->bInterval != 1)) {
 182                 /* hardware wants period = 1; USB allows 2^(Interval-1) */
 183                 DBG("%s, unsupported ISO period %dms\n", _ep->name,
 184                                 1 << (desc->bInterval - 1));
 185                 return -EDOM;
 186         }
 187 #else
 188         if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 189                 DBG("%s, ISO nyet\n", _ep->name);
 190                 return -EDOM;
 191         }
 192 #endif
 193
 194         /* xfer types must match, except that interrupt ~= bulk */
 195         if (ep->bmAttributes != desc->bmAttributes
 196                         && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
 197                         && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
 198                 DBG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
 199                 return -EINVAL;
 200         }
 201
 202         udc = ep->udc;
 203         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
 204                 DBG("%s, bogus device state\n", __FUNCTION__);
 205                 return -ESHUTDOWN;
 206         }
 207
 208         spin_lock_irqsave(&udc->lock, flags);
 209
 210         ep->desc = desc;
 211         ep->irqs = 0;
 212         ep->stopped = 0;
 213         ep->ep.maxpacket = maxp;
 214
 215         /* set endpoint to initial state */
 216         ep->dma_channel = 0;
 217         ep->has_dma = 0;
 218         ep->lch = -1;
 219         use_ep(ep, UDC_EP_SEL);
 220         UDC_CTRL_REG = udc->clr_halt;
 221         ep->ackwait = 0;
 222         deselect_ep();
 223
 224         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
 225                 list_add(&ep->iso, &udc->iso);
 226
 227         /* maybe assign a DMA channel to this endpoint */
 228         if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
 229                 /* FIXME ISO can dma, but prefers first channel */
 230                 dma_channel_claim(ep, 0);
 231
 232         /* PIO OUT may RX packets */
 233         if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
 234                         && !ep->has_dma
 235                         && !(ep->bEndpointAddress & USB_DIR_IN)) {
 236                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
 237                 ep->ackwait = 1 + ep->double_buf;
 238         }
 239
 240         spin_unlock_irqrestore(&udc->lock, flags);
 241         VDBG("%s enabled\n", _ep->name);
 242         return 0;
 243 }
 244
 245 static void nuke(struct omap_ep *, int status);
 246
 247 static int omap_ep_disable(struct usb_ep *_ep)
 248 {
 249         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 250         unsigned long   flags;
 251
 252         if (!_ep || !ep->desc) {
 253                 DBG("%s, %s not enabled\n", __FUNCTION__,
 254                         _ep ? ep->ep.name : NULL);
 255                 return -EINVAL;
 256         }
 257
 258         spin_lock_irqsave(&ep->udc->lock, flags);
 259         ep->desc = NULL;
 260         nuke (ep, -ESHUTDOWN);
 261         ep->ep.maxpacket = ep->maxpacket;
 262         ep->has_dma = 0;
 263         UDC_CTRL_REG = UDC_SET_HALT;
 264         list_del_init(&ep->iso);
 265         del_timer(&ep->timer);
 266
 267         spin_unlock_irqrestore(&ep->udc->lock, flags);
 268
 269         VDBG("%s disabled\n", _ep->name);
 270         return 0;
 271 }
 272
 273 /*-------------------------------------------------------------------------*/
 274
 275 static struct usb_request *
 276 omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
 277 {
 278         struct omap_req *req;
 279
 280         req = kzalloc(sizeof(*req), gfp_flags);
 281         if (req) {
 282                 req->req.dma = DMA_ADDR_INVALID;
 283                 INIT_LIST_HEAD (&req->queue);
 284         }
 285         return &req->req;
 286 }
 287
 288 static void
 289 omap_free_request(struct usb_ep *ep, struct usb_request *_req)
 290 {
 291         struct omap_req *req = container_of(_req, struct omap_req, req);
 292
 293         if (_req)
 294                 kfree (req);
 295 }
 296
 297 /*-------------------------------------------------------------------------*/
 298
 299 static void
 300 done(struct omap_ep *ep, struct omap_req *req, int status)
 301 {
 302         unsigned                stopped = ep->stopped;
 303
 304         list_del_init(&req->queue);
 305
 306         if (req->req.status == -EINPROGRESS)
 307                 req->req.status = status;
 308         else
 309                 status = req->req.status;
 310
 311         if (use_dma && ep->has_dma) {
 312                 if (req->mapped) {
 313                         dma_unmap_single(ep->udc->gadget.dev.parent,
 314                                 req->req.dma, req->req.length,
 315                                 (ep->bEndpointAddress & USB_DIR_IN)
 316                                         ? DMA_TO_DEVICE
 317                                         : DMA_FROM_DEVICE);
 318                         req->req.dma = DMA_ADDR_INVALID;
 319                         req->mapped = 0;
 320                 } else
 321                         dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
 322                                 req->req.dma, req->req.length,
 323                                 (ep->bEndpointAddress & USB_DIR_IN)
 324                                         ? DMA_TO_DEVICE
 325                                         : DMA_FROM_DEVICE);
 326         }
 327
 328 #ifndef USB_TRACE
 329         if (status && status != -ESHUTDOWN)
 330 #endif
 331                 VDBG("complete %s req %p stat %d len %u/%u\n",
 332                         ep->ep.name, &req->req, status,
 333                         req->req.actual, req->req.length);
 334
 335         /* don't modify queue heads during completion callback */
 336         ep->stopped = 1;
 337         spin_unlock(&ep->udc->lock);
 338         req->req.complete(&ep->ep, &req->req);
 339         spin_lock(&ep->udc->lock);
 340         ep->stopped = stopped;
 341 }
 342
 343 /*-------------------------------------------------------------------------*/
 344
 345 #define UDC_FIFO_FULL           (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
 346 #define UDC_FIFO_UNWRITABLE     (UDC_EP_HALTED | UDC_FIFO_FULL)
 347
 348 #define FIFO_EMPTY      (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
 349 #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
 350
 351 static inline int
 352 write_packet(u8 *buf, struct omap_req *req, unsigned max)
 353 {
 354         unsigned        len;
 355         u16             *wp;
 356
 357         len = min(req->req.length - req->req.actual, max);
 358         req->req.actual += len;
 359
 360         max = len;
 361         if (likely((((int)buf) & 1) == 0)) {
 362                 wp = (u16 *)buf;
 363                 while (max >= 2) {
 364                         UDC_DATA_REG = *wp++;
 365                         max -= 2;
 366                 }
 367                 buf = (u8 *)wp;
 368         }
 369         while (max--)
 370                 *(volatile u8 *)&UDC_DATA_REG = *buf++;
 371         return len;
 372 }
 373
 374 // FIXME change r/w fifo calling convention
 375
 376
 377 // return:  0 = still running, 1 = completed, negative = errno
 378 static int write_fifo(struct omap_ep *ep, struct omap_req *req)
 379 {
 380         u8              *buf;
 381         unsigned        count;
 382         int             is_last;
 383         u16             ep_stat;
 384
 385         buf = req->req.buf + req->req.actual;
 386         prefetch(buf);
 387
 388         /* PIO-IN isn't double buffered except for iso */
 389         ep_stat = UDC_STAT_FLG_REG;
 390         if (ep_stat & UDC_FIFO_UNWRITABLE)
 391                 return 0;
 392
 393         count = ep->ep.maxpacket;
 394         count = write_packet(buf, req, count);
 395         UDC_CTRL_REG = UDC_SET_FIFO_EN;
 396         ep->ackwait = 1;
 397
 398         /* last packet is often short (sometimes a zlp) */
 399         if (count != ep->ep.maxpacket)
 400                 is_last = 1;
 401         else if (req->req.length == req->req.actual
 402                         && !req->req.zero)
 403                 is_last = 1;
 404         else
 405                 is_last = 0;
 406
 407         /* NOTE:  requests complete when all IN data is in a
 408          * FIFO (or sometimes later, if a zlp was needed).
 409          * Use usb_ep_fifo_status() where needed.
 410          */
 411         if (is_last)
 412                 done(ep, req, 0);
 413         return is_last;
 414 }
 415
 416 static inline int
 417 read_packet(u8 *buf, struct omap_req *req, unsigned avail)
 418 {
 419         unsigned        len;
 420         u16             *wp;
 421
 422         len = min(req->req.length - req->req.actual, avail);
 423         req->req.actual += len;
 424         avail = len;
 425
 426         if (likely((((int)buf) & 1) == 0)) {
 427                 wp = (u16 *)buf;
 428                 while (avail >= 2) {
 429                         *wp++ = UDC_DATA_REG;
 430                         avail -= 2;
 431                 }
 432                 buf = (u8 *)wp;
 433         }
 434         while (avail--)
 435                 *buf++ = *(volatile u8 *)&UDC_DATA_REG;
 436         return len;
 437 }
 438
 439 // return:  0 = still running, 1 = queue empty, negative = errno
 440 static int read_fifo(struct omap_ep *ep, struct omap_req *req)
 441 {
 442         u8              *buf;
 443         unsigned        count, avail;
 444         int             is_last;
 445
 446         buf = req->req.buf + req->req.actual;
 447         prefetchw(buf);
 448
 449         for (;;) {
 450                 u16     ep_stat = UDC_STAT_FLG_REG;
 451
 452                 is_last = 0;
 453                 if (ep_stat & FIFO_EMPTY) {
 454                         if (!ep->double_buf)
 455                                 break;
 456                         ep->fnf = 1;
 457                 }
 458                 if (ep_stat & UDC_EP_HALTED)
 459                         break;
 460
 461                 if (ep_stat & UDC_FIFO_FULL)
 462                         avail = ep->ep.maxpacket;
 463                 else  {
 464                         avail = UDC_RXFSTAT_REG;
 465                         ep->fnf = ep->double_buf;
 466                 }
 467                 count = read_packet(buf, req, avail);
 468
 469                 /* partial packet reads may not be errors */
 470                 if (count < ep->ep.maxpacket) {
 471                         is_last = 1;
 472                         /* overflowed this request?  flush extra data */
 473                         if (count != avail) {
 474                                 req->req.status = -EOVERFLOW;
 475                                 avail -= count;
 476                                 while (avail--)
 477                                         (void) *(volatile u8 *)&UDC_DATA_REG;
 478                         }
 479                 } else if (req->req.length == req->req.actual)
 480                         is_last = 1;
 481                 else
 482                         is_last = 0;
 483
 484                 if (!ep->bEndpointAddress)
 485                         break;
 486                 if (is_last)
 487                         done(ep, req, 0);
 488                 break;
 489         }
 490         return is_last;
 491 }
 492
 493 /*-------------------------------------------------------------------------*/
 494
 495 static inline dma_addr_t dma_csac(unsigned lch)
 496 {
 497         dma_addr_t      csac;
 498
 499         /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
 500          * read before the DMA controller finished disabling the channel.
 501          */
 502         csac = OMAP_DMA_CSAC_REG(lch);
 503         if (csac == 0)
 504                 csac = OMAP_DMA_CSAC_REG(lch);
 505         return csac;
 506 }
 507
 508 static inline dma_addr_t dma_cdac(unsigned lch)
 509 {
 510         dma_addr_t      cdac;
 511
 512         /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
 513          * read before the DMA controller finished disabling the channel.
 514          */
 515         cdac = OMAP_DMA_CDAC_REG(lch);
 516         if (cdac == 0)
 517                 cdac = OMAP_DMA_CDAC_REG(lch);
 518         return cdac;
 519 }
 520
 521 static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
 522 {
 523         dma_addr_t      end;
 524
 525         /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
 526          * the last transfer's bytecount by more than a FIFO's worth.
 527          */
 528         if (cpu_is_omap15xx())
 529                 return 0;
 530
 531         end = dma_csac(ep->lch);
 532         if (end == ep->dma_counter)
 533                 return 0;
 534
 535         end |= start & (0xffff << 16);
 536         if (end < start)
 537                 end += 0x10000;
 538         return end - start;
 539 }
 540
 541 #define DMA_DEST_LAST(x) (cpu_is_omap15xx() \
 542                 ? OMAP_DMA_CSAC_REG(x) /* really: CPC */ \
 543                 : dma_cdac(x))
 544
 545 static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
 546 {
 547         dma_addr_t      end;
 548
 549         end = DMA_DEST_LAST(ep->lch);
 550         if (end == ep->dma_counter)
 551                 return 0;
 552
 553         end |= start & (0xffff << 16);
 554         if (cpu_is_omap15xx())
 555                 end++;
 556         if (end < start)
 557                 end += 0x10000;
 558         return end - start;
 559 }
 560
 561
 562 /* Each USB transfer request using DMA maps to one or more DMA transfers.
 563  * When DMA completion isn't request completion, the UDC continues with
 564  * the next DMA transfer for that USB transfer.
 565  */
 566
 567 static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
 568 {
 569         u16             txdma_ctrl;
 570         unsigned        length = req->req.length - req->req.actual;
 571         const int       sync_mode = cpu_is_omap15xx()
 572                                 ? OMAP_DMA_SYNC_FRAME
 573                                 : OMAP_DMA_SYNC_ELEMENT;
 574
 575         /* measure length in either bytes or packets */
 576         if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
 577                         || (cpu_is_omap15xx() && length < ep->maxpacket)) {
 578                 txdma_ctrl = UDC_TXN_EOT | length;
 579                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
 580                                 length, 1, sync_mode, 0, 0);
 581         } else {
 582                 length = min(length / ep->maxpacket,
 583                                 (unsigned) UDC_TXN_TSC + 1);
 584                 txdma_ctrl = length;
 585                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 586                                 ep->ep.maxpacket >> 1, length, sync_mode,
 587                                 0, 0);
 588                 length *= ep->maxpacket;
 589         }
 590         omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 591                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 592                 0, 0);
 593
 594         omap_start_dma(ep->lch);
 595         ep->dma_counter = dma_csac(ep->lch);
 596         UDC_DMA_IRQ_EN_REG |= UDC_TX_DONE_IE(ep->dma_channel);
 597         UDC_TXDMA_REG(ep->dma_channel) = UDC_TXN_START | txdma_ctrl;
 598         req->dma_bytes = length;
 599 }
 600
 601 static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
 602 {
 603         if (status == 0) {
 604                 req->req.actual += req->dma_bytes;
 605
 606                 /* return if this request needs to send data or zlp */
 607                 if (req->req.actual < req->req.length)
 608                         return;
 609                 if (req->req.zero
 610                                 && req->dma_bytes != 0
 611                                 && (req->req.actual % ep->maxpacket) == 0)
 612                         return;
 613         } else
 614                 req->req.actual += dma_src_len(ep, req->req.dma
 615                                                         + req->req.actual);
 616
 617         /* tx completion */
 618         omap_stop_dma(ep->lch);
 619         UDC_DMA_IRQ_EN_REG &= ~UDC_TX_DONE_IE(ep->dma_channel);
 620         done(ep, req, status);
 621 }
 622
 623 static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
 624 {
 625         unsigned packets;
 626
 627         /* NOTE:  we filtered out "short reads" before, so we know
 628          * the buffer has only whole numbers of packets.
 629          */
 630
 631         /* set up this DMA transfer, enable the fifo, start */
 632         packets = (req->req.length - req->req.actual) / ep->ep.maxpacket;
 633         packets = min(packets, (unsigned)UDC_RXN_TC + 1);
 634         req->dma_bytes = packets * ep->ep.maxpacket;
 635         omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 636                         ep->ep.maxpacket >> 1, packets,
 637                         OMAP_DMA_SYNC_ELEMENT,
 638                         0, 0);
 639         omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 640                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 641                 0, 0);
 642         ep->dma_counter = DMA_DEST_LAST(ep->lch);
 643
 644         UDC_RXDMA_REG(ep->dma_channel) = UDC_RXN_STOP | (packets - 1);
 645         UDC_DMA_IRQ_EN_REG |= UDC_RX_EOT_IE(ep->dma_channel);
 646         UDC_EP_NUM_REG = (ep->bEndpointAddress & 0xf);
 647         UDC_CTRL_REG = UDC_SET_FIFO_EN;
 648
 649         omap_start_dma(ep->lch);
 650 }
 651
 652 static void
 653 finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
 654 {
 655         u16     count;
 656
 657         if (status == 0)
 658                 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
 659         count = dma_dest_len(ep, req->req.dma + req->req.actual);
 660         count += req->req.actual;
 661         if (one)
 662                 count--;
 663         if (count <= req->req.length)
 664                 req->req.actual = count;
 665
 666         if (count != req->dma_bytes || status)
 667                 omap_stop_dma(ep->lch);
 668
 669         /* if this wasn't short, request may need another transfer */
 670         else if (req->req.actual < req->req.length)
 671                 return;
 672
 673         /* rx completion */
 674         UDC_DMA_IRQ_EN_REG &= ~UDC_RX_EOT_IE(ep->dma_channel);
 675         done(ep, req, status);
 676 }
 677
 678 static void dma_irq(struct omap_udc *udc, u16 irq_src)
 679 {
 680         u16             dman_stat = UDC_DMAN_STAT_REG;
 681         struct omap_ep  *ep;
 682         struct omap_req *req;
 683
 684         /* IN dma: tx to host */
 685         if (irq_src & UDC_TXN_DONE) {
 686                 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
 687                 ep->irqs++;
 688                 /* can see TXN_DONE after dma abort */
 689                 if (!list_empty(&ep->queue)) {
 690                         req = container_of(ep->queue.next,
 691                                                 struct omap_req, queue);
 692                         finish_in_dma(ep, req, 0);
 693                 }
 694                 UDC_IRQ_SRC_REG = UDC_TXN_DONE;
 695
 696                 if (!list_empty (&ep->queue)) {
 697                         req = container_of(ep->queue.next,
 698                                         struct omap_req, queue);
 699                         next_in_dma(ep, req);
 700                 }
 701         }
 702
 703         /* OUT dma: rx from host */
 704         if (irq_src & UDC_RXN_EOT) {
 705                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 706                 ep->irqs++;
 707                 /* can see RXN_EOT after dma abort */
 708                 if (!list_empty(&ep->queue)) {
 709                         req = container_of(ep->queue.next,
 710                                         struct omap_req, queue);
 711                         finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
 712                 }
 713                 UDC_IRQ_SRC_REG = UDC_RXN_EOT;
 714
 715                 if (!list_empty (&ep->queue)) {
 716                         req = container_of(ep->queue.next,
 717                                         struct omap_req, queue);
 718                         next_out_dma(ep, req);
 719                 }
 720         }
 721
 722         if (irq_src & UDC_RXN_CNT) {
 723                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 724                 ep->irqs++;
 725                 /* omap15xx does this unasked... */
 726                 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
 727                 UDC_IRQ_SRC_REG = UDC_RXN_CNT;
 728         }
 729 }
 730
 731 static void dma_error(int lch, u16 ch_status, void *data)
 732 {
 733         struct omap_ep  *ep = data;
 734
 735         /* if ch_status & OMAP_DMA_DROP_IRQ ... */
 736         /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
 737         ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
 738
 739         /* complete current transfer ... */
 740 }
 741
 742 static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
 743 {
 744         u16     reg;
 745         int     status, restart, is_in;
 746
 747         is_in = ep->bEndpointAddress & USB_DIR_IN;
 748         if (is_in)
 749                 reg = UDC_TXDMA_CFG_REG;
 750         else
 751                 reg = UDC_RXDMA_CFG_REG;
 752         reg |= UDC_DMA_REQ;             /* "pulse" activated */
 753
 754         ep->dma_channel = 0;
 755         ep->lch = -1;
 756         if (channel == 0 || channel > 3) {
 757                 if ((reg & 0x0f00) == 0)
 758                         channel = 3;
 759                 else if ((reg & 0x00f0) == 0)
 760                         channel = 2;
 761                 else if ((reg & 0x000f) == 0)   /* preferred for ISO */
 762                         channel = 1;
 763                 else {
 764                         status = -EMLINK;
 765                         goto just_restart;
 766                 }
 767         }
 768         reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
 769         ep->dma_channel = channel;
 770
 771         if (is_in) {
 772                 status = omap_request_dma(OMAP_DMA_USB_W2FC_TX0 - 1 + channel,
 773                         ep->ep.name, dma_error, ep, &ep->lch);
 774                 if (status == 0) {
 775                         UDC_TXDMA_CFG_REG = reg;
 776                         /* EMIFF */
 777                         omap_set_dma_src_burst_mode(ep->lch,
 778                                                 OMAP_DMA_DATA_BURST_4);
 779                         omap_set_dma_src_data_pack(ep->lch, 1);
 780                         /* TIPB */
 781                         omap_set_dma_dest_params(ep->lch,
 782                                 OMAP_DMA_PORT_TIPB,
 783                                 OMAP_DMA_AMODE_CONSTANT,
 784                                 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
 785                                 0, 0);
 786                 }
 787         } else {
 788                 status = omap_request_dma(OMAP_DMA_USB_W2FC_RX0 - 1 + channel,
 789                         ep->ep.name, dma_error, ep, &ep->lch);
 790                 if (status == 0) {
 791                         UDC_RXDMA_CFG_REG = reg;
 792                         /* TIPB */
 793                         omap_set_dma_src_params(ep->lch,
 794                                 OMAP_DMA_PORT_TIPB,
 795                                 OMAP_DMA_AMODE_CONSTANT,
 796                                 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
 797                                 0, 0);
 798                         /* EMIFF */
 799                         omap_set_dma_dest_burst_mode(ep->lch,
 800                                                 OMAP_DMA_DATA_BURST_4);
 801                         omap_set_dma_dest_data_pack(ep->lch, 1);
 802                 }
 803         }
 804         if (status)
 805                 ep->dma_channel = 0;
 806         else {
 807                 ep->has_dma = 1;
 808                 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
 809
 810                 /* channel type P: hw synch (fifo) */
 811                 if (!cpu_is_omap15xx())
 812                         OMAP1_DMA_LCH_CTRL_REG(ep->lch) = 2;
 813         }
 814
 815 just_restart:
 816         /* restart any queue, even if the claim failed  */
 817         restart = !ep->stopped && !list_empty(&ep->queue);
 818
 819         if (status)
 820                 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
 821                         restart ? " (restart)" : "");
 822         else
 823                 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
 824                         is_in ? 't' : 'r',
 825                         ep->dma_channel - 1, ep->lch,
 826                         restart ? " (restart)" : "");
 827
 828         if (restart) {
 829                 struct omap_req *req;
 830                 req = container_of(ep->queue.next, struct omap_req, queue);
 831                 if (ep->has_dma)
 832                         (is_in ? next_in_dma : next_out_dma)(ep, req);
 833                 else {
 834                         use_ep(ep, UDC_EP_SEL);
 835                         (is_in ? write_fifo : read_fifo)(ep, req);
 836                         deselect_ep();
 837                         if (!is_in) {
 838                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
 839                                 ep->ackwait = 1 + ep->double_buf;
 840                         }
 841                         /* IN: 6 wait states before it'll tx */
 842                 }
 843         }
 844 }
 845
 846 static void dma_channel_release(struct omap_ep *ep)
 847 {
 848         int             shift = 4 * (ep->dma_channel - 1);
 849         u16             mask = 0x0f << shift;
 850         struct omap_req *req;
 851         int             active;
 852
 853         /* abort any active usb transfer request */
 854         if (!list_empty(&ep->queue))
 855                 req = container_of(ep->queue.next, struct omap_req, queue);
 856         else
 857                 req = NULL;
 858
 859         active = ((1 << 7) & OMAP_DMA_CCR_REG(ep->lch)) != 0;
 860
 861         DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
 862                         active ? "active" : "idle",
 863                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
 864                         ep->dma_channel - 1, req);
 865
 866         /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
 867          * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
 868          */
 869
 870         /* wait till current packet DMA finishes, and fifo empties */
 871         if (ep->bEndpointAddress & USB_DIR_IN) {
 872                 UDC_TXDMA_CFG_REG = (UDC_TXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
 873
 874                 if (req) {
 875                         finish_in_dma(ep, req, -ECONNRESET);
 876
 877                         /* clear FIFO; hosts probably won't empty it */
 878                         use_ep(ep, UDC_EP_SEL);
 879                         UDC_CTRL_REG = UDC_CLR_EP;
 880                         deselect_ep();
 881                 }
 882                 while (UDC_TXDMA_CFG_REG & mask)
 883                         udelay(10);
 884         } else {
 885                 UDC_RXDMA_CFG_REG = (UDC_RXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
 886
 887                 /* dma empties the fifo */
 888                 while (UDC_RXDMA_CFG_REG & mask)
 889                         udelay(10);
 890                 if (req)
 891                         finish_out_dma(ep, req, -ECONNRESET, 0);
 892         }
 893         omap_free_dma(ep->lch);
 894         ep->dma_channel = 0;
 895         ep->lch = -1;
 896         /* has_dma still set, till endpoint is fully quiesced */
 897 }
 898
 899
 900 /*-------------------------------------------------------------------------*/
 901
 902 static int
 903 omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 904 {
 905         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 906         struct omap_req *req = container_of(_req, struct omap_req, req);
 907         struct omap_udc *udc;
 908         unsigned long   flags;
 909         int             is_iso = 0;
 910
 911         /* catch various bogus parameters */
 912         if (!_req || !req->req.complete || !req->req.buf
 913                         || !list_empty(&req->queue)) {
 914                 DBG("%s, bad params\n", __FUNCTION__);
 915                 return -EINVAL;
 916         }
 917         if (!_ep || (!ep->desc && ep->bEndpointAddress)) {
 918                 DBG("%s, bad ep\n", __FUNCTION__);
 919                 return -EINVAL;
 920         }
 921         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 922                 if (req->req.length > ep->ep.maxpacket)
 923                         return -EMSGSIZE;
 924                 is_iso = 1;
 925         }
 926
 927         /* this isn't bogus, but OMAP DMA isn't the only hardware to
 928          * have a hard time with partial packet reads...  reject it.
 929          */
 930         if (use_dma
 931                         && ep->has_dma
 932                         && ep->bEndpointAddress != 0
 933                         && (ep->bEndpointAddress & USB_DIR_IN) == 0
 934                         && (req->req.length % ep->ep.maxpacket) != 0) {
 935                 DBG("%s, no partial packet OUT reads\n", __FUNCTION__);
 936                 return -EMSGSIZE;
 937         }
 938
 939         udc = ep->udc;
 940         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 941                 return -ESHUTDOWN;
 942
 943         if (use_dma && ep->has_dma) {
 944                 if (req->req.dma == DMA_ADDR_INVALID) {
 945                         req->req.dma = dma_map_single(
 946                                 ep->udc->gadget.dev.parent,
 947                                 req->req.buf,
 948                                 req->req.length,
 949                                 (ep->bEndpointAddress & USB_DIR_IN)
 950                                         ? DMA_TO_DEVICE
 951                                         : DMA_FROM_DEVICE);
 952                         req->mapped = 1;
 953                 } else {
 954                         dma_sync_single_for_device(
 955                                 ep->udc->gadget.dev.parent,
 956                                 req->req.dma, req->req.length,
 957                                 (ep->bEndpointAddress & USB_DIR_IN)
 958                                         ? DMA_TO_DEVICE
 959                                         : DMA_FROM_DEVICE);
 960                         req->mapped = 0;
 961                 }
 962         }
 963
 964         VDBG("%s queue req %p, len %d buf %p\n",
 965                 ep->ep.name, _req, _req->length, _req->buf);
 966
 967         spin_lock_irqsave(&udc->lock, flags);
 968
 969         req->req.status = -EINPROGRESS;
 970         req->req.actual = 0;
 971
 972         /* maybe kickstart non-iso i/o queues */
 973         if (is_iso)
 974                 UDC_IRQ_EN_REG |= UDC_SOF_IE;
 975         else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
 976                 int     is_in;
 977
 978                 if (ep->bEndpointAddress == 0) {
 979                         if (!udc->ep0_pending || !list_empty (&ep->queue)) {
 980                                 spin_unlock_irqrestore(&udc->lock, flags);
 981                                 return -EL2HLT;
 982                         }
 983
 984                         /* empty DATA stage? */
 985                         is_in = udc->ep0_in;
 986                         if (!req->req.length) {
 987
 988                                 /* chip became CONFIGURED or ADDRESSED
 989                                  * earlier; drivers may already have queued
 990                                  * requests to non-control endpoints
 991                                  */
 992                                 if (udc->ep0_set_config) {
 993                                         u16     irq_en = UDC_IRQ_EN_REG;
 994
 995                                         irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
 996                                         if (!udc->ep0_reset_config)
 997                                                 irq_en |= UDC_EPN_RX_IE
 998                                                         | UDC_EPN_TX_IE;
 999                                         UDC_IRQ_EN_REG = irq_en;
1000                                 }
1001
1002                                 /* STATUS for zero length DATA stages is
1003                                  * always an IN ... even for IN transfers,
1004                                  * a wierd case which seem to stall OMAP.
1005                                  */
1006                                 UDC_EP_NUM_REG = (UDC_EP_SEL|UDC_EP_DIR);
1007                                 UDC_CTRL_REG = UDC_CLR_EP;
1008                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1009                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1010
1011                                 /* cleanup */
1012                                 udc->ep0_pending = 0;
1013                                 done(ep, req, 0);
1014                                 req = NULL;
1015
1016                         /* non-empty DATA stage */
1017                         } else if (is_in) {
1018                                 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1019                         } else {
1020                                 if (udc->ep0_setup)
1021                                         goto irq_wait;
1022                                 UDC_EP_NUM_REG = UDC_EP_SEL;
1023                         }
1024                 } else {
1025                         is_in = ep->bEndpointAddress & USB_DIR_IN;
1026                         if (!ep->has_dma)
1027                                 use_ep(ep, UDC_EP_SEL);
1028                         /* if ISO: SOF IRQs must be enabled/disabled! */
1029                 }
1030
1031                 if (ep->has_dma)
1032                         (is_in ? next_in_dma : next_out_dma)(ep, req);
1033                 else if (req) {
1034                         if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
1035                                 req = NULL;
1036                         deselect_ep();
1037                         if (!is_in) {
1038                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1039                                 ep->ackwait = 1 + ep->double_buf;
1040                         }
1041                         /* IN: 6 wait states before it'll tx */
1042                 }
1043         }
1044
1045 irq_wait:
1046         /* irq handler advances the queue */
1047         if (req != NULL)
1048                 list_add_tail(&req->queue, &ep->queue);
1049         spin_unlock_irqrestore(&udc->lock, flags);
1050
1051         return 0;
1052 }
1053
1054 static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1055 {
1056         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1057         struct omap_req *req;
1058         unsigned long   flags;
1059
1060         if (!_ep || !_req)
1061                 return -EINVAL;
1062
1063         spin_lock_irqsave(&ep->udc->lock, flags);
1064
1065         /* make sure it's actually queued on this endpoint */
1066         list_for_each_entry (req, &ep->queue, queue) {
1067                 if (&req->req == _req)
1068                         break;
1069         }
1070         if (&req->req != _req) {
1071                 spin_unlock_irqrestore(&ep->udc->lock, flags);
1072                 return -EINVAL;
1073         }
1074
1075         if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1076                 int channel = ep->dma_channel;
1077
1078                 /* releasing the channel cancels the request,
1079                  * reclaiming the channel restarts the queue
1080                  */
1081                 dma_channel_release(ep);
1082                 dma_channel_claim(ep, channel);
1083         } else
1084                 done(ep, req, -ECONNRESET);
1085         spin_unlock_irqrestore(&ep->udc->lock, flags);
1086         return 0;
1087 }
1088
1089 /*-------------------------------------------------------------------------*/
1090
1091 static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1092 {
1093         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1094         unsigned long   flags;
1095         int             status = -EOPNOTSUPP;
1096
1097         spin_lock_irqsave(&ep->udc->lock, flags);
1098
1099         /* just use protocol stalls for ep0; real halts are annoying */
1100         if (ep->bEndpointAddress == 0) {
1101                 if (!ep->udc->ep0_pending)
1102                         status = -EINVAL;
1103                 else if (value) {
1104                         if (ep->udc->ep0_set_config) {
1105                                 WARN("error changing config?\n");
1106                                 UDC_SYSCON2_REG = UDC_CLR_CFG;
1107                         }
1108                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1109                         ep->udc->ep0_pending = 0;
1110                         status = 0;
1111                 } else /* NOP */
1112                         status = 0;
1113
1114         /* otherwise, all active non-ISO endpoints can halt */
1115         } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->desc) {
1116
1117                 /* IN endpoints must already be idle */
1118                 if ((ep->bEndpointAddress & USB_DIR_IN)
1119                                 && !list_empty(&ep->queue)) {
1120                         status = -EAGAIN;
1121                         goto done;
1122                 }
1123
1124                 if (value) {
1125                         int     channel;
1126
1127                         if (use_dma && ep->dma_channel
1128                                         && !list_empty(&ep->queue)) {
1129                                 channel = ep->dma_channel;
1130                                 dma_channel_release(ep);
1131                         } else
1132                                 channel = 0;
1133
1134                         use_ep(ep, UDC_EP_SEL);
1135                         if (UDC_STAT_FLG_REG & UDC_NON_ISO_FIFO_EMPTY) {
1136                                 UDC_CTRL_REG = UDC_SET_HALT;
1137                                 status = 0;
1138                         } else
1139                                 status = -EAGAIN;
1140                         deselect_ep();
1141
1142                         if (channel)
1143                                 dma_channel_claim(ep, channel);
1144                 } else {
1145                         use_ep(ep, 0);
1146                         UDC_CTRL_REG = ep->udc->clr_halt;
1147                         ep->ackwait = 0;
1148                         if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1149                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1150                                 ep->ackwait = 1 + ep->double_buf;
1151                         }
1152                 }
1153         }
1154 done:
1155         VDBG("%s %s halt stat %d\n", ep->ep.name,
1156                 value ? "set" : "clear", status);
1157
1158         spin_unlock_irqrestore(&ep->udc->lock, flags);
1159         return status;
1160 }
1161
1162 static struct usb_ep_ops omap_ep_ops = {
1163         .enable         = omap_ep_enable,
1164         .disable        = omap_ep_disable,
1165
1166         .alloc_request  = omap_alloc_request,
1167         .free_request   = omap_free_request,
1168
1169         .queue          = omap_ep_queue,
1170         .dequeue        = omap_ep_dequeue,
1171
1172         .set_halt       = omap_ep_set_halt,
1173         // fifo_status ... report bytes in fifo
1174         // fifo_flush ... flush fifo
1175 };
1176
1177 /*-------------------------------------------------------------------------*/
1178
1179 static int omap_get_frame(struct usb_gadget *gadget)
1180 {
1181         u16     sof = UDC_SOF_REG;
1182         return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1183 }
1184
1185 static int omap_wakeup(struct usb_gadget *gadget)
1186 {
1187         struct omap_udc *udc;
1188         unsigned long   flags;
1189         int             retval = -EHOSTUNREACH;
1190
1191         udc = container_of(gadget, struct omap_udc, gadget);
1192
1193         spin_lock_irqsave(&udc->lock, flags);
1194         if (udc->devstat & UDC_SUS) {
1195                 /* NOTE:  OTG spec erratum says that OTG devices may
1196                  * issue wakeups without host enable.
1197                  */
1198                 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1199                         DBG("remote wakeup...\n");
1200                         UDC_SYSCON2_REG = UDC_RMT_WKP;
1201                         retval = 0;
1202                 }
1203
1204         /* NOTE:  non-OTG systems may use SRP TOO... */
1205         } else if (!(udc->devstat & UDC_ATT)) {
1206                 if (udc->transceiver)
1207                         retval = otg_start_srp(udc->transceiver);
1208         }
1209         spin_unlock_irqrestore(&udc->lock, flags);
1210
1211         return retval;
1212 }
1213
1214 static int
1215 omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1216 {
1217         struct omap_udc *udc;
1218         unsigned long   flags;
1219         u16             syscon1;
1220
1221         udc = container_of(gadget, struct omap_udc, gadget);
1222         spin_lock_irqsave(&udc->lock, flags);
1223         syscon1 = UDC_SYSCON1_REG;
1224         if (is_selfpowered)
1225                 syscon1 |= UDC_SELF_PWR;
1226         else
1227                 syscon1 &= ~UDC_SELF_PWR;
1228         UDC_SYSCON1_REG = syscon1;
1229         spin_unlock_irqrestore(&udc->lock, flags);
1230
1231         return 0;
1232 }
1233
1234 static int can_pullup(struct omap_udc *udc)
1235 {
1236         return udc->driver && udc->softconnect && udc->vbus_active;
1237 }
1238
1239 static void pullup_enable(struct omap_udc *udc)
1240 {
1241         udc->gadget.dev.parent->power.power_state = PMSG_ON;
1242         udc->gadget.dev.power.power_state = PMSG_ON;
1243         UDC_SYSCON1_REG |= UDC_PULLUP_EN;
1244 #ifndef CONFIG_USB_OTG
1245         if (!cpu_is_omap15xx())
1246                 OTG_CTRL_REG |= OTG_BSESSVLD;
1247 #endif
1248         UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1249 }
1250
1251 static void pullup_disable(struct omap_udc *udc)
1252 {
1253 #ifndef CONFIG_USB_OTG
1254         if (!cpu_is_omap15xx())
1255                 OTG_CTRL_REG &= ~OTG_BSESSVLD;
1256 #endif
1257         UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1258         UDC_SYSCON1_REG &= ~UDC_PULLUP_EN;
1259 }
1260
1261 static struct omap_udc *udc;
1262
1263 static void omap_udc_enable_clock(int enable)
1264 {
1265         if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1266                 return;
1267
1268         if (enable) {
1269                 clk_enable(udc->dc_clk);
1270                 clk_enable(udc->hhc_clk);
1271                 udelay(100);
1272         } else {
1273                 clk_disable(udc->hhc_clk);
1274                 clk_disable(udc->dc_clk);
1275         }
1276 }
1277
1278 /*
1279  * Called by whatever detects VBUS sessions:  external transceiver
1280  * driver, or maybe GPIO0 VBUS IRQ.  May request 48 MHz clock.
1281  */
1282 static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1283 {
1284         struct omap_udc *udc;
1285         unsigned long   flags;
1286
1287         udc = container_of(gadget, struct omap_udc, gadget);
1288         spin_lock_irqsave(&udc->lock, flags);
1289         VDBG("VBUS %s\n", is_active ? "on" : "off");
1290         udc->vbus_active = (is_active != 0);
1291         if (cpu_is_omap15xx()) {
1292                 /* "software" detect, ignored if !VBUS_MODE_1510 */
1293                 if (is_active)
1294                         FUNC_MUX_CTRL_0_REG |= VBUS_CTRL_1510;
1295                 else
1296                         FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
1297         }
1298         if (udc->dc_clk != NULL && is_active) {
1299                 if (!udc->clk_requested) {
1300                         omap_udc_enable_clock(1);
1301                         udc->clk_requested = 1;
1302                 }
1303         }
1304         if (can_pullup(udc))
1305                 pullup_enable(udc);
1306         else
1307                 pullup_disable(udc);
1308         if (udc->dc_clk != NULL && !is_active) {
1309                 if (udc->clk_requested) {
1310                         omap_udc_enable_clock(0);
1311                         udc->clk_requested = 0;
1312                 }
1313         }
1314         spin_unlock_irqrestore(&udc->lock, flags);
1315         return 0;
1316 }
1317
1318 static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1319 {
1320         struct omap_udc *udc;
1321
1322         udc = container_of(gadget, struct omap_udc, gadget);
1323         if (udc->transceiver)
1324                 return otg_set_power(udc->transceiver, mA);
1325         return -EOPNOTSUPP;
1326 }
1327
1328 static int omap_pullup(struct usb_gadget *gadget, int is_on)
1329 {
1330         struct omap_udc *udc;
1331         unsigned long   flags;
1332
1333         udc = container_of(gadget, struct omap_udc, gadget);
1334         spin_lock_irqsave(&udc->lock, flags);
1335         udc->softconnect = (is_on != 0);
1336         if (can_pullup(udc))
1337                 pullup_enable(udc);
1338         else
1339                 pullup_disable(udc);
1340         spin_unlock_irqrestore(&udc->lock, flags);
1341         return 0;
1342 }
1343
1344 static struct usb_gadget_ops omap_gadget_ops = {
1345         .get_frame              = omap_get_frame,
1346         .wakeup                 = omap_wakeup,
1347         .set_selfpowered        = omap_set_selfpowered,
1348         .vbus_session           = omap_vbus_session,
1349         .vbus_draw              = omap_vbus_draw,
1350         .pullup                 = omap_pullup,
1351 };
1352
1353 /*-------------------------------------------------------------------------*/
1354
1355 /* dequeue ALL requests; caller holds udc->lock */
1356 static void nuke(struct omap_ep *ep, int status)
1357 {
1358         struct omap_req *req;
1359
1360         ep->stopped = 1;
1361
1362         if (use_dma && ep->dma_channel)
1363                 dma_channel_release(ep);
1364
1365         use_ep(ep, 0);
1366         UDC_CTRL_REG = UDC_CLR_EP;
1367         if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1368                 UDC_CTRL_REG = UDC_SET_HALT;
1369
1370         while (!list_empty(&ep->queue)) {
1371                 req = list_entry(ep->queue.next, struct omap_req, queue);
1372                 done(ep, req, status);
1373         }
1374 }
1375
1376 /* caller holds udc->lock */
1377 static void udc_quiesce(struct omap_udc *udc)
1378 {
1379         struct omap_ep  *ep;
1380
1381         udc->gadget.speed = USB_SPEED_UNKNOWN;
1382         nuke(&udc->ep[0], -ESHUTDOWN);
1383         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list)
1384                 nuke(ep, -ESHUTDOWN);
1385 }
1386
1387 /*-------------------------------------------------------------------------*/
1388
1389 static void update_otg(struct omap_udc *udc)
1390 {
1391         u16     devstat;
1392
1393         if (!udc->gadget.is_otg)
1394                 return;
1395
1396         if (OTG_CTRL_REG & OTG_ID)
1397                 devstat = UDC_DEVSTAT_REG;
1398         else
1399                 devstat = 0;
1400
1401         udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1402         udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1403         udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1404
1405         /* Enable HNP early, avoiding races on suspend irq path.
1406          * ASSUMES OTG state machine B_BUS_REQ input is true.
1407          */
1408         if (udc->gadget.b_hnp_enable)
1409                 OTG_CTRL_REG = (OTG_CTRL_REG | OTG_B_HNPEN | OTG_B_BUSREQ)
1410                                 & ~OTG_PULLUP;
1411 }
1412
1413 static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1414 {
1415         struct omap_ep  *ep0 = &udc->ep[0];
1416         struct omap_req *req = NULL;
1417
1418         ep0->irqs++;
1419
1420         /* Clear any pending requests and then scrub any rx/tx state
1421          * before starting to handle the SETUP request.
1422          */
1423         if (irq_src & UDC_SETUP) {
1424                 u16     ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1425
1426                 nuke(ep0, 0);
1427                 if (ack) {
1428                         UDC_IRQ_SRC_REG = ack;
1429                         irq_src = UDC_SETUP;
1430                 }
1431         }
1432
1433         /* IN/OUT packets mean we're in the DATA or STATUS stage.
1434          * This driver uses only uses protocol stalls (ep0 never halts),
1435          * and if we got this far the gadget driver already had a
1436          * chance to stall.  Tries to be forgiving of host oddities.
1437          *
1438          * NOTE:  the last chance gadget drivers have to stall control
1439          * requests is during their request completion callback.
1440          */
1441         if (!list_empty(&ep0->queue))
1442                 req = container_of(ep0->queue.next, struct omap_req, queue);
1443
1444         /* IN == TX to host */
1445         if (irq_src & UDC_EP0_TX) {
1446                 int     stat;
1447
1448                 UDC_IRQ_SRC_REG = UDC_EP0_TX;
1449                 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1450                 stat = UDC_STAT_FLG_REG;
1451                 if (stat & UDC_ACK) {
1452                         if (udc->ep0_in) {
1453                                 /* write next IN packet from response,
1454                                  * or set up the status stage.
1455                                  */
1456                                 if (req)
1457                                         stat = write_fifo(ep0, req);
1458                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1459                                 if (!req && udc->ep0_pending) {
1460                                         UDC_EP_NUM_REG = UDC_EP_SEL;
1461                                         UDC_CTRL_REG = UDC_CLR_EP;
1462                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1463                                         UDC_EP_NUM_REG = 0;
1464                                         udc->ep0_pending = 0;
1465                                 } /* else:  6 wait states before it'll tx */
1466                         } else {
1467                                 /* ack status stage of OUT transfer */
1468                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1469                                 if (req)
1470                                         done(ep0, req, 0);
1471                         }
1472                         req = NULL;
1473                 } else if (stat & UDC_STALL) {
1474                         UDC_CTRL_REG = UDC_CLR_HALT;
1475                         UDC_EP_NUM_REG = UDC_EP_DIR;
1476                 } else {
1477                         UDC_EP_NUM_REG = UDC_EP_DIR;
1478                 }
1479         }
1480
1481         /* OUT == RX from host */
1482         if (irq_src & UDC_EP0_RX) {
1483                 int     stat;
1484
1485                 UDC_IRQ_SRC_REG = UDC_EP0_RX;
1486                 UDC_EP_NUM_REG = UDC_EP_SEL;
1487                 stat = UDC_STAT_FLG_REG;
1488                 if (stat & UDC_ACK) {
1489                         if (!udc->ep0_in) {
1490                                 stat = 0;
1491                                 /* read next OUT packet of request, maybe
1492                                  * reactiviting the fifo; stall on errors.
1493                                  */
1494                                 if (!req || (stat = read_fifo(ep0, req)) < 0) {
1495                                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1496                                         udc->ep0_pending = 0;
1497                                         stat = 0;
1498                                 } else if (stat == 0)
1499                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1500                                 UDC_EP_NUM_REG = 0;
1501
1502                                 /* activate status stage */
1503                                 if (stat == 1) {
1504                                         done(ep0, req, 0);
1505                                         /* that may have STALLed ep0... */
1506                                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1507                                         UDC_CTRL_REG = UDC_CLR_EP;
1508                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1509                                         UDC_EP_NUM_REG = UDC_EP_DIR;
1510                                         udc->ep0_pending = 0;
1511                                 }
1512                         } else {
1513                                 /* ack status stage of IN transfer */
1514                                 UDC_EP_NUM_REG = 0;
1515                                 if (req)
1516                                         done(ep0, req, 0);
1517                         }
1518                 } else if (stat & UDC_STALL) {
1519                         UDC_CTRL_REG = UDC_CLR_HALT;
1520                         UDC_EP_NUM_REG = 0;
1521                 } else {
1522                         UDC_EP_NUM_REG = 0;
1523                 }
1524         }
1525
1526         /* SETUP starts all control transfers */
1527         if (irq_src & UDC_SETUP) {
1528                 union u {
1529                         u16                     word[4];
1530                         struct usb_ctrlrequest  r;
1531                 } u;
1532                 int                     status = -EINVAL;
1533                 struct omap_ep          *ep;
1534
1535                 /* read the (latest) SETUP message */
1536                 do {
1537                         UDC_EP_NUM_REG = UDC_SETUP_SEL;
1538                         /* two bytes at a time */
1539                         u.word[0] = UDC_DATA_REG;
1540                         u.word[1] = UDC_DATA_REG;
1541                         u.word[2] = UDC_DATA_REG;
1542                         u.word[3] = UDC_DATA_REG;
1543                         UDC_EP_NUM_REG = 0;
1544                 } while (UDC_IRQ_SRC_REG & UDC_SETUP);
1545
1546 #define w_value         le16_to_cpu(u.r.wValue)
1547 #define w_index         le16_to_cpu(u.r.wIndex)
1548 #define w_length        le16_to_cpu(u.r.wLength)
1549
1550                 /* Delegate almost all control requests to the gadget driver,
1551                  * except for a handful of ch9 status/feature requests that
1552                  * hardware doesn't autodecode _and_ the gadget API hides.
1553                  */
1554                 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1555                 udc->ep0_set_config = 0;
1556                 udc->ep0_pending = 1;
1557                 ep0->stopped = 0;
1558                 ep0->ackwait = 0;
1559                 switch (u.r.bRequest) {
1560                 case USB_REQ_SET_CONFIGURATION:
1561                         /* udc needs to know when ep != 0 is valid */
1562                         if (u.r.bRequestType != USB_RECIP_DEVICE)
1563                                 goto delegate;
1564                         if (w_length != 0)
1565                                 goto do_stall;
1566                         udc->ep0_set_config = 1;
1567                         udc->ep0_reset_config = (w_value == 0);
1568                         VDBG("set config %d\n", w_value);
1569
1570                         /* update udc NOW since gadget driver may start
1571                          * queueing requests immediately; clear config
1572                          * later if it fails the request.
1573                          */
1574                         if (udc->ep0_reset_config)
1575                                 UDC_SYSCON2_REG = UDC_CLR_CFG;
1576                         else
1577                                 UDC_SYSCON2_REG = UDC_DEV_CFG;
1578                         update_otg(udc);
1579                         goto delegate;
1580                 case USB_REQ_CLEAR_FEATURE:
1581                         /* clear endpoint halt */
1582                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1583                                 goto delegate;
1584                         if (w_value != USB_ENDPOINT_HALT
1585                                         || w_length != 0)
1586                                 goto do_stall;
1587                         ep = &udc->ep[w_index & 0xf];
1588                         if (ep != ep0) {
1589                                 if (w_index & USB_DIR_IN)
1590                                         ep += 16;
1591                                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1592                                                 || !ep->desc)
1593                                         goto do_stall;
1594                                 use_ep(ep, 0);
1595                                 UDC_CTRL_REG = udc->clr_halt;
1596                                 ep->ackwait = 0;
1597                                 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1598                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1599                                         ep->ackwait = 1 + ep->double_buf;
1600                                 }
1601                                 /* NOTE:  assumes the host behaves sanely,
1602                                  * only clearing real halts.  Else we may
1603                                  * need to kill pending transfers and then
1604                                  * restart the queue... very messy for DMA!
1605                                  */
1606                         }
1607                         VDBG("%s halt cleared by host\n", ep->name);
1608                         goto ep0out_status_stage;
1609                 case USB_REQ_SET_FEATURE:
1610                         /* set endpoint halt */
1611                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1612                                 goto delegate;
1613                         if (w_value != USB_ENDPOINT_HALT
1614                                         || w_length != 0)
1615                                 goto do_stall;
1616                         ep = &udc->ep[w_index & 0xf];
1617                         if (w_index & USB_DIR_IN)
1618                                 ep += 16;
1619                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1620                                         || ep == ep0 || !ep->desc)
1621                                 goto do_stall;
1622                         if (use_dma && ep->has_dma) {
1623                                 /* this has rude side-effects (aborts) and
1624                                  * can't really work if DMA-IN is active
1625                                  */
1626                                 DBG("%s host set_halt, NYET \n", ep->name);
1627                                 goto do_stall;
1628                         }
1629                         use_ep(ep, 0);
1630                         /* can't halt if fifo isn't empty... */
1631                         UDC_CTRL_REG = UDC_CLR_EP;
1632                         UDC_CTRL_REG = UDC_SET_HALT;
1633                         VDBG("%s halted by host\n", ep->name);
1634 ep0out_status_stage:
1635                         status = 0;
1636                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1637                         UDC_CTRL_REG = UDC_CLR_EP;
1638                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1639                         UDC_EP_NUM_REG = UDC_EP_DIR;
1640                         udc->ep0_pending = 0;
1641                         break;
1642                 case USB_REQ_GET_STATUS:
1643                         /* USB_ENDPOINT_HALT status? */
1644                         if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
1645                                 goto intf_status;
1646
1647                         /* ep0 never stalls */
1648                         if (!(w_index & 0xf))
1649                                 goto zero_status;
1650
1651                         /* only active endpoints count */
1652                         ep = &udc->ep[w_index & 0xf];
1653                         if (w_index & USB_DIR_IN)
1654                                 ep += 16;
1655                         if (!ep->desc)
1656                                 goto do_stall;
1657
1658                         /* iso never stalls */
1659                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1660                                 goto zero_status;
1661
1662                         /* FIXME don't assume non-halted endpoints!! */
1663                         ERR("%s status, can't report\n", ep->ep.name);
1664                         goto do_stall;
1665
1666 intf_status:
1667                         /* return interface status.  if we were pedantic,
1668                          * we'd detect non-existent interfaces, and stall.
1669                          */
1670                         if (u.r.bRequestType
1671                                         != (USB_DIR_IN|USB_RECIP_INTERFACE))
1672                                 goto delegate;
1673
1674 zero_status:
1675                         /* return two zero bytes */
1676                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1677                         UDC_DATA_REG = 0;
1678                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1679                         UDC_EP_NUM_REG = UDC_EP_DIR;
1680                         status = 0;
1681                         VDBG("GET_STATUS, interface %d\n", w_index);
1682                         /* next, status stage */
1683                         break;
1684                 default:
1685 delegate:
1686                         /* activate the ep0out fifo right away */
1687                         if (!udc->ep0_in && w_length) {
1688                                 UDC_EP_NUM_REG = 0;
1689                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1690                         }
1691
1692                         /* gadget drivers see class/vendor specific requests,
1693                          * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1694                          * and more
1695                          */
1696                         VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1697                                 u.r.bRequestType, u.r.bRequest,
1698                                 w_value, w_index, w_length);
1699
1700 #undef  w_value
1701 #undef  w_index
1702 #undef  w_length
1703
1704                         /* The gadget driver may return an error here,
1705                          * causing an immediate protocol stall.
1706                          *
1707                          * Else it must issue a response, either queueing a
1708                          * response buffer for the DATA stage, or halting ep0
1709                          * (causing a protocol stall, not a real halt).  A
1710                          * zero length buffer means no DATA stage.
1711                          *
1712                          * It's fine to issue that response after the setup()
1713                          * call returns, and this IRQ was handled.
1714                          */
1715                         udc->ep0_setup = 1;
1716                         spin_unlock(&udc->lock);
1717                         status = udc->driver->setup (&udc->gadget, &u.r);
1718                         spin_lock(&udc->lock);
1719                         udc->ep0_setup = 0;
1720                 }
1721
1722                 if (status < 0) {
1723 do_stall:
1724                         VDBG("req %02x.%02x protocol STALL; stat %d\n",
1725                                         u.r.bRequestType, u.r.bRequest, status);
1726                         if (udc->ep0_set_config) {
1727                                 if (udc->ep0_reset_config)
1728                                         WARN("error resetting config?\n");
1729                                 else
1730                                         UDC_SYSCON2_REG = UDC_CLR_CFG;
1731                         }
1732                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1733                         udc->ep0_pending = 0;
1734                 }
1735         }
1736 }
1737
1738 /*-------------------------------------------------------------------------*/
1739
1740 #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1741
1742 static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1743 {
1744         u16     devstat, change;
1745
1746         devstat = UDC_DEVSTAT_REG;
1747         change = devstat ^ udc->devstat;
1748         udc->devstat = devstat;
1749
1750         if (change & (UDC_USB_RESET|UDC_ATT)) {
1751                 udc_quiesce(udc);
1752
1753                 if (change & UDC_ATT) {
1754                         /* driver for any external transceiver will
1755                          * have called omap_vbus_session() already
1756                          */
1757                         if (devstat & UDC_ATT) {
1758                                 udc->gadget.speed = USB_SPEED_FULL;
1759                                 VDBG("connect\n");
1760                                 if (!udc->transceiver)
1761                                         pullup_enable(udc);
1762                                 // if (driver->connect) call it
1763                         } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1764                                 udc->gadget.speed = USB_SPEED_UNKNOWN;
1765                                 if (!udc->transceiver)
1766                                         pullup_disable(udc);
1767                                 DBG("disconnect, gadget %s\n",
1768                                         udc->driver->driver.name);
1769                                 if (udc->driver->disconnect) {
1770                                         spin_unlock(&udc->lock);
1771                                         udc->driver->disconnect(&udc->gadget);
1772                                         spin_lock(&udc->lock);
1773                                 }
1774                         }
1775                         change &= ~UDC_ATT;
1776                 }
1777
1778                 if (change & UDC_USB_RESET) {
1779                         if (devstat & UDC_USB_RESET) {
1780                                 VDBG("RESET=1\n");
1781                         } else {
1782                                 udc->gadget.speed = USB_SPEED_FULL;
1783                                 INFO("USB reset done, gadget %s\n",
1784                                         udc->driver->driver.name);
1785                                 /* ep0 traffic is legal from now on */
1786                                 UDC_IRQ_EN_REG = UDC_DS_CHG_IE | UDC_EP0_IE;
1787                         }
1788                         change &= ~UDC_USB_RESET;
1789                 }
1790         }
1791         if (change & UDC_SUS) {
1792                 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1793                         // FIXME tell isp1301 to suspend/resume (?)
1794                         if (devstat & UDC_SUS) {
1795                                 VDBG("suspend\n");
1796                                 update_otg(udc);
1797                                 /* HNP could be under way already */
1798                                 if (udc->gadget.speed == USB_SPEED_FULL
1799                                                 && udc->driver->suspend) {
1800                                         spin_unlock(&udc->lock);
1801                                         udc->driver->suspend(&udc->gadget);
1802                                         spin_lock(&udc->lock);
1803                                 }
1804                                 if (udc->transceiver)
1805                                         otg_set_suspend(udc->transceiver, 1);
1806                         } else {
1807                                 VDBG("resume\n");
1808                                 if (udc->transceiver)
1809                                         otg_set_suspend(udc->transceiver, 0);
1810                                 if (udc->gadget.speed == USB_SPEED_FULL
1811                                                 && udc->driver->resume) {
1812                                         spin_unlock(&udc->lock);
1813                                         udc->driver->resume(&udc->gadget);
1814                                         spin_lock(&udc->lock);
1815                                 }
1816                         }
1817                 }
1818                 change &= ~UDC_SUS;
1819         }
1820         if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1821                 update_otg(udc);
1822                 change &= ~OTG_FLAGS;
1823         }
1824
1825         change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1826         if (change)
1827                 VDBG("devstat %03x, ignore change %03x\n",
1828                         devstat,  change);
1829
1830         UDC_IRQ_SRC_REG = UDC_DS_CHG;
1831 }
1832
1833 static irqreturn_t omap_udc_irq(int irq, void *_udc)
1834 {
1835         struct omap_udc *udc = _udc;
1836         u16             irq_src;
1837         irqreturn_t     status = IRQ_NONE;
1838         unsigned long   flags;
1839
1840         spin_lock_irqsave(&udc->lock, flags);
1841         irq_src = UDC_IRQ_SRC_REG;
1842
1843         /* Device state change (usb ch9 stuff) */
1844         if (irq_src & UDC_DS_CHG) {
1845                 devstate_irq(_udc, irq_src);
1846                 status = IRQ_HANDLED;
1847                 irq_src &= ~UDC_DS_CHG;
1848         }
1849
1850         /* EP0 control transfers */
1851         if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1852                 ep0_irq(_udc, irq_src);
1853                 status = IRQ_HANDLED;
1854                 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1855         }
1856
1857         /* DMA transfer completion */
1858         if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1859                 dma_irq(_udc, irq_src);
1860                 status = IRQ_HANDLED;
1861                 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1862         }
1863
1864         irq_src &= ~(UDC_SOF|UDC_EPN_TX|UDC_EPN_RX);
1865         if (irq_src)
1866                 DBG("udc_irq, unhandled %03x\n", irq_src);
1867         spin_unlock_irqrestore(&udc->lock, flags);
1868
1869         return status;
1870 }
1871
1872 /* workaround for seemingly-lost IRQs for RX ACKs... */
1873 #define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1874 #define HALF_FULL(f)    (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1875
1876 static void pio_out_timer(unsigned long _ep)
1877 {
1878         struct omap_ep  *ep = (void *) _ep;
1879         unsigned long   flags;
1880         u16             stat_flg;
1881
1882         spin_lock_irqsave(&ep->udc->lock, flags);
1883         if (!list_empty(&ep->queue) && ep->ackwait) {
1884                 use_ep(ep, UDC_EP_SEL);
1885                 stat_flg = UDC_STAT_FLG_REG;
1886
1887                 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1888                                 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1889                         struct omap_req *req;
1890
1891                         VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1892                         req = container_of(ep->queue.next,
1893                                         struct omap_req, queue);
1894                         (void) read_fifo(ep, req);
1895                         UDC_EP_NUM_REG = ep->bEndpointAddress;
1896                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1897                         ep->ackwait = 1 + ep->double_buf;
1898                 } else
1899                         deselect_ep();
1900         }
1901         mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1902         spin_unlock_irqrestore(&ep->udc->lock, flags);
1903 }
1904
1905 static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1906 {
1907         u16             epn_stat, irq_src;
1908         irqreturn_t     status = IRQ_NONE;
1909         struct omap_ep  *ep;
1910         int             epnum;
1911         struct omap_udc *udc = _dev;
1912         struct omap_req *req;
1913         unsigned long   flags;
1914
1915         spin_lock_irqsave(&udc->lock, flags);
1916         epn_stat = UDC_EPN_STAT_REG;
1917         irq_src = UDC_IRQ_SRC_REG;
1918
1919         /* handle OUT first, to avoid some wasteful NAKs */
1920         if (irq_src & UDC_EPN_RX) {
1921                 epnum = (epn_stat >> 8) & 0x0f;
1922                 UDC_IRQ_SRC_REG = UDC_EPN_RX;
1923                 status = IRQ_HANDLED;
1924                 ep = &udc->ep[epnum];
1925                 ep->irqs++;
1926
1927                 UDC_EP_NUM_REG = epnum | UDC_EP_SEL;
1928                 ep->fnf = 0;
1929                 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1930                         ep->ackwait--;
1931                         if (!list_empty(&ep->queue)) {
1932                                 int stat;
1933                                 req = container_of(ep->queue.next,
1934                                                 struct omap_req, queue);
1935                                 stat = read_fifo(ep, req);
1936                                 if (!ep->double_buf)
1937                                         ep->fnf = 1;
1938                         }
1939                 }
1940                 /* min 6 clock delay before clearing EP_SEL ... */
1941                 epn_stat = UDC_EPN_STAT_REG;
1942                 epn_stat = UDC_EPN_STAT_REG;
1943                 UDC_EP_NUM_REG = epnum;
1944
1945                 /* enabling fifo _after_ clearing ACK, contrary to docs,
1946                  * reduces lossage; timer still needed though (sigh).
1947                  */
1948                 if (ep->fnf) {
1949                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1950                         ep->ackwait = 1 + ep->double_buf;
1951                 }
1952                 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1953         }
1954
1955         /* then IN transfers */
1956         else if (irq_src & UDC_EPN_TX) {
1957                 epnum = epn_stat & 0x0f;
1958                 UDC_IRQ_SRC_REG = UDC_EPN_TX;
1959                 status = IRQ_HANDLED;
1960                 ep = &udc->ep[16 + epnum];
1961                 ep->irqs++;
1962
1963                 UDC_EP_NUM_REG = epnum | UDC_EP_DIR | UDC_EP_SEL;
1964                 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1965                         ep->ackwait = 0;
1966                         if (!list_empty(&ep->queue)) {
1967                                 req = container_of(ep->queue.next,
1968                                                 struct omap_req, queue);
1969                                 (void) write_fifo(ep, req);
1970                         }
1971                 }
1972                 /* min 6 clock delay before clearing EP_SEL ... */
1973                 epn_stat = UDC_EPN_STAT_REG;
1974                 epn_stat = UDC_EPN_STAT_REG;
1975                 UDC_EP_NUM_REG = epnum | UDC_EP_DIR;
1976                 /* then 6 clocks before it'd tx */
1977         }
1978
1979         spin_unlock_irqrestore(&udc->lock, flags);
1980         return status;
1981 }
1982
1983 #ifdef  USE_ISO
1984 static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
1985 {
1986         struct omap_udc *udc = _dev;
1987         struct omap_ep  *ep;
1988         int             pending = 0;
1989         unsigned long   flags;
1990
1991         spin_lock_irqsave(&udc->lock, flags);
1992
1993         /* handle all non-DMA ISO transfers */
1994         list_for_each_entry (ep, &udc->iso, iso) {
1995                 u16             stat;
1996                 struct omap_req *req;
1997
1998                 if (ep->has_dma || list_empty(&ep->queue))
1999                         continue;
2000                 req = list_entry(ep->queue.next, struct omap_req, queue);
2001
2002                 use_ep(ep, UDC_EP_SEL);
2003                 stat = UDC_STAT_FLG_REG;
2004
2005                 /* NOTE: like the other controller drivers, this isn't
2006                  * currently reporting lost or damaged frames.
2007                  */
2008                 if (ep->bEndpointAddress & USB_DIR_IN) {
2009                         if (stat & UDC_MISS_IN)
2010                                 /* done(ep, req, -EPROTO) */;
2011                         else
2012                                 write_fifo(ep, req);
2013                 } else {
2014                         int     status = 0;
2015
2016                         if (stat & UDC_NO_RXPACKET)
2017                                 status = -EREMOTEIO;
2018                         else if (stat & UDC_ISO_ERR)
2019                                 status = -EILSEQ;
2020                         else if (stat & UDC_DATA_FLUSH)
2021                                 status = -ENOSR;
2022
2023                         if (status)
2024                                 /* done(ep, req, status) */;
2025                         else
2026                                 read_fifo(ep, req);
2027                 }
2028                 deselect_ep();
2029                 /* 6 wait states before next EP */
2030
2031                 ep->irqs++;
2032                 if (!list_empty(&ep->queue))
2033                         pending = 1;
2034         }
2035         if (!pending)
2036                 UDC_IRQ_EN_REG &= ~UDC_SOF_IE;
2037         UDC_IRQ_SRC_REG = UDC_SOF;
2038
2039         spin_unlock_irqrestore(&udc->lock, flags);
2040         return IRQ_HANDLED;
2041 }
2042 #endif
2043
2044 /*-------------------------------------------------------------------------*/
2045
2046 static inline int machine_without_vbus_sense(void)
2047 {
2048         return (machine_is_omap_innovator()
2049                 || machine_is_omap_osk()
2050                 || machine_is_omap_apollon()
2051 #ifndef CONFIG_MACH_OMAP_H4_OTG
2052                 || machine_is_omap_h4()
2053 #endif
2054                 || machine_is_sx1()
2055                 );
2056 }
2057
2058 int usb_gadget_register_driver (struct usb_gadget_driver *driver)
2059 {
2060         int             status = -ENODEV;
2061         struct omap_ep  *ep;
2062         unsigned long   flags;
2063
2064         /* basic sanity tests */
2065         if (!udc)
2066                 return -ENODEV;
2067         if (!driver
2068                         // FIXME if otg, check:  driver->is_otg
2069                         || driver->speed < USB_SPEED_FULL
2070                         || !driver->bind
2071                         || !driver->setup)
2072                 return -EINVAL;
2073
2074         spin_lock_irqsave(&udc->lock, flags);
2075         if (udc->driver) {
2076                 spin_unlock_irqrestore(&udc->lock, flags);
2077                 return -EBUSY;
2078         }
2079
2080         /* reset state */
2081         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
2082                 ep->irqs = 0;
2083                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2084                         continue;
2085                 use_ep(ep, 0);
2086                 UDC_CTRL_REG = UDC_SET_HALT;
2087         }
2088         udc->ep0_pending = 0;
2089         udc->ep[0].irqs = 0;
2090         udc->softconnect = 1;
2091
2092         /* hook up the driver */
2093         driver->driver.bus = NULL;
2094         udc->driver = driver;
2095         udc->gadget.dev.driver = &driver->driver;
2096         spin_unlock_irqrestore(&udc->lock, flags);
2097
2098         if (udc->dc_clk != NULL)
2099                 omap_udc_enable_clock(1);
2100
2101         status = driver->bind (&udc->gadget);
2102         if (status) {
2103                 DBG("bind to %s --> %d\n", driver->driver.name, status);
2104                 udc->gadget.dev.driver = NULL;
2105                 udc->driver = NULL;
2106                 goto done;
2107         }
2108         DBG("bound to driver %s\n", driver->driver.name);
2109
2110         UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2111
2112         /* connect to bus through transceiver */
2113         if (udc->transceiver) {
2114                 status = otg_set_peripheral(udc->transceiver, &udc->gadget);
2115                 if (status < 0) {
2116                         ERR("can't bind to transceiver\n");
2117                         if (driver->unbind) {
2118                                 driver->unbind (&udc->gadget);
2119                                 udc->gadget.dev.driver = NULL;
2120                                 udc->driver = NULL;
2121                         }
2122                         goto done;
2123                 }
2124         } else {
2125                 if (can_pullup(udc))
2126                         pullup_enable (udc);
2127                 else
2128                         pullup_disable (udc);
2129         }
2130
2131         /* boards that don't have VBUS sensing can't autogate 48MHz;
2132          * can't enter deep sleep while a gadget driver is active.
2133          */
2134         if (machine_without_vbus_sense())
2135                 omap_vbus_session(&udc->gadget, 1);
2136
2137 done:
2138         if (udc->dc_clk != NULL)
2139                 omap_udc_enable_clock(0);
2140         return status;
2141 }
2142 EXPORT_SYMBOL(usb_gadget_register_driver);
2143
2144 int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
2145 {
2146         unsigned long   flags;
2147         int             status = -ENODEV;
2148
2149         if (!udc)
2150                 return -ENODEV;
2151         if (!driver || driver != udc->driver || !driver->unbind)
2152                 return -EINVAL;
2153
2154         if (udc->dc_clk != NULL)
2155                 omap_udc_enable_clock(1);
2156
2157         if (machine_without_vbus_sense())
2158                 omap_vbus_session(&udc->gadget, 0);
2159
2160         if (udc->transceiver)
2161                 (void) otg_set_peripheral(udc->transceiver, NULL);
2162         else
2163                 pullup_disable(udc);
2164
2165         spin_lock_irqsave(&udc->lock, flags);
2166         udc_quiesce(udc);
2167         spin_unlock_irqrestore(&udc->lock, flags);
2168
2169         driver->unbind(&udc->gadget);
2170         udc->gadget.dev.driver = NULL;
2171         udc->driver = NULL;
2172
2173         if (udc->dc_clk != NULL)
2174                 omap_udc_enable_clock(0);
2175         DBG("unregistered driver '%s'\n", driver->driver.name);
2176         return status;
2177 }
2178 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2179
2180
2181 /*-------------------------------------------------------------------------*/
2182
2183 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2184
2185 #include <linux/seq_file.h>
2186
2187 static const char proc_filename[] = "driver/udc";
2188
2189 #define FOURBITS "%s%s%s%s"
2190 #define EIGHTBITS FOURBITS FOURBITS
2191
2192 static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2193 {
2194         u16             stat_flg;
2195         struct omap_req *req;
2196         char            buf[20];
2197
2198         use_ep(ep, 0);
2199
2200         if (use_dma && ep->has_dma)
2201                 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2202                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2203                         ep->dma_channel - 1, ep->lch);
2204         else
2205                 buf[0] = 0;
2206
2207         stat_flg = UDC_STAT_FLG_REG;
2208         seq_printf(s,
2209                 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2210                 ep->name, buf,
2211                 ep->double_buf ? "dbuf " : "",
2212                 ({char *s; switch(ep->ackwait){
2213                 case 0: s = ""; break;
2214                 case 1: s = "(ackw) "; break;
2215                 case 2: s = "(ackw2) "; break;
2216                 default: s = "(?) "; break;
2217                 } s;}),
2218                 ep->irqs, stat_flg,
2219                 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2220                 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2221                 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2222                 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2223                 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2224                 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2225                 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2226                 (stat_flg & UDC_STALL) ? "STALL " : "",
2227                 (stat_flg & UDC_NAK) ? "NAK " : "",
2228                 (stat_flg & UDC_ACK) ? "ACK " : "",
2229                 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2230                 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2231                 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2232
2233         if (list_empty (&ep->queue))
2234                 seq_printf(s, "\t(queue empty)\n");
2235         else
2236                 list_for_each_entry (req, &ep->queue, queue) {
2237                         unsigned        length = req->req.actual;
2238
2239                         if (use_dma && buf[0]) {
2240                                 length += ((ep->bEndpointAddress & USB_DIR_IN)
2241                                                 ? dma_src_len : dma_dest_len)
2242                                         (ep, req->req.dma + length);
2243                                 buf[0] = 0;
2244                         }
2245                         seq_printf(s, "\treq %p len %d/%d buf %p\n",
2246                                         &req->req, length,
2247                                         req->req.length, req->req.buf);
2248                 }
2249 }
2250
2251 static char *trx_mode(unsigned m, int enabled)
2252 {
2253         switch (m) {
2254         case 0:         return enabled ? "*6wire" : "unused";
2255         case 1:         return "4wire";
2256         case 2:         return "3wire";
2257         case 3:         return "6wire";
2258         default:        return "unknown";
2259         }
2260 }
2261
2262 static int proc_otg_show(struct seq_file *s)
2263 {
2264         u32             tmp;
2265         u32             trans;
2266         char            *ctrl_name;
2267
2268         tmp = OTG_REV_REG;
2269         if (cpu_is_omap24xx()) {
2270                 ctrl_name = "control_devconf";
2271                 trans = CONTROL_DEVCONF_REG;
2272         } else {
2273                 ctrl_name = "tranceiver_ctrl";
2274                 trans = USB_TRANSCEIVER_CTRL_REG;
2275         }
2276         seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2277                 tmp >> 4, tmp & 0xf, ctrl_name, trans);
2278         tmp = OTG_SYSCON_1_REG;
2279         seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2280                         FOURBITS "\n", tmp,
2281                 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2282                 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2283                 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2284                         ? "internal"
2285                         : trx_mode(USB0_TRX_MODE(tmp), 1),
2286                 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2287                 (tmp & HST_IDLE_EN) ? " !host" : "",
2288                 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2289                 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2290         tmp = OTG_SYSCON_2_REG;
2291         seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2292                         " b_ase_brst=%d hmc=%d\n", tmp,
2293                 (tmp & OTG_EN) ? " otg_en" : "",
2294                 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2295                 // much more SRP stuff
2296                 (tmp & SRP_DATA) ? " srp_data" : "",
2297                 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2298                 (tmp & OTG_PADEN) ? " otg_paden" : "",
2299                 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2300                 (tmp & UHOST_EN) ? " uhost_en" : "",
2301                 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2302                 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2303                 B_ASE_BRST(tmp),
2304                 OTG_HMC(tmp));
2305         tmp = OTG_CTRL_REG;
2306         seq_printf(s, "otg_ctrl    %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2307                 (tmp & OTG_ASESSVLD) ? " asess" : "",
2308                 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2309                 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2310                 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2311                 (tmp & OTG_ID) ? " id" : "",
2312                 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2313                 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2314                 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2315                 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2316                 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2317                 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2318                 (tmp & OTG_PULLDOWN) ? " down" : "",
2319                 (tmp & OTG_PULLUP) ? " up" : "",
2320                 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2321                 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2322                 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2323                 (tmp & OTG_PU_ID) ? " pu_id" : ""
2324                 );
2325         tmp = OTG_IRQ_EN_REG;
2326         seq_printf(s, "otg_irq_en  %04x" "\n", tmp);
2327         tmp = OTG_IRQ_SRC_REG;
2328         seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2329         tmp = OTG_OUTCTRL_REG;
2330         seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2331         tmp = OTG_TEST_REG;
2332         seq_printf(s, "otg_test    %04x" "\n", tmp);
2333         return 0;
2334 }
2335
2336 static int proc_udc_show(struct seq_file *s, void *_)
2337 {
2338         u32             tmp;
2339         struct omap_ep  *ep;
2340         unsigned long   flags;
2341
2342         spin_lock_irqsave(&udc->lock, flags);
2343
2344         seq_printf(s, "%s, version: " DRIVER_VERSION
2345 #ifdef  USE_ISO
2346                 " (iso)"
2347 #endif
2348                 "%s\n",
2349                 driver_desc,
2350                 use_dma ?  " (dma)" : "");
2351
2352         tmp = UDC_REV_REG & 0xff;
2353         seq_printf(s,
2354                 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2355                 "hmc %d, transceiver %s\n",
2356                 tmp >> 4, tmp & 0xf,
2357                 fifo_mode,
2358                 udc->driver ? udc->driver->driver.name : "(none)",
2359                 HMC,
2360                 udc->transceiver
2361                         ? udc->transceiver->label
2362                         : ((cpu_is_omap1710() || cpu_is_omap24xx())
2363                                 ? "external" : "(none)"));
2364         if (cpu_class_is_omap1()) {
2365                 seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2366                         __REG16(ULPD_CLOCK_CTRL),
2367                         __REG16(ULPD_SOFT_REQ),
2368                         __REG16(ULPD_STATUS_REQ));
2369         }
2370
2371         /* OTG controller registers */
2372         if (!cpu_is_omap15xx())
2373                 proc_otg_show(s);
2374
2375         tmp = UDC_SYSCON1_REG;
2376         seq_printf(s, "\nsyscon1     %04x" EIGHTBITS "\n", tmp,
2377                 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2378                 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2379                 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2380                 (tmp & UDC_NAK_EN) ? " nak" : "",
2381                 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2382                 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2383                 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2384                 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2385         // syscon2 is write-only
2386
2387         /* UDC controller registers */
2388         if (!(tmp & UDC_PULLUP_EN)) {
2389                 seq_printf(s, "(suspended)\n");
2390                 spin_unlock_irqrestore(&udc->lock, flags);
2391                 return 0;
2392         }
2393
2394         tmp = UDC_DEVSTAT_REG;
2395         seq_printf(s, "devstat     %04x" EIGHTBITS "%s%s\n", tmp,
2396                 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2397                 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2398                 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2399                 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2400                 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2401                 (tmp & UDC_SUS) ? " SUS" : "",
2402                 (tmp & UDC_CFG) ? " CFG" : "",
2403                 (tmp & UDC_ADD) ? " ADD" : "",
2404                 (tmp & UDC_DEF) ? " DEF" : "",
2405                 (tmp & UDC_ATT) ? " ATT" : "");
2406         seq_printf(s, "sof         %04x\n", UDC_SOF_REG);
2407         tmp = UDC_IRQ_EN_REG;
2408         seq_printf(s, "irq_en      %04x" FOURBITS "%s\n", tmp,
2409                 (tmp & UDC_SOF_IE) ? " sof" : "",
2410                 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2411                 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2412                 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2413                 (tmp & UDC_EP0_IE) ? " ep0" : "");
2414         tmp = UDC_IRQ_SRC_REG;
2415         seq_printf(s, "irq_src     %04x" EIGHTBITS "%s%s\n", tmp,
2416                 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2417                 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2418                 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2419                 (tmp & UDC_SOF) ? " sof" : "",
2420                 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2421                 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2422                 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2423                 (tmp & UDC_SETUP) ? " setup" : "",
2424                 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2425                 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2426         if (use_dma) {
2427                 unsigned i;
2428
2429                 tmp = UDC_DMA_IRQ_EN_REG;
2430                 seq_printf(s, "dma_irq_en  %04x%s" EIGHTBITS "\n", tmp,
2431                         (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2432                         (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2433                         (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2434
2435                         (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2436                         (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2437                         (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2438
2439                         (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2440                         (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2441                         (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2442
2443                 tmp = UDC_RXDMA_CFG_REG;
2444                 seq_printf(s, "rxdma_cfg   %04x\n", tmp);
2445                 if (tmp) {
2446                         for (i = 0; i < 3; i++) {
2447                                 if ((tmp & (0x0f << (i * 4))) == 0)
2448                                         continue;
2449                                 seq_printf(s, "rxdma[%d]    %04x\n", i,
2450                                                 UDC_RXDMA_REG(i + 1));
2451                         }
2452                 }
2453                 tmp = UDC_TXDMA_CFG_REG;
2454                 seq_printf(s, "txdma_cfg   %04x\n", tmp);
2455                 if (tmp) {
2456                         for (i = 0; i < 3; i++) {
2457                                 if (!(tmp & (0x0f << (i * 4))))
2458                                         continue;
2459                                 seq_printf(s, "txdma[%d]    %04x\n", i,
2460                                                 UDC_TXDMA_REG(i + 1));
2461                         }
2462                 }
2463         }
2464
2465         tmp = UDC_DEVSTAT_REG;
2466         if (tmp & UDC_ATT) {
2467                 proc_ep_show(s, &udc->ep[0]);
2468                 if (tmp & UDC_ADD) {
2469                         list_for_each_entry (ep, &udc->gadget.ep_list,
2470                                         ep.ep_list) {
2471                                 if (ep->desc)
2472                                         proc_ep_show(s, ep);
2473                         }
2474                 }
2475         }
2476         spin_unlock_irqrestore(&udc->lock, flags);
2477         return 0;
2478 }
2479
2480 static int proc_udc_open(struct inode *inode, struct file *file)
2481 {
2482         return single_open(file, proc_udc_show, NULL);
2483 }
2484
2485 static const struct file_operations proc_ops = {
2486         .open           = proc_udc_open,
2487         .read           = seq_read,
2488         .llseek         = seq_lseek,
2489         .release        = single_release,
2490 };
2491
2492 static void create_proc_file(void)
2493 {
2494         struct proc_dir_entry *pde;
2495
2496         pde = create_proc_entry (proc_filename, 0, NULL);
2497         if (pde)
2498                 pde->proc_fops = &proc_ops;
2499 }
2500
2501 static void remove_proc_file(void)
2502 {
2503         remove_proc_entry(proc_filename, NULL);
2504 }
2505
2506 #else
2507
2508 static inline void create_proc_file(void) {}
2509 static inline void remove_proc_file(void) {}
2510
2511 #endif
2512
2513 /*-------------------------------------------------------------------------*/
2514
2515 /* Before this controller can enumerate, we need to pick an endpoint
2516  * configuration, or "fifo_mode"  That involves allocating 2KB of packet
2517  * buffer space among the endpoints we'll be operating.
2518  *
2519  * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2520  * UDC_SYSCON_1_REG.CFG_LOCK is set can now work.  We won't use that
2521  * capability yet though.
2522  */
2523 static unsigned __init
2524 omap_ep_setup(char *name, u8 addr, u8 type,
2525                 unsigned buf, unsigned maxp, int dbuf)
2526 {
2527         struct omap_ep  *ep;
2528         u16             epn_rxtx = 0;
2529
2530         /* OUT endpoints first, then IN */
2531         ep = &udc->ep[addr & 0xf];
2532         if (addr & USB_DIR_IN)
2533                 ep += 16;
2534
2535         /* in case of ep init table bugs */
2536         BUG_ON(ep->name[0]);
2537
2538         /* chip setup ... bit values are same for IN, OUT */
2539         if (type == USB_ENDPOINT_XFER_ISOC) {
2540                 switch (maxp) {
2541                 case 8:         epn_rxtx = 0 << 12; break;
2542                 case 16:        epn_rxtx = 1 << 12; break;
2543                 case 32:        epn_rxtx = 2 << 12; break;
2544                 case 64:        epn_rxtx = 3 << 12; break;
2545                 case 128:       epn_rxtx = 4 << 12; break;
2546                 case 256:       epn_rxtx = 5 << 12; break;
2547                 case 512:       epn_rxtx = 6 << 12; break;
2548                 default:        BUG();
2549                 }
2550                 epn_rxtx |= UDC_EPN_RX_ISO;
2551                 dbuf = 1;
2552         } else {
2553                 /* double-buffering "not supported" on 15xx,
2554                  * and ignored for PIO-IN on newer chips
2555                  * (for more reliable behavior)
2556                  */
2557                 if (!use_dma || cpu_is_omap15xx() || cpu_is_omap24xx())
2558                         dbuf = 0;
2559
2560                 switch (maxp) {
2561                 case 8:         epn_rxtx = 0 << 12; break;
2562                 case 16:        epn_rxtx = 1 << 12; break;
2563                 case 32:        epn_rxtx = 2 << 12; break;
2564                 case 64:        epn_rxtx = 3 << 12; break;
2565                 default:        BUG();
2566                 }
2567                 if (dbuf && addr)
2568                         epn_rxtx |= UDC_EPN_RX_DB;
2569                 init_timer(&ep->timer);
2570                 ep->timer.function = pio_out_timer;
2571                 ep->timer.data = (unsigned long) ep;
2572         }
2573         if (addr)
2574                 epn_rxtx |= UDC_EPN_RX_VALID;
2575         BUG_ON(buf & 0x07);
2576         epn_rxtx |= buf >> 3;
2577
2578         DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2579                 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2580
2581         if (addr & USB_DIR_IN)
2582                 UDC_EP_TX_REG(addr & 0xf) = epn_rxtx;
2583         else
2584                 UDC_EP_RX_REG(addr) = epn_rxtx;
2585
2586         /* next endpoint's buffer starts after this one's */
2587         buf += maxp;
2588         if (dbuf)
2589                 buf += maxp;
2590         BUG_ON(buf > 2048);
2591
2592         /* set up driver data structures */
2593         BUG_ON(strlen(name) >= sizeof ep->name);
2594         strlcpy(ep->name, name, sizeof ep->name);
2595         INIT_LIST_HEAD(&ep->queue);
2596         INIT_LIST_HEAD(&ep->iso);
2597         ep->bEndpointAddress = addr;
2598         ep->bmAttributes = type;
2599         ep->double_buf = dbuf;
2600         ep->udc = udc;
2601
2602         ep->ep.name = ep->name;
2603         ep->ep.ops = &omap_ep_ops;
2604         ep->ep.maxpacket = ep->maxpacket = maxp;
2605         list_add_tail (&ep->ep.ep_list, &udc->gadget.ep_list);
2606
2607         return buf;
2608 }
2609
2610 static void omap_udc_release(struct device *dev)
2611 {
2612         complete(udc->done);
2613         kfree (udc);
2614         udc = NULL;
2615 }
2616
2617 static int __init
2618 omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
2619 {
2620         unsigned        tmp, buf;
2621
2622         /* abolish any previous hardware state */
2623         UDC_SYSCON1_REG = 0;
2624         UDC_IRQ_EN_REG = 0;
2625         UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2626         UDC_DMA_IRQ_EN_REG = 0;
2627         UDC_RXDMA_CFG_REG = 0;
2628         UDC_TXDMA_CFG_REG = 0;
2629
2630         /* UDC_PULLUP_EN gates the chip clock */
2631         // OTG_SYSCON_1_REG |= DEV_IDLE_EN;
2632
2633         udc = kzalloc(sizeof(*udc), GFP_KERNEL);
2634         if (!udc)
2635                 return -ENOMEM;
2636
2637         spin_lock_init (&udc->lock);
2638
2639         udc->gadget.ops = &omap_gadget_ops;
2640         udc->gadget.ep0 = &udc->ep[0].ep;
2641         INIT_LIST_HEAD(&udc->gadget.ep_list);
2642         INIT_LIST_HEAD(&udc->iso);
2643         udc->gadget.speed = USB_SPEED_UNKNOWN;
2644         udc->gadget.name = driver_name;
2645
2646         device_initialize(&udc->gadget.dev);
2647         strcpy (udc->gadget.dev.bus_id, "gadget");
2648         udc->gadget.dev.release = omap_udc_release;
2649         udc->gadget.dev.parent = &odev->dev;
2650         if (use_dma)
2651                 udc->gadget.dev.dma_mask = odev->dev.dma_mask;
2652
2653         udc->transceiver = xceiv;
2654
2655         /* ep0 is special; put it right after the SETUP buffer */
2656         buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2657                         8 /* after SETUP */, 64 /* maxpacket */, 0);
2658         list_del_init(&udc->ep[0].ep.ep_list);
2659
2660         /* initially disable all non-ep0 endpoints */
2661         for (tmp = 1; tmp < 15; tmp++) {
2662                 UDC_EP_RX_REG(tmp) = 0;
2663                 UDC_EP_TX_REG(tmp) = 0;
2664         }
2665
2666 #define OMAP_BULK_EP(name,addr) \
2667         buf = omap_ep_setup(name "-bulk", addr, \
2668                         USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2669 #define OMAP_INT_EP(name,addr, maxp) \
2670         buf = omap_ep_setup(name "-int", addr, \
2671                         USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2672 #define OMAP_ISO_EP(name,addr, maxp) \
2673         buf = omap_ep_setup(name "-iso", addr, \
2674                         USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2675
2676         switch (fifo_mode) {
2677         case 0:
2678                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2679                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2680                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2681                 break;
2682         case 1:
2683                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2684                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2685                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2686
2687                 OMAP_BULK_EP("ep3in",  USB_DIR_IN  | 3);
2688                 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2689                 OMAP_INT_EP("ep10in",  USB_DIR_IN  | 10, 16);
2690
2691                 OMAP_BULK_EP("ep5in",  USB_DIR_IN  | 5);
2692                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2693                 OMAP_INT_EP("ep11in",  USB_DIR_IN  | 11, 16);
2694
2695                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2696                 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2697                 OMAP_INT_EP("ep12in",  USB_DIR_IN  | 12, 16);
2698
2699                 OMAP_BULK_EP("ep7in",  USB_DIR_IN  | 7);
2700                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2701                 OMAP_INT_EP("ep13in",  USB_DIR_IN  | 13, 16);
2702                 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2703
2704                 OMAP_BULK_EP("ep8in",  USB_DIR_IN  | 8);
2705                 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2706                 OMAP_INT_EP("ep14in",  USB_DIR_IN  | 14, 16);
2707                 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2708
2709                 OMAP_BULK_EP("ep15in",  USB_DIR_IN  | 15);
2710                 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2711
2712                 break;
2713
2714 #ifdef  USE_ISO
2715         case 2:                 /* mixed iso/bulk */
2716                 OMAP_ISO_EP("ep1in",   USB_DIR_IN  | 1, 256);
2717                 OMAP_ISO_EP("ep2out",  USB_DIR_OUT | 2, 256);
2718                 OMAP_ISO_EP("ep3in",   USB_DIR_IN  | 3, 128);
2719                 OMAP_ISO_EP("ep4out",  USB_DIR_OUT | 4, 128);
2720
2721                 OMAP_INT_EP("ep5in",   USB_DIR_IN  | 5, 16);
2722
2723                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2724                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2725                 OMAP_INT_EP("ep8in",   USB_DIR_IN  | 8, 16);
2726                 break;
2727         case 3:                 /* mixed bulk/iso */
2728                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2729                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2730                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2731
2732                 OMAP_BULK_EP("ep4in",  USB_DIR_IN  | 4);
2733                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2734                 OMAP_INT_EP("ep6in",   USB_DIR_IN  | 6, 16);
2735
2736                 OMAP_ISO_EP("ep7in",   USB_DIR_IN  | 7, 256);
2737                 OMAP_ISO_EP("ep8out",  USB_DIR_OUT | 8, 256);
2738                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2739                 break;
2740 #endif
2741
2742         /* add more modes as needed */
2743
2744         default:
2745                 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2746                 return -ENODEV;
2747         }
2748         UDC_SYSCON1_REG = UDC_CFG_LOCK|UDC_SELF_PWR;
2749         INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2750         return 0;
2751 }
2752
2753 static int __init omap_udc_probe(struct platform_device *pdev)
2754 {
2755         int                     status = -ENODEV;
2756         int                     hmc;
2757         struct otg_transceiver  *xceiv = NULL;
2758         const char              *type = NULL;
2759         struct omap_usb_config  *config = pdev->dev.platform_data;
2760         struct clk              *dc_clk;
2761         struct clk              *hhc_clk;
2762
2763         /* NOTE:  "knows" the order of the resources! */
2764         if (!request_mem_region(pdev->resource[0].start,
2765                         pdev->resource[0].end - pdev->resource[0].start + 1,
2766                         driver_name)) {
2767                 DBG("request_mem_region failed\n");
2768                 return -EBUSY;
2769         }
2770
2771         if (cpu_is_omap16xx()) {
2772                 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2773                 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2774                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2775                 /* can't use omap_udc_enable_clock yet */
2776                 clk_enable(dc_clk);
2777                 clk_enable(hhc_clk);
2778                 udelay(100);
2779         }
2780
2781         if (cpu_is_omap24xx()) {
2782                 dc_clk = clk_get(&pdev->dev, "usb_fck");
2783                 hhc_clk = clk_get(&pdev->dev, "usb_l4_ick");
2784                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2785                 /* can't use omap_udc_enable_clock yet */
2786                 clk_enable(dc_clk);
2787                 clk_enable(hhc_clk);
2788                 udelay(100);
2789         }
2790
2791         INFO("OMAP UDC rev %d.%d%s\n",
2792                 UDC_REV_REG >> 4, UDC_REV_REG & 0xf,
2793                 config->otg ? ", Mini-AB" : "");
2794
2795         /* use the mode given to us by board init code */
2796         if (cpu_is_omap15xx()) {
2797                 hmc = HMC_1510;
2798                 type = "(unknown)";
2799
2800                 if (machine_without_vbus_sense()) {
2801                         /* just set up software VBUS detect, and then
2802                          * later rig it so we always report VBUS.
2803                          * FIXME without really sensing VBUS, we can't
2804                          * know when to turn PULLUP_EN on/off; and that
2805                          * means we always "need" the 48MHz clock.
2806                          */
2807                         u32 tmp = FUNC_MUX_CTRL_0_REG;
2808
2809                         FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
2810                         tmp |= VBUS_MODE_1510;
2811                         tmp &= ~VBUS_CTRL_1510;
2812                         FUNC_MUX_CTRL_0_REG = tmp;
2813                 }
2814         } else {
2815                 /* The transceiver may package some GPIO logic or handle
2816                  * loopback and/or transceiverless setup; if we find one,
2817                  * use it.  Except for OTG, we don't _need_ to talk to one;
2818                  * but not having one probably means no VBUS detection.
2819                  */
2820                 xceiv = otg_get_transceiver();
2821                 if (xceiv)
2822                         type = xceiv->label;
2823                 else if (config->otg) {
2824                         DBG("OTG requires external transceiver!\n");
2825                         goto cleanup0;
2826                 }
2827
2828                 hmc = HMC_1610;
2829
2830                 if (cpu_is_omap24xx()) {
2831                         /* this could be transceiverless in one of the
2832                          * "we don't need to know" modes.
2833                          */
2834                         type = "external";
2835                         goto known;
2836                 }
2837
2838                 switch (hmc) {
2839                 case 0:                 /* POWERUP DEFAULT == 0 */
2840                 case 4:
2841                 case 12:
2842                 case 20:
2843                         if (!cpu_is_omap1710()) {
2844                                 type = "integrated";
2845                                 break;
2846                         }
2847                         /* FALL THROUGH */
2848                 case 3:
2849                 case 11:
2850                 case 16:
2851                 case 19:
2852                 case 25:
2853                         if (!xceiv) {
2854                                 DBG("external transceiver not registered!\n");
2855                                 type = "unknown";
2856                         }
2857                         break;
2858                 case 21:                        /* internal loopback */
2859                         type = "loopback";
2860                         break;
2861                 case 14:                        /* transceiverless */
2862                         if (cpu_is_omap1710())
2863                                 goto bad_on_1710;
2864                         /* FALL THROUGH */
2865                 case 13:
2866                 case 15:
2867                         type = "no";
2868                         break;
2869
2870                 default:
2871 bad_on_1710:
2872                         ERR("unrecognized UDC HMC mode %d\n", hmc);
2873                         goto cleanup0;
2874                 }
2875         }
2876 known:
2877         INFO("hmc mode %d, %s transceiver\n", hmc, type);
2878
2879         /* a "gadget" abstracts/virtualizes the controller */
2880         status = omap_udc_setup(pdev, xceiv);
2881         if (status) {
2882                 goto cleanup0;
2883         }
2884         xceiv = NULL;
2885         // "udc" is now valid
2886         pullup_disable(udc);
2887 #if     defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2888         udc->gadget.is_otg = (config->otg != 0);
2889 #endif
2890
2891         /* starting with omap1710 es2.0, clear toggle is a separate bit */
2892         if (UDC_REV_REG >= 0x61)
2893                 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2894         else
2895                 udc->clr_halt = UDC_RESET_EP;
2896
2897         /* USB general purpose IRQ:  ep0, state changes, dma, etc */
2898         status = request_irq(pdev->resource[1].start, omap_udc_irq,
2899                         IRQF_SAMPLE_RANDOM, driver_name, udc);
2900         if (status != 0) {
2901                 ERR("can't get irq %d, err %d\n",
2902                         (int) pdev->resource[1].start, status);
2903                 goto cleanup1;
2904         }
2905
2906         /* USB "non-iso" IRQ (PIO for all but ep0) */
2907         status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
2908                         IRQF_SAMPLE_RANDOM, "omap_udc pio", udc);
2909         if (status != 0) {
2910                 ERR("can't get irq %d, err %d\n",
2911                         (int) pdev->resource[2].start, status);
2912                 goto cleanup2;
2913         }
2914 #ifdef  USE_ISO
2915         status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
2916                         IRQF_DISABLED, "omap_udc iso", udc);
2917         if (status != 0) {
2918                 ERR("can't get irq %d, err %d\n",
2919                         (int) pdev->resource[3].start, status);
2920                 goto cleanup3;
2921         }
2922 #endif
2923         if (cpu_is_omap16xx()) {
2924                 udc->dc_clk = dc_clk;
2925                 udc->hhc_clk = hhc_clk;
2926                 clk_disable(hhc_clk);
2927                 clk_disable(dc_clk);
2928         }
2929
2930         if (cpu_is_omap24xx()) {
2931                 udc->dc_clk = dc_clk;
2932                 udc->hhc_clk = hhc_clk;
2933                 /* FIXME OMAP2 don't release hhc & dc clock */
2934 #if 0
2935                 clk_disable(hhc_clk);
2936                 clk_disable(dc_clk);
2937 #endif
2938         }
2939
2940         create_proc_file();
2941         status = device_add(&udc->gadget.dev);
2942         if (!status)
2943                 return status;
2944         /* If fail, fall through */
2945 #ifdef  USE_ISO
2946 cleanup3:
2947         free_irq(pdev->resource[2].start, udc);
2948 #endif
2949
2950 cleanup2:
2951         free_irq(pdev->resource[1].start, udc);
2952
2953 cleanup1:
2954         kfree (udc);
2955         udc = NULL;
2956
2957 cleanup0:
2958         if (xceiv)
2959                 put_device(xceiv->dev);
2960
2961         if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
2962                 clk_disable(hhc_clk);
2963                 clk_disable(dc_clk);
2964                 clk_put(hhc_clk);
2965                 clk_put(dc_clk);
2966         }
2967
2968         release_mem_region(pdev->resource[0].start,
2969                         pdev->resource[0].end - pdev->resource[0].start + 1);
2970
2971         return status;
2972 }
2973
2974 static int __exit omap_udc_remove(struct platform_device *pdev)
2975 {
2976         DECLARE_COMPLETION_ONSTACK(done);
2977
2978         if (!udc)
2979                 return -ENODEV;
2980         if (udc->driver)
2981                 return -EBUSY;
2982
2983         udc->done = &done;
2984
2985         pullup_disable(udc);
2986         if (udc->transceiver) {
2987                 put_device(udc->transceiver->dev);
2988                 udc->transceiver = NULL;
2989         }
2990         UDC_SYSCON1_REG = 0;
2991
2992         remove_proc_file();
2993
2994 #ifdef  USE_ISO
2995         free_irq(pdev->resource[3].start, udc);
2996 #endif
2997         free_irq(pdev->resource[2].start, udc);
2998         free_irq(pdev->resource[1].start, udc);
2999
3000         if (udc->dc_clk) {
3001                 if (udc->clk_requested)
3002                         omap_udc_enable_clock(0);
3003                 clk_put(udc->hhc_clk);
3004                 clk_put(udc->dc_clk);
3005         }
3006
3007         release_mem_region(pdev->resource[0].start,
3008                         pdev->resource[0].end - pdev->resource[0].start + 1);
3009
3010         device_unregister(&udc->gadget.dev);
3011         wait_for_completion(&done);
3012
3013         return 0;
3014 }
3015
3016 /* suspend/resume/wakeup from sysfs (echo > power/state) or when the
3017  * system is forced into deep sleep
3018  *
3019  * REVISIT we should probably reject suspend requests when there's a host
3020  * session active, rather than disconnecting, at least on boards that can
3021  * report VBUS irqs (UDC_DEVSTAT_REG.UDC_ATT).  And in any case, we need to
3022  * make host resumes and VBUS detection trigger OMAP wakeup events; that
3023  * may involve talking to an external transceiver (e.g. isp1301).
3024  */
3025
3026 static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
3027 {
3028         u32     devstat;
3029
3030         devstat = UDC_DEVSTAT_REG;
3031
3032         /* we're requesting 48 MHz clock if the pullup is enabled
3033          * (== we're attached to the host) and we're not suspended,
3034          * which would prevent entry to deep sleep...
3035          */
3036         if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
3037                 WARN("session active; suspend requires disconnect\n");
3038                 omap_pullup(&udc->gadget, 0);
3039         }
3040
3041         udc->gadget.dev.power.power_state = PMSG_SUSPEND;
3042         udc->gadget.dev.parent->power.power_state = PMSG_SUSPEND;
3043         return 0;
3044 }
3045
3046 static int omap_udc_resume(struct platform_device *dev)
3047 {
3048         DBG("resume + wakeup/SRP\n");
3049         omap_pullup(&udc->gadget, 1);
3050
3051         /* maybe the host would enumerate us if we nudged it */
3052         msleep(100);
3053         return omap_wakeup(&udc->gadget);
3054 }
3055
3056 /*-------------------------------------------------------------------------*/
3057
3058 static struct platform_driver udc_driver = {
3059         .probe          = omap_udc_probe,
3060         .remove         = __exit_p(omap_udc_remove),
3061         .suspend        = omap_udc_suspend,
3062         .resume         = omap_udc_resume,
3063         .driver         = {
3064                 .owner  = THIS_MODULE,
3065                 .name   = (char *) driver_name,
3066         },
3067 };
3068
3069 static int __init udc_init(void)
3070 {
3071         INFO("%s, version: " DRIVER_VERSION
3072 #ifdef  USE_ISO
3073                 " (iso)"
3074 #endif
3075                 "%s\n", driver_desc,
3076                 use_dma ?  " (dma)" : "");
3077         return platform_driver_register(&udc_driver);
3078 }
3079 module_init(udc_init);
3080
3081 static void __exit udc_exit(void)
3082 {
3083         platform_driver_unregister(&udc_driver);
3084 }
3085 module_exit(udc_exit);
3086
3087 MODULE_DESCRIPTION(DRIVER_DESC);
3088 MODULE_LICENSE("GPL");
3089