2 * This file contains miscellaneous low-level functions.
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
7 * Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com)
8 * PPC64 updates by Dave Engebretsen (engebret@us.ibm.com)
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
17 #include <linux/sys.h>
18 #include <asm/unistd.h>
19 #include <asm/errno.h>
20 #include <asm/processor.h>
22 #include <asm/cache.h>
23 #include <asm/ppc_asm.h>
24 #include <asm/asm-offsets.h>
25 #include <asm/cputable.h>
26 #include <asm/thread_info.h>
42 #ifdef CONFIG_IRQSTACKS
43 _GLOBAL(call_do_softirq)
46 stdu r1,THREAD_SIZE-112(r3)
54 _GLOBAL(call___do_IRQ)
57 stdu r1,THREAD_SIZE-112(r5)
64 #endif /* CONFIG_IRQSTACKS */
68 .tc ppc64_caches[TC],ppc64_caches
72 * Write any modified data cache blocks out to memory
73 * and invalidate the corresponding instruction cache blocks.
75 * flush_icache_range(unsigned long start, unsigned long stop)
77 * flush all bytes from start through stop-1 inclusive
80 _KPROBE(__flush_icache_range)
83 * Flush the data cache to memory
85 * Different systems have different cache line sizes
86 * and in some cases i-cache and d-cache line sizes differ from
89 ld r10,PPC64_CACHES@toc(r2)
90 lwz r7,DCACHEL1LINESIZE(r10)/* Get cache line size */
92 andc r6,r3,r5 /* round low to line bdy */
93 subf r8,r6,r4 /* compute length */
94 add r8,r8,r5 /* ensure we get enough */
95 lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of cache line size */
96 srw. r8,r8,r9 /* compute line count */
97 beqlr /* nothing to do? */
104 /* Now invalidate the instruction cache */
106 lwz r7,ICACHEL1LINESIZE(r10) /* Get Icache line size */
108 andc r6,r3,r5 /* round low to line bdy */
109 subf r8,r6,r4 /* compute length */
111 lwz r9,ICACHEL1LOGLINESIZE(r10) /* Get log-2 of Icache line size */
112 srw. r8,r8,r9 /* compute line count */
113 beqlr /* nothing to do? */
122 * Like above, but only do the D-cache.
124 * flush_dcache_range(unsigned long start, unsigned long stop)
126 * flush all bytes from start to stop-1 inclusive
128 _GLOBAL(flush_dcache_range)
131 * Flush the data cache to memory
133 * Different systems have different cache line sizes
135 ld r10,PPC64_CACHES@toc(r2)
136 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
138 andc r6,r3,r5 /* round low to line bdy */
139 subf r8,r6,r4 /* compute length */
140 add r8,r8,r5 /* ensure we get enough */
141 lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */
142 srw. r8,r8,r9 /* compute line count */
143 beqlr /* nothing to do? */
152 * Like above, but works on non-mapped physical addresses.
153 * Use only for non-LPAR setups ! It also assumes real mode
154 * is cacheable. Used for flushing out the DART before using
155 * it as uncacheable memory
157 * flush_dcache_phys_range(unsigned long start, unsigned long stop)
159 * flush all bytes from start to stop-1 inclusive
161 _GLOBAL(flush_dcache_phys_range)
162 ld r10,PPC64_CACHES@toc(r2)
163 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
165 andc r6,r3,r5 /* round low to line bdy */
166 subf r8,r6,r4 /* compute length */
167 add r8,r8,r5 /* ensure we get enough */
168 lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */
169 srw. r8,r8,r9 /* compute line count */
170 beqlr /* nothing to do? */
171 mfmsr r5 /* Disable MMU Data Relocation */
184 mtmsr r5 /* Re-enable MMU Data Relocation */
189 _GLOBAL(flush_inval_dcache_range)
190 ld r10,PPC64_CACHES@toc(r2)
191 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
193 andc r6,r3,r5 /* round low to line bdy */
194 subf r8,r6,r4 /* compute length */
195 add r8,r8,r5 /* ensure we get enough */
196 lwz r9,DCACHEL1LOGLINESIZE(r10)/* Get log-2 of dcache line size */
197 srw. r8,r8,r9 /* compute line count */
198 beqlr /* nothing to do? */
211 * Flush a particular page from the data cache to RAM.
212 * Note: this is necessary because the instruction cache does *not*
213 * snoop from the data cache.
215 * void __flush_dcache_icache(void *page)
217 _GLOBAL(__flush_dcache_icache)
219 * Flush the data cache to memory
221 * Different systems have different cache line sizes
224 /* Flush the dcache */
225 ld r7,PPC64_CACHES@toc(r2)
226 clrrdi r3,r3,PAGE_SHIFT /* Page align */
227 lwz r4,DCACHEL1LINESPERPAGE(r7) /* Get # dcache lines per page */
228 lwz r5,DCACHEL1LINESIZE(r7) /* Get dcache line size */
236 /* Now invalidate the icache */
238 lwz r4,ICACHEL1LINESPERPAGE(r7) /* Get # icache lines per page */
239 lwz r5,ICACHEL1LINESIZE(r7) /* Get icache line size */
248 * identify_cpu and calls setup_cpu
249 * In: r3 = base of the cpu_specs array
250 * r4 = address of cur_cpu_spec
251 * r5 = relocation offset
253 _GLOBAL(identify_cpu)
256 lwz r8,CPU_SPEC_PVR_MASK(r3)
258 lwz r9,CPU_SPEC_PVR_VALUE(r3)
261 addi r3,r3,CPU_SPEC_ENTRY_SIZE
266 ld r4,CPU_SPEC_SETUP(r3)
273 /* Calling convention for cpu setup is r3=offset, r4=cur_cpu_spec */
279 * do_cpu_ftr_fixups - goes through the list of CPU feature fixups
280 * and writes nop's over sections of code that don't apply for this cpu.
281 * r3 = data offset (not changed)
283 _GLOBAL(do_cpu_ftr_fixups)
284 /* Get CPU 0 features */
285 LOAD_REG_IMMEDIATE(r6,cur_cpu_spec)
289 ld r4,CPU_SPEC_FEATURES(r4)
290 /* Get the fixup table */
291 LOAD_REG_IMMEDIATE(r6,__start___ftr_fixup)
293 LOAD_REG_IMMEDIATE(r7,__stop___ftr_fixup)
299 ld r8,-32(r6) /* mask */
301 ld r9,-24(r6) /* value */
304 ld r8,-16(r6) /* section begin */
305 ld r9,-8(r6) /* section end */
308 /* write nops over the section of code */
309 /* todo: if large section, add a branch at the start of it */
313 lis r0,0x60000000@h /* nop */
315 andi. r10,r4,CPU_FTR_SPLIT_ID_CACHE@l
317 dcbst 0,r8 /* suboptimal, but simpler */
322 sync /* additional sync needed on g4 */
326 #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE)
328 * Do an IO access in real mode
359 * Do an IO access in real mode
388 #endif /* defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) */
390 #ifdef CONFIG_CPU_FREQ_PMAC64
392 * SCOM access functions for 970 (FX only for now)
394 * unsigned long scom970_read(unsigned int address);
395 * void scom970_write(unsigned int address, unsigned long value);
397 * The address passed in is the 24 bits register address. This code
398 * is 970 specific and will not check the status bits, so you should
399 * know what you are doing.
401 _GLOBAL(scom970_read)
408 /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
409 * (including parity). On current CPUs they must be 0'd,
410 * and finally or in RW bit
415 /* do the actual scom read */
424 /* XXX: fixup result on some buggy 970's (ouch ! we lost a bit, bah
425 * that's the best we can do). Not implemented yet as we don't use
426 * the scom on any of the bogus CPUs yet, but may have to be done
430 /* restore interrupts */
435 _GLOBAL(scom970_write)
442 /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
443 * (including parity). On current CPUs they must be 0'd.
449 mtspr SPRN_SCOMD,r4 /* write data */
451 mtspr SPRN_SCOMC,r3 /* write command */
456 /* restore interrupts */
459 #endif /* CONFIG_CPU_FREQ_PMAC64 */
463 * Create a kernel thread
464 * kernel_thread(fn, arg, flags)
466 _GLOBAL(kernel_thread)
469 stdu r1,-STACK_FRAME_OVERHEAD(r1)
472 ori r3,r5,CLONE_VM /* flags */
473 oris r3,r3,(CLONE_UNTRACED>>16)
474 li r4,0 /* new sp (unused) */
477 cmpdi 0,r3,0 /* parent or child? */
478 bne 1f /* return if parent */
480 stdu r0,-STACK_FRAME_OVERHEAD(r1)
483 mtlr r29 /* fn addr in lr */
484 mr r3,r30 /* load arg and call fn */
486 li r0,__NR_exit /* exit after child exits */
489 1: addi r1,r1,STACK_FRAME_OVERHEAD
495 * disable_kernel_fp()
498 _GLOBAL(disable_kernel_fp)
500 rldicl r0,r3,(63-MSR_FP_LG),1
501 rldicl r3,r0,(MSR_FP_LG+1),0
502 mtmsrd r3 /* disable use of fpu now */
506 #ifdef CONFIG_ALTIVEC
508 #if 0 /* this has no callers for now */
510 * disable_kernel_altivec()
513 _GLOBAL(disable_kernel_altivec)
515 rldicl r0,r3,(63-MSR_VEC_LG),1
516 rldicl r3,r0,(MSR_VEC_LG+1),0
517 mtmsrd r3 /* disable use of VMX now */
523 * giveup_altivec(tsk)
524 * Disable VMX for the task given as the argument,
525 * and save the vector registers in its thread_struct.
526 * Enables the VMX for use in the kernel on return.
528 _GLOBAL(giveup_altivec)
531 mtmsrd r5 /* enable use of VMX now */
534 beqlr- /* if no previous owner, done */
535 addi r3,r3,THREAD /* want THREAD of task */
543 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
545 andc r4,r4,r3 /* disable FP for previous task */
546 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
550 ld r4,last_task_used_altivec@got(r2)
552 #endif /* CONFIG_SMP */
555 #endif /* CONFIG_ALTIVEC */
564 /* kexec_wait(phys_cpu)
566 * wait for the flag to change, indicating this kernel is going away but
567 * the slave code for the next one is at addresses 0 to 100.
569 * This is used by all slaves.
571 * Physical (hardware) cpu id should be in r3.
576 addi r5,r5,kexec_flag-1b
579 #ifdef CONFIG_KEXEC /* use no memory without kexec */
586 /* this can be in text because we won't change it until we are
587 * running in real anyways
595 /* kexec_smp_wait(void)
597 * call with interrupts off
598 * note: this is a terminal routine, it does not save lr
600 * get phys id from paca
601 * set paca id to -1 to say we got here
602 * switch to real mode
603 * join other cpus in kexec_wait(phys_id)
605 _GLOBAL(kexec_smp_wait)
606 lhz r3,PACAHWCPUID(r13)
608 sth r4,PACAHWCPUID(r13) /* let others know we left */
613 * switch to real mode (turn mmu off)
614 * we use the early kernel trick that the hardware ignores bits
615 * 0 and 1 (big endian) of the effective address in real mode
617 * don't overwrite r3 here, it is live for kexec_wait above.
619 real_mode: /* assume normal blr return */
622 mflr r11 /* return address to SRR0 */
634 * kexec_sequence(newstack, start, image, control, clear_all())
636 * does the grungy work with stack switching and real mode switches
637 * also does simple calls to other code
640 _GLOBAL(kexec_sequence)
644 /* switch stacks to newstack -- &kexec_stack.stack */
645 stdu r1,THREAD_SIZE-112(r3)
651 /* save regs for local vars on new stack.
652 * yes, we won't go back, but ...
664 /* save args into preserved regs */
665 mr r31,r3 /* newstack (both) */
666 mr r30,r4 /* start (real) */
667 mr r29,r5 /* image (virt) */
668 mr r28,r6 /* control, unused */
669 mr r27,r7 /* clear_all() fn desc */
670 mr r26,r8 /* spare */
671 lhz r25,PACAHWCPUID(r13) /* get our phys cpu from paca */
673 /* disable interrupts, we are overwriting kernel data next */
678 /* copy dest pages, flush whole dest image */
680 bl .kexec_copy_flush /* (image) */
685 /* clear out hardware hash page table and tlb */
686 ld r5,0(r27) /* deref function descriptor */
688 bctrl /* ppc_md.hash_clear_all(void); */
691 * kexec image calling is:
692 * the first 0x100 bytes of the entry point are copied to 0
694 * all slaves branch to slave = 0x60 (absolute)
695 * slave(phys_cpu_id);
697 * master goes to start = entry point
698 * start(phys_cpu_id, start, 0);
701 * a wrapper is needed to call existing kernels, here is an approximate
702 * description of one method:
705 * start will be near the boot_block (maybe 0x100 bytes before it?)
706 * it will have a 0x60, which will b to boot_block, where it will wait
707 * and 0 will store phys into struct boot-block and load r3 from there,
708 * copy kernel 0-0x100 and tell slaves to back down to 0x60 again
711 * boot block will have all cpus scanning device tree to see if they
712 * are the boot cpu ?????
713 * other device tree differences (prop sizes, va vs pa, etc)...
716 /* copy 0x100 bytes starting at start to 0 */
721 bl .copy_and_flush /* (dest, src, copy limit, start offset) */
722 1: /* assume normal blr return */
724 /* release other cpus to the new kernel secondary start at 0x60 */
727 stw r6,kexec_flag-1b(5)
728 mr r3,r25 # my phys cpu
729 mr r4,r30 # start, aka phys mem offset
732 blr /* image->start(physid, image->start, 0); */
733 #endif /* CONFIG_KEXEC */