2 * Intel IXP4xx Ethernet driver for Linux
4 * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
10 * Ethernet port config (0x00 is not present on IXP42X):
12 * logical port 0x00 0x10 0x20
13 * NPE 0 (NPE-A) 1 (NPE-B) 2 (NPE-C)
14 * physical PortId 2 0 1
16 * RX-free queue 26 27 28
17 * TX-done queue is always 31, per-port RX and TX-ready queues are configurable
21 * bits 0 -> 1 - NPE ID (RX and TX-done)
22 * bits 0 -> 2 - priority (TX, per 802.1D)
23 * bits 3 -> 4 - port ID (user-set?)
24 * bits 5 -> 31 - physical descriptor address
27 #include <linux/delay.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/dmapool.h>
30 #include <linux/etherdevice.h>
32 #include <linux/kernel.h>
33 #include <linux/mii.h>
34 #include <linux/platform_device.h>
36 #include <mach/qmgr.h>
38 #define DEBUG_QUEUES 0
42 #define DEBUG_PKT_BYTES 0
46 #define DRV_NAME "ixp4xx_eth"
50 #define RX_DESCS 64 /* also length of all RX queues */
51 #define TX_DESCS 16 /* also length of all TX queues */
52 #define TXDONE_QUEUE_LEN 64 /* dwords */
54 #define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
55 #define REGS_SIZE 0x1000
56 #define MAX_MRU 1536 /* 0x600 */
57 #define RX_BUFF_SIZE ALIGN((NET_IP_ALIGN) + MAX_MRU, 4)
59 #define NAPI_WEIGHT 16
60 #define MDIO_INTERVAL (3 * HZ)
61 #define MAX_MDIO_RETRIES 100 /* microseconds, typically 30 cycles */
62 #define MAX_MII_RESET_RETRIES 100 /* mdio_read() cycles, typically 4 */
63 #define MAX_CLOSE_WAIT 1000 /* microseconds, typically 2-3 cycles */
65 #define NPE_ID(port_id) ((port_id) >> 4)
66 #define PHYSICAL_ID(port_id) ((NPE_ID(port_id) + 2) % 3)
67 #define TX_QUEUE(port_id) (NPE_ID(port_id) + 23)
68 #define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26)
69 #define TXDONE_QUEUE 31
71 /* TX Control Registers */
72 #define TX_CNTRL0_TX_EN 0x01
73 #define TX_CNTRL0_HALFDUPLEX 0x02
74 #define TX_CNTRL0_RETRY 0x04
75 #define TX_CNTRL0_PAD_EN 0x08
76 #define TX_CNTRL0_APPEND_FCS 0x10
77 #define TX_CNTRL0_2DEFER 0x20
78 #define TX_CNTRL0_RMII 0x40 /* reduced MII */
79 #define TX_CNTRL1_RETRIES 0x0F /* 4 bits */
81 /* RX Control Registers */
82 #define RX_CNTRL0_RX_EN 0x01
83 #define RX_CNTRL0_PADSTRIP_EN 0x02
84 #define RX_CNTRL0_SEND_FCS 0x04
85 #define RX_CNTRL0_PAUSE_EN 0x08
86 #define RX_CNTRL0_LOOP_EN 0x10
87 #define RX_CNTRL0_ADDR_FLTR_EN 0x20
88 #define RX_CNTRL0_RX_RUNT_EN 0x40
89 #define RX_CNTRL0_BCAST_DIS 0x80
90 #define RX_CNTRL1_DEFER_EN 0x01
92 /* Core Control Register */
93 #define CORE_RESET 0x01
94 #define CORE_RX_FIFO_FLUSH 0x02
95 #define CORE_TX_FIFO_FLUSH 0x04
96 #define CORE_SEND_JAM 0x08
97 #define CORE_MDC_EN 0x10 /* MDIO using NPE-B ETH-0 only */
99 #define DEFAULT_TX_CNTRL0 (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY | \
100 TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \
102 #define DEFAULT_RX_CNTRL0 RX_CNTRL0_RX_EN
103 #define DEFAULT_CORE_CNTRL CORE_MDC_EN
106 /* NPE message codes */
107 #define NPE_GETSTATUS 0x00
108 #define NPE_EDB_SETPORTADDRESS 0x01
109 #define NPE_EDB_GETMACADDRESSDATABASE 0x02
110 #define NPE_EDB_SETMACADDRESSSDATABASE 0x03
111 #define NPE_GETSTATS 0x04
112 #define NPE_RESETSTATS 0x05
113 #define NPE_SETMAXFRAMELENGTHS 0x06
114 #define NPE_VLAN_SETRXTAGMODE 0x07
115 #define NPE_VLAN_SETDEFAULTRXVID 0x08
116 #define NPE_VLAN_SETPORTVLANTABLEENTRY 0x09
117 #define NPE_VLAN_SETPORTVLANTABLERANGE 0x0A
118 #define NPE_VLAN_SETRXQOSENTRY 0x0B
119 #define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C
120 #define NPE_STP_SETBLOCKINGSTATE 0x0D
121 #define NPE_FW_SETFIREWALLMODE 0x0E
122 #define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F
123 #define NPE_PC_SETAPMACTABLE 0x11
124 #define NPE_SETLOOPBACK_MODE 0x12
125 #define NPE_PC_SETBSSIDTABLE 0x13
126 #define NPE_ADDRESS_FILTER_CONFIG 0x14
127 #define NPE_APPENDFCSCONFIG 0x15
128 #define NPE_NOTIFY_MAC_RECOVERY_DONE 0x16
129 #define NPE_MAC_RECOVERY_START 0x17
133 typedef struct sk_buff buffer_t;
134 #define free_buffer dev_kfree_skb
135 #define free_buffer_irq dev_kfree_skb_irq
137 typedef void buffer_t;
138 #define free_buffer kfree
139 #define free_buffer_irq kfree
143 u32 tx_control[2], __res1[2]; /* 000 */
144 u32 rx_control[2], __res2[2]; /* 010 */
145 u32 random_seed, __res3[3]; /* 020 */
146 u32 partial_empty_threshold, __res4; /* 030 */
147 u32 partial_full_threshold, __res5; /* 038 */
148 u32 tx_start_bytes, __res6[3]; /* 040 */
149 u32 tx_deferral, rx_deferral, __res7[2];/* 050 */
150 u32 tx_2part_deferral[2], __res8[2]; /* 060 */
151 u32 slot_time, __res9[3]; /* 070 */
152 u32 mdio_command[4]; /* 080 */
153 u32 mdio_status[4]; /* 090 */
154 u32 mcast_mask[6], __res10[2]; /* 0A0 */
155 u32 mcast_addr[6], __res11[2]; /* 0C0 */
156 u32 int_clock_threshold, __res12[3]; /* 0E0 */
157 u32 hw_addr[6], __res13[61]; /* 0F0 */
158 u32 core_control; /* 1FC */
162 struct resource *mem_res;
163 struct eth_regs __iomem *regs;
165 struct net_device *netdev;
166 struct napi_struct napi;
167 struct mii_if_info mii;
168 struct delayed_work mdio_thread;
169 struct eth_plat_info *plat;
170 buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
171 struct desc *desc_tab; /* coherent */
173 int id; /* logical port ID */
177 /* NPE message structure */
180 u8 cmd, eth_id, byte2, byte3;
181 u8 byte4, byte5, byte6, byte7;
183 u8 byte3, byte2, eth_id, cmd;
184 u8 byte7, byte6, byte5, byte4;
188 /* Ethernet packet descriptor */
190 u32 next; /* pointer to next buffer, unused */
193 u16 buf_len; /* buffer length */
194 u16 pkt_len; /* packet length */
195 u32 data; /* pointer to data buffer in RAM */
203 u16 pkt_len; /* packet length */
204 u16 buf_len; /* buffer length */
205 u32 data; /* pointer to data buffer in RAM */
215 u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3;
216 u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1;
217 u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5;
219 u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0;
220 u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4;
221 u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2;
226 #define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
227 (n) * sizeof(struct desc))
228 #define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
230 #define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
231 ((n) + RX_DESCS) * sizeof(struct desc))
232 #define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
235 static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
238 for (i = 0; i < cnt; i++)
239 dest[i] = swab32(src[i]);
243 static spinlock_t mdio_lock;
244 static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */
245 static int ports_open;
246 static struct port *npe_port_tab[MAX_NPES];
247 static struct dma_pool *dma_pool;
250 static u16 mdio_cmd(struct net_device *dev, int phy_id, int location,
255 if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) {
256 printk(KERN_ERR "%s: MII not ready to transmit\n", dev->name);
261 __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]);
262 __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]);
264 __raw_writel(((phy_id << 5) | location) & 0xFF,
265 &mdio_regs->mdio_command[2]);
266 __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */,
267 &mdio_regs->mdio_command[3]);
269 while ((cycles < MAX_MDIO_RETRIES) &&
270 (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) {
275 if (cycles == MAX_MDIO_RETRIES) {
276 printk(KERN_ERR "%s: MII write failed\n", dev->name);
281 printk(KERN_DEBUG "%s: mdio_cmd() took %i cycles\n", dev->name,
288 if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) {
289 printk(KERN_ERR "%s: MII read failed\n", dev->name);
293 return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) |
294 (__raw_readl(&mdio_regs->mdio_status[1]) << 8);
297 static int mdio_read(struct net_device *dev, int phy_id, int location)
302 spin_lock_irqsave(&mdio_lock, flags);
303 val = mdio_cmd(dev, phy_id, location, 0, 0);
304 spin_unlock_irqrestore(&mdio_lock, flags);
308 static void mdio_write(struct net_device *dev, int phy_id, int location,
313 spin_lock_irqsave(&mdio_lock, flags);
314 mdio_cmd(dev, phy_id, location, 1, val);
315 spin_unlock_irqrestore(&mdio_lock, flags);
318 static void phy_reset(struct net_device *dev, int phy_id)
320 struct port *port = netdev_priv(dev);
323 mdio_write(dev, phy_id, MII_BMCR, port->mii_bmcr | BMCR_RESET);
325 while (cycles < MAX_MII_RESET_RETRIES) {
326 if (!(mdio_read(dev, phy_id, MII_BMCR) & BMCR_RESET)) {
328 printk(KERN_DEBUG "%s: phy_reset() took %i cycles\n",
337 printk(KERN_ERR "%s: MII reset failed\n", dev->name);
340 static void eth_set_duplex(struct port *port)
342 if (port->mii.full_duplex)
343 __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX,
344 &port->regs->tx_control[0]);
346 __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX,
347 &port->regs->tx_control[0]);
351 static void phy_check_media(struct port *port, int init)
353 if (mii_check_media(&port->mii, 1, init))
354 eth_set_duplex(port);
355 if (port->mii.force_media) { /* mii_check_media() doesn't work */
356 struct net_device *dev = port->netdev;
357 int cur_link = mii_link_ok(&port->mii);
358 int prev_link = netif_carrier_ok(dev);
360 if (!prev_link && cur_link) {
361 printk(KERN_INFO "%s: link up\n", dev->name);
362 netif_carrier_on(dev);
363 } else if (prev_link && !cur_link) {
364 printk(KERN_INFO "%s: link down\n", dev->name);
365 netif_carrier_off(dev);
371 static void mdio_thread(struct work_struct *work)
373 struct port *port = container_of(work, struct port, mdio_thread.work);
375 phy_check_media(port, 0);
376 schedule_delayed_work(&port->mdio_thread, MDIO_INTERVAL);
380 static inline void debug_pkt(struct net_device *dev, const char *func,
386 printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
387 for (i = 0; i < len; i++) {
388 if (i >= DEBUG_PKT_BYTES)
391 ((i == 6) || (i == 12) || (i >= 14)) ? " " : "",
399 static inline void debug_desc(u32 phys, struct desc *desc)
402 printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X"
403 " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n",
404 phys, desc->next, desc->buf_len, desc->pkt_len,
405 desc->data, desc->dest_id, desc->src_id, desc->flags,
406 desc->qos, desc->padlen, desc->vlan_tci,
407 desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2,
408 desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5,
409 desc->src_mac_0, desc->src_mac_1, desc->src_mac_2,
410 desc->src_mac_3, desc->src_mac_4, desc->src_mac_5);
414 static inline void debug_queue(unsigned int queue, int is_get, u32 phys)
421 { TX_QUEUE(0x10), "TX#0 " },
422 { TX_QUEUE(0x20), "TX#1 " },
423 { TX_QUEUE(0x00), "TX#2 " },
424 { RXFREE_QUEUE(0x10), "RX-free#0 " },
425 { RXFREE_QUEUE(0x20), "RX-free#1 " },
426 { RXFREE_QUEUE(0x00), "RX-free#2 " },
427 { TXDONE_QUEUE, "TX-done " },
431 for (i = 0; i < ARRAY_SIZE(names); i++)
432 if (names[i].queue == queue)
435 printk(KERN_DEBUG "Queue %i %s%s %X\n", queue,
436 i < ARRAY_SIZE(names) ? names[i].name : "",
437 is_get ? "->" : "<-", phys);
441 static inline u32 queue_get_entry(unsigned int queue)
443 u32 phys = qmgr_get_entry(queue);
444 debug_queue(queue, 1, phys);
448 static inline int queue_get_desc(unsigned int queue, struct port *port,
451 u32 phys, tab_phys, n_desc;
454 if (!(phys = queue_get_entry(queue)))
457 phys &= ~0x1F; /* mask out non-address bits */
458 tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
459 tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
460 n_desc = (phys - tab_phys) / sizeof(struct desc);
461 BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
462 debug_desc(phys, &tab[n_desc]);
463 BUG_ON(tab[n_desc].next);
467 static inline void queue_put_desc(unsigned int queue, u32 phys,
470 debug_queue(queue, 0, phys);
471 debug_desc(phys, desc);
473 qmgr_put_entry(queue, phys);
474 BUG_ON(qmgr_stat_overflow(queue));
478 static inline void dma_unmap_tx(struct port *port, struct desc *desc)
481 dma_unmap_single(&port->netdev->dev, desc->data,
482 desc->buf_len, DMA_TO_DEVICE);
484 dma_unmap_single(&port->netdev->dev, desc->data & ~3,
485 ALIGN((desc->data & 3) + desc->buf_len, 4),
491 static void eth_rx_irq(void *pdev)
493 struct net_device *dev = pdev;
494 struct port *port = netdev_priv(dev);
497 printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name);
499 qmgr_disable_irq(port->plat->rxq);
500 netif_rx_schedule(dev, &port->napi);
503 static int eth_poll(struct napi_struct *napi, int budget)
505 struct port *port = container_of(napi, struct port, napi);
506 struct net_device *dev = port->netdev;
507 unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id);
511 printk(KERN_DEBUG "%s: eth_poll\n", dev->name);
514 while (received < budget) {
519 struct sk_buff *temp;
523 if ((n = queue_get_desc(rxq, port, 0)) < 0) {
525 printk(KERN_DEBUG "%s: eth_poll netif_rx_complete\n",
528 netif_rx_complete(dev, napi);
529 qmgr_enable_irq(rxq);
530 if (!qmgr_stat_empty(rxq) &&
531 netif_rx_reschedule(dev, napi)) {
533 printk(KERN_DEBUG "%s: eth_poll"
534 " netif_rx_reschedule successed\n",
537 qmgr_disable_irq(rxq);
541 printk(KERN_DEBUG "%s: eth_poll all done\n",
544 return received; /* all work done */
547 desc = rx_desc_ptr(port, n);
550 if ((skb = netdev_alloc_skb(dev, RX_BUFF_SIZE))) {
551 phys = dma_map_single(&dev->dev, skb->data,
552 RX_BUFF_SIZE, DMA_FROM_DEVICE);
553 if (dma_mapping_error(&dev->dev, phys)) {
559 skb = netdev_alloc_skb(dev,
560 ALIGN(NET_IP_ALIGN + desc->pkt_len, 4));
564 dev->stats.rx_dropped++;
565 /* put the desc back on RX-ready queue */
566 desc->buf_len = MAX_MRU;
568 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
572 /* process received frame */
575 skb = port->rx_buff_tab[n];
576 dma_unmap_single(&dev->dev, desc->data - NET_IP_ALIGN,
577 RX_BUFF_SIZE, DMA_FROM_DEVICE);
579 dma_sync_single(&dev->dev, desc->data - NET_IP_ALIGN,
580 RX_BUFF_SIZE, DMA_FROM_DEVICE);
581 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
582 ALIGN(NET_IP_ALIGN + desc->pkt_len, 4) / 4);
584 skb_reserve(skb, NET_IP_ALIGN);
585 skb_put(skb, desc->pkt_len);
587 debug_pkt(dev, "eth_poll", skb->data, skb->len);
589 skb->protocol = eth_type_trans(skb, dev);
590 dev->stats.rx_packets++;
591 dev->stats.rx_bytes += skb->len;
592 netif_receive_skb(skb);
594 /* put the new buffer on RX-free queue */
596 port->rx_buff_tab[n] = temp;
597 desc->data = phys + NET_IP_ALIGN;
599 desc->buf_len = MAX_MRU;
601 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
606 printk(KERN_DEBUG "eth_poll(): end, not all work done\n");
608 return received; /* not all work done */
612 static void eth_txdone_irq(void *unused)
617 printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n");
619 while ((phys = queue_get_entry(TXDONE_QUEUE)) != 0) {
626 BUG_ON(npe_id >= MAX_NPES);
627 port = npe_port_tab[npe_id];
629 phys &= ~0x1F; /* mask out non-address bits */
630 n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc);
631 BUG_ON(n_desc >= TX_DESCS);
632 desc = tx_desc_ptr(port, n_desc);
633 debug_desc(phys, desc);
635 if (port->tx_buff_tab[n_desc]) { /* not the draining packet */
636 port->netdev->stats.tx_packets++;
637 port->netdev->stats.tx_bytes += desc->pkt_len;
639 dma_unmap_tx(port, desc);
641 printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n",
642 port->netdev->name, port->tx_buff_tab[n_desc]);
644 free_buffer_irq(port->tx_buff_tab[n_desc]);
645 port->tx_buff_tab[n_desc] = NULL;
648 start = qmgr_stat_empty(port->plat->txreadyq);
649 queue_put_desc(port->plat->txreadyq, phys, desc);
652 printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n",
655 netif_wake_queue(port->netdev);
660 static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
662 struct port *port = netdev_priv(dev);
663 unsigned int txreadyq = port->plat->txreadyq;
664 int len, offset, bytes, n;
670 printk(KERN_DEBUG "%s: eth_xmit\n", dev->name);
673 if (unlikely(skb->len > MAX_MRU)) {
675 dev->stats.tx_errors++;
679 debug_pkt(dev, "eth_xmit", skb->data, skb->len);
683 offset = 0; /* no need to keep alignment */
687 offset = (int)skb->data & 3; /* keep 32-bit alignment */
688 bytes = ALIGN(offset + len, 4);
689 if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
691 dev->stats.tx_dropped++;
694 memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
698 phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
699 if (dma_mapping_error(&dev->dev, phys)) {
705 dev->stats.tx_dropped++;
709 n = queue_get_desc(txreadyq, port, 1);
711 desc = tx_desc_ptr(port, n);
714 port->tx_buff_tab[n] = skb;
716 port->tx_buff_tab[n] = mem;
718 desc->data = phys + offset;
719 desc->buf_len = desc->pkt_len = len;
721 /* NPE firmware pads short frames with zeros internally */
723 queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc);
724 dev->trans_start = jiffies;
726 if (qmgr_stat_empty(txreadyq)) {
728 printk(KERN_DEBUG "%s: eth_xmit queue full\n", dev->name);
730 netif_stop_queue(dev);
731 /* we could miss TX ready interrupt */
732 if (!qmgr_stat_empty(txreadyq)) {
734 printk(KERN_DEBUG "%s: eth_xmit ready again\n",
737 netif_wake_queue(dev);
742 printk(KERN_DEBUG "%s: eth_xmit end\n", dev->name);
748 static void eth_set_mcast_list(struct net_device *dev)
750 struct port *port = netdev_priv(dev);
751 struct dev_mc_list *mclist = dev->mc_list;
752 u8 diffs[ETH_ALEN], *addr;
753 int cnt = dev->mc_count, i;
755 if ((dev->flags & IFF_PROMISC) || !mclist || !cnt) {
756 __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN,
757 &port->regs->rx_control[0]);
761 memset(diffs, 0, ETH_ALEN);
762 addr = mclist->dmi_addr; /* first MAC address */
764 while (--cnt && (mclist = mclist->next))
765 for (i = 0; i < ETH_ALEN; i++)
766 diffs[i] |= addr[i] ^ mclist->dmi_addr[i];
768 for (i = 0; i < ETH_ALEN; i++) {
769 __raw_writel(addr[i], &port->regs->mcast_addr[i]);
770 __raw_writel(~diffs[i], &port->regs->mcast_mask[i]);
773 __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
774 &port->regs->rx_control[0]);
778 static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
780 struct port *port = netdev_priv(dev);
781 unsigned int duplex_chg;
784 if (!netif_running(dev))
786 err = generic_mii_ioctl(&port->mii, if_mii(req), cmd, &duplex_chg);
788 eth_set_duplex(port);
793 static int request_queues(struct port *port)
797 err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0);
801 err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0);
805 err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0);
809 err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0);
813 /* TX-done queue handles skbs sent out by the NPEs */
815 err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0);
822 qmgr_release_queue(port->plat->txreadyq);
824 qmgr_release_queue(TX_QUEUE(port->id));
826 qmgr_release_queue(port->plat->rxq);
828 qmgr_release_queue(RXFREE_QUEUE(port->id));
829 printk(KERN_DEBUG "%s: unable to request hardware queues\n",
834 static void release_queues(struct port *port)
836 qmgr_release_queue(RXFREE_QUEUE(port->id));
837 qmgr_release_queue(port->plat->rxq);
838 qmgr_release_queue(TX_QUEUE(port->id));
839 qmgr_release_queue(port->plat->txreadyq);
842 qmgr_release_queue(TXDONE_QUEUE);
845 static int init_queues(struct port *port)
850 if (!(dma_pool = dma_pool_create(DRV_NAME, NULL,
851 POOL_ALLOC_SIZE, 32, 0)))
854 if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
855 &port->desc_tab_phys)))
857 memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
858 memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
859 memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
861 /* Setup RX buffers */
862 for (i = 0; i < RX_DESCS; i++) {
863 struct desc *desc = rx_desc_ptr(port, i);
864 buffer_t *buff; /* skb or kmalloc()ated memory */
867 if (!(buff = netdev_alloc_skb(port->netdev, RX_BUFF_SIZE)))
871 if (!(buff = kmalloc(RX_BUFF_SIZE, GFP_KERNEL)))
875 desc->buf_len = MAX_MRU;
876 desc->data = dma_map_single(&port->netdev->dev, data,
877 RX_BUFF_SIZE, DMA_FROM_DEVICE);
878 if (dma_mapping_error(&port->netdev->dev, desc->data)) {
882 desc->data += NET_IP_ALIGN;
883 port->rx_buff_tab[i] = buff;
889 static void destroy_queues(struct port *port)
893 if (port->desc_tab) {
894 for (i = 0; i < RX_DESCS; i++) {
895 struct desc *desc = rx_desc_ptr(port, i);
896 buffer_t *buff = port->rx_buff_tab[i];
898 dma_unmap_single(&port->netdev->dev,
899 desc->data - NET_IP_ALIGN,
900 RX_BUFF_SIZE, DMA_FROM_DEVICE);
904 for (i = 0; i < TX_DESCS; i++) {
905 struct desc *desc = tx_desc_ptr(port, i);
906 buffer_t *buff = port->tx_buff_tab[i];
908 dma_unmap_tx(port, desc);
912 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
913 port->desc_tab = NULL;
916 if (!ports_open && dma_pool) {
917 dma_pool_destroy(dma_pool);
922 static int eth_open(struct net_device *dev)
924 struct port *port = netdev_priv(dev);
925 struct npe *npe = port->npe;
929 if (!npe_running(npe)) {
930 err = npe_load_firmware(npe, npe_name(npe), &dev->dev);
934 if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) {
935 printk(KERN_ERR "%s: %s not responding\n", dev->name,
941 mdio_write(dev, port->plat->phy, MII_BMCR, port->mii_bmcr);
943 memset(&msg, 0, sizeof(msg));
944 msg.cmd = NPE_VLAN_SETRXQOSENTRY;
945 msg.eth_id = port->id;
946 msg.byte5 = port->plat->rxq | 0x80;
947 msg.byte7 = port->plat->rxq << 4;
948 for (i = 0; i < 8; i++) {
950 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ"))
954 msg.cmd = NPE_EDB_SETPORTADDRESS;
955 msg.eth_id = PHYSICAL_ID(port->id);
956 msg.byte2 = dev->dev_addr[0];
957 msg.byte3 = dev->dev_addr[1];
958 msg.byte4 = dev->dev_addr[2];
959 msg.byte5 = dev->dev_addr[3];
960 msg.byte6 = dev->dev_addr[4];
961 msg.byte7 = dev->dev_addr[5];
962 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC"))
965 memset(&msg, 0, sizeof(msg));
966 msg.cmd = NPE_FW_SETFIREWALLMODE;
967 msg.eth_id = port->id;
968 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE"))
971 if ((err = request_queues(port)) != 0)
974 if ((err = init_queues(port)) != 0) {
975 destroy_queues(port);
976 release_queues(port);
980 for (i = 0; i < ETH_ALEN; i++)
981 __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]);
982 __raw_writel(0x08, &port->regs->random_seed);
983 __raw_writel(0x12, &port->regs->partial_empty_threshold);
984 __raw_writel(0x30, &port->regs->partial_full_threshold);
985 __raw_writel(0x08, &port->regs->tx_start_bytes);
986 __raw_writel(0x15, &port->regs->tx_deferral);
987 __raw_writel(0x08, &port->regs->tx_2part_deferral[0]);
988 __raw_writel(0x07, &port->regs->tx_2part_deferral[1]);
989 __raw_writel(0x80, &port->regs->slot_time);
990 __raw_writel(0x01, &port->regs->int_clock_threshold);
992 /* Populate queues with buffers, no failure after this point */
993 for (i = 0; i < TX_DESCS; i++)
994 queue_put_desc(port->plat->txreadyq,
995 tx_desc_phys(port, i), tx_desc_ptr(port, i));
997 for (i = 0; i < RX_DESCS; i++)
998 queue_put_desc(RXFREE_QUEUE(port->id),
999 rx_desc_phys(port, i), rx_desc_ptr(port, i));
1001 __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]);
1002 __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]);
1003 __raw_writel(0, &port->regs->rx_control[1]);
1004 __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]);
1006 napi_enable(&port->napi);
1007 phy_check_media(port, 1);
1008 eth_set_mcast_list(dev);
1009 netif_start_queue(dev);
1010 schedule_delayed_work(&port->mdio_thread, MDIO_INTERVAL);
1012 qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY,
1015 qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY,
1016 eth_txdone_irq, NULL);
1017 qmgr_enable_irq(TXDONE_QUEUE);
1020 /* we may already have RX data, enables IRQ */
1021 netif_rx_schedule(dev, &port->napi);
1025 static int eth_close(struct net_device *dev)
1027 struct port *port = netdev_priv(dev);
1029 int buffs = RX_DESCS; /* allocated RX buffers */
1033 qmgr_disable_irq(port->plat->rxq);
1034 napi_disable(&port->napi);
1035 netif_stop_queue(dev);
1037 while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0)
1040 memset(&msg, 0, sizeof(msg));
1041 msg.cmd = NPE_SETLOOPBACK_MODE;
1042 msg.eth_id = port->id;
1044 if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK"))
1045 printk(KERN_CRIT "%s: unable to enable loopback\n", dev->name);
1048 do { /* drain RX buffers */
1049 while (queue_get_desc(port->plat->rxq, port, 0) >= 0)
1053 if (qmgr_stat_empty(TX_QUEUE(port->id))) {
1054 /* we have to inject some packet */
1057 int n = queue_get_desc(port->plat->txreadyq, port, 1);
1059 desc = tx_desc_ptr(port, n);
1060 phys = tx_desc_phys(port, n);
1061 desc->buf_len = desc->pkt_len = 1;
1063 queue_put_desc(TX_QUEUE(port->id), phys, desc);
1066 } while (++i < MAX_CLOSE_WAIT);
1069 printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
1070 " left in NPE\n", dev->name, buffs);
1073 printk(KERN_DEBUG "Draining RX queue took %i cycles\n", i);
1077 while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0)
1078 buffs--; /* cancel TX */
1082 while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
1086 } while (++i < MAX_CLOSE_WAIT);
1089 printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
1090 "left in NPE\n", dev->name, buffs);
1093 printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
1097 if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK"))
1098 printk(KERN_CRIT "%s: unable to disable loopback\n",
1101 port->mii_bmcr = mdio_read(dev, port->plat->phy, MII_BMCR) &
1102 ~(BMCR_RESET | BMCR_PDOWN); /* may have been altered */
1103 mdio_write(dev, port->plat->phy, MII_BMCR,
1104 port->mii_bmcr | BMCR_PDOWN);
1107 qmgr_disable_irq(TXDONE_QUEUE);
1108 cancel_rearming_delayed_work(&port->mdio_thread);
1109 destroy_queues(port);
1110 release_queues(port);
1114 static int __devinit eth_init_one(struct platform_device *pdev)
1117 struct net_device *dev;
1118 struct eth_plat_info *plat = pdev->dev.platform_data;
1122 if (!(dev = alloc_etherdev(sizeof(struct port))))
1125 SET_NETDEV_DEV(dev, &pdev->dev);
1126 port = netdev_priv(dev);
1128 port->id = pdev->id;
1131 case IXP4XX_ETH_NPEA:
1132 port->regs = (struct eth_regs __iomem *)IXP4XX_EthA_BASE_VIRT;
1133 regs_phys = IXP4XX_EthA_BASE_PHYS;
1135 case IXP4XX_ETH_NPEB:
1136 port->regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
1137 regs_phys = IXP4XX_EthB_BASE_PHYS;
1139 case IXP4XX_ETH_NPEC:
1140 port->regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
1141 regs_phys = IXP4XX_EthC_BASE_PHYS;
1148 dev->open = eth_open;
1149 dev->hard_start_xmit = eth_xmit;
1150 dev->stop = eth_close;
1151 dev->do_ioctl = eth_ioctl;
1152 dev->set_multicast_list = eth_set_mcast_list;
1153 dev->tx_queue_len = 100;
1155 netif_napi_add(dev, &port->napi, eth_poll, NAPI_WEIGHT);
1157 if (!(port->npe = npe_request(NPE_ID(port->id)))) {
1162 if (register_netdev(dev)) {
1167 port->mem_res = request_mem_region(regs_phys, REGS_SIZE, dev->name);
1168 if (!port->mem_res) {
1174 npe_port_tab[NPE_ID(port->id)] = port;
1175 memcpy(dev->dev_addr, plat->hwaddr, ETH_ALEN);
1177 platform_set_drvdata(pdev, dev);
1179 __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET,
1180 &port->regs->core_control);
1182 __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
1185 port->mii.dev = dev;
1186 port->mii.mdio_read = mdio_read;
1187 port->mii.mdio_write = mdio_write;
1188 port->mii.phy_id = plat->phy;
1189 port->mii.phy_id_mask = 0x1F;
1190 port->mii.reg_num_mask = 0x1F;
1192 printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy,
1193 npe_name(port->npe));
1195 phy_reset(dev, plat->phy);
1196 port->mii_bmcr = mdio_read(dev, plat->phy, MII_BMCR) &
1197 ~(BMCR_RESET | BMCR_PDOWN);
1198 mdio_write(dev, plat->phy, MII_BMCR, port->mii_bmcr | BMCR_PDOWN);
1200 INIT_DELAYED_WORK(&port->mdio_thread, mdio_thread);
1204 unregister_netdev(dev);
1206 npe_release(port->npe);
1212 static int __devexit eth_remove_one(struct platform_device *pdev)
1214 struct net_device *dev = platform_get_drvdata(pdev);
1215 struct port *port = netdev_priv(dev);
1217 unregister_netdev(dev);
1218 npe_port_tab[NPE_ID(port->id)] = NULL;
1219 platform_set_drvdata(pdev, NULL);
1220 npe_release(port->npe);
1221 release_resource(port->mem_res);
1226 static struct platform_driver ixp4xx_eth_driver = {
1227 .driver.name = DRV_NAME,
1228 .probe = eth_init_one,
1229 .remove = eth_remove_one,
1232 static int __init eth_init_module(void)
1234 if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0))
1237 /* All MII PHY accesses use NPE-B Ethernet registers */
1238 spin_lock_init(&mdio_lock);
1239 mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
1240 __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
1242 return platform_driver_register(&ixp4xx_eth_driver);
1245 static void __exit eth_cleanup_module(void)
1247 platform_driver_unregister(&ixp4xx_eth_driver);
1250 MODULE_AUTHOR("Krzysztof Halasa");
1251 MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver");
1252 MODULE_LICENSE("GPL v2");
1253 MODULE_ALIAS("platform:ixp4xx_eth");
1254 module_init(eth_init_module);
1255 module_exit(eth_cleanup_module);