2 * Copyright (c) 2001 by David Brownell
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 /* this file is part of ehci-hcd.c */
21 /*-------------------------------------------------------------------------*/
24 * There's basically three types of memory:
25 * - data used only by the HCD ... kmalloc is fine
26 * - async and periodic schedules, shared by HC and HCD ... these
27 * need to use dma_pool or dma_alloc_coherent
28 * - driver buffers, read/written by HC ... single shot DMA mapped
30 * There's also "register" data (e.g. PCI or SOC), which is memory mapped.
31 * No memory seen by this driver is pageable.
34 /*-------------------------------------------------------------------------*/
36 /* Allocate the key transfer structures from the previously allocated pool */
38 static inline void ehci_qtd_init(struct ehci_hcd *ehci, struct ehci_qtd *qtd,
41 memset (qtd, 0, sizeof *qtd);
43 qtd->hw_token = cpu_to_le32 (QTD_STS_HALT);
44 qtd->hw_next = EHCI_LIST_END(ehci);
45 qtd->hw_alt_next = EHCI_LIST_END(ehci);
46 INIT_LIST_HEAD (&qtd->qtd_list);
49 static struct ehci_qtd *ehci_qtd_alloc (struct ehci_hcd *ehci, gfp_t flags)
54 qtd = dma_pool_alloc (ehci->qtd_pool, flags, &dma);
56 ehci_qtd_init(ehci, qtd, dma);
61 static inline void ehci_qtd_free (struct ehci_hcd *ehci, struct ehci_qtd *qtd)
63 dma_pool_free (ehci->qtd_pool, qtd, qtd->qtd_dma);
67 static void qh_destroy(struct ehci_qh *qh)
69 struct ehci_hcd *ehci = qh->ehci;
71 /* clean qtds first, and know this is not linked */
72 if (!list_empty (&qh->qtd_list) || qh->qh_next.ptr) {
73 ehci_dbg (ehci, "unused qh not empty!\n");
77 ehci_qtd_free (ehci, qh->dummy);
78 dma_pool_free (ehci->qh_pool, qh, qh->qh_dma);
81 static struct ehci_qh *ehci_qh_alloc (struct ehci_hcd *ehci, gfp_t flags)
86 qh = (struct ehci_qh *)
87 dma_pool_alloc (ehci->qh_pool, flags, &dma);
91 memset (qh, 0, sizeof *qh);
95 // INIT_LIST_HEAD (&qh->qh_list);
96 INIT_LIST_HEAD (&qh->qtd_list);
98 /* dummy td enables safe urb queuing */
99 qh->dummy = ehci_qtd_alloc (ehci, flags);
100 if (qh->dummy == NULL) {
101 ehci_dbg (ehci, "no dummy td\n");
102 dma_pool_free (ehci->qh_pool, qh, qh->qh_dma);
108 /* to share a qh (cpu threads, or hc) */
109 static inline struct ehci_qh *qh_get (struct ehci_qh *qh)
111 WARN_ON(!qh->refcount);
116 static inline void qh_put (struct ehci_qh *qh)
122 /*-------------------------------------------------------------------------*/
124 /* The queue heads and transfer descriptors are managed from pools tied
125 * to each of the "per device" structures.
126 * This is the initialisation and cleanup code.
129 static void ehci_mem_cleanup (struct ehci_hcd *ehci)
132 qh_put (ehci->async);
135 /* DMA consistent memory and pools */
137 dma_pool_destroy (ehci->qtd_pool);
138 ehci->qtd_pool = NULL;
141 dma_pool_destroy (ehci->qh_pool);
142 ehci->qh_pool = NULL;
146 dma_pool_destroy (ehci->itd_pool);
147 ehci->itd_pool = NULL;
150 dma_pool_destroy (ehci->sitd_pool);
151 ehci->sitd_pool = NULL;
154 dma_free_coherent (ehci_to_hcd(ehci)->self.controller,
155 ehci->periodic_size * sizeof (u32),
156 ehci->periodic, ehci->periodic_dma);
157 ehci->periodic = NULL;
159 /* shadow periodic table */
160 kfree(ehci->pshadow);
161 ehci->pshadow = NULL;
164 /* remember to add cleanup code (above) if you add anything here */
165 static int ehci_mem_init (struct ehci_hcd *ehci, gfp_t flags)
169 /* QTDs for control/bulk/intr transfers */
170 ehci->qtd_pool = dma_pool_create ("ehci_qtd",
171 ehci_to_hcd(ehci)->self.controller,
172 sizeof (struct ehci_qtd),
173 32 /* byte alignment (for hw parts) */,
174 4096 /* can't cross 4K */);
175 if (!ehci->qtd_pool) {
179 /* QHs for control/bulk/intr transfers */
180 ehci->qh_pool = dma_pool_create ("ehci_qh",
181 ehci_to_hcd(ehci)->self.controller,
182 sizeof (struct ehci_qh),
183 32 /* byte alignment (for hw parts) */,
184 4096 /* can't cross 4K */);
185 if (!ehci->qh_pool) {
188 ehci->async = ehci_qh_alloc (ehci, flags);
193 /* ITD for high speed ISO transfers */
194 ehci->itd_pool = dma_pool_create ("ehci_itd",
195 ehci_to_hcd(ehci)->self.controller,
196 sizeof (struct ehci_itd),
197 32 /* byte alignment (for hw parts) */,
198 4096 /* can't cross 4K */);
199 if (!ehci->itd_pool) {
203 /* SITD for full/low speed split ISO transfers */
204 ehci->sitd_pool = dma_pool_create ("ehci_sitd",
205 ehci_to_hcd(ehci)->self.controller,
206 sizeof (struct ehci_sitd),
207 32 /* byte alignment (for hw parts) */,
208 4096 /* can't cross 4K */);
209 if (!ehci->sitd_pool) {
213 /* Hardware periodic table */
214 ehci->periodic = (__le32 *)
215 dma_alloc_coherent (ehci_to_hcd(ehci)->self.controller,
216 ehci->periodic_size * sizeof(__le32),
217 &ehci->periodic_dma, 0);
218 if (ehci->periodic == NULL) {
221 for (i = 0; i < ehci->periodic_size; i++)
222 ehci->periodic [i] = EHCI_LIST_END(ehci);
224 /* software shadow of hardware table */
225 ehci->pshadow = kcalloc(ehci->periodic_size, sizeof(void *), flags);
226 if (ehci->pshadow != NULL)
230 ehci_dbg (ehci, "couldn't init memory\n");
231 ehci_mem_cleanup (ehci);