git.oblomov.eu Git - linux-2.6/blob - drivers/i2c/busses/i2c-i801.c

   1 /*
   2     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   3     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   4     <mdsxyz123@yahoo.com>
   5     Copyright (C) 2007, 2008   Jean Delvare <khali@linux-fr.org>
   6
   7     This program is free software; you can redistribute it and/or modify
   8     it under the terms of the GNU General Public License as published by
   9     the Free Software Foundation; either version 2 of the License, or
  10     (at your option) any later version.
  11
  12     This program is distributed in the hope that it will be useful,
  13     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15     GNU General Public License for more details.
  16
  17     You should have received a copy of the GNU General Public License
  18     along with this program; if not, write to the Free Software
  19     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20 */
  21
  22 /*
  23   Supports the following Intel I/O Controller Hubs (ICH):
  24
  25                                   I/O                     Block   I2C
  26                                   region  SMBus   Block   proc.   block
  27   Chip name             PCI ID    size    PEC     buffer  call    read
  28   ----------------------------------------------------------------------
  29   82801AA  (ICH)        0x2413     16      no      no      no      no
  30   82801AB  (ICH0)       0x2423     16      no      no      no      no
  31   82801BA  (ICH2)       0x2443     16      no      no      no      no
  32   82801CA  (ICH3)       0x2483     32     soft     no      no      no
  33   82801DB  (ICH4)       0x24c3     32     hard     yes     no      no
  34   82801E   (ICH5)       0x24d3     32     hard     yes     yes     yes
  35   6300ESB               0x25a4     32     hard     yes     yes     yes
  36   82801F   (ICH6)       0x266a     32     hard     yes     yes     yes
  37   6310ESB/6320ESB       0x269b     32     hard     yes     yes     yes
  38   82801G   (ICH7)       0x27da     32     hard     yes     yes     yes
  39   82801H   (ICH8)       0x283e     32     hard     yes     yes     yes
  40   82801I   (ICH9)       0x2930     32     hard     yes     yes     yes
  41   Tolapai               0x5032     32     hard     yes     yes     yes
  42   ICH10                 0x3a30     32     hard     yes     yes     yes
  43   ICH10                 0x3a60     32     hard     yes     yes     yes
  44   PCH                   0x3b30     32     hard     yes     yes     yes
  45
  46   Features supported by this driver:
  47   Software PEC                     no
  48   Hardware PEC                     yes
  49   Block buffer                     yes
  50   Block process call transaction   no
  51   I2C block read transaction       yes  (doesn't use the block buffer)
  52
  53   See the file Documentation/i2c/busses/i2c-i801 for details.
  54 */
  55
  56 /* Note: we assume there can only be one I801, with one SMBus interface */
  57
  58 #include <linux/module.h>
  59 #include <linux/pci.h>
  60 #include <linux/kernel.h>
  61 #include <linux/stddef.h>
  62 #include <linux/delay.h>
  63 #include <linux/ioport.h>
  64 #include <linux/init.h>
  65 #include <linux/i2c.h>
  66 #include <linux/acpi.h>
  67 #include <asm/io.h>
  68
  69 /* I801 SMBus address offsets */
  70 #define SMBHSTSTS       (0 + i801_smba)
  71 #define SMBHSTCNT       (2 + i801_smba)
  72 #define SMBHSTCMD       (3 + i801_smba)
  73 #define SMBHSTADD       (4 + i801_smba)
  74 #define SMBHSTDAT0      (5 + i801_smba)
  75 #define SMBHSTDAT1      (6 + i801_smba)
  76 #define SMBBLKDAT       (7 + i801_smba)
  77 #define SMBPEC          (8 + i801_smba)         /* ICH3 and later */
  78 #define SMBAUXSTS       (12 + i801_smba)        /* ICH4 and later */
  79 #define SMBAUXCTL       (13 + i801_smba)        /* ICH4 and later */
  80
  81 /* PCI Address Constants */
  82 #define SMBBAR          4
  83 #define SMBHSTCFG       0x040
  84
  85 /* Host configuration bits for SMBHSTCFG */
  86 #define SMBHSTCFG_HST_EN        1
  87 #define SMBHSTCFG_SMB_SMI_EN    2
  88 #define SMBHSTCFG_I2C_EN        4
  89
  90 /* Auxillary control register bits, ICH4+ only */
  91 #define SMBAUXCTL_CRC           1
  92 #define SMBAUXCTL_E32B          2
  93
  94 /* kill bit for SMBHSTCNT */
  95 #define SMBHSTCNT_KILL          2
  96
  97 /* Other settings */
  98 #define MAX_TIMEOUT             100
  99 #define ENABLE_INT9             0       /* set to 0x01 to enable - untested */
 100
 101 /* I801 command constants */
 102 #define I801_QUICK              0x00
 103 #define I801_BYTE               0x04
 104 #define I801_BYTE_DATA          0x08
 105 #define I801_WORD_DATA          0x0C
 106 #define I801_PROC_CALL          0x10    /* unimplemented */
 107 #define I801_BLOCK_DATA         0x14
 108 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 109 #define I801_BLOCK_LAST         0x34
 110 #define I801_I2C_BLOCK_LAST     0x38    /* ICH5 and later */
 111 #define I801_START              0x40
 112 #define I801_PEC_EN             0x80    /* ICH3 and later */
 113
 114 /* I801 Hosts Status register bits */
 115 #define SMBHSTSTS_BYTE_DONE     0x80
 116 #define SMBHSTSTS_INUSE_STS     0x40
 117 #define SMBHSTSTS_SMBALERT_STS  0x20
 118 #define SMBHSTSTS_FAILED        0x10
 119 #define SMBHSTSTS_BUS_ERR       0x08
 120 #define SMBHSTSTS_DEV_ERR       0x04
 121 #define SMBHSTSTS_INTR          0x02
 122 #define SMBHSTSTS_HOST_BUSY     0x01
 123
 124 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_FAILED | \
 125                                  SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \
 126                                  SMBHSTSTS_INTR)
 127
 128 static unsigned long i801_smba;
 129 static unsigned char i801_original_hstcfg;
 130 static struct pci_driver i801_driver;
 131 static struct pci_dev *I801_dev;
 132
 133 #define FEATURE_SMBUS_PEC       (1 << 0)
 134 #define FEATURE_BLOCK_BUFFER    (1 << 1)
 135 #define FEATURE_BLOCK_PROC      (1 << 2)
 136 #define FEATURE_I2C_BLOCK_READ  (1 << 3)
 137 static unsigned int i801_features;
 138
 139 /* Make sure the SMBus host is ready to start transmitting.
 140    Return 0 if it is, -EBUSY if it is not. */
 141 static int i801_check_pre(void)
 142 {
 143         int status;
 144
 145         status = inb_p(SMBHSTSTS);
 146         if (status & SMBHSTSTS_HOST_BUSY) {
 147                 dev_err(&I801_dev->dev, "SMBus is busy, can't use it!\n");
 148                 return -EBUSY;
 149         }
 150
 151         status &= STATUS_FLAGS;
 152         if (status) {
 153                 dev_dbg(&I801_dev->dev, "Clearing status flags (%02x)\n",
 154                         status);
 155                 outb_p(status, SMBHSTSTS);
 156                 status = inb_p(SMBHSTSTS) & STATUS_FLAGS;
 157                 if (status) {
 158                         dev_err(&I801_dev->dev,
 159                                 "Failed clearing status flags (%02x)\n",
 160                                 status);
 161                         return -EBUSY;
 162                 }
 163         }
 164
 165         return 0;
 166 }
 167
 168 /* Convert the status register to an error code, and clear it. */
 169 static int i801_check_post(int status, int timeout)
 170 {
 171         int result = 0;
 172
 173         /* If the SMBus is still busy, we give up */
 174         if (timeout) {
 175                 dev_err(&I801_dev->dev, "Transaction timeout\n");
 176                 /* try to stop the current command */
 177                 dev_dbg(&I801_dev->dev, "Terminating the current operation\n");
 178                 outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT);
 179                 msleep(1);
 180                 outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL), SMBHSTCNT);
 181
 182                 /* Check if it worked */
 183                 status = inb_p(SMBHSTSTS);
 184                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 185                     !(status & SMBHSTSTS_FAILED))
 186                         dev_err(&I801_dev->dev,
 187                                 "Failed terminating the transaction\n");
 188                 outb_p(STATUS_FLAGS, SMBHSTSTS);
 189                 return -ETIMEDOUT;
 190         }
 191
 192         if (status & SMBHSTSTS_FAILED) {
 193                 result = -EIO;
 194                 dev_err(&I801_dev->dev, "Transaction failed\n");
 195         }
 196         if (status & SMBHSTSTS_DEV_ERR) {
 197                 result = -ENXIO;
 198                 dev_dbg(&I801_dev->dev, "No response\n");
 199         }
 200         if (status & SMBHSTSTS_BUS_ERR) {
 201                 result = -EAGAIN;
 202                 dev_dbg(&I801_dev->dev, "Lost arbitration\n");
 203         }
 204
 205         if (result) {
 206                 /* Clear error flags */
 207                 outb_p(status & STATUS_FLAGS, SMBHSTSTS);
 208                 status = inb_p(SMBHSTSTS) & STATUS_FLAGS;
 209                 if (status) {
 210                         dev_warn(&I801_dev->dev, "Failed clearing status "
 211                                  "flags at end of transaction (%02x)\n",
 212                                  status);
 213                 }
 214         }
 215
 216         return result;
 217 }
 218
 219 static int i801_transaction(int xact)
 220 {
 221         int status;
 222         int result;
 223         int timeout = 0;
 224
 225         result = i801_check_pre();
 226         if (result < 0)
 227                 return result;
 228
 229         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 230          * INTREN, SMBSCMD are passed in xact */
 231         outb_p(xact | I801_START, SMBHSTCNT);
 232
 233         /* We will always wait for a fraction of a second! */
 234         do {
 235                 msleep(1);
 236                 status = inb_p(SMBHSTSTS);
 237         } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
 238
 239         result = i801_check_post(status, timeout >= MAX_TIMEOUT);
 240         if (result < 0)
 241                 return result;
 242
 243         outb_p(SMBHSTSTS_INTR, SMBHSTSTS);
 244         return 0;
 245 }
 246
 247 /* wait for INTR bit as advised by Intel */
 248 static void i801_wait_hwpec(void)
 249 {
 250         int timeout = 0;
 251         int status;
 252
 253         do {
 254                 msleep(1);
 255                 status = inb_p(SMBHSTSTS);
 256         } while ((!(status & SMBHSTSTS_INTR))
 257                  && (timeout++ < MAX_TIMEOUT));
 258
 259         if (timeout >= MAX_TIMEOUT) {
 260                 dev_dbg(&I801_dev->dev, "PEC Timeout!\n");
 261         }
 262         outb_p(status, SMBHSTSTS);
 263 }
 264
 265 static int i801_block_transaction_by_block(union i2c_smbus_data *data,
 266                                            char read_write, int hwpec)
 267 {
 268         int i, len;
 269         int status;
 270
 271         inb_p(SMBHSTCNT); /* reset the data buffer index */
 272
 273         /* Use 32-byte buffer to process this transaction */
 274         if (read_write == I2C_SMBUS_WRITE) {
 275                 len = data->block[0];
 276                 outb_p(len, SMBHSTDAT0);
 277                 for (i = 0; i < len; i++)
 278                         outb_p(data->block[i+1], SMBBLKDAT);
 279         }
 280
 281         status = i801_transaction(I801_BLOCK_DATA | ENABLE_INT9 |
 282                                   I801_PEC_EN * hwpec);
 283         if (status)
 284                 return status;
 285
 286         if (read_write == I2C_SMBUS_READ) {
 287                 len = inb_p(SMBHSTDAT0);
 288                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 289                         return -EPROTO;
 290
 291                 data->block[0] = len;
 292                 for (i = 0; i < len; i++)
 293                         data->block[i + 1] = inb_p(SMBBLKDAT);
 294         }
 295         return 0;
 296 }
 297
 298 static int i801_block_transaction_byte_by_byte(union i2c_smbus_data *data,
 299                                                char read_write, int command,
 300                                                int hwpec)
 301 {
 302         int i, len;
 303         int smbcmd;
 304         int status;
 305         int result;
 306         int timeout;
 307
 308         result = i801_check_pre();
 309         if (result < 0)
 310                 return result;
 311
 312         len = data->block[0];
 313
 314         if (read_write == I2C_SMBUS_WRITE) {
 315                 outb_p(len, SMBHSTDAT0);
 316                 outb_p(data->block[1], SMBBLKDAT);
 317         }
 318
 319         for (i = 1; i <= len; i++) {
 320                 if (i == len && read_write == I2C_SMBUS_READ) {
 321                         if (command == I2C_SMBUS_I2C_BLOCK_DATA)
 322                                 smbcmd = I801_I2C_BLOCK_LAST;
 323                         else
 324                                 smbcmd = I801_BLOCK_LAST;
 325                 } else {
 326                         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 327                          && read_write == I2C_SMBUS_READ)
 328                                 smbcmd = I801_I2C_BLOCK_DATA;
 329                         else
 330                                 smbcmd = I801_BLOCK_DATA;
 331                 }
 332                 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT);
 333
 334                 if (i == 1)
 335                         outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);
 336
 337                 /* We will always wait for a fraction of a second! */
 338                 timeout = 0;
 339                 do {
 340                         msleep(1);
 341                         status = inb_p(SMBHSTSTS);
 342                 }
 343                 while ((!(status & SMBHSTSTS_BYTE_DONE))
 344                        && (timeout++ < MAX_TIMEOUT));
 345
 346                 result = i801_check_post(status, timeout >= MAX_TIMEOUT);
 347                 if (result < 0)
 348                         return result;
 349
 350                 if (i == 1 && read_write == I2C_SMBUS_READ
 351                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 352                         len = inb_p(SMBHSTDAT0);
 353                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 354                                 dev_err(&I801_dev->dev,
 355                                         "Illegal SMBus block read size %d\n",
 356                                         len);
 357                                 /* Recover */
 358                                 while (inb_p(SMBHSTSTS) & SMBHSTSTS_HOST_BUSY)
 359                                         outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS);
 360                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS);
 361                                 return -EPROTO;
 362                         }
 363                         data->block[0] = len;
 364                 }
 365
 366                 /* Retrieve/store value in SMBBLKDAT */
 367                 if (read_write == I2C_SMBUS_READ)
 368                         data->block[i] = inb_p(SMBBLKDAT);
 369                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 370                         outb_p(data->block[i+1], SMBBLKDAT);
 371
 372                 /* signals SMBBLKDAT ready */
 373                 outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS);
 374         }
 375
 376         return 0;
 377 }
 378
 379 static int i801_set_block_buffer_mode(void)
 380 {
 381         outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_E32B, SMBAUXCTL);
 382         if ((inb_p(SMBAUXCTL) & SMBAUXCTL_E32B) == 0)
 383                 return -EIO;
 384         return 0;
 385 }
 386
 387 /* Block transaction function */
 388 static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
 389                                   int command, int hwpec)
 390 {
 391         int result = 0;
 392         unsigned char hostc;
 393
 394         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 395                 if (read_write == I2C_SMBUS_WRITE) {
 396                         /* set I2C_EN bit in configuration register */
 397                         pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
 398                         pci_write_config_byte(I801_dev, SMBHSTCFG,
 399                                               hostc | SMBHSTCFG_I2C_EN);
 400                 } else if (!(i801_features & FEATURE_I2C_BLOCK_READ)) {
 401                         dev_err(&I801_dev->dev,
 402                                 "I2C block read is unsupported!\n");
 403                         return -EOPNOTSUPP;
 404                 }
 405         }
 406
 407         if (read_write == I2C_SMBUS_WRITE
 408          || command == I2C_SMBUS_I2C_BLOCK_DATA) {
 409                 if (data->block[0] < 1)
 410                         data->block[0] = 1;
 411                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 412                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
 413         } else {
 414                 data->block[0] = 32;    /* max for SMBus block reads */
 415         }
 416
 417         if ((i801_features & FEATURE_BLOCK_BUFFER)
 418          && !(command == I2C_SMBUS_I2C_BLOCK_DATA
 419               && read_write == I2C_SMBUS_READ)
 420          && i801_set_block_buffer_mode() == 0)
 421                 result = i801_block_transaction_by_block(data, read_write,
 422                                                          hwpec);
 423         else
 424                 result = i801_block_transaction_byte_by_byte(data, read_write,
 425                                                              command, hwpec);
 426
 427         if (result == 0 && hwpec)
 428                 i801_wait_hwpec();
 429
 430         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 431          && read_write == I2C_SMBUS_WRITE) {
 432                 /* restore saved configuration register value */
 433                 pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
 434         }
 435         return result;
 436 }
 437
 438 /* Return negative errno on error. */
 439 static s32 i801_access(struct i2c_adapter * adap, u16 addr,
 440                        unsigned short flags, char read_write, u8 command,
 441                        int size, union i2c_smbus_data * data)
 442 {
 443         int hwpec;
 444         int block = 0;
 445         int ret, xact = 0;
 446
 447         hwpec = (i801_features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 448                 && size != I2C_SMBUS_QUICK
 449                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 450
 451         switch (size) {
 452         case I2C_SMBUS_QUICK:
 453                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 454                        SMBHSTADD);
 455                 xact = I801_QUICK;
 456                 break;
 457         case I2C_SMBUS_BYTE:
 458                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 459                        SMBHSTADD);
 460                 if (read_write == I2C_SMBUS_WRITE)
 461                         outb_p(command, SMBHSTCMD);
 462                 xact = I801_BYTE;
 463                 break;
 464         case I2C_SMBUS_BYTE_DATA:
 465                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 466                        SMBHSTADD);
 467                 outb_p(command, SMBHSTCMD);
 468                 if (read_write == I2C_SMBUS_WRITE)
 469                         outb_p(data->byte, SMBHSTDAT0);
 470                 xact = I801_BYTE_DATA;
 471                 break;
 472         case I2C_SMBUS_WORD_DATA:
 473                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 474                        SMBHSTADD);
 475                 outb_p(command, SMBHSTCMD);
 476                 if (read_write == I2C_SMBUS_WRITE) {
 477                         outb_p(data->word & 0xff, SMBHSTDAT0);
 478                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
 479                 }
 480                 xact = I801_WORD_DATA;
 481                 break;
 482         case I2C_SMBUS_BLOCK_DATA:
 483                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 484                        SMBHSTADD);
 485                 outb_p(command, SMBHSTCMD);
 486                 block = 1;
 487                 break;
 488         case I2C_SMBUS_I2C_BLOCK_DATA:
 489                 /* NB: page 240 of ICH5 datasheet shows that the R/#W
 490                  * bit should be cleared here, even when reading */
 491                 outb_p((addr & 0x7f) << 1, SMBHSTADD);
 492                 if (read_write == I2C_SMBUS_READ) {
 493                         /* NB: page 240 of ICH5 datasheet also shows
 494                          * that DATA1 is the cmd field when reading */
 495                         outb_p(command, SMBHSTDAT1);
 496                 } else
 497                         outb_p(command, SMBHSTCMD);
 498                 block = 1;
 499                 break;
 500         default:
 501                 dev_err(&I801_dev->dev, "Unsupported transaction %d\n", size);
 502                 return -EOPNOTSUPP;
 503         }
 504
 505         if (hwpec)      /* enable/disable hardware PEC */
 506                 outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_CRC, SMBAUXCTL);
 507         else
 508                 outb_p(inb_p(SMBAUXCTL) & (~SMBAUXCTL_CRC), SMBAUXCTL);
 509
 510         if(block)
 511                 ret = i801_block_transaction(data, read_write, size, hwpec);
 512         else
 513                 ret = i801_transaction(xact | ENABLE_INT9);
 514
 515         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 516            time, so we forcibly disable it after every transaction. Turn off
 517            E32B for the same reason. */
 518         if (hwpec || block)
 519                 outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
 520                        SMBAUXCTL);
 521
 522         if(block)
 523                 return ret;
 524         if(ret)
 525                 return ret;
 526         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 527                 return 0;
 528
 529         switch (xact & 0x7f) {
 530         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 531         case I801_BYTE_DATA:
 532                 data->byte = inb_p(SMBHSTDAT0);
 533                 break;
 534         case I801_WORD_DATA:
 535                 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
 536                 break;
 537         }
 538         return 0;
 539 }
 540
 541
 542 static u32 i801_func(struct i2c_adapter *adapter)
 543 {
 544         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 545                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 546                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 547                ((i801_features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 548                ((i801_features & FEATURE_I2C_BLOCK_READ) ?
 549                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
 550 }
 551
 552 static const struct i2c_algorithm smbus_algorithm = {
 553         .smbus_xfer     = i801_access,
 554         .functionality  = i801_func,
 555 };
 556
 557 static struct i2c_adapter i801_adapter = {
 558         .owner          = THIS_MODULE,
 559         .id             = I2C_HW_SMBUS_I801,
 560         .class          = I2C_CLASS_HWMON | I2C_CLASS_SPD,
 561         .algo           = &smbus_algorithm,
 562 };
 563
 564 static struct pci_device_id i801_ids[] = {
 565         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
 566         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
 567         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
 568         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
 569         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
 570         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
 571         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
 572         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
 573         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
 574         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
 575         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
 576         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
 577         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TOLAPAI_1) },
 578         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
 579         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
 580         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PCH_SMBUS) },
 581         { 0, }
 582 };
 583
 584 MODULE_DEVICE_TABLE (pci, i801_ids);
 585
 586 static int __devinit i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
 587 {
 588         unsigned char temp;
 589         int err;
 590
 591         I801_dev = dev;
 592         i801_features = 0;
 593         switch (dev->device) {
 594         case PCI_DEVICE_ID_INTEL_82801EB_3:
 595         case PCI_DEVICE_ID_INTEL_ESB_4:
 596         case PCI_DEVICE_ID_INTEL_ICH6_16:
 597         case PCI_DEVICE_ID_INTEL_ICH7_17:
 598         case PCI_DEVICE_ID_INTEL_ESB2_17:
 599         case PCI_DEVICE_ID_INTEL_ICH8_5:
 600         case PCI_DEVICE_ID_INTEL_ICH9_6:
 601         case PCI_DEVICE_ID_INTEL_TOLAPAI_1:
 602         case PCI_DEVICE_ID_INTEL_ICH10_4:
 603         case PCI_DEVICE_ID_INTEL_ICH10_5:
 604         case PCI_DEVICE_ID_INTEL_PCH_SMBUS:
 605                 i801_features |= FEATURE_I2C_BLOCK_READ;
 606                 /* fall through */
 607         case PCI_DEVICE_ID_INTEL_82801DB_3:
 608                 i801_features |= FEATURE_SMBUS_PEC;
 609                 i801_features |= FEATURE_BLOCK_BUFFER;
 610                 break;
 611         }
 612
 613         err = pci_enable_device(dev);
 614         if (err) {
 615                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
 616                         err);
 617                 goto exit;
 618         }
 619
 620         /* Determine the address of the SMBus area */
 621         i801_smba = pci_resource_start(dev, SMBBAR);
 622         if (!i801_smba) {
 623                 dev_err(&dev->dev, "SMBus base address uninitialized, "
 624                         "upgrade BIOS\n");
 625                 err = -ENODEV;
 626                 goto exit;
 627         }
 628
 629         err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
 630         if (err)
 631                 goto exit;
 632
 633         err = pci_request_region(dev, SMBBAR, i801_driver.name);
 634         if (err) {
 635                 dev_err(&dev->dev, "Failed to request SMBus region "
 636                         "0x%lx-0x%Lx\n", i801_smba,
 637                         (unsigned long long)pci_resource_end(dev, SMBBAR));
 638                 goto exit;
 639         }
 640
 641         pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
 642         i801_original_hstcfg = temp;
 643         temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
 644         if (!(temp & SMBHSTCFG_HST_EN)) {
 645                 dev_info(&dev->dev, "Enabling SMBus device\n");
 646                 temp |= SMBHSTCFG_HST_EN;
 647         }
 648         pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
 649
 650         if (temp & SMBHSTCFG_SMB_SMI_EN)
 651                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
 652         else
 653                 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
 654
 655         /* Clear special mode bits */
 656         if (i801_features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
 657                 outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
 658                        SMBAUXCTL);
 659
 660         /* set up the sysfs linkage to our parent device */
 661         i801_adapter.dev.parent = &dev->dev;
 662
 663         snprintf(i801_adapter.name, sizeof(i801_adapter.name),
 664                 "SMBus I801 adapter at %04lx", i801_smba);
 665         err = i2c_add_adapter(&i801_adapter);
 666         if (err) {
 667                 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
 668                 goto exit_release;
 669         }
 670         return 0;
 671
 672 exit_release:
 673         pci_release_region(dev, SMBBAR);
 674 exit:
 675         return err;
 676 }
 677
 678 static void __devexit i801_remove(struct pci_dev *dev)
 679 {
 680         i2c_del_adapter(&i801_adapter);
 681         pci_write_config_byte(I801_dev, SMBHSTCFG, i801_original_hstcfg);
 682         pci_release_region(dev, SMBBAR);
 683         /*
 684          * do not call pci_disable_device(dev) since it can cause hard hangs on
 685          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
 686          */
 687 }
 688
 689 #ifdef CONFIG_PM
 690 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
 691 {
 692         pci_save_state(dev);
 693         pci_write_config_byte(dev, SMBHSTCFG, i801_original_hstcfg);
 694         pci_set_power_state(dev, pci_choose_state(dev, mesg));
 695         return 0;
 696 }
 697
 698 static int i801_resume(struct pci_dev *dev)
 699 {
 700         pci_set_power_state(dev, PCI_D0);
 701         pci_restore_state(dev);
 702         return pci_enable_device(dev);
 703 }
 704 #else
 705 #define i801_suspend NULL
 706 #define i801_resume NULL
 707 #endif
 708
 709 static struct pci_driver i801_driver = {
 710         .name           = "i801_smbus",
 711         .id_table       = i801_ids,
 712         .probe          = i801_probe,
 713         .remove         = __devexit_p(i801_remove),
 714         .suspend        = i801_suspend,
 715         .resume         = i801_resume,
 716 };
 717
 718 static int __init i2c_i801_init(void)
 719 {
 720         return pci_register_driver(&i801_driver);
 721 }
 722
 723 static void __exit i2c_i801_exit(void)
 724 {
 725         pci_unregister_driver(&i801_driver);
 726 }
 727
 728 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
 729               "Jean Delvare <khali@linux-fr.org>");
 730 MODULE_DESCRIPTION("I801 SMBus driver");
 731 MODULE_LICENSE("GPL");
 732
 733 module_init(i2c_i801_init);
 734 module_exit(i2c_i801_exit);