Merge branch 'core/debug' into core/core
[linux-2.6] / drivers / mtd / nand / pxa3xx_nand.c
1 /*
2  * drivers/mtd/nand/pxa3xx_nand.c
3  *
4  * Copyright © 2005 Intel Corporation
5  * Copyright © 2006 Marvell International Ltd.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  */
11
12 #include <linux/module.h>
13 #include <linux/interrupt.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/delay.h>
17 #include <linux/clk.h>
18 #include <linux/mtd/mtd.h>
19 #include <linux/mtd/nand.h>
20 #include <linux/mtd/partitions.h>
21 #include <linux/io.h>
22 #include <linux/irq.h>
23 #include <asm/dma.h>
24
25 #include <mach/pxa-regs.h>
26 #include <mach/pxa3xx_nand.h>
27
28 #define CHIP_DELAY_TIMEOUT      (2 * HZ/10)
29
30 /* registers and bit definitions */
31 #define NDCR            (0x00) /* Control register */
32 #define NDTR0CS0        (0x04) /* Timing Parameter 0 for CS0 */
33 #define NDTR1CS0        (0x0C) /* Timing Parameter 1 for CS0 */
34 #define NDSR            (0x14) /* Status Register */
35 #define NDPCR           (0x18) /* Page Count Register */
36 #define NDBDR0          (0x1C) /* Bad Block Register 0 */
37 #define NDBDR1          (0x20) /* Bad Block Register 1 */
38 #define NDDB            (0x40) /* Data Buffer */
39 #define NDCB0           (0x48) /* Command Buffer0 */
40 #define NDCB1           (0x4C) /* Command Buffer1 */
41 #define NDCB2           (0x50) /* Command Buffer2 */
42
43 #define NDCR_SPARE_EN           (0x1 << 31)
44 #define NDCR_ECC_EN             (0x1 << 30)
45 #define NDCR_DMA_EN             (0x1 << 29)
46 #define NDCR_ND_RUN             (0x1 << 28)
47 #define NDCR_DWIDTH_C           (0x1 << 27)
48 #define NDCR_DWIDTH_M           (0x1 << 26)
49 #define NDCR_PAGE_SZ            (0x1 << 24)
50 #define NDCR_NCSX               (0x1 << 23)
51 #define NDCR_ND_MODE            (0x3 << 21)
52 #define NDCR_NAND_MODE          (0x0)
53 #define NDCR_CLR_PG_CNT         (0x1 << 20)
54 #define NDCR_CLR_ECC            (0x1 << 19)
55 #define NDCR_RD_ID_CNT_MASK     (0x7 << 16)
56 #define NDCR_RD_ID_CNT(x)       (((x) << 16) & NDCR_RD_ID_CNT_MASK)
57
58 #define NDCR_RA_START           (0x1 << 15)
59 #define NDCR_PG_PER_BLK         (0x1 << 14)
60 #define NDCR_ND_ARB_EN          (0x1 << 12)
61
62 #define NDSR_MASK               (0xfff)
63 #define NDSR_RDY                (0x1 << 11)
64 #define NDSR_CS0_PAGED          (0x1 << 10)
65 #define NDSR_CS1_PAGED          (0x1 << 9)
66 #define NDSR_CS0_CMDD           (0x1 << 8)
67 #define NDSR_CS1_CMDD           (0x1 << 7)
68 #define NDSR_CS0_BBD            (0x1 << 6)
69 #define NDSR_CS1_BBD            (0x1 << 5)
70 #define NDSR_DBERR              (0x1 << 4)
71 #define NDSR_SBERR              (0x1 << 3)
72 #define NDSR_WRDREQ             (0x1 << 2)
73 #define NDSR_RDDREQ             (0x1 << 1)
74 #define NDSR_WRCMDREQ           (0x1)
75
76 #define NDCB0_AUTO_RS           (0x1 << 25)
77 #define NDCB0_CSEL              (0x1 << 24)
78 #define NDCB0_CMD_TYPE_MASK     (0x7 << 21)
79 #define NDCB0_CMD_TYPE(x)       (((x) << 21) & NDCB0_CMD_TYPE_MASK)
80 #define NDCB0_NC                (0x1 << 20)
81 #define NDCB0_DBC               (0x1 << 19)
82 #define NDCB0_ADDR_CYC_MASK     (0x7 << 16)
83 #define NDCB0_ADDR_CYC(x)       (((x) << 16) & NDCB0_ADDR_CYC_MASK)
84 #define NDCB0_CMD2_MASK         (0xff << 8)
85 #define NDCB0_CMD1_MASK         (0xff)
86 #define NDCB0_ADDR_CYC_SHIFT    (16)
87
88 /* dma-able I/O address for the NAND data and commands */
89 #define NDCB0_DMA_ADDR          (0x43100048)
90 #define NDDB_DMA_ADDR           (0x43100040)
91
92 /* macros for registers read/write */
93 #define nand_writel(info, off, val)     \
94         __raw_writel((val), (info)->mmio_base + (off))
95
96 #define nand_readl(info, off)           \
97         __raw_readl((info)->mmio_base + (off))
98
99 /* error code and state */
100 enum {
101         ERR_NONE        = 0,
102         ERR_DMABUSERR   = -1,
103         ERR_SENDCMD     = -2,
104         ERR_DBERR       = -3,
105         ERR_BBERR       = -4,
106 };
107
108 enum {
109         STATE_READY     = 0,
110         STATE_CMD_HANDLE,
111         STATE_DMA_READING,
112         STATE_DMA_WRITING,
113         STATE_DMA_DONE,
114         STATE_PIO_READING,
115         STATE_PIO_WRITING,
116 };
117
118 struct pxa3xx_nand_info {
119         struct nand_chip        nand_chip;
120
121         struct platform_device   *pdev;
122         const struct pxa3xx_nand_flash *flash_info;
123
124         struct clk              *clk;
125         void __iomem            *mmio_base;
126
127         unsigned int            buf_start;
128         unsigned int            buf_count;
129
130         /* DMA information */
131         int                     drcmr_dat;
132         int                     drcmr_cmd;
133
134         unsigned char           *data_buff;
135         dma_addr_t              data_buff_phys;
136         size_t                  data_buff_size;
137         int                     data_dma_ch;
138         struct pxa_dma_desc     *data_desc;
139         dma_addr_t              data_desc_addr;
140
141         uint32_t                reg_ndcr;
142
143         /* saved column/page_addr during CMD_SEQIN */
144         int                     seqin_column;
145         int                     seqin_page_addr;
146
147         /* relate to the command */
148         unsigned int            state;
149
150         int                     use_ecc;        /* use HW ECC ? */
151         int                     use_dma;        /* use DMA ? */
152
153         size_t                  data_size;      /* data size in FIFO */
154         int                     retcode;
155         struct completion       cmd_complete;
156
157         /* generated NDCBx register values */
158         uint32_t                ndcb0;
159         uint32_t                ndcb1;
160         uint32_t                ndcb2;
161
162         /* calculated from pxa3xx_nand_flash data */
163         size_t          oob_size;
164         size_t          read_id_bytes;
165
166         unsigned int    col_addr_cycles;
167         unsigned int    row_addr_cycles;
168 };
169
170 static int use_dma = 1;
171 module_param(use_dma, bool, 0444);
172 MODULE_PARM_DESC(use_dma, "enable DMA for data transfering to/from NAND HW");
173
174 #ifdef CONFIG_MTD_NAND_PXA3xx_BUILTIN
175 static struct pxa3xx_nand_cmdset smallpage_cmdset = {
176         .read1          = 0x0000,
177         .read2          = 0x0050,
178         .program        = 0x1080,
179         .read_status    = 0x0070,
180         .read_id        = 0x0090,
181         .erase          = 0xD060,
182         .reset          = 0x00FF,
183         .lock           = 0x002A,
184         .unlock         = 0x2423,
185         .lock_status    = 0x007A,
186 };
187
188 static struct pxa3xx_nand_cmdset largepage_cmdset = {
189         .read1          = 0x3000,
190         .read2          = 0x0050,
191         .program        = 0x1080,
192         .read_status    = 0x0070,
193         .read_id        = 0x0090,
194         .erase          = 0xD060,
195         .reset          = 0x00FF,
196         .lock           = 0x002A,
197         .unlock         = 0x2423,
198         .lock_status    = 0x007A,
199 };
200
201 static struct pxa3xx_nand_timing samsung512MbX16_timing = {
202         .tCH    = 10,
203         .tCS    = 0,
204         .tWH    = 20,
205         .tWP    = 40,
206         .tRH    = 30,
207         .tRP    = 40,
208         .tR     = 11123,
209         .tWHR   = 110,
210         .tAR    = 10,
211 };
212
213 static struct pxa3xx_nand_flash samsung512MbX16 = {
214         .timing         = &samsung512MbX16_timing,
215         .cmdset         = &smallpage_cmdset,
216         .page_per_block = 32,
217         .page_size      = 512,
218         .flash_width    = 16,
219         .dfc_width      = 16,
220         .num_blocks     = 4096,
221         .chip_id        = 0x46ec,
222 };
223
224 static struct pxa3xx_nand_timing micron_timing = {
225         .tCH    = 10,
226         .tCS    = 25,
227         .tWH    = 15,
228         .tWP    = 25,
229         .tRH    = 15,
230         .tRP    = 25,
231         .tR     = 25000,
232         .tWHR   = 60,
233         .tAR    = 10,
234 };
235
236 static struct pxa3xx_nand_flash micron1GbX8 = {
237         .timing         = &micron_timing,
238         .cmdset         = &largepage_cmdset,
239         .page_per_block = 64,
240         .page_size      = 2048,
241         .flash_width    = 8,
242         .dfc_width      = 8,
243         .num_blocks     = 1024,
244         .chip_id        = 0xa12c,
245 };
246
247 static struct pxa3xx_nand_flash micron1GbX16 = {
248         .timing         = &micron_timing,
249         .cmdset         = &largepage_cmdset,
250         .page_per_block = 64,
251         .page_size      = 2048,
252         .flash_width    = 16,
253         .dfc_width      = 16,
254         .num_blocks     = 1024,
255         .chip_id        = 0xb12c,
256 };
257
258 static struct pxa3xx_nand_timing stm2GbX16_timing = {
259         .tCH = 10,
260         .tCS = 35,
261         .tWH = 15,
262         .tWP = 25,
263         .tRH = 15,
264         .tRP = 25,
265         .tR = 25000,
266         .tWHR = 60,
267         .tAR = 10,
268 };
269
270 static struct pxa3xx_nand_flash stm2GbX16 = {
271         .timing = &stm2GbX16_timing,
272         .cmdset = &largepage_cmdset,
273         .page_per_block = 64,
274         .page_size = 2048,
275         .flash_width = 16,
276         .dfc_width = 16,
277         .num_blocks = 2048,
278         .chip_id = 0xba20,
279 };
280
281 static struct pxa3xx_nand_flash *builtin_flash_types[] = {
282         &samsung512MbX16,
283         &micron1GbX8,
284         &micron1GbX16,
285         &stm2GbX16,
286 };
287 #endif /* CONFIG_MTD_NAND_PXA3xx_BUILTIN */
288
289 #define NDTR0_tCH(c)    (min((c), 7) << 19)
290 #define NDTR0_tCS(c)    (min((c), 7) << 16)
291 #define NDTR0_tWH(c)    (min((c), 7) << 11)
292 #define NDTR0_tWP(c)    (min((c), 7) << 8)
293 #define NDTR0_tRH(c)    (min((c), 7) << 3)
294 #define NDTR0_tRP(c)    (min((c), 7) << 0)
295
296 #define NDTR1_tR(c)     (min((c), 65535) << 16)
297 #define NDTR1_tWHR(c)   (min((c), 15) << 4)
298 #define NDTR1_tAR(c)    (min((c), 15) << 0)
299
300 /* convert nano-seconds to nand flash controller clock cycles */
301 #define ns2cycle(ns, clk)       (int)(((ns) * (clk / 1000000) / 1000) + 1)
302
303 static void pxa3xx_nand_set_timing(struct pxa3xx_nand_info *info,
304                                    const struct pxa3xx_nand_timing *t)
305 {
306         unsigned long nand_clk = clk_get_rate(info->clk);
307         uint32_t ndtr0, ndtr1;
308
309         ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
310                 NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
311                 NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
312                 NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
313                 NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
314                 NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
315
316         ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
317                 NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
318                 NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
319
320         nand_writel(info, NDTR0CS0, ndtr0);
321         nand_writel(info, NDTR1CS0, ndtr1);
322 }
323
324 #define WAIT_EVENT_TIMEOUT      10
325
326 static int wait_for_event(struct pxa3xx_nand_info *info, uint32_t event)
327 {
328         int timeout = WAIT_EVENT_TIMEOUT;
329         uint32_t ndsr;
330
331         while (timeout--) {
332                 ndsr = nand_readl(info, NDSR) & NDSR_MASK;
333                 if (ndsr & event) {
334                         nand_writel(info, NDSR, ndsr);
335                         return 0;
336                 }
337                 udelay(10);
338         }
339
340         return -ETIMEDOUT;
341 }
342
343 static int prepare_read_prog_cmd(struct pxa3xx_nand_info *info,
344                         uint16_t cmd, int column, int page_addr)
345 {
346         const struct pxa3xx_nand_flash *f = info->flash_info;
347         const struct pxa3xx_nand_cmdset *cmdset = f->cmdset;
348
349         /* calculate data size */
350         switch (f->page_size) {
351         case 2048:
352                 info->data_size = (info->use_ecc) ? 2088 : 2112;
353                 break;
354         case 512:
355                 info->data_size = (info->use_ecc) ? 520 : 528;
356                 break;
357         default:
358                 return -EINVAL;
359         }
360
361         /* generate values for NDCBx registers */
362         info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
363         info->ndcb1 = 0;
364         info->ndcb2 = 0;
365         info->ndcb0 |= NDCB0_ADDR_CYC(info->row_addr_cycles + info->col_addr_cycles);
366
367         if (info->col_addr_cycles == 2) {
368                 /* large block, 2 cycles for column address
369                  * row address starts from 3rd cycle
370                  */
371                 info->ndcb1 |= (page_addr << 16) | (column & 0xffff);
372                 if (info->row_addr_cycles == 3)
373                         info->ndcb2 = (page_addr >> 16) & 0xff;
374         } else
375                 /* small block, 1 cycles for column address
376                  * row address starts from 2nd cycle
377                  */
378                 info->ndcb1 = (page_addr << 8) | (column & 0xff);
379
380         if (cmd == cmdset->program)
381                 info->ndcb0 |= NDCB0_CMD_TYPE(1) | NDCB0_AUTO_RS;
382
383         return 0;
384 }
385
386 static int prepare_erase_cmd(struct pxa3xx_nand_info *info,
387                         uint16_t cmd, int page_addr)
388 {
389         info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
390         info->ndcb0 |= NDCB0_CMD_TYPE(2) | NDCB0_AUTO_RS | NDCB0_ADDR_CYC(3);
391         info->ndcb1 = page_addr;
392         info->ndcb2 = 0;
393         return 0;
394 }
395
396 static int prepare_other_cmd(struct pxa3xx_nand_info *info, uint16_t cmd)
397 {
398         const struct pxa3xx_nand_cmdset *cmdset = info->flash_info->cmdset;
399
400         info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
401         info->ndcb1 = 0;
402         info->ndcb2 = 0;
403
404         if (cmd == cmdset->read_id) {
405                 info->ndcb0 |= NDCB0_CMD_TYPE(3);
406                 info->data_size = 8;
407         } else if (cmd == cmdset->read_status) {
408                 info->ndcb0 |= NDCB0_CMD_TYPE(4);
409                 info->data_size = 8;
410         } else if (cmd == cmdset->reset || cmd == cmdset->lock ||
411                    cmd == cmdset->unlock) {
412                 info->ndcb0 |= NDCB0_CMD_TYPE(5);
413         } else
414                 return -EINVAL;
415
416         return 0;
417 }
418
419 static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
420 {
421         uint32_t ndcr;
422
423         ndcr = nand_readl(info, NDCR);
424         nand_writel(info, NDCR, ndcr & ~int_mask);
425 }
426
427 static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
428 {
429         uint32_t ndcr;
430
431         ndcr = nand_readl(info, NDCR);
432         nand_writel(info, NDCR, ndcr | int_mask);
433 }
434
435 /* NOTE: it is a must to set ND_RUN firstly, then write command buffer
436  * otherwise, it does not work
437  */
438 static int write_cmd(struct pxa3xx_nand_info *info)
439 {
440         uint32_t ndcr;
441
442         /* clear status bits and run */
443         nand_writel(info, NDSR, NDSR_MASK);
444
445         ndcr = info->reg_ndcr;
446
447         ndcr |= info->use_ecc ? NDCR_ECC_EN : 0;
448         ndcr |= info->use_dma ? NDCR_DMA_EN : 0;
449         ndcr |= NDCR_ND_RUN;
450
451         nand_writel(info, NDCR, ndcr);
452
453         if (wait_for_event(info, NDSR_WRCMDREQ)) {
454                 printk(KERN_ERR "timed out writing command\n");
455                 return -ETIMEDOUT;
456         }
457
458         nand_writel(info, NDCB0, info->ndcb0);
459         nand_writel(info, NDCB0, info->ndcb1);
460         nand_writel(info, NDCB0, info->ndcb2);
461         return 0;
462 }
463
464 static int handle_data_pio(struct pxa3xx_nand_info *info)
465 {
466         int ret, timeout = CHIP_DELAY_TIMEOUT;
467
468         switch (info->state) {
469         case STATE_PIO_WRITING:
470                 __raw_writesl(info->mmio_base + NDDB, info->data_buff,
471                                 info->data_size << 2);
472
473                 enable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
474
475                 ret = wait_for_completion_timeout(&info->cmd_complete, timeout);
476                 if (!ret) {
477                         printk(KERN_ERR "program command time out\n");
478                         return -1;
479                 }
480                 break;
481         case STATE_PIO_READING:
482                 __raw_readsl(info->mmio_base + NDDB, info->data_buff,
483                                 info->data_size << 2);
484                 break;
485         default:
486                 printk(KERN_ERR "%s: invalid state %d\n", __func__,
487                                 info->state);
488                 return -EINVAL;
489         }
490
491         info->state = STATE_READY;
492         return 0;
493 }
494
495 static void start_data_dma(struct pxa3xx_nand_info *info, int dir_out)
496 {
497         struct pxa_dma_desc *desc = info->data_desc;
498         int dma_len = ALIGN(info->data_size, 32);
499
500         desc->ddadr = DDADR_STOP;
501         desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
502
503         if (dir_out) {
504                 desc->dsadr = info->data_buff_phys;
505                 desc->dtadr = NDDB_DMA_ADDR;
506                 desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG;
507         } else {
508                 desc->dtadr = info->data_buff_phys;
509                 desc->dsadr = NDDB_DMA_ADDR;
510                 desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
511         }
512
513         DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch;
514         DDADR(info->data_dma_ch) = info->data_desc_addr;
515         DCSR(info->data_dma_ch) |= DCSR_RUN;
516 }
517
518 static void pxa3xx_nand_data_dma_irq(int channel, void *data)
519 {
520         struct pxa3xx_nand_info *info = data;
521         uint32_t dcsr;
522
523         dcsr = DCSR(channel);
524         DCSR(channel) = dcsr;
525
526         if (dcsr & DCSR_BUSERR) {
527                 info->retcode = ERR_DMABUSERR;
528                 complete(&info->cmd_complete);
529         }
530
531         if (info->state == STATE_DMA_WRITING) {
532                 info->state = STATE_DMA_DONE;
533                 enable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
534         } else {
535                 info->state = STATE_READY;
536                 complete(&info->cmd_complete);
537         }
538 }
539
540 static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
541 {
542         struct pxa3xx_nand_info *info = devid;
543         unsigned int status;
544
545         status = nand_readl(info, NDSR);
546
547         if (status & (NDSR_RDDREQ | NDSR_DBERR)) {
548                 if (status & NDSR_DBERR)
549                         info->retcode = ERR_DBERR;
550
551                 disable_int(info, NDSR_RDDREQ | NDSR_DBERR);
552
553                 if (info->use_dma) {
554                         info->state = STATE_DMA_READING;
555                         start_data_dma(info, 0);
556                 } else {
557                         info->state = STATE_PIO_READING;
558                         complete(&info->cmd_complete);
559                 }
560         } else if (status & NDSR_WRDREQ) {
561                 disable_int(info, NDSR_WRDREQ);
562                 if (info->use_dma) {
563                         info->state = STATE_DMA_WRITING;
564                         start_data_dma(info, 1);
565                 } else {
566                         info->state = STATE_PIO_WRITING;
567                         complete(&info->cmd_complete);
568                 }
569         } else if (status & (NDSR_CS0_BBD | NDSR_CS0_CMDD)) {
570                 if (status & NDSR_CS0_BBD)
571                         info->retcode = ERR_BBERR;
572
573                 disable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
574                 info->state = STATE_READY;
575                 complete(&info->cmd_complete);
576         }
577         nand_writel(info, NDSR, status);
578         return IRQ_HANDLED;
579 }
580
581 static int pxa3xx_nand_do_cmd(struct pxa3xx_nand_info *info, uint32_t event)
582 {
583         uint32_t ndcr;
584         int ret, timeout = CHIP_DELAY_TIMEOUT;
585
586         if (write_cmd(info)) {
587                 info->retcode = ERR_SENDCMD;
588                 goto fail_stop;
589         }
590
591         info->state = STATE_CMD_HANDLE;
592
593         enable_int(info, event);
594
595         ret = wait_for_completion_timeout(&info->cmd_complete, timeout);
596         if (!ret) {
597                 printk(KERN_ERR "command execution timed out\n");
598                 info->retcode = ERR_SENDCMD;
599                 goto fail_stop;
600         }
601
602         if (info->use_dma == 0 && info->data_size > 0)
603                 if (handle_data_pio(info))
604                         goto fail_stop;
605
606         return 0;
607
608 fail_stop:
609         ndcr = nand_readl(info, NDCR);
610         nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
611         udelay(10);
612         return -ETIMEDOUT;
613 }
614
615 static int pxa3xx_nand_dev_ready(struct mtd_info *mtd)
616 {
617         struct pxa3xx_nand_info *info = mtd->priv;
618         return (nand_readl(info, NDSR) & NDSR_RDY) ? 1 : 0;
619 }
620
621 static inline int is_buf_blank(uint8_t *buf, size_t len)
622 {
623         for (; len > 0; len--)
624                 if (*buf++ != 0xff)
625                         return 0;
626         return 1;
627 }
628
629 static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
630                                 int column, int page_addr)
631 {
632         struct pxa3xx_nand_info *info = mtd->priv;
633         const struct pxa3xx_nand_flash *flash_info = info->flash_info;
634         const struct pxa3xx_nand_cmdset *cmdset = flash_info->cmdset;
635         int ret;
636
637         info->use_dma = (use_dma) ? 1 : 0;
638         info->use_ecc = 0;
639         info->data_size = 0;
640         info->state = STATE_READY;
641
642         init_completion(&info->cmd_complete);
643
644         switch (command) {
645         case NAND_CMD_READOOB:
646                 /* disable HW ECC to get all the OOB data */
647                 info->buf_count = mtd->writesize + mtd->oobsize;
648                 info->buf_start = mtd->writesize + column;
649
650                 if (prepare_read_prog_cmd(info, cmdset->read1, column, page_addr))
651                         break;
652
653                 pxa3xx_nand_do_cmd(info, NDSR_RDDREQ | NDSR_DBERR);
654
655                 /* We only are OOB, so if the data has error, does not matter */
656                 if (info->retcode == ERR_DBERR)
657                         info->retcode = ERR_NONE;
658                 break;
659
660         case NAND_CMD_READ0:
661                 info->use_ecc = 1;
662                 info->retcode = ERR_NONE;
663                 info->buf_start = column;
664                 info->buf_count = mtd->writesize + mtd->oobsize;
665                 memset(info->data_buff, 0xFF, info->buf_count);
666
667                 if (prepare_read_prog_cmd(info, cmdset->read1, column, page_addr))
668                         break;
669
670                 pxa3xx_nand_do_cmd(info, NDSR_RDDREQ | NDSR_DBERR);
671
672                 if (info->retcode == ERR_DBERR) {
673                         /* for blank page (all 0xff), HW will calculate its ECC as
674                          * 0, which is different from the ECC information within
675                          * OOB, ignore such double bit errors
676                          */
677                         if (is_buf_blank(info->data_buff, mtd->writesize))
678                                 info->retcode = ERR_NONE;
679                 }
680                 break;
681         case NAND_CMD_SEQIN:
682                 info->buf_start = column;
683                 info->buf_count = mtd->writesize + mtd->oobsize;
684                 memset(info->data_buff, 0xff, info->buf_count);
685
686                 /* save column/page_addr for next CMD_PAGEPROG */
687                 info->seqin_column = column;
688                 info->seqin_page_addr = page_addr;
689                 break;
690         case NAND_CMD_PAGEPROG:
691                 info->use_ecc = (info->seqin_column >= mtd->writesize) ? 0 : 1;
692
693                 if (prepare_read_prog_cmd(info, cmdset->program,
694                                 info->seqin_column, info->seqin_page_addr))
695                         break;
696
697                 pxa3xx_nand_do_cmd(info, NDSR_WRDREQ);
698                 break;
699         case NAND_CMD_ERASE1:
700                 if (prepare_erase_cmd(info, cmdset->erase, page_addr))
701                         break;
702
703                 pxa3xx_nand_do_cmd(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
704                 break;
705         case NAND_CMD_ERASE2:
706                 break;
707         case NAND_CMD_READID:
708         case NAND_CMD_STATUS:
709                 info->use_dma = 0;      /* force PIO read */
710                 info->buf_start = 0;
711                 info->buf_count = (command == NAND_CMD_READID) ?
712                                 info->read_id_bytes : 1;
713
714                 if (prepare_other_cmd(info, (command == NAND_CMD_READID) ?
715                                 cmdset->read_id : cmdset->read_status))
716                         break;
717
718                 pxa3xx_nand_do_cmd(info, NDSR_RDDREQ);
719                 break;
720         case NAND_CMD_RESET:
721                 if (prepare_other_cmd(info, cmdset->reset))
722                         break;
723
724                 ret = pxa3xx_nand_do_cmd(info, NDSR_CS0_CMDD);
725                 if (ret == 0) {
726                         int timeout = 2;
727                         uint32_t ndcr;
728
729                         while (timeout--) {
730                                 if (nand_readl(info, NDSR) & NDSR_RDY)
731                                         break;
732                                 msleep(10);
733                         }
734
735                         ndcr = nand_readl(info, NDCR);
736                         nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
737                 }
738                 break;
739         default:
740                 printk(KERN_ERR "non-supported command.\n");
741                 break;
742         }
743
744         if (info->retcode == ERR_DBERR) {
745                 printk(KERN_ERR "double bit error @ page %08x\n", page_addr);
746                 info->retcode = ERR_NONE;
747         }
748 }
749
750 static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
751 {
752         struct pxa3xx_nand_info *info = mtd->priv;
753         char retval = 0xFF;
754
755         if (info->buf_start < info->buf_count)
756                 /* Has just send a new command? */
757                 retval = info->data_buff[info->buf_start++];
758
759         return retval;
760 }
761
762 static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
763 {
764         struct pxa3xx_nand_info *info = mtd->priv;
765         u16 retval = 0xFFFF;
766
767         if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
768                 retval = *((u16 *)(info->data_buff+info->buf_start));
769                 info->buf_start += 2;
770         }
771         return retval;
772 }
773
774 static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
775 {
776         struct pxa3xx_nand_info *info = mtd->priv;
777         int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
778
779         memcpy(buf, info->data_buff + info->buf_start, real_len);
780         info->buf_start += real_len;
781 }
782
783 static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
784                 const uint8_t *buf, int len)
785 {
786         struct pxa3xx_nand_info *info = mtd->priv;
787         int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
788
789         memcpy(info->data_buff + info->buf_start, buf, real_len);
790         info->buf_start += real_len;
791 }
792
793 static int pxa3xx_nand_verify_buf(struct mtd_info *mtd,
794                 const uint8_t *buf, int len)
795 {
796         return 0;
797 }
798
799 static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
800 {
801         return;
802 }
803
804 static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
805 {
806         struct pxa3xx_nand_info *info = mtd->priv;
807
808         /* pxa3xx_nand_send_command has waited for command complete */
809         if (this->state == FL_WRITING || this->state == FL_ERASING) {
810                 if (info->retcode == ERR_NONE)
811                         return 0;
812                 else {
813                         /*
814                          * any error make it return 0x01 which will tell
815                          * the caller the erase and write fail
816                          */
817                         return 0x01;
818                 }
819         }
820
821         return 0;
822 }
823
824 static void pxa3xx_nand_ecc_hwctl(struct mtd_info *mtd, int mode)
825 {
826         return;
827 }
828
829 static int pxa3xx_nand_ecc_calculate(struct mtd_info *mtd,
830                 const uint8_t *dat, uint8_t *ecc_code)
831 {
832         return 0;
833 }
834
835 static int pxa3xx_nand_ecc_correct(struct mtd_info *mtd,
836                 uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc)
837 {
838         struct pxa3xx_nand_info *info = mtd->priv;
839         /*
840          * Any error include ERR_SEND_CMD, ERR_DBERR, ERR_BUSERR, we
841          * consider it as a ecc error which will tell the caller the
842          * read fail We have distinguish all the errors, but the
843          * nand_read_ecc only check this function return value
844          */
845         if (info->retcode != ERR_NONE)
846                 return -1;
847
848         return 0;
849 }
850
851 static int __readid(struct pxa3xx_nand_info *info, uint32_t *id)
852 {
853         const struct pxa3xx_nand_flash *f = info->flash_info;
854         const struct pxa3xx_nand_cmdset *cmdset = f->cmdset;
855         uint32_t ndcr;
856         uint8_t  id_buff[8];
857
858         if (prepare_other_cmd(info, cmdset->read_id)) {
859                 printk(KERN_ERR "failed to prepare command\n");
860                 return -EINVAL;
861         }
862
863         /* Send command */
864         if (write_cmd(info))
865                 goto fail_timeout;
866
867         /* Wait for CMDDM(command done successfully) */
868         if (wait_for_event(info, NDSR_RDDREQ))
869                 goto fail_timeout;
870
871         __raw_readsl(info->mmio_base + NDDB, id_buff, 2);
872         *id = id_buff[0] | (id_buff[1] << 8);
873         return 0;
874
875 fail_timeout:
876         ndcr = nand_readl(info, NDCR);
877         nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
878         udelay(10);
879         return -ETIMEDOUT;
880 }
881
882 static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
883                                     const struct pxa3xx_nand_flash *f)
884 {
885         struct platform_device *pdev = info->pdev;
886         struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
887         uint32_t ndcr = 0x00000FFF; /* disable all interrupts */
888
889         if (f->page_size != 2048 && f->page_size != 512)
890                 return -EINVAL;
891
892         if (f->flash_width != 16 && f->flash_width != 8)
893                 return -EINVAL;
894
895         /* calculate flash information */
896         info->oob_size = (f->page_size == 2048) ? 64 : 16;
897         info->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
898
899         /* calculate addressing information */
900         info->col_addr_cycles = (f->page_size == 2048) ? 2 : 1;
901
902         if (f->num_blocks * f->page_per_block > 65536)
903                 info->row_addr_cycles = 3;
904         else
905                 info->row_addr_cycles = 2;
906
907         ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
908         ndcr |= (info->col_addr_cycles == 2) ? NDCR_RA_START : 0;
909         ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0;
910         ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0;
911         ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0;
912         ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
913
914         ndcr |= NDCR_RD_ID_CNT(info->read_id_bytes);
915         ndcr |= NDCR_SPARE_EN; /* enable spare by default */
916
917         info->reg_ndcr = ndcr;
918
919         pxa3xx_nand_set_timing(info, f->timing);
920         info->flash_info = f;
921         return 0;
922 }
923
924 static int pxa3xx_nand_detect_flash(struct pxa3xx_nand_info *info,
925                                     const struct pxa3xx_nand_platform_data *pdata)
926 {
927         const struct pxa3xx_nand_flash *f;
928         uint32_t id = -1;
929         int i;
930
931         for (i = 0; i<pdata->num_flash; ++i) {
932                 f = pdata->flash + i;
933
934                 if (pxa3xx_nand_config_flash(info, f))
935                         continue;
936
937                 if (__readid(info, &id))
938                         continue;
939
940                 if (id == f->chip_id)
941                         return 0;
942         }
943
944 #ifdef CONFIG_MTD_NAND_PXA3xx_BUILTIN
945         for (i = 0; i < ARRAY_SIZE(builtin_flash_types); i++) {
946
947                 f = builtin_flash_types[i];
948
949                 if (pxa3xx_nand_config_flash(info, f))
950                         continue;
951
952                 if (__readid(info, &id))
953                         continue;
954
955                 if (id == f->chip_id)
956                         return 0;
957         }
958 #endif
959
960         dev_warn(&info->pdev->dev,
961                  "failed to detect configured nand flash; found %04x instead of\n",
962                  id);
963         return -ENODEV;
964 }
965
966 /* the maximum possible buffer size for large page with OOB data
967  * is: 2048 + 64 = 2112 bytes, allocate a page here for both the
968  * data buffer and the DMA descriptor
969  */
970 #define MAX_BUFF_SIZE   PAGE_SIZE
971
972 static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
973 {
974         struct platform_device *pdev = info->pdev;
975         int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc);
976
977         if (use_dma == 0) {
978                 info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
979                 if (info->data_buff == NULL)
980                         return -ENOMEM;
981                 return 0;
982         }
983
984         info->data_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE,
985                                 &info->data_buff_phys, GFP_KERNEL);
986         if (info->data_buff == NULL) {
987                 dev_err(&pdev->dev, "failed to allocate dma buffer\n");
988                 return -ENOMEM;
989         }
990
991         info->data_buff_size = MAX_BUFF_SIZE;
992         info->data_desc = (void *)info->data_buff + data_desc_offset;
993         info->data_desc_addr = info->data_buff_phys + data_desc_offset;
994
995         info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW,
996                                 pxa3xx_nand_data_dma_irq, info);
997         if (info->data_dma_ch < 0) {
998                 dev_err(&pdev->dev, "failed to request data dma\n");
999                 dma_free_coherent(&pdev->dev, info->data_buff_size,
1000                                 info->data_buff, info->data_buff_phys);
1001                 return info->data_dma_ch;
1002         }
1003
1004         return 0;
1005 }
1006
1007 static struct nand_ecclayout hw_smallpage_ecclayout = {
1008         .eccbytes = 6,
1009         .eccpos = {8, 9, 10, 11, 12, 13 },
1010         .oobfree = { {2, 6} }
1011 };
1012
1013 static struct nand_ecclayout hw_largepage_ecclayout = {
1014         .eccbytes = 24,
1015         .eccpos = {
1016                 40, 41, 42, 43, 44, 45, 46, 47,
1017                 48, 49, 50, 51, 52, 53, 54, 55,
1018                 56, 57, 58, 59, 60, 61, 62, 63},
1019         .oobfree = { {2, 38} }
1020 };
1021
1022 static void pxa3xx_nand_init_mtd(struct mtd_info *mtd,
1023                                  struct pxa3xx_nand_info *info)
1024 {
1025         const struct pxa3xx_nand_flash *f = info->flash_info;
1026         struct nand_chip *this = &info->nand_chip;
1027
1028         this->options = (f->flash_width == 16) ? NAND_BUSWIDTH_16: 0;
1029
1030         this->waitfunc          = pxa3xx_nand_waitfunc;
1031         this->select_chip       = pxa3xx_nand_select_chip;
1032         this->dev_ready         = pxa3xx_nand_dev_ready;
1033         this->cmdfunc           = pxa3xx_nand_cmdfunc;
1034         this->read_word         = pxa3xx_nand_read_word;
1035         this->read_byte         = pxa3xx_nand_read_byte;
1036         this->read_buf          = pxa3xx_nand_read_buf;
1037         this->write_buf         = pxa3xx_nand_write_buf;
1038         this->verify_buf        = pxa3xx_nand_verify_buf;
1039
1040         this->ecc.mode          = NAND_ECC_HW;
1041         this->ecc.hwctl         = pxa3xx_nand_ecc_hwctl;
1042         this->ecc.calculate     = pxa3xx_nand_ecc_calculate;
1043         this->ecc.correct       = pxa3xx_nand_ecc_correct;
1044         this->ecc.size          = f->page_size;
1045
1046         if (f->page_size == 2048)
1047                 this->ecc.layout = &hw_largepage_ecclayout;
1048         else
1049                 this->ecc.layout = &hw_smallpage_ecclayout;
1050
1051         this->chip_delay = 25;
1052 }
1053
1054 static int pxa3xx_nand_probe(struct platform_device *pdev)
1055 {
1056         struct pxa3xx_nand_platform_data *pdata;
1057         struct pxa3xx_nand_info *info;
1058         struct nand_chip *this;
1059         struct mtd_info *mtd;
1060         struct resource *r;
1061         int ret = 0, irq;
1062
1063         pdata = pdev->dev.platform_data;
1064
1065         if (!pdata) {
1066                 dev_err(&pdev->dev, "no platform data defined\n");
1067                 return -ENODEV;
1068         }
1069
1070         mtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct pxa3xx_nand_info),
1071                         GFP_KERNEL);
1072         if (!mtd) {
1073                 dev_err(&pdev->dev, "failed to allocate memory\n");
1074                 return -ENOMEM;
1075         }
1076
1077         info = (struct pxa3xx_nand_info *)(&mtd[1]);
1078         info->pdev = pdev;
1079
1080         this = &info->nand_chip;
1081         mtd->priv = info;
1082
1083         info->clk = clk_get(&pdev->dev, "NANDCLK");
1084         if (IS_ERR(info->clk)) {
1085                 dev_err(&pdev->dev, "failed to get nand clock\n");
1086                 ret = PTR_ERR(info->clk);
1087                 goto fail_free_mtd;
1088         }
1089         clk_enable(info->clk);
1090
1091         r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1092         if (r == NULL) {
1093                 dev_err(&pdev->dev, "no resource defined for data DMA\n");
1094                 ret = -ENXIO;
1095                 goto fail_put_clk;
1096         }
1097         info->drcmr_dat = r->start;
1098
1099         r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1100         if (r == NULL) {
1101                 dev_err(&pdev->dev, "no resource defined for command DMA\n");
1102                 ret = -ENXIO;
1103                 goto fail_put_clk;
1104         }
1105         info->drcmr_cmd = r->start;
1106
1107         irq = platform_get_irq(pdev, 0);
1108         if (irq < 0) {
1109                 dev_err(&pdev->dev, "no IRQ resource defined\n");
1110                 ret = -ENXIO;
1111                 goto fail_put_clk;
1112         }
1113
1114         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1115         if (r == NULL) {
1116                 dev_err(&pdev->dev, "no IO memory resource defined\n");
1117                 ret = -ENODEV;
1118                 goto fail_put_clk;
1119         }
1120
1121         r = request_mem_region(r->start, r->end - r->start + 1, pdev->name);
1122         if (r == NULL) {
1123                 dev_err(&pdev->dev, "failed to request memory resource\n");
1124                 ret = -EBUSY;
1125                 goto fail_put_clk;
1126         }
1127
1128         info->mmio_base = ioremap(r->start, r->end - r->start + 1);
1129         if (info->mmio_base == NULL) {
1130                 dev_err(&pdev->dev, "ioremap() failed\n");
1131                 ret = -ENODEV;
1132                 goto fail_free_res;
1133         }
1134
1135         ret = pxa3xx_nand_init_buff(info);
1136         if (ret)
1137                 goto fail_free_io;
1138
1139         ret = request_irq(IRQ_NAND, pxa3xx_nand_irq, IRQF_DISABLED,
1140                                 pdev->name, info);
1141         if (ret < 0) {
1142                 dev_err(&pdev->dev, "failed to request IRQ\n");
1143                 goto fail_free_buf;
1144         }
1145
1146         ret = pxa3xx_nand_detect_flash(info, pdata);
1147         if (ret) {
1148                 dev_err(&pdev->dev, "failed to detect flash\n");
1149                 ret = -ENODEV;
1150                 goto fail_free_irq;
1151         }
1152
1153         pxa3xx_nand_init_mtd(mtd, info);
1154
1155         platform_set_drvdata(pdev, mtd);
1156
1157         if (nand_scan(mtd, 1)) {
1158                 dev_err(&pdev->dev, "failed to scan nand\n");
1159                 ret = -ENXIO;
1160                 goto fail_free_irq;
1161         }
1162
1163         return add_mtd_partitions(mtd, pdata->parts, pdata->nr_parts);
1164
1165 fail_free_irq:
1166         free_irq(IRQ_NAND, info);
1167 fail_free_buf:
1168         if (use_dma) {
1169                 pxa_free_dma(info->data_dma_ch);
1170                 dma_free_coherent(&pdev->dev, info->data_buff_size,
1171                         info->data_buff, info->data_buff_phys);
1172         } else
1173                 kfree(info->data_buff);
1174 fail_free_io:
1175         iounmap(info->mmio_base);
1176 fail_free_res:
1177         release_mem_region(r->start, r->end - r->start + 1);
1178 fail_put_clk:
1179         clk_disable(info->clk);
1180         clk_put(info->clk);
1181 fail_free_mtd:
1182         kfree(mtd);
1183         return ret;
1184 }
1185
1186 static int pxa3xx_nand_remove(struct platform_device *pdev)
1187 {
1188         struct mtd_info *mtd = platform_get_drvdata(pdev);
1189         struct pxa3xx_nand_info *info = mtd->priv;
1190
1191         platform_set_drvdata(pdev, NULL);
1192
1193         del_mtd_device(mtd);
1194         del_mtd_partitions(mtd);
1195         free_irq(IRQ_NAND, info);
1196         if (use_dma) {
1197                 pxa_free_dma(info->data_dma_ch);
1198                 dma_free_writecombine(&pdev->dev, info->data_buff_size,
1199                                 info->data_buff, info->data_buff_phys);
1200         } else
1201                 kfree(info->data_buff);
1202         kfree(mtd);
1203         return 0;
1204 }
1205
1206 #ifdef CONFIG_PM
1207 static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state)
1208 {
1209         struct mtd_info *mtd = (struct mtd_info *)platform_get_drvdata(pdev);
1210         struct pxa3xx_nand_info *info = mtd->priv;
1211
1212         if (info->state != STATE_READY) {
1213                 dev_err(&pdev->dev, "driver busy, state = %d\n", info->state);
1214                 return -EAGAIN;
1215         }
1216
1217         return 0;
1218 }
1219
1220 static int pxa3xx_nand_resume(struct platform_device *pdev)
1221 {
1222         struct mtd_info *mtd = (struct mtd_info *)platform_get_drvdata(pdev);
1223         struct pxa3xx_nand_info *info = mtd->priv;
1224
1225         clk_enable(info->clk);
1226
1227         return pxa3xx_nand_config_flash(info, info->flash_info);
1228 }
1229 #else
1230 #define pxa3xx_nand_suspend     NULL
1231 #define pxa3xx_nand_resume      NULL
1232 #endif
1233
1234 static struct platform_driver pxa3xx_nand_driver = {
1235         .driver = {
1236                 .name   = "pxa3xx-nand",
1237         },
1238         .probe          = pxa3xx_nand_probe,
1239         .remove         = pxa3xx_nand_remove,
1240         .suspend        = pxa3xx_nand_suspend,
1241         .resume         = pxa3xx_nand_resume,
1242 };
1243
1244 static int __init pxa3xx_nand_init(void)
1245 {
1246         return platform_driver_register(&pxa3xx_nand_driver);
1247 }
1248 module_init(pxa3xx_nand_init);
1249
1250 static void __exit pxa3xx_nand_exit(void)
1251 {
1252         platform_driver_unregister(&pxa3xx_nand_driver);
1253 }
1254 module_exit(pxa3xx_nand_exit);
1255
1256 MODULE_LICENSE("GPL");
1257 MODULE_DESCRIPTION("PXA3xx NAND controller driver");