1 # drivers/mtd/chips/Kconfig
3 menu "RAM/ROM/Flash chip drivers"
7 tristate "Detect flash chips by Common Flash Interface (CFI) probe"
11 The Common Flash Interface specification was developed by Intel,
12 AMD and other flash manufactures that provides a universal method
13 for probing the capabilities of flash devices. If you wish to
14 support any device that is CFI-compliant, you need to enable this
15 option. Visit <http://www.amd.com/products/nvd/overview/cfi.html>
16 for more information on CFI.
19 tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
22 This option enables JEDEC-style probing of flash chips which are not
23 compatible with the Common Flash Interface, but will use the common
24 CFI-targetted flash drivers for any chips which are identified which
25 are in fact compatible in all but the probe method. This actually
26 covers most AMD/Fujitsu-compatible chips and also non-CFI
32 config MTD_CFI_ADV_OPTIONS
33 bool "Flash chip driver advanced configuration options"
34 depends on MTD_GEN_PROBE
36 If you need to specify a specific endianness for access to flash
37 chips, or if you wish to reduce the size of the kernel by including
38 support for only specific arrangements of flash chips, say 'Y'. This
39 option does not directly affect the code, but will enable other
40 configuration options which allow you to do so.
45 prompt "Flash cmd/query data swapping"
46 depends on MTD_CFI_ADV_OPTIONS
47 default MTD_CFI_NOSWAP
52 This option defines the way in which the CPU attempts to arrange
53 data bits when writing the 'magic' commands to the chips. Saying
54 'NO', which is the default when CONFIG_MTD_CFI_ADV_OPTIONS isn't
55 enabled, means that the CPU will not do any swapping; the chips
56 are expected to be wired to the CPU in 'host-endian' form.
57 Specific arrangements are possible with the BIG_ENDIAN_BYTE and
58 LITTLE_ENDIAN_BYTE, if the bytes are reversed.
60 If you have a LART, on which the data (and address) lines were
61 connected in a fashion which ensured that the nets were as short
62 as possible, resulting in a bit-shuffling which seems utterly
63 random to the untrained eye, you need the LART_ENDIAN_BYTE option.
65 Yes, there really exists something sicker than PDP-endian :)
67 config MTD_CFI_BE_BYTE_SWAP
68 bool "BIG_ENDIAN_BYTE"
70 config MTD_CFI_LE_BYTE_SWAP
71 bool "LITTLE_ENDIAN_BYTE"
75 config MTD_CFI_GEOMETRY
76 bool "Specific CFI Flash geometry selection"
77 depends on MTD_CFI_ADV_OPTIONS
79 This option does not affect the code directly, but will enable
80 some other configuration options which would allow you to reduce
81 the size of the kernel by including support for only certain
82 arrangements of CFI chips. If unsure, say 'N' and all options
83 which are supported by the current code will be enabled.
85 config MTD_MAP_BANK_WIDTH_1
86 bool "Support 8-bit buswidth" if MTD_CFI_GEOMETRY
89 If you wish to support CFI devices on a physical bus which is
92 config MTD_MAP_BANK_WIDTH_2
93 bool "Support 16-bit buswidth" if MTD_CFI_GEOMETRY
96 If you wish to support CFI devices on a physical bus which is
97 16 bits wide, say 'Y'.
99 config MTD_MAP_BANK_WIDTH_4
100 bool "Support 32-bit buswidth" if MTD_CFI_GEOMETRY
103 If you wish to support CFI devices on a physical bus which is
104 32 bits wide, say 'Y'.
106 config MTD_MAP_BANK_WIDTH_8
107 bool "Support 64-bit buswidth" if MTD_CFI_GEOMETRY
110 If you wish to support CFI devices on a physical bus which is
111 64 bits wide, say 'Y'.
113 config MTD_MAP_BANK_WIDTH_16
114 bool "Support 128-bit buswidth" if MTD_CFI_GEOMETRY
117 If you wish to support CFI devices on a physical bus which is
118 128 bits wide, say 'Y'.
120 config MTD_MAP_BANK_WIDTH_32
121 bool "Support 256-bit buswidth" if MTD_CFI_GEOMETRY
124 If you wish to support CFI devices on a physical bus which is
125 256 bits wide, say 'Y'.
128 bool "Support 1-chip flash interleave" if MTD_CFI_GEOMETRY
131 If your flash chips are not interleaved - i.e. you only have one
132 flash chip addressed by each bus cycle, then say 'Y'.
135 bool "Support 2-chip flash interleave" if MTD_CFI_GEOMETRY
138 If your flash chips are interleaved in pairs - i.e. you have two
139 flash chips addressed by each bus cycle, then say 'Y'.
142 bool "Support 4-chip flash interleave" if MTD_CFI_GEOMETRY
145 If your flash chips are interleaved in fours - i.e. you have four
146 flash chips addressed by each bus cycle, then say 'Y'.
149 bool "Support 8-chip flash interleave" if MTD_CFI_GEOMETRY
152 If your flash chips are interleaved in eights - i.e. you have eight
153 flash chips addressed by each bus cycle, then say 'Y'.
156 bool "Protection Registers aka one-time programmable (OTP) bits"
157 depends on MTD_CFI_ADV_OPTIONS
161 This enables support for reading, writing and locking so called
162 "Protection Registers" present on some flash chips.
163 A subset of them are pre-programmed at the factory with a
164 unique set of values. The rest is user-programmable.
166 The user-programmable Protection Registers contain one-time
167 programmable (OTP) bits; when programmed, register bits cannot be
168 erased. Each Protection Register can be accessed multiple times to
169 program individual bits, as long as the register remains unlocked.
171 Each Protection Register has an associated Lock Register bit. When a
172 Lock Register bit is programmed, the associated Protection Register
173 can only be read; it can no longer be programmed. Additionally,
174 because the Lock Register bits themselves are OTP, when programmed,
175 Lock Register bits cannot be erased. Therefore, when a Protection
176 Register is locked, it cannot be unlocked.
178 This feature should therefore be used with extreme care. Any mistake
179 in the programming of OTP bits will waste them.
181 config MTD_CFI_INTELEXT
182 tristate "Support for Intel/Sharp flash chips"
183 depends on MTD_GEN_PROBE
186 The Common Flash Interface defines a number of different command
187 sets which a CFI-compliant chip may claim to implement. This code
188 provides support for one of those command sets, used on Intel
189 StrataFlash and other parts.
191 config MTD_CFI_AMDSTD
192 tristate "Support for AMD/Fujitsu/Spansion flash chips"
193 depends on MTD_GEN_PROBE
196 The Common Flash Interface defines a number of different command
197 sets which a CFI-compliant chip may claim to implement. This code
198 provides support for one of those command sets, used on chips
199 including the AMD Am29LV320.
202 tristate "Support for ST (Advanced Architecture) flash chips"
203 depends on MTD_GEN_PROBE
206 The Common Flash Interface defines a number of different command
207 sets which a CFI-compliant chip may claim to implement. This code
208 provides support for one of those command sets.
214 tristate "Support for RAM chips in bus mapping"
216 This option enables basic support for RAM chips accessed through
217 a bus mapping driver.
220 tristate "Support for ROM chips in bus mapping"
222 This option enables basic support for ROM chips accessed through
223 a bus mapping driver.
226 tristate "Support for absent chips in bus mapping"
228 This option enables support for a dummy probing driver used to
229 allocated placeholder MTD devices on systems that have socketed
230 or removable media. Use of this driver as a fallback chip probe
231 preserves the expected registration order of MTD device nodes on
232 the system regardless of media presence. Device nodes created
233 with this driver will return -ENODEV upon access.
236 bool "XIP aware MTD support"
237 depends on !SMP && (MTD_CFI_INTELEXT || MTD_CFI_AMDSTD) && EXPERIMENTAL && ARCH_MTD_XIP
238 default y if XIP_KERNEL
240 This allows MTD support to work with flash memory which is also
241 used for XIP purposes. If you're not sure what this is all about