Merge git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/pci-2.6
[linux-2.6] / include / linux / harrier_defs.h
1 /*
2  * include/linux/harrier_defs.h
3  *
4  * Definitions for Motorola MCG Harrier North Bridge & Memory controller
5  *
6  * Author: Dale Farnsworth
7  *         dale.farnsworth@mvista.com
8  *
9  * Extracted from asm-ppc/harrier.h by:
10  *         Randy Vinson
11  *         rvinson@mvista.com
12  *
13  * Copyright 2001-2002 MontaVista Software Inc.
14  *
15  * This program is free software; you can redistribute  it and/or modify it
16  * under  the terms of  the GNU General  Public License as published by the
17  * Free Software Foundation;  either version 2 of the  License, or (at your
18  * option) any later version.
19  */
20
21 #ifndef __ASMPPC_HARRIER_DEFS_H
22 #define __ASMPPC_HARRIER_DEFS_H
23
24 #define HARRIER_DEFAULT_XCSR_BASE       0xfeff0000
25
26 #define HARRIER_VEND_DEV_ID             0x1057480b
27
28 #define HARRIER_VENI_OFF                0x00
29
30 #define HARRIER_REVI_OFF                0x05
31 #define HARRIER_UCTL_OFF                0xd0
32 #define HARRIER_XTAL64_MASK             0x02
33
34 #define HARRIER_MISC_CSR_OFF            0x1c
35 #define HARRIER_RSTOUT                  0x01000000
36 #define HARRIER_SYSCON                  0x08000000
37 #define HARRIER_EREADY                  0x10000000
38 #define HARRIER_ERDYS                   0x20000000
39
40 /* Function exception registers */
41 #define HARRIER_FEEN_OFF                0x40    /* enable */
42 #define HARRIER_FEST_OFF                0x44    /* status */
43 #define HARRIER_FEMA_OFF                0x48    /* mask */
44 #define HARRIER_FECL_OFF                0x4c    /* clear */
45
46 #define HARRIER_FE_DMA                  0x80
47 #define HARRIER_FE_MIDB                 0x40
48 #define HARRIER_FE_MIM0                 0x20
49 #define HARRIER_FE_MIM1                 0x10
50 #define HARRIER_FE_MIP                  0x08
51 #define HARRIER_FE_UA0                  0x04
52 #define HARRIER_FE_UA1                  0x02
53 #define HARRIER_FE_ABT                  0x01
54
55 #define HARRIER_SERIAL_0_OFF            0xc0
56
57 #define HARRIER_MBAR_OFF                0xe0
58 #define HARRIER_MBAR_MSK                0xfffc0000
59 #define HARRIER_MPIC_CSR_OFF            0xe4
60 #define HARRIER_MPIC_OPI_ENABLE         0x40
61 #define HARRIER_MPIC_IFEVP_OFF          0x10200
62 #define HARRIER_MPIC_IFEVP_VECT_MSK     0xff
63 #define HARRIER_MPIC_IFEDE_OFF          0x10210
64
65 /*
66  * Define the Memory Controller register offsets.
67  */
68 #define HARRIER_SDBA_OFF                0x110
69 #define HARRIER_SDBB_OFF                0x114
70 #define HARRIER_SDBC_OFF                0x118
71 #define HARRIER_SDBD_OFF                0x11c
72 #define HARRIER_SDBE_OFF                0x120
73 #define HARRIER_SDBF_OFF                0x124
74 #define HARRIER_SDBG_OFF                0x128
75 #define HARRIER_SDBH_OFF                0x12c
76
77 #define HARRIER_SDB_ENABLE              0x00000100
78 #define HARRIER_SDB_SIZE_MASK           0xf
79 #define HARRIER_SDB_SIZE_SHIFT          16
80 #define HARRIER_SDB_BASE_MASK           0xff
81 #define HARRIER_SDB_BASE_SHIFT          24
82
83 /*
84  * Define outbound register offsets.
85  */
86 #define HARRIER_OTAD0_OFF               0x220
87 #define HARRIER_OTOF0_OFF               0x224
88 #define HARRIER_OTAD1_OFF               0x228
89 #define HARRIER_OTOF1_OFF               0x22c
90 #define HARRIER_OTAD2_OFF               0x230
91 #define HARRIER_OTOF2_OFF               0x234
92 #define HARRIER_OTAD3_OFF               0x238
93 #define HARRIER_OTOF3_OFF               0x23c
94
95 #define HARRIER_OTADX_START_MSK         0xffff0000UL
96 #define HARRIER_OTADX_END_MSK           0x0000ffffUL
97
98 #define HARRIER_OTOFX_OFF_MSK           0xffff0000UL
99 #define HARRIER_OTOFX_ENA               0x80UL
100 #define HARRIER_OTOFX_WPE               0x10UL
101 #define HARRIER_OTOFX_SGE               0x08UL
102 #define HARRIER_OTOFX_RAE               0x04UL
103 #define HARRIER_OTOFX_MEM               0x02UL
104 #define HARRIER_OTOFX_IOM               0x01UL
105
106 /*
107  * Define generic message passing register offsets
108  */
109 /* Mirrored registers (visible from both PowerPC and PCI space) */
110 #define HARRIER_XCSR_MP_BASE_OFF        0x290   /* base offset in XCSR space */
111 #define HARRIER_PMEP_MP_BASE_OFF        0x100   /* base offset in PMEM space */
112 #define HARRIER_MGOM0_OFF               0x00    /* outbound msg 0 */
113 #define HARRIER_MGOM1_OFF               0x04    /* outbound msg 1 */
114 #define HARRIER_MGOD_OFF                0x08    /* outbound doorbells */
115
116 #define HARRIER_MGIM0_OFF               0x10    /* inbound msg 0 */
117 #define HARRIER_MGIM1_OFF               0x14    /* inbound msg 1 */
118 #define HARRIER_MGID_OFF                0x18    /* inbound doorbells */
119
120 /* PowerPC-only registers */
121 #define HARRIER_MGIDM_OFF               0x20    /* inbound doorbell mask */
122
123 /* PCI-only registers */
124 #define HARRIER_PMEP_MGST_OFF           0x20    /* (outbound) interrupt status */
125 #define HARRIER_PMEP_MGMS_OFF           0x24    /* (outbound) interrupt mask */
126 #define HARRIER_MG_OMI0                 (1<<4)
127 #define HARRIER_MG_OMI1                 (1<<5)
128
129 #define HARRIER_PMEP_MGODM_OFF          0x28    /* outbound doorbell mask */
130
131 /*
132  * Define PCI configuration space register offsets
133  */
134 #define HARRIER_XCSR_TO_PCFS_OFF        0x300
135
136 /*
137  * Define message passing attribute register offset
138  */
139 #define HARRIER_MPAT_OFF                0x44
140
141 /*
142  * Define inbound attribute register offsets.
143  */
144 #define HARRIER_ITSZ0_OFF               0x48
145 #define HARRIER_ITAT0_OFF               0x4c
146
147 #define HARRIER_ITSZ1_OFF               0x50
148 #define HARRIER_ITAT1_OFF               0x54
149
150 #define HARRIER_ITSZ2_OFF               0x58
151 #define HARRIER_ITAT2_OFF               0x5c
152
153 #define HARRIER_ITSZ3_OFF               0x60
154 #define HARRIER_ITAT3_OFF               0x64
155
156 /* inbound translation size constants */
157 #define HARRIER_ITSZ_MSK                0xff
158 #define HARRIER_ITSZ_4KB                0x00
159 #define HARRIER_ITSZ_8KB                0x01
160 #define HARRIER_ITSZ_16KB               0x02
161 #define HARRIER_ITSZ_32KB               0x03
162 #define HARRIER_ITSZ_64KB               0x04
163 #define HARRIER_ITSZ_128KB              0x05
164 #define HARRIER_ITSZ_256KB              0x06
165 #define HARRIER_ITSZ_512KB              0x07
166 #define HARRIER_ITSZ_1MB                0x08
167 #define HARRIER_ITSZ_2MB                0x09
168 #define HARRIER_ITSZ_4MB                0x0A
169 #define HARRIER_ITSZ_8MB                0x0B
170 #define HARRIER_ITSZ_16MB               0x0C
171 #define HARRIER_ITSZ_32MB               0x0D
172 #define HARRIER_ITSZ_64MB               0x0E
173 #define HARRIER_ITSZ_128MB              0x0F
174 #define HARRIER_ITSZ_256MB              0x10
175 #define HARRIER_ITSZ_512MB              0x11
176 #define HARRIER_ITSZ_1GB                0x12
177 #define HARRIER_ITSZ_2GB                0x13
178
179 /* inbound translation offset */
180 #define HARRIER_ITOF_SHIFT              0x10
181 #define HARRIER_ITOF_MSK                0xffff
182
183 /* inbound translation atttributes */
184 #define HARRIER_ITAT_PRE                (1<<3)
185 #define HARRIER_ITAT_RAE                (1<<4)
186 #define HARRIER_ITAT_WPE                (1<<5)
187 #define HARRIER_ITAT_MEM                (1<<6)
188 #define HARRIER_ITAT_ENA                (1<<7)
189 #define HARRIER_ITAT_GBL                (1<<16)
190
191 #define HARRIER_LBA_OFF                 0x80
192 #define HARRIER_LBA_MSK                 (1<<31)
193
194 #define HARRIER_XCSR_SIZE               1024
195
196 /* macros to calculate message passing register offsets */
197 #define HARRIER_MP_XCSR(x) ((u32)HARRIER_XCSR_MP_BASE_OFF + (u32)x)
198
199 #define HARRIER_MP_PMEP(x) ((u32)HARRIER_PMEP_MP_BASE_OFF + (u32)x)
200
201 /*
202  * Define PCI configuration space register offsets
203  */
204 #define HARRIER_MPBAR_OFF               PCI_BASE_ADDRESS_0
205 #define HARRIER_ITBAR0_OFF              PCI_BASE_ADDRESS_1
206 #define HARRIER_ITBAR1_OFF              PCI_BASE_ADDRESS_2
207 #define HARRIER_ITBAR2_OFF              PCI_BASE_ADDRESS_3
208 #define HARRIER_ITBAR3_OFF              PCI_BASE_ADDRESS_4
209
210 #define HARRIER_XCSR_CONFIG(x) ((u32)HARRIER_XCSR_TO_PCFS_OFF + (u32)x)
211
212 #endif                          /* __ASMPPC_HARRIER_DEFS_H */