2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
54 #include <net/ieee80211_radiotap.h>
56 #include <asm/unaligned.h>
62 static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
63 static int modparam_nohwcrypt;
64 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
65 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
73 MODULE_AUTHOR("Jiri Slaby");
74 MODULE_AUTHOR("Nick Kossifidis");
75 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
76 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
77 MODULE_LICENSE("Dual BSD/GPL");
78 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
82 static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
83 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
84 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
85 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
86 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
87 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
88 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
89 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
90 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
91 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
95 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
98 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
99 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
100 { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
103 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
106 static struct ath5k_srev_name srev_names[] = {
107 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
108 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
109 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
110 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
111 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
112 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
113 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
114 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
115 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
116 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
117 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
118 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
119 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
120 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
121 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
122 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
123 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
124 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
125 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
126 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
127 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
128 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
129 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
130 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
131 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
132 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
133 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
134 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
135 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
136 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
137 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
138 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
139 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
140 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
141 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
142 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
145 static struct ieee80211_rate ath5k_rates[] = {
147 .hw_value = ATH5K_RATE_CODE_1M, },
149 .hw_value = ATH5K_RATE_CODE_2M,
150 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
151 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
153 .hw_value = ATH5K_RATE_CODE_5_5M,
154 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
157 .hw_value = ATH5K_RATE_CODE_11M,
158 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
161 .hw_value = ATH5K_RATE_CODE_6M,
164 .hw_value = ATH5K_RATE_CODE_9M,
167 .hw_value = ATH5K_RATE_CODE_12M,
170 .hw_value = ATH5K_RATE_CODE_18M,
173 .hw_value = ATH5K_RATE_CODE_24M,
176 .hw_value = ATH5K_RATE_CODE_36M,
179 .hw_value = ATH5K_RATE_CODE_48M,
182 .hw_value = ATH5K_RATE_CODE_54M,
188 * Prototypes - PCI stack related functions
190 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
191 const struct pci_device_id *id);
192 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
194 static int ath5k_pci_suspend(struct pci_dev *pdev,
196 static int ath5k_pci_resume(struct pci_dev *pdev);
198 #define ath5k_pci_suspend NULL
199 #define ath5k_pci_resume NULL
200 #endif /* CONFIG_PM */
202 static struct pci_driver ath5k_pci_driver = {
203 .name = KBUILD_MODNAME,
204 .id_table = ath5k_pci_id_table,
205 .probe = ath5k_pci_probe,
206 .remove = __devexit_p(ath5k_pci_remove),
207 .suspend = ath5k_pci_suspend,
208 .resume = ath5k_pci_resume,
214 * Prototypes - MAC 802.11 stack related functions
216 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
217 static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
218 static int ath5k_reset_wake(struct ath5k_softc *sc);
219 static int ath5k_start(struct ieee80211_hw *hw);
220 static void ath5k_stop(struct ieee80211_hw *hw);
221 static int ath5k_add_interface(struct ieee80211_hw *hw,
222 struct ieee80211_if_init_conf *conf);
223 static void ath5k_remove_interface(struct ieee80211_hw *hw,
224 struct ieee80211_if_init_conf *conf);
225 static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
226 static int ath5k_config_interface(struct ieee80211_hw *hw,
227 struct ieee80211_vif *vif,
228 struct ieee80211_if_conf *conf);
229 static void ath5k_configure_filter(struct ieee80211_hw *hw,
230 unsigned int changed_flags,
231 unsigned int *new_flags,
232 int mc_count, struct dev_mc_list *mclist);
233 static int ath5k_set_key(struct ieee80211_hw *hw,
234 enum set_key_cmd cmd,
235 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
236 struct ieee80211_key_conf *key);
237 static int ath5k_get_stats(struct ieee80211_hw *hw,
238 struct ieee80211_low_level_stats *stats);
239 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
240 struct ieee80211_tx_queue_stats *stats);
241 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
242 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
243 static int ath5k_beacon_update(struct ath5k_softc *sc,
244 struct sk_buff *skb);
245 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
246 struct ieee80211_vif *vif,
247 struct ieee80211_bss_conf *bss_conf,
250 static struct ieee80211_ops ath5k_hw_ops = {
252 .start = ath5k_start,
254 .add_interface = ath5k_add_interface,
255 .remove_interface = ath5k_remove_interface,
256 .config = ath5k_config,
257 .config_interface = ath5k_config_interface,
258 .configure_filter = ath5k_configure_filter,
259 .set_key = ath5k_set_key,
260 .get_stats = ath5k_get_stats,
262 .get_tx_stats = ath5k_get_tx_stats,
263 .get_tsf = ath5k_get_tsf,
264 .reset_tsf = ath5k_reset_tsf,
265 .bss_info_changed = ath5k_bss_info_changed,
269 * Prototypes - Internal functions
272 static int ath5k_attach(struct pci_dev *pdev,
273 struct ieee80211_hw *hw);
274 static void ath5k_detach(struct pci_dev *pdev,
275 struct ieee80211_hw *hw);
276 /* Channel/mode setup */
277 static inline short ath5k_ieee2mhz(short chan);
278 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
279 struct ieee80211_channel *channels,
282 static int ath5k_setup_bands(struct ieee80211_hw *hw);
283 static int ath5k_chan_set(struct ath5k_softc *sc,
284 struct ieee80211_channel *chan);
285 static void ath5k_setcurmode(struct ath5k_softc *sc,
287 static void ath5k_mode_setup(struct ath5k_softc *sc);
289 /* Descriptor setup */
290 static int ath5k_desc_alloc(struct ath5k_softc *sc,
291 struct pci_dev *pdev);
292 static void ath5k_desc_free(struct ath5k_softc *sc,
293 struct pci_dev *pdev);
295 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
296 struct ath5k_buf *bf);
297 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
298 struct ath5k_buf *bf);
299 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
300 struct ath5k_buf *bf)
305 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
307 dev_kfree_skb_any(bf->skb);
312 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
313 int qtype, int subtype);
314 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
315 static int ath5k_beaconq_config(struct ath5k_softc *sc);
316 static void ath5k_txq_drainq(struct ath5k_softc *sc,
317 struct ath5k_txq *txq);
318 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
319 static void ath5k_txq_release(struct ath5k_softc *sc);
321 static int ath5k_rx_start(struct ath5k_softc *sc);
322 static void ath5k_rx_stop(struct ath5k_softc *sc);
323 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
324 struct ath5k_desc *ds,
326 struct ath5k_rx_status *rs);
327 static void ath5k_tasklet_rx(unsigned long data);
329 static void ath5k_tx_processq(struct ath5k_softc *sc,
330 struct ath5k_txq *txq);
331 static void ath5k_tasklet_tx(unsigned long data);
332 /* Beacon handling */
333 static int ath5k_beacon_setup(struct ath5k_softc *sc,
334 struct ath5k_buf *bf);
335 static void ath5k_beacon_send(struct ath5k_softc *sc);
336 static void ath5k_beacon_config(struct ath5k_softc *sc);
337 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
339 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
341 u64 tsf = ath5k_hw_get_tsf64(ah);
343 if ((tsf & 0x7fff) < rstamp)
346 return (tsf & ~0x7fff) | rstamp;
349 /* Interrupt handling */
350 static int ath5k_init(struct ath5k_softc *sc, bool is_resume);
351 static int ath5k_stop_locked(struct ath5k_softc *sc);
352 static int ath5k_stop_hw(struct ath5k_softc *sc, bool is_suspend);
353 static irqreturn_t ath5k_intr(int irq, void *dev_id);
354 static void ath5k_tasklet_reset(unsigned long data);
356 static void ath5k_calibrate(unsigned long data);
358 static int ath5k_init_leds(struct ath5k_softc *sc);
359 static void ath5k_led_enable(struct ath5k_softc *sc);
360 static void ath5k_led_off(struct ath5k_softc *sc);
361 static void ath5k_unregister_leds(struct ath5k_softc *sc);
364 * Module init/exit functions
373 ret = pci_register_driver(&ath5k_pci_driver);
375 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
385 pci_unregister_driver(&ath5k_pci_driver);
387 ath5k_debug_finish();
390 module_init(init_ath5k_pci);
391 module_exit(exit_ath5k_pci);
394 /********************\
395 * PCI Initialization *
396 \********************/
399 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
401 const char *name = "xxxxx";
404 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
405 if (srev_names[i].sr_type != type)
408 if ((val & 0xf0) == srev_names[i].sr_val)
409 name = srev_names[i].sr_name;
411 if ((val & 0xff) == srev_names[i].sr_val) {
412 name = srev_names[i].sr_name;
421 ath5k_pci_probe(struct pci_dev *pdev,
422 const struct pci_device_id *id)
425 struct ath5k_softc *sc;
426 struct ieee80211_hw *hw;
430 ret = pci_enable_device(pdev);
432 dev_err(&pdev->dev, "can't enable device\n");
436 /* XXX 32-bit addressing only */
437 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
439 dev_err(&pdev->dev, "32-bit DMA not available\n");
444 * Cache line size is used to size and align various
445 * structures used to communicate with the hardware.
447 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
450 * Linux 2.4.18 (at least) writes the cache line size
451 * register as a 16-bit wide register which is wrong.
452 * We must have this setup properly for rx buffer
453 * DMA to work so force a reasonable value here if it
456 csz = L1_CACHE_BYTES / sizeof(u32);
457 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
460 * The default setting of latency timer yields poor results,
461 * set it to the value used by other systems. It may be worth
462 * tweaking this setting more.
464 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
466 /* Enable bus mastering */
467 pci_set_master(pdev);
470 * Disable the RETRY_TIMEOUT register (0x41) to keep
471 * PCI Tx retries from interfering with C3 CPU state.
473 pci_write_config_byte(pdev, 0x41, 0);
475 ret = pci_request_region(pdev, 0, "ath5k");
477 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
481 mem = pci_iomap(pdev, 0, 0);
483 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
489 * Allocate hw (mac80211 main struct)
490 * and hw->priv (driver private data)
492 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
494 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
499 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
501 /* Initialize driver private data */
502 SET_IEEE80211_DEV(hw, &pdev->dev);
503 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
504 IEEE80211_HW_SIGNAL_DBM |
505 IEEE80211_HW_NOISE_DBM;
507 hw->wiphy->interface_modes =
508 BIT(NL80211_IFTYPE_STATION) |
509 BIT(NL80211_IFTYPE_ADHOC) |
510 BIT(NL80211_IFTYPE_MESH_POINT);
512 hw->extra_tx_headroom = 2;
513 hw->channel_change_time = 5000;
518 ath5k_debug_init_device(sc);
521 * Mark the device as detached to avoid processing
522 * interrupts until setup is complete.
524 __set_bit(ATH_STAT_INVALID, sc->status);
526 sc->iobase = mem; /* So we can unmap it on detach */
527 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
528 sc->opmode = NL80211_IFTYPE_STATION;
529 mutex_init(&sc->lock);
530 spin_lock_init(&sc->rxbuflock);
531 spin_lock_init(&sc->txbuflock);
532 spin_lock_init(&sc->block);
534 /* Set private data */
535 pci_set_drvdata(pdev, hw);
537 /* Setup interrupt handler */
538 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
540 ATH5K_ERR(sc, "request_irq failed\n");
544 /* Initialize device */
545 sc->ah = ath5k_hw_attach(sc, id->driver_data);
546 if (IS_ERR(sc->ah)) {
547 ret = PTR_ERR(sc->ah);
551 /* set up multi-rate retry capabilities */
552 if (sc->ah->ah_version == AR5K_AR5212) {
554 hw->max_rate_tries = 11;
557 /* Finish private driver data initialization */
558 ret = ath5k_attach(pdev, hw);
562 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
563 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
565 sc->ah->ah_phy_revision);
567 if (!sc->ah->ah_single_chip) {
568 /* Single chip radio (!RF5111) */
569 if (sc->ah->ah_radio_5ghz_revision &&
570 !sc->ah->ah_radio_2ghz_revision) {
571 /* No 5GHz support -> report 2GHz radio */
572 if (!test_bit(AR5K_MODE_11A,
573 sc->ah->ah_capabilities.cap_mode)) {
574 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
575 ath5k_chip_name(AR5K_VERSION_RAD,
576 sc->ah->ah_radio_5ghz_revision),
577 sc->ah->ah_radio_5ghz_revision);
578 /* No 2GHz support (5110 and some
579 * 5Ghz only cards) -> report 5Ghz radio */
580 } else if (!test_bit(AR5K_MODE_11B,
581 sc->ah->ah_capabilities.cap_mode)) {
582 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
583 ath5k_chip_name(AR5K_VERSION_RAD,
584 sc->ah->ah_radio_5ghz_revision),
585 sc->ah->ah_radio_5ghz_revision);
586 /* Multiband radio */
588 ATH5K_INFO(sc, "RF%s multiband radio found"
590 ath5k_chip_name(AR5K_VERSION_RAD,
591 sc->ah->ah_radio_5ghz_revision),
592 sc->ah->ah_radio_5ghz_revision);
595 /* Multi chip radio (RF5111 - RF2111) ->
596 * report both 2GHz/5GHz radios */
597 else if (sc->ah->ah_radio_5ghz_revision &&
598 sc->ah->ah_radio_2ghz_revision){
599 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
600 ath5k_chip_name(AR5K_VERSION_RAD,
601 sc->ah->ah_radio_5ghz_revision),
602 sc->ah->ah_radio_5ghz_revision);
603 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
604 ath5k_chip_name(AR5K_VERSION_RAD,
605 sc->ah->ah_radio_2ghz_revision),
606 sc->ah->ah_radio_2ghz_revision);
611 /* ready to process interrupts */
612 __clear_bit(ATH_STAT_INVALID, sc->status);
616 ath5k_hw_detach(sc->ah);
618 free_irq(pdev->irq, sc);
620 ieee80211_free_hw(hw);
622 pci_iounmap(pdev, mem);
624 pci_release_region(pdev, 0);
626 pci_disable_device(pdev);
631 static void __devexit
632 ath5k_pci_remove(struct pci_dev *pdev)
634 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
635 struct ath5k_softc *sc = hw->priv;
637 ath5k_debug_finish_device(sc);
638 ath5k_detach(pdev, hw);
639 ath5k_hw_detach(sc->ah);
640 free_irq(pdev->irq, sc);
641 pci_iounmap(pdev, sc->iobase);
642 pci_release_region(pdev, 0);
643 pci_disable_device(pdev);
644 ieee80211_free_hw(hw);
649 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
651 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
652 struct ath5k_softc *sc = hw->priv;
656 ath5k_stop_hw(sc, true);
658 free_irq(pdev->irq, sc);
659 pci_save_state(pdev);
660 pci_disable_device(pdev);
661 pci_set_power_state(pdev, PCI_D3hot);
667 ath5k_pci_resume(struct pci_dev *pdev)
669 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
670 struct ath5k_softc *sc = hw->priv;
673 pci_restore_state(pdev);
675 err = pci_enable_device(pdev);
680 * Suspend/Resume resets the PCI configuration space, so we have to
681 * re-disable the RETRY_TIMEOUT register (0x41) to keep
682 * PCI Tx retries from interfering with C3 CPU state
684 pci_write_config_byte(pdev, 0x41, 0);
686 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
688 ATH5K_ERR(sc, "request_irq failed\n");
692 err = ath5k_init(sc, true);
695 ath5k_led_enable(sc);
699 free_irq(pdev->irq, sc);
701 pci_disable_device(pdev);
704 #endif /* CONFIG_PM */
707 /***********************\
708 * Driver Initialization *
709 \***********************/
712 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
714 struct ath5k_softc *sc = hw->priv;
715 struct ath5k_hw *ah = sc->ah;
716 u8 mac[ETH_ALEN] = {};
719 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
722 * Check if the MAC has multi-rate retry support.
723 * We do this by trying to setup a fake extended
724 * descriptor. MAC's that don't have support will
725 * return false w/o doing anything. MAC's that do
726 * support it will return true w/o doing anything.
728 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
732 __set_bit(ATH_STAT_MRRETRY, sc->status);
735 * Collect the channel list. The 802.11 layer
736 * is resposible for filtering this list based
737 * on settings like the phy mode and regulatory
738 * domain restrictions.
740 ret = ath5k_setup_bands(hw);
742 ATH5K_ERR(sc, "can't get channels\n");
746 /* NB: setup here so ath5k_rate_update is happy */
747 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
748 ath5k_setcurmode(sc, AR5K_MODE_11A);
750 ath5k_setcurmode(sc, AR5K_MODE_11B);
753 * Allocate tx+rx descriptors and populate the lists.
755 ret = ath5k_desc_alloc(sc, pdev);
757 ATH5K_ERR(sc, "can't allocate descriptors\n");
762 * Allocate hardware transmit queues: one queue for
763 * beacon frames and one data queue for each QoS
764 * priority. Note that hw functions handle reseting
765 * these queues at the needed time.
767 ret = ath5k_beaconq_setup(ah);
769 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
774 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
775 if (IS_ERR(sc->txq)) {
776 ATH5K_ERR(sc, "can't setup xmit queue\n");
777 ret = PTR_ERR(sc->txq);
781 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
782 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
783 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
784 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
786 ret = ath5k_eeprom_read_mac(ah, mac);
788 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
793 SET_IEEE80211_PERM_ADDR(hw, mac);
794 /* All MAC address bits matter for ACKs */
795 memset(sc->bssidmask, 0xff, ETH_ALEN);
796 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
798 ret = ieee80211_register_hw(hw);
800 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
808 ath5k_txq_release(sc);
810 ath5k_hw_release_tx_queue(ah, sc->bhalq);
812 ath5k_desc_free(sc, pdev);
818 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
820 struct ath5k_softc *sc = hw->priv;
823 * NB: the order of these is important:
824 * o call the 802.11 layer before detaching ath5k_hw to
825 * insure callbacks into the driver to delete global
826 * key cache entries can be handled
827 * o reclaim the tx queue data structures after calling
828 * the 802.11 layer as we'll get called back to reclaim
829 * node state and potentially want to use them
830 * o to cleanup the tx queues the hal is called, so detach
832 * XXX: ??? detach ath5k_hw ???
833 * Other than that, it's straightforward...
835 ieee80211_unregister_hw(hw);
836 ath5k_desc_free(sc, pdev);
837 ath5k_txq_release(sc);
838 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
839 ath5k_unregister_leds(sc);
842 * NB: can't reclaim these until after ieee80211_ifdetach
843 * returns because we'll get called back to reclaim node
844 * state and potentially want to use them.
851 /********************\
852 * Channel/mode setup *
853 \********************/
856 * Convert IEEE channel number to MHz frequency.
859 ath5k_ieee2mhz(short chan)
861 if (chan <= 14 || chan >= 27)
862 return ieee80211chan2mhz(chan);
864 return 2212 + chan * 20;
868 ath5k_copy_channels(struct ath5k_hw *ah,
869 struct ieee80211_channel *channels,
873 unsigned int i, count, size, chfreq, freq, ch;
875 if (!test_bit(mode, ah->ah_modes))
880 case AR5K_MODE_11A_TURBO:
881 /* 1..220, but 2GHz frequencies are filtered by check_channel */
883 chfreq = CHANNEL_5GHZ;
887 case AR5K_MODE_11G_TURBO:
889 chfreq = CHANNEL_2GHZ;
892 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
896 for (i = 0, count = 0; i < size && max > 0; i++) {
898 freq = ath5k_ieee2mhz(ch);
900 /* Check if channel is supported by the chipset */
901 if (!ath5k_channel_ok(ah, freq, chfreq))
904 /* Write channel info and increment counter */
905 channels[count].center_freq = freq;
906 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
907 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
911 channels[count].hw_value = chfreq | CHANNEL_OFDM;
913 case AR5K_MODE_11A_TURBO:
914 case AR5K_MODE_11G_TURBO:
915 channels[count].hw_value = chfreq |
916 CHANNEL_OFDM | CHANNEL_TURBO;
919 channels[count].hw_value = CHANNEL_B;
930 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
934 for (i = 0; i < AR5K_MAX_RATES; i++)
935 sc->rate_idx[b->band][i] = -1;
937 for (i = 0; i < b->n_bitrates; i++) {
938 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
939 if (b->bitrates[i].hw_value_short)
940 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
945 ath5k_setup_bands(struct ieee80211_hw *hw)
947 struct ath5k_softc *sc = hw->priv;
948 struct ath5k_hw *ah = sc->ah;
949 struct ieee80211_supported_band *sband;
950 int max_c, count_c = 0;
953 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
954 max_c = ARRAY_SIZE(sc->channels);
957 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
958 sband->band = IEEE80211_BAND_2GHZ;
959 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
961 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
963 memcpy(sband->bitrates, &ath5k_rates[0],
964 sizeof(struct ieee80211_rate) * 12);
965 sband->n_bitrates = 12;
967 sband->channels = sc->channels;
968 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
969 AR5K_MODE_11G, max_c);
971 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
972 count_c = sband->n_channels;
974 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
976 memcpy(sband->bitrates, &ath5k_rates[0],
977 sizeof(struct ieee80211_rate) * 4);
978 sband->n_bitrates = 4;
980 /* 5211 only supports B rates and uses 4bit rate codes
981 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
984 if (ah->ah_version == AR5K_AR5211) {
985 for (i = 0; i < 4; i++) {
986 sband->bitrates[i].hw_value =
987 sband->bitrates[i].hw_value & 0xF;
988 sband->bitrates[i].hw_value_short =
989 sband->bitrates[i].hw_value_short & 0xF;
993 sband->channels = sc->channels;
994 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
995 AR5K_MODE_11B, max_c);
997 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
998 count_c = sband->n_channels;
1001 ath5k_setup_rate_idx(sc, sband);
1003 /* 5GHz band, A mode */
1004 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
1005 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1006 sband->band = IEEE80211_BAND_5GHZ;
1007 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
1009 memcpy(sband->bitrates, &ath5k_rates[4],
1010 sizeof(struct ieee80211_rate) * 8);
1011 sband->n_bitrates = 8;
1013 sband->channels = &sc->channels[count_c];
1014 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1015 AR5K_MODE_11A, max_c);
1017 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1019 ath5k_setup_rate_idx(sc, sband);
1021 ath5k_debug_dump_bands(sc);
1027 * Set/change channels. If the channel is really being changed,
1028 * it's done by reseting the chip. To accomplish this we must
1029 * first cleanup any pending DMA, then restart stuff after a la
1033 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1035 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1036 sc->curchan->center_freq, chan->center_freq);
1038 if (chan->center_freq != sc->curchan->center_freq ||
1039 chan->hw_value != sc->curchan->hw_value) {
1042 sc->curband = &sc->sbands[chan->band];
1045 * To switch channels clear any pending DMA operations;
1046 * wait long enough for the RX fifo to drain, reset the
1047 * hardware at the new frequency, and then re-enable
1048 * the relevant bits of the h/w.
1050 return ath5k_reset(sc, true, true);
1057 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1061 if (mode == AR5K_MODE_11A) {
1062 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1064 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1069 ath5k_mode_setup(struct ath5k_softc *sc)
1071 struct ath5k_hw *ah = sc->ah;
1074 /* configure rx filter */
1075 rfilt = sc->filter_flags;
1076 ath5k_hw_set_rx_filter(ah, rfilt);
1078 if (ath5k_hw_hasbssidmask(ah))
1079 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1081 /* configure operational mode */
1082 ath5k_hw_set_opmode(ah);
1084 ath5k_hw_set_mcast_filter(ah, 0, 0);
1085 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1089 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1091 WARN_ON(hw_rix < 0 || hw_rix > AR5K_MAX_RATES);
1092 return sc->rate_idx[sc->curband->band][hw_rix];
1100 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1102 struct sk_buff *skb;
1106 * Allocate buffer with headroom_needed space for the
1107 * fake physical layer header at the start.
1109 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1112 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1113 sc->rxbufsize + sc->cachelsz - 1);
1117 * Cache-line-align. This is important (for the
1118 * 5210 at least) as not doing so causes bogus data
1121 off = ((unsigned long)skb->data) % sc->cachelsz;
1123 skb_reserve(skb, sc->cachelsz - off);
1125 *skb_addr = pci_map_single(sc->pdev,
1126 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1127 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1128 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1136 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1138 struct ath5k_hw *ah = sc->ah;
1139 struct sk_buff *skb = bf->skb;
1140 struct ath5k_desc *ds;
1143 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1150 * Setup descriptors. For receive we always terminate
1151 * the descriptor list with a self-linked entry so we'll
1152 * not get overrun under high load (as can happen with a
1153 * 5212 when ANI processing enables PHY error frames).
1155 * To insure the last descriptor is self-linked we create
1156 * each descriptor as self-linked and add it to the end. As
1157 * each additional descriptor is added the previous self-linked
1158 * entry is ``fixed'' naturally. This should be safe even
1159 * if DMA is happening. When processing RX interrupts we
1160 * never remove/process the last, self-linked, entry on the
1161 * descriptor list. This insures the hardware always has
1162 * someplace to write a new frame.
1165 ds->ds_link = bf->daddr; /* link to self */
1166 ds->ds_data = bf->skbaddr;
1167 ah->ah_setup_rx_desc(ah, ds,
1168 skb_tailroom(skb), /* buffer size */
1171 if (sc->rxlink != NULL)
1172 *sc->rxlink = bf->daddr;
1173 sc->rxlink = &ds->ds_link;
1178 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1180 struct ath5k_hw *ah = sc->ah;
1181 struct ath5k_txq *txq = sc->txq;
1182 struct ath5k_desc *ds = bf->desc;
1183 struct sk_buff *skb = bf->skb;
1184 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1185 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1186 struct ieee80211_rate *rate;
1187 unsigned int mrr_rate[3], mrr_tries[3];
1190 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1192 /* XXX endianness */
1193 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1196 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1197 flags |= AR5K_TXDESC_NOACK;
1201 if (info->control.hw_key) {
1202 keyidx = info->control.hw_key->hw_key_idx;
1203 pktlen += info->control.hw_key->icv_len;
1205 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1206 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1207 (sc->power_level * 2),
1208 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1209 info->control.rates[0].count, keyidx, 0, flags, 0, 0);
1213 memset(mrr_rate, 0, sizeof(mrr_rate));
1214 memset(mrr_tries, 0, sizeof(mrr_tries));
1215 for (i = 0; i < 3; i++) {
1216 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1220 mrr_rate[i] = rate->hw_value;
1221 mrr_tries[i] = info->control.rates[i + 1].count;
1224 ah->ah_setup_mrr_tx_desc(ah, ds,
1225 mrr_rate[0], mrr_tries[0],
1226 mrr_rate[1], mrr_tries[1],
1227 mrr_rate[2], mrr_tries[2]);
1230 ds->ds_data = bf->skbaddr;
1232 spin_lock_bh(&txq->lock);
1233 list_add_tail(&bf->list, &txq->q);
1234 sc->tx_stats[txq->qnum].len++;
1235 if (txq->link == NULL) /* is this first packet? */
1236 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1237 else /* no, so only link it */
1238 *txq->link = bf->daddr;
1240 txq->link = &ds->ds_link;
1241 ath5k_hw_start_tx_dma(ah, txq->qnum);
1243 spin_unlock_bh(&txq->lock);
1247 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1251 /*******************\
1252 * Descriptors setup *
1253 \*******************/
1256 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1258 struct ath5k_desc *ds;
1259 struct ath5k_buf *bf;
1264 /* allocate descriptors */
1265 sc->desc_len = sizeof(struct ath5k_desc) *
1266 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1267 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1268 if (sc->desc == NULL) {
1269 ATH5K_ERR(sc, "can't allocate descriptors\n");
1274 da = sc->desc_daddr;
1275 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1276 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1278 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1279 sizeof(struct ath5k_buf), GFP_KERNEL);
1281 ATH5K_ERR(sc, "can't allocate bufptr\n");
1287 INIT_LIST_HEAD(&sc->rxbuf);
1288 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1291 list_add_tail(&bf->list, &sc->rxbuf);
1294 INIT_LIST_HEAD(&sc->txbuf);
1295 sc->txbuf_len = ATH_TXBUF;
1296 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1297 da += sizeof(*ds)) {
1300 list_add_tail(&bf->list, &sc->txbuf);
1310 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1317 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1319 struct ath5k_buf *bf;
1321 ath5k_txbuf_free(sc, sc->bbuf);
1322 list_for_each_entry(bf, &sc->txbuf, list)
1323 ath5k_txbuf_free(sc, bf);
1324 list_for_each_entry(bf, &sc->rxbuf, list)
1325 ath5k_txbuf_free(sc, bf);
1327 /* Free memory associated with all descriptors */
1328 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1342 static struct ath5k_txq *
1343 ath5k_txq_setup(struct ath5k_softc *sc,
1344 int qtype, int subtype)
1346 struct ath5k_hw *ah = sc->ah;
1347 struct ath5k_txq *txq;
1348 struct ath5k_txq_info qi = {
1349 .tqi_subtype = subtype,
1350 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1351 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1352 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1357 * Enable interrupts only for EOL and DESC conditions.
1358 * We mark tx descriptors to receive a DESC interrupt
1359 * when a tx queue gets deep; otherwise waiting for the
1360 * EOL to reap descriptors. Note that this is done to
1361 * reduce interrupt load and this only defers reaping
1362 * descriptors, never transmitting frames. Aside from
1363 * reducing interrupts this also permits more concurrency.
1364 * The only potential downside is if the tx queue backs
1365 * up in which case the top half of the kernel may backup
1366 * due to a lack of tx descriptors.
1368 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1369 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1370 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1373 * NB: don't print a message, this happens
1374 * normally on parts with too few tx queues
1376 return ERR_PTR(qnum);
1378 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1379 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1380 qnum, ARRAY_SIZE(sc->txqs));
1381 ath5k_hw_release_tx_queue(ah, qnum);
1382 return ERR_PTR(-EINVAL);
1384 txq = &sc->txqs[qnum];
1388 INIT_LIST_HEAD(&txq->q);
1389 spin_lock_init(&txq->lock);
1392 return &sc->txqs[qnum];
1396 ath5k_beaconq_setup(struct ath5k_hw *ah)
1398 struct ath5k_txq_info qi = {
1399 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1400 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1401 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1402 /* NB: for dynamic turbo, don't enable any other interrupts */
1403 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1406 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1410 ath5k_beaconq_config(struct ath5k_softc *sc)
1412 struct ath5k_hw *ah = sc->ah;
1413 struct ath5k_txq_info qi;
1416 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1419 if (sc->opmode == NL80211_IFTYPE_AP ||
1420 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1422 * Always burst out beacon and CAB traffic
1423 * (aifs = cwmin = cwmax = 0)
1428 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1430 * Adhoc mode; backoff between 0 and (2 * cw_min).
1434 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1437 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1438 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1439 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1441 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1443 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1444 "hardware queue!\n", __func__);
1448 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1452 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1454 struct ath5k_buf *bf, *bf0;
1457 * NB: this assumes output has been stopped and
1458 * we do not need to block ath5k_tx_tasklet
1460 spin_lock_bh(&txq->lock);
1461 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1462 ath5k_debug_printtxbuf(sc, bf);
1464 ath5k_txbuf_free(sc, bf);
1466 spin_lock_bh(&sc->txbuflock);
1467 sc->tx_stats[txq->qnum].len--;
1468 list_move_tail(&bf->list, &sc->txbuf);
1470 spin_unlock_bh(&sc->txbuflock);
1473 spin_unlock_bh(&txq->lock);
1477 * Drain the transmit queues and reclaim resources.
1480 ath5k_txq_cleanup(struct ath5k_softc *sc)
1482 struct ath5k_hw *ah = sc->ah;
1485 /* XXX return value */
1486 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1487 /* don't touch the hardware if marked invalid */
1488 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1489 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1490 ath5k_hw_get_txdp(ah, sc->bhalq));
1491 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1492 if (sc->txqs[i].setup) {
1493 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1494 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1497 ath5k_hw_get_txdp(ah,
1502 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
1504 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1505 if (sc->txqs[i].setup)
1506 ath5k_txq_drainq(sc, &sc->txqs[i]);
1510 ath5k_txq_release(struct ath5k_softc *sc)
1512 struct ath5k_txq *txq = sc->txqs;
1515 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1517 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1530 * Enable the receive h/w following a reset.
1533 ath5k_rx_start(struct ath5k_softc *sc)
1535 struct ath5k_hw *ah = sc->ah;
1536 struct ath5k_buf *bf;
1539 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1541 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1542 sc->cachelsz, sc->rxbufsize);
1546 spin_lock_bh(&sc->rxbuflock);
1547 list_for_each_entry(bf, &sc->rxbuf, list) {
1548 ret = ath5k_rxbuf_setup(sc, bf);
1550 spin_unlock_bh(&sc->rxbuflock);
1554 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1555 spin_unlock_bh(&sc->rxbuflock);
1557 ath5k_hw_set_rxdp(ah, bf->daddr);
1558 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1559 ath5k_mode_setup(sc); /* set filters, etc. */
1560 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1568 * Disable the receive h/w in preparation for a reset.
1571 ath5k_rx_stop(struct ath5k_softc *sc)
1573 struct ath5k_hw *ah = sc->ah;
1575 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1576 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1577 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1579 ath5k_debug_printrxbuffs(sc, ah);
1581 sc->rxlink = NULL; /* just in case */
1585 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1586 struct sk_buff *skb, struct ath5k_rx_status *rs)
1588 struct ieee80211_hdr *hdr = (void *)skb->data;
1589 unsigned int keyix, hlen;
1591 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1592 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1593 return RX_FLAG_DECRYPTED;
1595 /* Apparently when a default key is used to decrypt the packet
1596 the hw does not set the index used to decrypt. In such cases
1597 get the index from the packet. */
1598 hlen = ieee80211_hdrlen(hdr->frame_control);
1599 if (ieee80211_has_protected(hdr->frame_control) &&
1600 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1601 skb->len >= hlen + 4) {
1602 keyix = skb->data[hlen + 3] >> 6;
1604 if (test_bit(keyix, sc->keymap))
1605 return RX_FLAG_DECRYPTED;
1613 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1614 struct ieee80211_rx_status *rxs)
1618 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1620 if (ieee80211_is_beacon(mgmt->frame_control) &&
1621 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1622 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1624 * Received an IBSS beacon with the same BSSID. Hardware *must*
1625 * have updated the local TSF. We have to work around various
1626 * hardware bugs, though...
1628 tsf = ath5k_hw_get_tsf64(sc->ah);
1629 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1630 hw_tu = TSF_TO_TU(tsf);
1632 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1633 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1634 (unsigned long long)bc_tstamp,
1635 (unsigned long long)rxs->mactime,
1636 (unsigned long long)(rxs->mactime - bc_tstamp),
1637 (unsigned long long)tsf);
1640 * Sometimes the HW will give us a wrong tstamp in the rx
1641 * status, causing the timestamp extension to go wrong.
1642 * (This seems to happen especially with beacon frames bigger
1643 * than 78 byte (incl. FCS))
1644 * But we know that the receive timestamp must be later than the
1645 * timestamp of the beacon since HW must have synced to that.
1647 * NOTE: here we assume mactime to be after the frame was
1648 * received, not like mac80211 which defines it at the start.
1650 if (bc_tstamp > rxs->mactime) {
1651 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1652 "fixing mactime from %llx to %llx\n",
1653 (unsigned long long)rxs->mactime,
1654 (unsigned long long)tsf);
1659 * Local TSF might have moved higher than our beacon timers,
1660 * in that case we have to update them to continue sending
1661 * beacons. This also takes care of synchronizing beacon sending
1662 * times with other stations.
1664 if (hw_tu >= sc->nexttbtt)
1665 ath5k_beacon_update_timers(sc, bc_tstamp);
1671 ath5k_tasklet_rx(unsigned long data)
1673 struct ieee80211_rx_status rxs = {};
1674 struct ath5k_rx_status rs = {};
1675 struct sk_buff *skb, *next_skb;
1676 dma_addr_t next_skb_addr;
1677 struct ath5k_softc *sc = (void *)data;
1678 struct ath5k_buf *bf, *bf_last;
1679 struct ath5k_desc *ds;
1684 spin_lock(&sc->rxbuflock);
1685 if (list_empty(&sc->rxbuf)) {
1686 ATH5K_WARN(sc, "empty rx buf pool\n");
1689 bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
1693 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1694 BUG_ON(bf->skb == NULL);
1699 * last buffer must not be freed to ensure proper hardware
1700 * function. When the hardware finishes also a packet next to
1701 * it, we are sure, it doesn't use it anymore and we can go on.
1706 struct ath5k_buf *bf_next = list_entry(bf->list.next,
1707 struct ath5k_buf, list);
1708 ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1713 /* skip the overwritten one (even status is martian) */
1717 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1718 if (unlikely(ret == -EINPROGRESS))
1720 else if (unlikely(ret)) {
1721 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1722 spin_unlock(&sc->rxbuflock);
1726 if (unlikely(rs.rs_more)) {
1727 ATH5K_WARN(sc, "unsupported jumbo\n");
1731 if (unlikely(rs.rs_status)) {
1732 if (rs.rs_status & AR5K_RXERR_PHY)
1734 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1736 * Decrypt error. If the error occurred
1737 * because there was no hardware key, then
1738 * let the frame through so the upper layers
1739 * can process it. This is necessary for 5210
1740 * parts which have no way to setup a ``clear''
1743 * XXX do key cache faulting
1745 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1746 !(rs.rs_status & AR5K_RXERR_CRC))
1749 if (rs.rs_status & AR5K_RXERR_MIC) {
1750 rxs.flag |= RX_FLAG_MMIC_ERROR;
1754 /* let crypto-error packets fall through in MNTR */
1756 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1757 sc->opmode != NL80211_IFTYPE_MONITOR)
1761 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1764 * If we can't replace bf->skb with a new skb under memory
1765 * pressure, just skip this packet
1770 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1771 PCI_DMA_FROMDEVICE);
1772 skb_put(skb, rs.rs_datalen);
1774 /* The MAC header is padded to have 32-bit boundary if the
1775 * packet payload is non-zero. The general calculation for
1776 * padsize would take into account odd header lengths:
1777 * padsize = (4 - hdrlen % 4) % 4; However, since only
1778 * even-length headers are used, padding can only be 0 or 2
1779 * bytes and we can optimize this a bit. In addition, we must
1780 * not try to remove padding from short control frames that do
1781 * not have payload. */
1782 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1783 padsize = ath5k_pad_size(hdrlen);
1785 memmove(skb->data + padsize, skb->data, hdrlen);
1786 skb_pull(skb, padsize);
1790 * always extend the mac timestamp, since this information is
1791 * also needed for proper IBSS merging.
1793 * XXX: it might be too late to do it here, since rs_tstamp is
1794 * 15bit only. that means TSF extension has to be done within
1795 * 32768usec (about 32ms). it might be necessary to move this to
1796 * the interrupt handler, like it is done in madwifi.
1798 * Unfortunately we don't know when the hardware takes the rx
1799 * timestamp (beginning of phy frame, data frame, end of rx?).
1800 * The only thing we know is that it is hardware specific...
1801 * On AR5213 it seems the rx timestamp is at the end of the
1802 * frame, but i'm not sure.
1804 * NOTE: mac80211 defines mactime at the beginning of the first
1805 * data symbol. Since we don't have any time references it's
1806 * impossible to comply to that. This affects IBSS merge only
1807 * right now, so it's not too bad...
1809 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1810 rxs.flag |= RX_FLAG_TSFT;
1812 rxs.freq = sc->curchan->center_freq;
1813 rxs.band = sc->curband->band;
1815 rxs.noise = sc->ah->ah_noise_floor;
1816 rxs.signal = rxs.noise + rs.rs_rssi;
1818 /* An rssi of 35 indicates you should be able use
1819 * 54 Mbps reliably. A more elaborate scheme can be used
1820 * here but it requires a map of SNR/throughput for each
1821 * possible mode used */
1822 rxs.qual = rs.rs_rssi * 100 / 35;
1824 /* rssi can be more than 35 though, anything above that
1825 * should be considered at 100% */
1829 rxs.antenna = rs.rs_antenna;
1830 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1831 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1833 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1834 sc->curband->bitrates[rxs.rate_idx].hw_value_short)
1835 rxs.flag |= RX_FLAG_SHORTPRE;
1837 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1839 /* check beacons in IBSS mode */
1840 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1841 ath5k_check_ibss_tsf(sc, skb, &rxs);
1843 __ieee80211_rx(sc->hw, skb, &rxs);
1846 bf->skbaddr = next_skb_addr;
1848 list_move_tail(&bf->list, &sc->rxbuf);
1849 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1851 spin_unlock(&sc->rxbuflock);
1862 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1864 struct ath5k_tx_status ts = {};
1865 struct ath5k_buf *bf, *bf0;
1866 struct ath5k_desc *ds;
1867 struct sk_buff *skb;
1868 struct ieee80211_tx_info *info;
1871 spin_lock(&txq->lock);
1872 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1875 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1876 if (unlikely(ret == -EINPROGRESS))
1878 else if (unlikely(ret)) {
1879 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1885 info = IEEE80211_SKB_CB(skb);
1888 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1891 ieee80211_tx_info_clear_status(info);
1892 for (i = 0; i < 4; i++) {
1893 struct ieee80211_tx_rate *r =
1894 &info->status.rates[i];
1896 if (ts.ts_rate[i]) {
1897 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1898 r->count = ts.ts_retry[i];
1905 /* count the successful attempt as well */
1906 info->status.rates[ts.ts_final_idx].count++;
1908 if (unlikely(ts.ts_status)) {
1909 sc->ll_stats.dot11ACKFailureCount++;
1910 if (ts.ts_status & AR5K_TXERR_FILT)
1911 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1913 info->flags |= IEEE80211_TX_STAT_ACK;
1914 info->status.ack_signal = ts.ts_rssi;
1917 ieee80211_tx_status(sc->hw, skb);
1918 sc->tx_stats[txq->qnum].count++;
1920 spin_lock(&sc->txbuflock);
1921 sc->tx_stats[txq->qnum].len--;
1922 list_move_tail(&bf->list, &sc->txbuf);
1924 spin_unlock(&sc->txbuflock);
1926 if (likely(list_empty(&txq->q)))
1928 spin_unlock(&txq->lock);
1929 if (sc->txbuf_len > ATH_TXBUF / 5)
1930 ieee80211_wake_queues(sc->hw);
1934 ath5k_tasklet_tx(unsigned long data)
1936 struct ath5k_softc *sc = (void *)data;
1938 ath5k_tx_processq(sc, sc->txq);
1947 * Setup the beacon frame for transmit.
1950 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1952 struct sk_buff *skb = bf->skb;
1953 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1954 struct ath5k_hw *ah = sc->ah;
1955 struct ath5k_desc *ds;
1956 int ret, antenna = 0;
1959 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1961 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1962 "skbaddr %llx\n", skb, skb->data, skb->len,
1963 (unsigned long long)bf->skbaddr);
1964 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
1965 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1971 flags = AR5K_TXDESC_NOACK;
1972 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
1973 ds->ds_link = bf->daddr; /* self-linked */
1974 flags |= AR5K_TXDESC_VEOL;
1976 * Let hardware handle antenna switching if txantenna is not set
1981 * Switch antenna every 4 beacons if txantenna is not set
1982 * XXX assumes two antennas
1985 antenna = sc->bsent & 4 ? 2 : 1;
1988 ds->ds_data = bf->skbaddr;
1989 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
1990 ieee80211_get_hdrlen_from_skb(skb),
1991 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
1992 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1993 1, AR5K_TXKEYIX_INVALID,
1994 antenna, flags, 0, 0);
2000 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2005 * Transmit a beacon frame at SWBA. Dynamic updates to the
2006 * frame contents are done as needed and the slot time is
2007 * also adjusted based on current state.
2009 * this is usually called from interrupt context (ath5k_intr())
2010 * but also from ath5k_beacon_config() in IBSS mode which in turn
2011 * can be called from a tasklet and user context
2014 ath5k_beacon_send(struct ath5k_softc *sc)
2016 struct ath5k_buf *bf = sc->bbuf;
2017 struct ath5k_hw *ah = sc->ah;
2019 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
2021 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2022 sc->opmode == NL80211_IFTYPE_MONITOR)) {
2023 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2027 * Check if the previous beacon has gone out. If
2028 * not don't don't try to post another, skip this
2029 * period and wait for the next. Missed beacons
2030 * indicate a problem and should not occur. If we
2031 * miss too many consecutive beacons reset the device.
2033 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2035 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2036 "missed %u consecutive beacons\n", sc->bmisscount);
2037 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
2038 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2039 "stuck beacon time (%u missed)\n",
2041 tasklet_schedule(&sc->restq);
2045 if (unlikely(sc->bmisscount != 0)) {
2046 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2047 "resume beacon xmit after %u misses\n",
2053 * Stop any current dma and put the new frame on the queue.
2054 * This should never fail since we check above that no frames
2055 * are still pending on the queue.
2057 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2058 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2059 /* NB: hw still stops DMA, so proceed */
2062 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2063 ath5k_hw_start_tx_dma(ah, sc->bhalq);
2064 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2065 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2072 * ath5k_beacon_update_timers - update beacon timers
2074 * @sc: struct ath5k_softc pointer we are operating on
2075 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2076 * beacon timer update based on the current HW TSF.
2078 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2079 * of a received beacon or the current local hardware TSF and write it to the
2080 * beacon timer registers.
2082 * This is called in a variety of situations, e.g. when a beacon is received,
2083 * when a TSF update has been detected, but also when an new IBSS is created or
2084 * when we otherwise know we have to update the timers, but we keep it in this
2085 * function to have it all together in one place.
2088 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2090 struct ath5k_hw *ah = sc->ah;
2091 u32 nexttbtt, intval, hw_tu, bc_tu;
2094 intval = sc->bintval & AR5K_BEACON_PERIOD;
2095 if (WARN_ON(!intval))
2098 /* beacon TSF converted to TU */
2099 bc_tu = TSF_TO_TU(bc_tsf);
2101 /* current TSF converted to TU */
2102 hw_tsf = ath5k_hw_get_tsf64(ah);
2103 hw_tu = TSF_TO_TU(hw_tsf);
2106 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2109 * no beacons received, called internally.
2110 * just need to refresh timers based on HW TSF.
2112 nexttbtt = roundup(hw_tu + FUDGE, intval);
2113 } else if (bc_tsf == 0) {
2115 * no beacon received, probably called by ath5k_reset_tsf().
2116 * reset TSF to start with 0.
2119 intval |= AR5K_BEACON_RESET_TSF;
2120 } else if (bc_tsf > hw_tsf) {
2122 * beacon received, SW merge happend but HW TSF not yet updated.
2123 * not possible to reconfigure timers yet, but next time we
2124 * receive a beacon with the same BSSID, the hardware will
2125 * automatically update the TSF and then we need to reconfigure
2128 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2129 "need to wait for HW TSF sync\n");
2133 * most important case for beacon synchronization between STA.
2135 * beacon received and HW TSF has been already updated by HW.
2136 * update next TBTT based on the TSF of the beacon, but make
2137 * sure it is ahead of our local TSF timer.
2139 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2143 sc->nexttbtt = nexttbtt;
2145 intval |= AR5K_BEACON_ENA;
2146 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2149 * debugging output last in order to preserve the time critical aspect
2153 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2154 "reconfigured timers based on HW TSF\n");
2155 else if (bc_tsf == 0)
2156 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2157 "reset HW TSF and timers\n");
2159 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2160 "updated timers based on beacon TSF\n");
2162 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2163 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2164 (unsigned long long) bc_tsf,
2165 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2166 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2167 intval & AR5K_BEACON_PERIOD,
2168 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2169 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2174 * ath5k_beacon_config - Configure the beacon queues and interrupts
2176 * @sc: struct ath5k_softc pointer we are operating on
2178 * When operating in station mode we want to receive a BMISS interrupt when we
2179 * stop seeing beacons from the AP we've associated with so we can look for
2180 * another AP to associate with.
2182 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2183 * interrupts to detect TSF updates only.
2186 ath5k_beacon_config(struct ath5k_softc *sc)
2188 struct ath5k_hw *ah = sc->ah;
2190 ath5k_hw_set_imr(ah, 0);
2192 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2194 if (sc->opmode == NL80211_IFTYPE_STATION) {
2195 sc->imask |= AR5K_INT_BMISS;
2196 } else if (sc->opmode == NL80211_IFTYPE_ADHOC ||
2197 sc->opmode == NL80211_IFTYPE_MESH_POINT ||
2198 sc->opmode == NL80211_IFTYPE_AP) {
2200 * In IBSS mode we use a self-linked tx descriptor and let the
2201 * hardware send the beacons automatically. We have to load it
2203 * We use the SWBA interrupt only to keep track of the beacon
2204 * timers in order to detect automatic TSF updates.
2206 ath5k_beaconq_config(sc);
2208 sc->imask |= AR5K_INT_SWBA;
2210 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2211 if (ath5k_hw_hasveol(ah)) {
2212 spin_lock(&sc->block);
2213 ath5k_beacon_send(sc);
2214 spin_unlock(&sc->block);
2217 ath5k_beacon_update_timers(sc, -1);
2220 ath5k_hw_set_imr(ah, sc->imask);
2224 /********************\
2225 * Interrupt handling *
2226 \********************/
2229 ath5k_init(struct ath5k_softc *sc, bool is_resume)
2231 struct ath5k_hw *ah = sc->ah;
2234 mutex_lock(&sc->lock);
2236 if (is_resume && !test_bit(ATH_STAT_STARTED, sc->status))
2239 __clear_bit(ATH_STAT_STARTED, sc->status);
2241 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2244 * Stop anything previously setup. This is safe
2245 * no matter this is the first time through or not.
2247 ath5k_stop_locked(sc);
2250 * The basic interface to setting the hardware in a good
2251 * state is ``reset''. On return the hardware is known to
2252 * be powered up and with interrupts disabled. This must
2253 * be followed by initialization of the appropriate bits
2254 * and then setup of the interrupt mask.
2256 sc->curchan = sc->hw->conf.channel;
2257 sc->curband = &sc->sbands[sc->curchan->band];
2258 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2259 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2260 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
2261 ret = ath5k_reset(sc, false, false);
2266 * Reset the key cache since some parts do not reset the
2267 * contents on initial power up or resume from suspend.
2269 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2270 ath5k_hw_reset_key(ah, i);
2272 __set_bit(ATH_STAT_STARTED, sc->status);
2274 /* Set ack to be sent at low bit-rates */
2275 ath5k_hw_set_ack_bitrate_high(ah, false);
2277 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2278 msecs_to_jiffies(ath5k_calinterval * 1000)));
2284 mutex_unlock(&sc->lock);
2289 ath5k_stop_locked(struct ath5k_softc *sc)
2291 struct ath5k_hw *ah = sc->ah;
2293 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2294 test_bit(ATH_STAT_INVALID, sc->status));
2297 * Shutdown the hardware and driver:
2298 * stop output from above
2299 * disable interrupts
2301 * turn off the radio
2302 * clear transmit machinery
2303 * clear receive machinery
2304 * drain and release tx queues
2305 * reclaim beacon resources
2306 * power down hardware
2308 * Note that some of this work is not possible if the
2309 * hardware is gone (invalid).
2311 ieee80211_stop_queues(sc->hw);
2313 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2315 ath5k_hw_set_imr(ah, 0);
2316 synchronize_irq(sc->pdev->irq);
2318 ath5k_txq_cleanup(sc);
2319 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2321 ath5k_hw_phy_disable(ah);
2329 * Stop the device, grabbing the top-level lock to protect
2330 * against concurrent entry through ath5k_init (which can happen
2331 * if another thread does a system call and the thread doing the
2332 * stop is preempted).
2335 ath5k_stop_hw(struct ath5k_softc *sc, bool is_suspend)
2339 mutex_lock(&sc->lock);
2340 ret = ath5k_stop_locked(sc);
2341 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2343 * Set the chip in full sleep mode. Note that we are
2344 * careful to do this only when bringing the interface
2345 * completely to a stop. When the chip is in this state
2346 * it must be carefully woken up or references to
2347 * registers in the PCI clock domain may freeze the bus
2348 * (and system). This varies by chip and is mostly an
2349 * issue with newer parts that go to sleep more quickly.
2351 if (sc->ah->ah_mac_srev >= 0x78) {
2354 * don't put newer MAC revisions > 7.8 to sleep because
2355 * of the above mentioned problems
2357 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2358 "not putting device to sleep\n");
2360 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2361 "putting device to full sleep\n");
2362 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2365 ath5k_txbuf_free(sc, sc->bbuf);
2367 __clear_bit(ATH_STAT_STARTED, sc->status);
2370 mutex_unlock(&sc->lock);
2372 del_timer_sync(&sc->calib_tim);
2373 tasklet_kill(&sc->rxtq);
2374 tasklet_kill(&sc->txtq);
2375 tasklet_kill(&sc->restq);
2381 ath5k_intr(int irq, void *dev_id)
2383 struct ath5k_softc *sc = dev_id;
2384 struct ath5k_hw *ah = sc->ah;
2385 enum ath5k_int status;
2386 unsigned int counter = 1000;
2388 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2389 !ath5k_hw_is_intr_pending(ah)))
2394 * Figure out the reason(s) for the interrupt. Note
2395 * that get_isr returns a pseudo-ISR that may include
2396 * bits we haven't explicitly enabled so we mask the
2397 * value to insure we only process bits we requested.
2399 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2400 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2402 status &= sc->imask; /* discard unasked for bits */
2403 if (unlikely(status & AR5K_INT_FATAL)) {
2405 * Fatal errors are unrecoverable.
2406 * Typically these are caused by DMA errors.
2408 tasklet_schedule(&sc->restq);
2409 } else if (unlikely(status & AR5K_INT_RXORN)) {
2410 tasklet_schedule(&sc->restq);
2412 if (status & AR5K_INT_SWBA) {
2414 * Software beacon alert--time to send a beacon.
2415 * Handle beacon transmission directly; deferring
2416 * this is too slow to meet timing constraints
2419 * In IBSS mode we use this interrupt just to
2420 * keep track of the next TBTT (target beacon
2421 * transmission time) in order to detect wether
2422 * automatic TSF updates happened.
2424 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2425 /* XXX: only if VEOL suppported */
2426 u64 tsf = ath5k_hw_get_tsf64(ah);
2427 sc->nexttbtt += sc->bintval;
2428 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2429 "SWBA nexttbtt: %x hw_tu: %x "
2433 (unsigned long long) tsf);
2435 spin_lock(&sc->block);
2436 ath5k_beacon_send(sc);
2437 spin_unlock(&sc->block);
2440 if (status & AR5K_INT_RXEOL) {
2442 * NB: the hardware should re-read the link when
2443 * RXE bit is written, but it doesn't work at
2444 * least on older hardware revs.
2448 if (status & AR5K_INT_TXURN) {
2449 /* bump tx trigger level */
2450 ath5k_hw_update_tx_triglevel(ah, true);
2452 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2453 tasklet_schedule(&sc->rxtq);
2454 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2455 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2456 tasklet_schedule(&sc->txtq);
2457 if (status & AR5K_INT_BMISS) {
2459 if (status & AR5K_INT_MIB) {
2461 * These stats are also used for ANI i think
2462 * so how about updating them more often ?
2464 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2467 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2469 if (unlikely(!counter))
2470 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2476 ath5k_tasklet_reset(unsigned long data)
2478 struct ath5k_softc *sc = (void *)data;
2480 ath5k_reset_wake(sc);
2484 * Periodically recalibrate the PHY to account
2485 * for temperature/environment changes.
2488 ath5k_calibrate(unsigned long data)
2490 struct ath5k_softc *sc = (void *)data;
2491 struct ath5k_hw *ah = sc->ah;
2493 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2494 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2495 sc->curchan->hw_value);
2497 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2499 * Rfgain is out of bounds, reset the chip
2500 * to load new gain values.
2502 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2503 ath5k_reset_wake(sc);
2505 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2506 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2507 ieee80211_frequency_to_channel(
2508 sc->curchan->center_freq));
2510 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2511 msecs_to_jiffies(ath5k_calinterval * 1000)));
2521 ath5k_led_enable(struct ath5k_softc *sc)
2523 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2524 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2530 ath5k_led_on(struct ath5k_softc *sc)
2532 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2534 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
2538 ath5k_led_off(struct ath5k_softc *sc)
2540 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2542 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2546 ath5k_led_brightness_set(struct led_classdev *led_dev,
2547 enum led_brightness brightness)
2549 struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2552 if (brightness == LED_OFF)
2553 ath5k_led_off(led->sc);
2555 ath5k_led_on(led->sc);
2559 ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2560 const char *name, char *trigger)
2565 strncpy(led->name, name, sizeof(led->name));
2566 led->led_dev.name = led->name;
2567 led->led_dev.default_trigger = trigger;
2568 led->led_dev.brightness_set = ath5k_led_brightness_set;
2570 err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
2572 ATH5K_WARN(sc, "could not register LED %s\n", name);
2579 ath5k_unregister_led(struct ath5k_led *led)
2583 led_classdev_unregister(&led->led_dev);
2584 ath5k_led_off(led->sc);
2589 ath5k_unregister_leds(struct ath5k_softc *sc)
2591 ath5k_unregister_led(&sc->rx_led);
2592 ath5k_unregister_led(&sc->tx_led);
2597 ath5k_init_leds(struct ath5k_softc *sc)
2600 struct ieee80211_hw *hw = sc->hw;
2601 struct pci_dev *pdev = sc->pdev;
2602 char name[ATH5K_LED_MAX_NAME_LEN + 1];
2605 * Auto-enable soft led processing for IBM cards and for
2606 * 5211 minipci cards.
2608 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2609 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2610 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2612 sc->led_on = 0; /* active low */
2614 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2615 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2616 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2618 sc->led_on = 1; /* active high */
2620 /* Pin 3 on Foxconn chips used in Acer Aspire One (0x105b:e008) */
2621 if (pdev->subsystem_vendor == PCI_VENDOR_ID_FOXCONN) {
2622 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2624 sc->led_on = 0; /* active low */
2627 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2630 ath5k_led_enable(sc);
2632 snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2633 ret = ath5k_register_led(sc, &sc->rx_led, name,
2634 ieee80211_get_rx_led_name(hw));
2638 snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2639 ret = ath5k_register_led(sc, &sc->tx_led, name,
2640 ieee80211_get_tx_led_name(hw));
2646 /********************\
2647 * Mac80211 functions *
2648 \********************/
2651 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2653 struct ath5k_softc *sc = hw->priv;
2654 struct ath5k_buf *bf;
2655 unsigned long flags;
2659 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2661 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2662 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2665 * the hardware expects the header padded to 4 byte boundaries
2666 * if this is not the case we add the padding after the header
2668 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2669 padsize = ath5k_pad_size(hdrlen);
2672 if (skb_headroom(skb) < padsize) {
2673 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2674 " headroom to pad %d\n", hdrlen, padsize);
2675 return NETDEV_TX_BUSY;
2677 skb_push(skb, padsize);
2678 memmove(skb->data, skb->data+padsize, hdrlen);
2681 spin_lock_irqsave(&sc->txbuflock, flags);
2682 if (list_empty(&sc->txbuf)) {
2683 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2684 spin_unlock_irqrestore(&sc->txbuflock, flags);
2685 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2686 return NETDEV_TX_BUSY;
2688 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2689 list_del(&bf->list);
2691 if (list_empty(&sc->txbuf))
2692 ieee80211_stop_queues(hw);
2693 spin_unlock_irqrestore(&sc->txbuflock, flags);
2697 if (ath5k_txbuf_setup(sc, bf)) {
2699 spin_lock_irqsave(&sc->txbuflock, flags);
2700 list_add_tail(&bf->list, &sc->txbuf);
2702 spin_unlock_irqrestore(&sc->txbuflock, flags);
2703 dev_kfree_skb_any(skb);
2704 return NETDEV_TX_OK;
2707 return NETDEV_TX_OK;
2711 ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
2713 struct ath5k_hw *ah = sc->ah;
2716 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2719 ath5k_hw_set_imr(ah, 0);
2720 ath5k_txq_cleanup(sc);
2723 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2725 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2730 * This is needed only to setup initial state
2731 * but it's best done after a reset.
2733 ath5k_hw_set_txpower_limit(sc->ah, 0);
2735 ret = ath5k_rx_start(sc);
2737 ATH5K_ERR(sc, "can't start recv logic\n");
2742 * Change channels and update the h/w rate map if we're switching;
2743 * e.g. 11a to 11b/g.
2745 * We may be doing a reset in response to an ioctl that changes the
2746 * channel so update any state that might change as a result.
2750 /* ath5k_chan_change(sc, c); */
2752 ath5k_beacon_config(sc);
2753 /* intrs are enabled by ath5k_beacon_config */
2761 ath5k_reset_wake(struct ath5k_softc *sc)
2765 ret = ath5k_reset(sc, true, true);
2767 ieee80211_wake_queues(sc->hw);
2772 static int ath5k_start(struct ieee80211_hw *hw)
2774 return ath5k_init(hw->priv, false);
2777 static void ath5k_stop(struct ieee80211_hw *hw)
2779 ath5k_stop_hw(hw->priv, false);
2782 static int ath5k_add_interface(struct ieee80211_hw *hw,
2783 struct ieee80211_if_init_conf *conf)
2785 struct ath5k_softc *sc = hw->priv;
2788 mutex_lock(&sc->lock);
2794 sc->vif = conf->vif;
2796 switch (conf->type) {
2797 case NL80211_IFTYPE_AP:
2798 case NL80211_IFTYPE_STATION:
2799 case NL80211_IFTYPE_ADHOC:
2800 case NL80211_IFTYPE_MESH_POINT:
2801 case NL80211_IFTYPE_MONITOR:
2802 sc->opmode = conf->type;
2809 /* Set to a reasonable value. Note that this will
2810 * be set to mac80211's value at ath5k_config(). */
2812 ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
2816 mutex_unlock(&sc->lock);
2821 ath5k_remove_interface(struct ieee80211_hw *hw,
2822 struct ieee80211_if_init_conf *conf)
2824 struct ath5k_softc *sc = hw->priv;
2825 u8 mac[ETH_ALEN] = {};
2827 mutex_lock(&sc->lock);
2828 if (sc->vif != conf->vif)
2831 ath5k_hw_set_lladdr(sc->ah, mac);
2834 mutex_unlock(&sc->lock);
2838 * TODO: Phy disable/diversity etc
2841 ath5k_config(struct ieee80211_hw *hw, u32 changed)
2843 struct ath5k_softc *sc = hw->priv;
2844 struct ieee80211_conf *conf = &hw->conf;
2846 sc->bintval = conf->beacon_int;
2847 sc->power_level = conf->power_level;
2849 return ath5k_chan_set(sc, conf->channel);
2853 ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2854 struct ieee80211_if_conf *conf)
2856 struct ath5k_softc *sc = hw->priv;
2857 struct ath5k_hw *ah = sc->ah;
2860 mutex_lock(&sc->lock);
2861 if (sc->vif != vif) {
2865 if (conf->changed & IEEE80211_IFCC_BSSID && conf->bssid) {
2866 /* Cache for later use during resets */
2867 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2868 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2869 * a clean way of letting us retrieve this yet. */
2870 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2873 if (conf->changed & IEEE80211_IFCC_BEACON &&
2874 (vif->type == NL80211_IFTYPE_ADHOC ||
2875 vif->type == NL80211_IFTYPE_MESH_POINT ||
2876 vif->type == NL80211_IFTYPE_AP)) {
2877 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2882 ath5k_beacon_update(sc, beacon);
2884 mutex_unlock(&sc->lock);
2886 return ath5k_reset_wake(sc);
2888 mutex_unlock(&sc->lock);
2892 #define SUPPORTED_FIF_FLAGS \
2893 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2894 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2895 FIF_BCN_PRBRESP_PROMISC
2897 * o always accept unicast, broadcast, and multicast traffic
2898 * o multicast traffic for all BSSIDs will be enabled if mac80211
2900 * o maintain current state of phy ofdm or phy cck error reception.
2901 * If the hardware detects any of these type of errors then
2902 * ath5k_hw_get_rx_filter() will pass to us the respective
2903 * hardware filters to be able to receive these type of frames.
2904 * o probe request frames are accepted only when operating in
2905 * hostap, adhoc, or monitor modes
2906 * o enable promiscuous mode according to the interface state
2908 * - when operating in adhoc mode so the 802.11 layer creates
2909 * node table entries for peers,
2910 * - when operating in station mode for collecting rssi data when
2911 * the station is otherwise quiet, or
2914 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2915 unsigned int changed_flags,
2916 unsigned int *new_flags,
2917 int mc_count, struct dev_mc_list *mclist)
2919 struct ath5k_softc *sc = hw->priv;
2920 struct ath5k_hw *ah = sc->ah;
2921 u32 mfilt[2], val, rfilt;
2928 /* Only deal with supported flags */
2929 changed_flags &= SUPPORTED_FIF_FLAGS;
2930 *new_flags &= SUPPORTED_FIF_FLAGS;
2932 /* If HW detects any phy or radar errors, leave those filters on.
2933 * Also, always enable Unicast, Broadcasts and Multicast
2934 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2935 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2936 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2937 AR5K_RX_FILTER_MCAST);
2939 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2940 if (*new_flags & FIF_PROMISC_IN_BSS) {
2941 rfilt |= AR5K_RX_FILTER_PROM;
2942 __set_bit(ATH_STAT_PROMISC, sc->status);
2944 __clear_bit(ATH_STAT_PROMISC, sc->status);
2948 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2949 if (*new_flags & FIF_ALLMULTI) {
2953 for (i = 0; i < mc_count; i++) {
2956 /* calculate XOR of eight 6-bit values */
2957 val = get_unaligned_le32(mclist->dmi_addr + 0);
2958 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2959 val = get_unaligned_le32(mclist->dmi_addr + 3);
2960 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2962 mfilt[pos / 32] |= (1 << (pos % 32));
2963 /* XXX: we might be able to just do this instead,
2964 * but not sure, needs testing, if we do use this we'd
2965 * neet to inform below to not reset the mcast */
2966 /* ath5k_hw_set_mcast_filterindex(ah,
2967 * mclist->dmi_addr[5]); */
2968 mclist = mclist->next;
2972 /* This is the best we can do */
2973 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2974 rfilt |= AR5K_RX_FILTER_PHYERR;
2976 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2977 * and probes for any BSSID, this needs testing */
2978 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2979 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2981 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2982 * set we should only pass on control frames for this
2983 * station. This needs testing. I believe right now this
2984 * enables *all* control frames, which is OK.. but
2985 * but we should see if we can improve on granularity */
2986 if (*new_flags & FIF_CONTROL)
2987 rfilt |= AR5K_RX_FILTER_CONTROL;
2989 /* Additional settings per mode -- this is per ath5k */
2991 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2993 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2994 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2995 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2996 if (sc->opmode != NL80211_IFTYPE_STATION)
2997 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2998 if (sc->opmode != NL80211_IFTYPE_AP &&
2999 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
3000 test_bit(ATH_STAT_PROMISC, sc->status))
3001 rfilt |= AR5K_RX_FILTER_PROM;
3002 if ((sc->opmode == NL80211_IFTYPE_STATION && sc->assoc) ||
3003 sc->opmode == NL80211_IFTYPE_ADHOC ||
3004 sc->opmode == NL80211_IFTYPE_AP)
3005 rfilt |= AR5K_RX_FILTER_BEACON;
3006 if (sc->opmode == NL80211_IFTYPE_MESH_POINT)
3007 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
3008 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
3011 ath5k_hw_set_rx_filter(ah, rfilt);
3013 /* Set multicast bits */
3014 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
3015 /* Set the cached hw filter flags, this will alter actually
3017 sc->filter_flags = rfilt;
3021 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3022 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3023 struct ieee80211_key_conf *key)
3025 struct ath5k_softc *sc = hw->priv;
3028 if (modparam_nohwcrypt)
3042 mutex_lock(&sc->lock);
3046 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
3047 sta ? sta->addr : NULL);
3049 ATH5K_ERR(sc, "can't set the key\n");
3052 __set_bit(key->keyidx, sc->keymap);
3053 key->hw_key_idx = key->keyidx;
3054 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3055 IEEE80211_KEY_FLAG_GENERATE_MMIC);
3058 ath5k_hw_reset_key(sc->ah, key->keyidx);
3059 __clear_bit(key->keyidx, sc->keymap);
3068 mutex_unlock(&sc->lock);
3073 ath5k_get_stats(struct ieee80211_hw *hw,
3074 struct ieee80211_low_level_stats *stats)
3076 struct ath5k_softc *sc = hw->priv;
3077 struct ath5k_hw *ah = sc->ah;
3080 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
3082 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3088 ath5k_get_tx_stats(struct ieee80211_hw *hw,
3089 struct ieee80211_tx_queue_stats *stats)
3091 struct ath5k_softc *sc = hw->priv;
3093 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3099 ath5k_get_tsf(struct ieee80211_hw *hw)
3101 struct ath5k_softc *sc = hw->priv;
3103 return ath5k_hw_get_tsf64(sc->ah);
3107 ath5k_reset_tsf(struct ieee80211_hw *hw)
3109 struct ath5k_softc *sc = hw->priv;
3112 * in IBSS mode we need to update the beacon timers too.
3113 * this will also reset the TSF if we call it with 0
3115 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3116 ath5k_beacon_update_timers(sc, 0);
3118 ath5k_hw_reset_tsf(sc->ah);
3122 ath5k_beacon_update(struct ath5k_softc *sc, struct sk_buff *skb)
3124 unsigned long flags;
3127 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3129 spin_lock_irqsave(&sc->block, flags);
3130 ath5k_txbuf_free(sc, sc->bbuf);
3131 sc->bbuf->skb = skb;
3132 ret = ath5k_beacon_setup(sc, sc->bbuf);
3134 sc->bbuf->skb = NULL;
3135 spin_unlock_irqrestore(&sc->block, flags);
3137 ath5k_beacon_config(sc);
3144 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3146 struct ath5k_softc *sc = hw->priv;
3147 struct ath5k_hw *ah = sc->ah;
3149 rfilt = ath5k_hw_get_rx_filter(ah);
3151 rfilt |= AR5K_RX_FILTER_BEACON;
3153 rfilt &= ~AR5K_RX_FILTER_BEACON;
3154 ath5k_hw_set_rx_filter(ah, rfilt);
3155 sc->filter_flags = rfilt;
3158 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3159 struct ieee80211_vif *vif,
3160 struct ieee80211_bss_conf *bss_conf,
3163 struct ath5k_softc *sc = hw->priv;
3164 if (changes & BSS_CHANGED_ASSOC) {
3165 mutex_lock(&sc->lock);
3166 sc->assoc = bss_conf->assoc;
3167 if (sc->opmode == NL80211_IFTYPE_STATION)
3168 set_beacon_filter(hw, sc->assoc);
3169 mutex_unlock(&sc->lock);
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