i2c-omap: FIFO handling support and broken hw workaround for i2c-omap
[linux-2.6] / drivers / i2c / busses / i2c-omap.c
1 /*
2  * TI OMAP I2C master mode driver
3  *
4  * Copyright (C) 2003 MontaVista Software, Inc.
5  * Copyright (C) 2004 Texas Instruments.
6  *
7  * Updated to work with multiple I2C interfaces on 24xx by
8  * Tony Lindgren <tony@atomide.com> and Imre Deak <imre.deak@nokia.com>
9  * Copyright (C) 2005 Nokia Corporation
10  *
11  * Cleaned up by Juha Yrjölä <juha.yrjola@nokia.com>
12  *
13  * This program is free software; you can redistribute it and/or modify
14  * it under the terms of the GNU General Public License as published by
15  * the Free Software Foundation; either version 2 of the License, or
16  * (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software
25  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26  */
27
28 #include <linux/module.h>
29 #include <linux/delay.h>
30 #include <linux/i2c.h>
31 #include <linux/err.h>
32 #include <linux/interrupt.h>
33 #include <linux/completion.h>
34 #include <linux/platform_device.h>
35 #include <linux/clk.h>
36
37 #include <asm/io.h>
38
39 /* timeout waiting for the controller to respond */
40 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
41
42 #define OMAP_I2C_REV_REG                0x00
43 #define OMAP_I2C_IE_REG                 0x04
44 #define OMAP_I2C_STAT_REG               0x08
45 #define OMAP_I2C_IV_REG                 0x0c
46 #define OMAP_I2C_SYSS_REG               0x10
47 #define OMAP_I2C_BUF_REG                0x14
48 #define OMAP_I2C_CNT_REG                0x18
49 #define OMAP_I2C_DATA_REG               0x1c
50 #define OMAP_I2C_SYSC_REG               0x20
51 #define OMAP_I2C_CON_REG                0x24
52 #define OMAP_I2C_OA_REG                 0x28
53 #define OMAP_I2C_SA_REG                 0x2c
54 #define OMAP_I2C_PSC_REG                0x30
55 #define OMAP_I2C_SCLL_REG               0x34
56 #define OMAP_I2C_SCLH_REG               0x38
57 #define OMAP_I2C_SYSTEST_REG            0x3c
58 #define OMAP_I2C_BUFSTAT_REG            0x40
59
60 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
61 #define OMAP_I2C_IE_XDR         (1 << 14)       /* TX Buffer drain int enable */
62 #define OMAP_I2C_IE_RDR         (1 << 13)       /* RX Buffer drain int enable */
63 #define OMAP_I2C_IE_XRDY        (1 << 4)        /* TX data ready int enable */
64 #define OMAP_I2C_IE_RRDY        (1 << 3)        /* RX data ready int enable */
65 #define OMAP_I2C_IE_ARDY        (1 << 2)        /* Access ready int enable */
66 #define OMAP_I2C_IE_NACK        (1 << 1)        /* No ack interrupt enable */
67 #define OMAP_I2C_IE_AL          (1 << 0)        /* Arbitration lost int ena */
68
69 /* I2C Status Register (OMAP_I2C_STAT): */
70 #define OMAP_I2C_STAT_XDR       (1 << 14)       /* TX Buffer draining */
71 #define OMAP_I2C_STAT_RDR       (1 << 13)       /* RX Buffer draining */
72 #define OMAP_I2C_STAT_BB        (1 << 12)       /* Bus busy */
73 #define OMAP_I2C_STAT_ROVR      (1 << 11)       /* Receive overrun */
74 #define OMAP_I2C_STAT_XUDF      (1 << 10)       /* Transmit underflow */
75 #define OMAP_I2C_STAT_AAS       (1 << 9)        /* Address as slave */
76 #define OMAP_I2C_STAT_AD0       (1 << 8)        /* Address zero */
77 #define OMAP_I2C_STAT_XRDY      (1 << 4)        /* Transmit data ready */
78 #define OMAP_I2C_STAT_RRDY      (1 << 3)        /* Receive data ready */
79 #define OMAP_I2C_STAT_ARDY      (1 << 2)        /* Register access ready */
80 #define OMAP_I2C_STAT_NACK      (1 << 1)        /* No ack interrupt enable */
81 #define OMAP_I2C_STAT_AL        (1 << 0)        /* Arbitration lost int ena */
82
83 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
84 #define OMAP_I2C_BUF_RDMA_EN    (1 << 15)       /* RX DMA channel enable */
85 #define OMAP_I2C_BUF_RXFIF_CLR  (1 << 14)       /* RX FIFO Clear */
86 #define OMAP_I2C_BUF_XDMA_EN    (1 << 7)        /* TX DMA channel enable */
87 #define OMAP_I2C_BUF_TXFIF_CLR  (1 << 6)        /* TX FIFO Clear */
88
89 /* I2C Configuration Register (OMAP_I2C_CON): */
90 #define OMAP_I2C_CON_EN         (1 << 15)       /* I2C module enable */
91 #define OMAP_I2C_CON_BE         (1 << 14)       /* Big endian mode */
92 #define OMAP_I2C_CON_OPMODE_HS  (1 << 12)       /* High Speed support */
93 #define OMAP_I2C_CON_STB        (1 << 11)       /* Start byte mode (master) */
94 #define OMAP_I2C_CON_MST        (1 << 10)       /* Master/slave mode */
95 #define OMAP_I2C_CON_TRX        (1 << 9)        /* TX/RX mode (master only) */
96 #define OMAP_I2C_CON_XA         (1 << 8)        /* Expand address */
97 #define OMAP_I2C_CON_RM         (1 << 2)        /* Repeat mode (master only) */
98 #define OMAP_I2C_CON_STP        (1 << 1)        /* Stop cond (master only) */
99 #define OMAP_I2C_CON_STT        (1 << 0)        /* Start condition (master) */
100
101 /* I2C SCL time value when Master */
102 #define OMAP_I2C_SCLL_HSSCLL    8
103 #define OMAP_I2C_SCLH_HSSCLH    8
104
105 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
106 #ifdef DEBUG
107 #define OMAP_I2C_SYSTEST_ST_EN          (1 << 15)       /* System test enable */
108 #define OMAP_I2C_SYSTEST_FREE           (1 << 14)       /* Free running mode */
109 #define OMAP_I2C_SYSTEST_TMODE_MASK     (3 << 12)       /* Test mode select */
110 #define OMAP_I2C_SYSTEST_TMODE_SHIFT    (12)            /* Test mode select */
111 #define OMAP_I2C_SYSTEST_SCL_I          (1 << 3)        /* SCL line sense in */
112 #define OMAP_I2C_SYSTEST_SCL_O          (1 << 2)        /* SCL line drive out */
113 #define OMAP_I2C_SYSTEST_SDA_I          (1 << 1)        /* SDA line sense in */
114 #define OMAP_I2C_SYSTEST_SDA_O          (1 << 0)        /* SDA line drive out */
115 #endif
116
117 /* I2C System Status register (OMAP_I2C_SYSS): */
118 #define OMAP_I2C_SYSS_RDONE             (1 << 0)        /* Reset Done */
119
120 /* I2C System Configuration Register (OMAP_I2C_SYSC): */
121 #define OMAP_I2C_SYSC_SRST              (1 << 1)        /* Soft Reset */
122
123 struct omap_i2c_dev {
124         struct device           *dev;
125         void __iomem            *base;          /* virtual */
126         int                     irq;
127         struct clk              *iclk;          /* Interface clock */
128         struct clk              *fclk;          /* Functional clock */
129         struct completion       cmd_complete;
130         struct resource         *ioarea;
131         u32                     speed;          /* Speed of bus in Khz */
132         u16                     cmd_err;
133         u8                      *buf;
134         size_t                  buf_len;
135         struct i2c_adapter      adapter;
136         u8                      fifo_size;      /* use as flag and value
137                                                  * fifo_size==0 implies no fifo
138                                                  * if set, should be trsh+1
139                                                  */
140         unsigned                rev1:1;
141         unsigned                b_hw:1;         /* bad h/w fixes */
142         unsigned                idle:1;
143         u16                     iestate;        /* Saved interrupt register */
144 };
145
146 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
147                                       int reg, u16 val)
148 {
149         __raw_writew(val, i2c_dev->base + reg);
150 }
151
152 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
153 {
154         return __raw_readw(i2c_dev->base + reg);
155 }
156
157 static int omap_i2c_get_clocks(struct omap_i2c_dev *dev)
158 {
159         if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
160                 dev->iclk = clk_get(dev->dev, "i2c_ick");
161                 if (IS_ERR(dev->iclk)) {
162                         dev->iclk = NULL;
163                         return -ENODEV;
164                 }
165         }
166
167         dev->fclk = clk_get(dev->dev, "i2c_fck");
168         if (IS_ERR(dev->fclk)) {
169                 if (dev->iclk != NULL) {
170                         clk_put(dev->iclk);
171                         dev->iclk = NULL;
172                 }
173                 dev->fclk = NULL;
174                 return -ENODEV;
175         }
176
177         return 0;
178 }
179
180 static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
181 {
182         clk_put(dev->fclk);
183         dev->fclk = NULL;
184         if (dev->iclk != NULL) {
185                 clk_put(dev->iclk);
186                 dev->iclk = NULL;
187         }
188 }
189
190 static void omap_i2c_unidle(struct omap_i2c_dev *dev)
191 {
192         if (dev->iclk != NULL)
193                 clk_enable(dev->iclk);
194         clk_enable(dev->fclk);
195         dev->idle = 0;
196         if (dev->iestate)
197                 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
198 }
199
200 static void omap_i2c_idle(struct omap_i2c_dev *dev)
201 {
202         u16 iv;
203
204         dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
205         omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
206         if (dev->rev1) {
207                 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);   /* Read clears */
208         } else {
209                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
210
211                 /* Flush posted write before the dev->idle store occurs */
212                 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
213         }
214         dev->idle = 1;
215         clk_disable(dev->fclk);
216         if (dev->iclk != NULL)
217                 clk_disable(dev->iclk);
218 }
219
220 static int omap_i2c_init(struct omap_i2c_dev *dev)
221 {
222         u16 psc = 0, scll = 0, sclh = 0;
223         u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
224         unsigned long fclk_rate = 12000000;
225         unsigned long timeout;
226         unsigned long internal_clk = 0;
227
228         if (!dev->rev1) {
229                 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, OMAP_I2C_SYSC_SRST);
230                 /* For some reason we need to set the EN bit before the
231                  * reset done bit gets set. */
232                 timeout = jiffies + OMAP_I2C_TIMEOUT;
233                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
234                 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
235                          OMAP_I2C_SYSS_RDONE)) {
236                         if (time_after(jiffies, timeout)) {
237                                 dev_warn(dev->dev, "timeout waiting "
238                                                 "for controller reset\n");
239                                 return -ETIMEDOUT;
240                         }
241                         msleep(1);
242                 }
243         }
244         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
245
246         if (cpu_class_is_omap1()) {
247                 struct clk *armxor_ck;
248
249                 armxor_ck = clk_get(NULL, "armxor_ck");
250                 if (IS_ERR(armxor_ck))
251                         dev_warn(dev->dev, "Could not get armxor_ck\n");
252                 else {
253                         fclk_rate = clk_get_rate(armxor_ck);
254                         clk_put(armxor_ck);
255                 }
256                 /* TRM for 5912 says the I2C clock must be prescaled to be
257                  * between 7 - 12 MHz. The XOR input clock is typically
258                  * 12, 13 or 19.2 MHz. So we should have code that produces:
259                  *
260                  * XOR MHz      Divider         Prescaler
261                  * 12           1               0
262                  * 13           2               1
263                  * 19.2         2               1
264                  */
265                 if (fclk_rate > 12000000)
266                         psc = fclk_rate / 12000000;
267         }
268
269         if (cpu_is_omap2430()) {
270
271                 /* HSI2C controller internal clk rate should be 19.2 Mhz */
272                 internal_clk = 19200;
273                 fclk_rate = clk_get_rate(dev->fclk) / 1000;
274
275                 /* Compute prescaler divisor */
276                 psc = fclk_rate / internal_clk;
277                 psc = psc - 1;
278
279                 /* If configured for High Speed */
280                 if (dev->speed > 400) {
281                         /* For first phase of HS mode */
282                         fsscll = internal_clk / (400 * 2) - 6;
283                         fssclh = internal_clk / (400 * 2) - 6;
284
285                         /* For second phase of HS mode */
286                         hsscll = fclk_rate / (dev->speed * 2) - 6;
287                         hssclh = fclk_rate / (dev->speed * 2) - 6;
288                 } else {
289                         /* To handle F/S modes */
290                         fsscll = internal_clk / (dev->speed * 2) - 6;
291                         fssclh = internal_clk / (dev->speed * 2) - 6;
292                 }
293                 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
294                 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
295         } else {
296                 /* Program desired operating rate */
297                 fclk_rate /= (psc + 1) * 1000;
298                 if (psc > 2)
299                         psc = 2;
300                 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
301                 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
302         }
303
304         /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
305         omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
306
307         /* SCL low and high time values */
308         omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
309         omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
310
311         if (dev->fifo_size)
312                 /* Note: setup required fifo size - 1 */
313                 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG,
314                                         (dev->fifo_size - 1) << 8 | /* RTRSH */
315                                         OMAP_I2C_BUF_RXFIF_CLR |
316                                         (dev->fifo_size - 1) | /* XTRSH */
317                                         OMAP_I2C_BUF_TXFIF_CLR);
318
319         /* Take the I2C module out of reset: */
320         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
321
322         /* Enable interrupts */
323         omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
324                            (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
325                             OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
326                             OMAP_I2C_IE_AL)  | ((dev->fifo_size) ?
327                                 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0));
328         return 0;
329 }
330
331 /*
332  * Waiting on Bus Busy
333  */
334 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
335 {
336         unsigned long timeout;
337
338         timeout = jiffies + OMAP_I2C_TIMEOUT;
339         while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
340                 if (time_after(jiffies, timeout)) {
341                         dev_warn(dev->dev, "timeout waiting for bus ready\n");
342                         return -ETIMEDOUT;
343                 }
344                 msleep(1);
345         }
346
347         return 0;
348 }
349
350 /*
351  * Low level master read/write transaction.
352  */
353 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
354                              struct i2c_msg *msg, int stop)
355 {
356         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
357         int r;
358         u16 w;
359
360         dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
361                 msg->addr, msg->len, msg->flags, stop);
362
363         if (msg->len == 0)
364                 return -EINVAL;
365
366         omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
367
368         /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
369         dev->buf = msg->buf;
370         dev->buf_len = msg->len;
371
372         omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
373
374         /* Clear the FIFO Buffers */
375         w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
376         w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
377         omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
378
379         init_completion(&dev->cmd_complete);
380         dev->cmd_err = 0;
381
382         w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
383
384         /* High speed configuration */
385         if (dev->speed > 400)
386                 w |= OMAP_I2C_CON_OPMODE_HS;
387
388         if (msg->flags & I2C_M_TEN)
389                 w |= OMAP_I2C_CON_XA;
390         if (!(msg->flags & I2C_M_RD))
391                 w |= OMAP_I2C_CON_TRX;
392         if (!dev->b_hw && stop)
393                 w |= OMAP_I2C_CON_STP;
394         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
395
396         /*
397          * Don't write stt and stp together on some hardware.
398          */
399         if (dev->b_hw && stop) {
400                 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
401                 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
402                 while (con & OMAP_I2C_CON_STT) {
403                         con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
404
405                         /* Let the user know if i2c is in a bad state */
406                         if (time_after(jiffies, delay)) {
407                                 dev_err(dev->dev, "controller timed out "
408                                 "waiting for start condition to finish\n");
409                                 return -ETIMEDOUT;
410                         }
411                         cpu_relax();
412                 }
413
414                 w |= OMAP_I2C_CON_STP;
415                 w &= ~OMAP_I2C_CON_STT;
416                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
417         }
418
419         /*
420          * REVISIT: We should abort the transfer on signals, but the bus goes
421          * into arbitration and we're currently unable to recover from it.
422          */
423         r = wait_for_completion_timeout(&dev->cmd_complete,
424                                         OMAP_I2C_TIMEOUT);
425         dev->buf_len = 0;
426         if (r < 0)
427                 return r;
428         if (r == 0) {
429                 dev_err(dev->dev, "controller timed out\n");
430                 omap_i2c_init(dev);
431                 return -ETIMEDOUT;
432         }
433
434         if (likely(!dev->cmd_err))
435                 return 0;
436
437         /* We have an error */
438         if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
439                             OMAP_I2C_STAT_XUDF)) {
440                 omap_i2c_init(dev);
441                 return -EIO;
442         }
443
444         if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
445                 if (msg->flags & I2C_M_IGNORE_NAK)
446                         return 0;
447                 if (stop) {
448                         w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
449                         w |= OMAP_I2C_CON_STP;
450                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
451                 }
452                 return -EREMOTEIO;
453         }
454         return -EIO;
455 }
456
457
458 /*
459  * Prepare controller for a transaction and call omap_i2c_xfer_msg
460  * to do the work during IRQ processing.
461  */
462 static int
463 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
464 {
465         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
466         int i;
467         int r;
468
469         omap_i2c_unidle(dev);
470
471         if ((r = omap_i2c_wait_for_bb(dev)) < 0)
472                 goto out;
473
474         for (i = 0; i < num; i++) {
475                 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
476                 if (r != 0)
477                         break;
478         }
479
480         if (r == 0)
481                 r = num;
482 out:
483         omap_i2c_idle(dev);
484         return r;
485 }
486
487 static u32
488 omap_i2c_func(struct i2c_adapter *adap)
489 {
490         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
491 }
492
493 static inline void
494 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
495 {
496         dev->cmd_err |= err;
497         complete(&dev->cmd_complete);
498 }
499
500 static inline void
501 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
502 {
503         omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
504 }
505
506 static irqreturn_t
507 omap_i2c_rev1_isr(int this_irq, void *dev_id)
508 {
509         struct omap_i2c_dev *dev = dev_id;
510         u16 iv, w;
511
512         if (dev->idle)
513                 return IRQ_NONE;
514
515         iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
516         switch (iv) {
517         case 0x00:      /* None */
518                 break;
519         case 0x01:      /* Arbitration lost */
520                 dev_err(dev->dev, "Arbitration lost\n");
521                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
522                 break;
523         case 0x02:      /* No acknowledgement */
524                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
525                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
526                 break;
527         case 0x03:      /* Register access ready */
528                 omap_i2c_complete_cmd(dev, 0);
529                 break;
530         case 0x04:      /* Receive data ready */
531                 if (dev->buf_len) {
532                         w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
533                         *dev->buf++ = w;
534                         dev->buf_len--;
535                         if (dev->buf_len) {
536                                 *dev->buf++ = w >> 8;
537                                 dev->buf_len--;
538                         }
539                 } else
540                         dev_err(dev->dev, "RRDY IRQ while no data requested\n");
541                 break;
542         case 0x05:      /* Transmit data ready */
543                 if (dev->buf_len) {
544                         w = *dev->buf++;
545                         dev->buf_len--;
546                         if (dev->buf_len) {
547                                 w |= *dev->buf++ << 8;
548                                 dev->buf_len--;
549                         }
550                         omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
551                 } else
552                         dev_err(dev->dev, "XRDY IRQ while no data to send\n");
553                 break;
554         default:
555                 return IRQ_NONE;
556         }
557
558         return IRQ_HANDLED;
559 }
560
561 static irqreturn_t
562 omap_i2c_isr(int this_irq, void *dev_id)
563 {
564         struct omap_i2c_dev *dev = dev_id;
565         u16 bits;
566         u16 stat, w;
567         int err, count = 0;
568
569         if (dev->idle)
570                 return IRQ_NONE;
571
572         bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
573         while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
574                 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
575                 if (count++ == 100) {
576                         dev_warn(dev->dev, "Too much work in one IRQ\n");
577                         break;
578                 }
579
580                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
581
582                 err = 0;
583                 if (stat & OMAP_I2C_STAT_NACK) {
584                         err |= OMAP_I2C_STAT_NACK;
585                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
586                                            OMAP_I2C_CON_STP);
587                 }
588                 if (stat & OMAP_I2C_STAT_AL) {
589                         dev_err(dev->dev, "Arbitration lost\n");
590                         err |= OMAP_I2C_STAT_AL;
591                 }
592                 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
593                                         OMAP_I2C_STAT_AL))
594                         omap_i2c_complete_cmd(dev, err);
595                 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
596                         u8 num_bytes = 1;
597                         if (dev->fifo_size) {
598                                 if (stat & OMAP_I2C_STAT_RRDY)
599                                         num_bytes = dev->fifo_size;
600                                 else
601                                         num_bytes = omap_i2c_read_reg(dev,
602                                                         OMAP_I2C_BUFSTAT_REG);
603                         }
604                         while (num_bytes) {
605                                 num_bytes--;
606                                 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
607                                 if (dev->buf_len) {
608                                         *dev->buf++ = w;
609                                         dev->buf_len--;
610                                         /* Data reg from 2430 is 8 bit wide */
611                                         if (!cpu_is_omap2430()) {
612                                                 if (dev->buf_len) {
613                                                         *dev->buf++ = w >> 8;
614                                                         dev->buf_len--;
615                                                 }
616                                         }
617                                 } else {
618                                         if (stat & OMAP_I2C_STAT_RRDY)
619                                                 dev_err(dev->dev,
620                                                         "RRDY IRQ while no data"
621                                                                 " requested\n");
622                                         if (stat & OMAP_I2C_STAT_RDR)
623                                                 dev_err(dev->dev,
624                                                         "RDR IRQ while no data"
625                                                                 " requested\n");
626                                         break;
627                                 }
628                         }
629                         omap_i2c_ack_stat(dev,
630                                 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
631                         continue;
632                 }
633                 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
634                         u8 num_bytes = 1;
635                         if (dev->fifo_size) {
636                                 if (stat & OMAP_I2C_STAT_XRDY)
637                                         num_bytes = dev->fifo_size;
638                                 else
639                                         num_bytes = omap_i2c_read_reg(dev,
640                                                         OMAP_I2C_BUFSTAT_REG);
641                         }
642                         while (num_bytes) {
643                                 num_bytes--;
644                                 w = 0;
645                                 if (dev->buf_len) {
646                                         w = *dev->buf++;
647                                         dev->buf_len--;
648                                         /* Data reg from  2430 is 8 bit wide */
649                                         if (!cpu_is_omap2430()) {
650                                                 if (dev->buf_len) {
651                                                         w |= *dev->buf++ << 8;
652                                                         dev->buf_len--;
653                                                 }
654                                         }
655                                 } else {
656                                         if (stat & OMAP_I2C_STAT_XRDY)
657                                                 dev_err(dev->dev,
658                                                         "XRDY IRQ while no "
659                                                         "data to send\n");
660                                         if (stat & OMAP_I2C_STAT_XDR)
661                                                 dev_err(dev->dev,
662                                                         "XDR IRQ while no "
663                                                         "data to send\n");
664                                         break;
665                                 }
666                                 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
667                         }
668                         omap_i2c_ack_stat(dev,
669                                 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
670                         continue;
671                 }
672                 if (stat & OMAP_I2C_STAT_ROVR) {
673                         dev_err(dev->dev, "Receive overrun\n");
674                         dev->cmd_err |= OMAP_I2C_STAT_ROVR;
675                 }
676                 if (stat & OMAP_I2C_STAT_XUDF) {
677                         dev_err(dev->dev, "Transmit underflow\n");
678                         dev->cmd_err |= OMAP_I2C_STAT_XUDF;
679                 }
680         }
681
682         return count ? IRQ_HANDLED : IRQ_NONE;
683 }
684
685 static const struct i2c_algorithm omap_i2c_algo = {
686         .master_xfer    = omap_i2c_xfer,
687         .functionality  = omap_i2c_func,
688 };
689
690 static int
691 omap_i2c_probe(struct platform_device *pdev)
692 {
693         struct omap_i2c_dev     *dev;
694         struct i2c_adapter      *adap;
695         struct resource         *mem, *irq, *ioarea;
696         int r;
697         u32 *speed = NULL;
698
699         /* NOTE: driver uses the static register mapping */
700         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
701         if (!mem) {
702                 dev_err(&pdev->dev, "no mem resource?\n");
703                 return -ENODEV;
704         }
705         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
706         if (!irq) {
707                 dev_err(&pdev->dev, "no irq resource?\n");
708                 return -ENODEV;
709         }
710
711         ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
712                         pdev->name);
713         if (!ioarea) {
714                 dev_err(&pdev->dev, "I2C region already claimed\n");
715                 return -EBUSY;
716         }
717
718         dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
719         if (!dev) {
720                 r = -ENOMEM;
721                 goto err_release_region;
722         }
723
724         if (pdev->dev.platform_data != NULL)
725                 speed = (u32 *) pdev->dev.platform_data;
726         else
727                 *speed = 100; /* Defualt speed */
728
729         dev->speed = *speed;
730         dev->dev = &pdev->dev;
731         dev->irq = irq->start;
732         dev->base = ioremap(mem->start, mem->end - mem->start + 1);
733         if (!dev->base) {
734                 r = -ENOMEM;
735                 goto err_free_mem;
736         }
737
738         platform_set_drvdata(pdev, dev);
739
740         if ((r = omap_i2c_get_clocks(dev)) != 0)
741                 goto err_iounmap;
742
743         omap_i2c_unidle(dev);
744
745         if (cpu_is_omap15xx())
746                 dev->rev1 = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) < 0x20;
747
748         if (cpu_is_omap2430()) {
749                 u16 s;
750
751                 /* Set up the fifo size - Get total size */
752                 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
753                 dev->fifo_size = 0x8 << s;
754
755                 /*
756                  * Set up notification threshold as half the total available
757                  * size. This is to ensure that we can handle the status on int
758                  * call back latencies.
759                  */
760                 dev->fifo_size = (dev->fifo_size / 2);
761                 dev->b_hw = 1; /* Enable hardware fixes */
762         }
763
764         /* reset ASAP, clearing any IRQs */
765         omap_i2c_init(dev);
766
767         r = request_irq(dev->irq, dev->rev1 ? omap_i2c_rev1_isr : omap_i2c_isr,
768                         0, pdev->name, dev);
769
770         if (r) {
771                 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
772                 goto err_unuse_clocks;
773         }
774         r = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
775         dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
776                  pdev->id, r >> 4, r & 0xf, dev->speed);
777
778         adap = &dev->adapter;
779         i2c_set_adapdata(adap, dev);
780         adap->owner = THIS_MODULE;
781         adap->class = I2C_CLASS_HWMON;
782         strncpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
783         adap->algo = &omap_i2c_algo;
784         adap->dev.parent = &pdev->dev;
785
786         /* i2c device drivers may be active on return from add_adapter() */
787         adap->nr = pdev->id;
788         r = i2c_add_numbered_adapter(adap);
789         if (r) {
790                 dev_err(dev->dev, "failure adding adapter\n");
791                 goto err_free_irq;
792         }
793
794         omap_i2c_idle(dev);
795
796         return 0;
797
798 err_free_irq:
799         free_irq(dev->irq, dev);
800 err_unuse_clocks:
801         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
802         omap_i2c_idle(dev);
803         omap_i2c_put_clocks(dev);
804 err_iounmap:
805         iounmap(dev->base);
806 err_free_mem:
807         platform_set_drvdata(pdev, NULL);
808         kfree(dev);
809 err_release_region:
810         release_mem_region(mem->start, (mem->end - mem->start) + 1);
811
812         return r;
813 }
814
815 static int
816 omap_i2c_remove(struct platform_device *pdev)
817 {
818         struct omap_i2c_dev     *dev = platform_get_drvdata(pdev);
819         struct resource         *mem;
820
821         platform_set_drvdata(pdev, NULL);
822
823         free_irq(dev->irq, dev);
824         i2c_del_adapter(&dev->adapter);
825         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
826         omap_i2c_put_clocks(dev);
827         iounmap(dev->base);
828         kfree(dev);
829         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
830         release_mem_region(mem->start, (mem->end - mem->start) + 1);
831         return 0;
832 }
833
834 static struct platform_driver omap_i2c_driver = {
835         .probe          = omap_i2c_probe,
836         .remove         = omap_i2c_remove,
837         .driver         = {
838                 .name   = "i2c_omap",
839                 .owner  = THIS_MODULE,
840         },
841 };
842
843 /* I2C may be needed to bring up other drivers */
844 static int __init
845 omap_i2c_init_driver(void)
846 {
847         return platform_driver_register(&omap_i2c_driver);
848 }
849 subsys_initcall(omap_i2c_init_driver);
850
851 static void __exit omap_i2c_exit_driver(void)
852 {
853         platform_driver_unregister(&omap_i2c_driver);
854 }
855 module_exit(omap_i2c_exit_driver);
856
857 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
858 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
859 MODULE_LICENSE("GPL");
860 MODULE_ALIAS("platform:i2c_omap");