1 /* $Id: bkm_a8.c,v 1.22.2.4 2004/01/15 14:02:34 keil Exp $
3 * low level stuff for Scitel Quadro (4*S0, passive)
5 * Author Roland Klabunde
6 * Copyright by Roland Klabunde <R.Klabunde@Berkom.de>
8 * This software may be used and distributed according to the terms
9 * of the GNU General Public License, incorporated herein by reference.
14 #include <linux/init.h>
20 #include <linux/pci.h>
25 #define ATTEMPT_PCI_REMAPPING /* Required for PLX rev 1 */
27 extern const char *CardType[];
29 static const char sct_quadro_revision[] = "$Revision: 1.22.2.4 $";
31 static const char *sct_quadro_subtypes[] =
41 #define wordout(addr,val) outw(val,addr)
42 #define wordin(addr) inw(addr)
45 readreg(unsigned int ale, unsigned int adr, u_char off)
49 ret = wordin(adr) & 0xFF;
54 readfifo(unsigned int ale, unsigned int adr, u_char off, u_char * data, int size)
58 for (i = 0; i < size; i++)
59 data[i] = wordin(adr) & 0xFF;
64 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data)
71 writefifo(unsigned int ale, unsigned int adr, u_char off, u_char * data, int size)
75 for (i = 0; i < size; i++)
76 wordout(adr, data[i]);
79 /* Interface functions */
82 ReadISAC(struct IsdnCardState *cs, u_char offset)
84 return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80));
88 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value)
90 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80, value);
94 ReadISACfifo(struct IsdnCardState *cs, u_char * data, int size)
96 readfifo(cs->hw.ax.base, cs->hw.ax.data_adr, 0x80, data, size);
100 WriteISACfifo(struct IsdnCardState *cs, u_char * data, int size)
102 writefifo(cs->hw.ax.base, cs->hw.ax.data_adr, 0x80, data, size);
107 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset)
109 return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0)));
113 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value)
115 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0), value);
118 /* Set the specific ipac to active */
120 set_ipac_active(struct IsdnCardState *cs, u_int active)
123 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK,
124 active ? 0xc0 : 0xff);
128 * fast interrupt HSCX stuff goes here
131 #define READHSCX(cs, nr, reg) readreg(cs->hw.ax.base, \
132 cs->hw.ax.data_adr, reg + (nr ? 0x40 : 0))
133 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.ax.base, \
134 cs->hw.ax.data_adr, reg + (nr ? 0x40 : 0), data)
135 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.ax.base, \
136 cs->hw.ax.data_adr, (nr ? 0x40 : 0), ptr, cnt)
137 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.ax.base, \
138 cs->hw.ax.data_adr, (nr ? 0x40 : 0), ptr, cnt)
140 #include "hscx_irq.c"
143 bkm_interrupt_ipac(int intno, void *dev_id)
145 struct IsdnCardState *cs = dev_id;
146 u_char ista, val, icnt = 5;
149 spin_lock_irqsave(&cs->lock, flags);
150 ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA);
151 if (!(ista & 0x3f)) { /* not this IPAC */
152 spin_unlock_irqrestore(&cs->lock, flags);
156 if (cs->debug & L1_DEB_IPAC)
157 debugl1(cs, "IPAC ISTA %02X", ista);
159 val = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, HSCX_ISTA + 0x40);
167 hscx_int_main(cs, val);
171 val = 0xfe & readreg(cs->hw.ax.base, cs->hw.ax.data_adr, ISAC_ISTA | 0x80);
173 isac_interrupt(cs, val);
178 isac_interrupt(cs, val);
180 ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA);
181 if ((ista & 0x3f) && icnt) {
186 printk(KERN_WARNING "HiSax: %s (%s) IRQ LOOP\n",
188 sct_quadro_subtypes[cs->subtyp]);
189 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xFF);
190 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xC0);
191 spin_unlock_irqrestore(&cs->lock, flags);
196 release_io_sct_quadro(struct IsdnCardState *cs)
198 release_region(cs->hw.ax.base & 0xffffffc0, 128);
199 if (cs->subtyp == SCT_1)
200 release_region(cs->hw.ax.plx_adr, 64);
204 enable_bkm_int(struct IsdnCardState *cs, unsigned bEnable)
206 if (cs->typ == ISDN_CTYPE_SCT_QUADRO) {
208 wordout(cs->hw.ax.plx_adr + 0x4C, (wordin(cs->hw.ax.plx_adr + 0x4C) | 0x41));
210 wordout(cs->hw.ax.plx_adr + 0x4C, (wordin(cs->hw.ax.plx_adr + 0x4C) & ~0x41));
215 reset_bkm(struct IsdnCardState *cs)
217 if (cs->subtyp == SCT_1) {
218 wordout(cs->hw.ax.plx_adr + 0x50, (wordin(cs->hw.ax.plx_adr + 0x50) & ~4));
220 /* Remove the soft reset */
221 wordout(cs->hw.ax.plx_adr + 0x50, (wordin(cs->hw.ax.plx_adr + 0x50) | 4));
227 BKM_card_msg(struct IsdnCardState *cs, int mt, void *arg)
233 spin_lock_irqsave(&cs->lock, flags);
235 set_ipac_active(cs, 0);
236 enable_bkm_int(cs, 0);
238 spin_unlock_irqrestore(&cs->lock, flags);
242 spin_lock_irqsave(&cs->lock, flags);
243 set_ipac_active(cs, 0);
244 enable_bkm_int(cs, 0);
245 spin_unlock_irqrestore(&cs->lock, flags);
246 release_io_sct_quadro(cs);
249 spin_lock_irqsave(&cs->lock, flags);
250 cs->debug |= L1_DEB_IPAC;
251 set_ipac_active(cs, 1);
254 enable_bkm_int(cs, 1);
255 spin_unlock_irqrestore(&cs->lock, flags);
264 sct_alloc_io(u_int adr, u_int len)
266 if (!request_region(adr, len, "scitel")) {
268 "HiSax: Scitel port %#x-%#x already in use\n",
275 static struct pci_dev *dev_a8 __devinitdata = NULL;
276 static u16 sub_vendor_id __devinitdata = 0;
277 static u16 sub_sys_id __devinitdata = 0;
278 static u_char pci_bus __devinitdata = 0;
279 static u_char pci_device_fn __devinitdata = 0;
280 static u_char pci_irq __devinitdata = 0;
282 #endif /* CONFIG_PCI */
285 setup_sct_quadro(struct IsdnCard *card)
288 struct IsdnCardState *cs = card->cs;
292 u_int pci_ioaddr1, pci_ioaddr2, pci_ioaddr3, pci_ioaddr4, pci_ioaddr5;
294 strcpy(tmp, sct_quadro_revision);
295 printk(KERN_INFO "HiSax: T-Berkom driver Rev. %s\n", HiSax_getrev(tmp));
296 if (cs->typ == ISDN_CTYPE_SCT_QUADRO) {
297 cs->subtyp = SCT_1; /* Preset */
301 /* Identify subtype by para[0] */
302 if (card->para[0] >= SCT_1 && card->para[0] <= SCT_4)
303 cs->subtyp = card->para[0];
305 printk(KERN_WARNING "HiSax: %s: Invalid subcontroller in configuration, default to 1\n",
306 CardType[card->typ]);
309 if ((cs->subtyp != SCT_1) && ((sub_sys_id != PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO) ||
310 (sub_vendor_id != PCI_VENDOR_ID_BERKOM)))
312 if (cs->subtyp == SCT_1) {
313 while ((dev_a8 = pci_find_device(PCI_VENDOR_ID_PLX,
314 PCI_DEVICE_ID_PLX_9050, dev_a8))) {
316 sub_vendor_id = dev_a8->subsystem_vendor;
317 sub_sys_id = dev_a8->subsystem_device;
318 if ((sub_sys_id == PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO) &&
319 (sub_vendor_id == PCI_VENDOR_ID_BERKOM)) {
320 if (pci_enable_device(dev_a8))
322 pci_ioaddr1 = pci_resource_start(dev_a8, 1);
323 pci_irq = dev_a8->irq;
324 pci_bus = dev_a8->bus->number;
325 pci_device_fn = dev_a8->devfn;
331 printk(KERN_WARNING "HiSax: %s (%s): Card not found\n",
333 sct_quadro_subtypes[cs->subtyp]);
336 #ifdef ATTEMPT_PCI_REMAPPING
337 /* HACK: PLX revision 1 bug: PLX address bit 7 must not be set */
338 pci_read_config_byte(dev_a8, PCI_REVISION_ID, &pci_rev_id);
339 if ((pci_ioaddr1 & 0x80) && (pci_rev_id == 1)) {
340 printk(KERN_WARNING "HiSax: %s (%s): PLX rev 1, remapping required!\n",
342 sct_quadro_subtypes[cs->subtyp]);
343 /* Restart PCI negotiation */
344 pci_write_config_dword(dev_a8, PCI_BASE_ADDRESS_1, (u_int) - 1);
345 /* Move up by 0x80 byte */
347 pci_ioaddr1 &= PCI_BASE_ADDRESS_IO_MASK;
348 pci_write_config_dword(dev_a8, PCI_BASE_ADDRESS_1, pci_ioaddr1);
349 dev_a8->resource[ 1].start = pci_ioaddr1;
351 #endif /* End HACK */
353 if (!pci_irq) { /* IRQ range check ?? */
354 printk(KERN_WARNING "HiSax: %s (%s): No IRQ\n",
356 sct_quadro_subtypes[cs->subtyp]);
359 pci_read_config_dword(dev_a8, PCI_BASE_ADDRESS_1, &pci_ioaddr1);
360 pci_read_config_dword(dev_a8, PCI_BASE_ADDRESS_2, &pci_ioaddr2);
361 pci_read_config_dword(dev_a8, PCI_BASE_ADDRESS_3, &pci_ioaddr3);
362 pci_read_config_dword(dev_a8, PCI_BASE_ADDRESS_4, &pci_ioaddr4);
363 pci_read_config_dword(dev_a8, PCI_BASE_ADDRESS_5, &pci_ioaddr5);
364 if (!pci_ioaddr1 || !pci_ioaddr2 || !pci_ioaddr3 || !pci_ioaddr4 || !pci_ioaddr5) {
365 printk(KERN_WARNING "HiSax: %s (%s): No IO base address(es)\n",
367 sct_quadro_subtypes[cs->subtyp]);
370 pci_ioaddr1 &= PCI_BASE_ADDRESS_IO_MASK;
371 pci_ioaddr2 &= PCI_BASE_ADDRESS_IO_MASK;
372 pci_ioaddr3 &= PCI_BASE_ADDRESS_IO_MASK;
373 pci_ioaddr4 &= PCI_BASE_ADDRESS_IO_MASK;
374 pci_ioaddr5 &= PCI_BASE_ADDRESS_IO_MASK;
377 cs->irq_flags |= IRQF_SHARED;
378 /* pci_ioaddr1 is unique to all subdevices */
379 /* pci_ioaddr2 is for the fourth subdevice only */
380 /* pci_ioaddr3 is for the third subdevice only */
381 /* pci_ioaddr4 is for the second subdevice only */
382 /* pci_ioaddr5 is for the first subdevice only */
383 cs->hw.ax.plx_adr = pci_ioaddr1;
384 /* Enter all ipac_base addresses */
387 cs->hw.ax.base = pci_ioaddr5 + 0x00;
388 if (sct_alloc_io(pci_ioaddr1, 128))
390 if (sct_alloc_io(pci_ioaddr5, 64))
392 /* disable all IPAC */
393 writereg(pci_ioaddr5, pci_ioaddr5 + 4,
395 writereg(pci_ioaddr4 + 0x08, pci_ioaddr4 + 0x0c,
397 writereg(pci_ioaddr3 + 0x10, pci_ioaddr3 + 0x14,
399 writereg(pci_ioaddr2 + 0x20, pci_ioaddr2 + 0x24,
403 cs->hw.ax.base = pci_ioaddr4 + 0x08;
404 if (sct_alloc_io(pci_ioaddr4, 64))
408 cs->hw.ax.base = pci_ioaddr3 + 0x10;
409 if (sct_alloc_io(pci_ioaddr3, 64))
413 cs->hw.ax.base = pci_ioaddr2 + 0x20;
414 if (sct_alloc_io(pci_ioaddr2, 64))
418 /* For isac and hscx data path */
419 cs->hw.ax.data_adr = cs->hw.ax.base + 4;
421 printk(KERN_INFO "HiSax: %s (%s) configured at 0x%.4lX, 0x%.4lX, 0x%.4lX and IRQ %d\n",
423 sct_quadro_subtypes[cs->subtyp],
429 test_and_set_bit(HW_IPAC, &cs->HW_Flags);
431 cs->readisac = &ReadISAC;
432 cs->writeisac = &WriteISAC;
433 cs->readisacfifo = &ReadISACfifo;
434 cs->writeisacfifo = &WriteISACfifo;
436 cs->BC_Read_Reg = &ReadHSCX;
437 cs->BC_Write_Reg = &WriteHSCX;
438 cs->BC_Send_Data = &hscx_fill_fifo;
439 cs->cardmsg = &BKM_card_msg;
440 cs->irq_func = &bkm_interrupt_ipac;
442 printk(KERN_INFO "HiSax: %s (%s): IPAC Version %d\n",
444 sct_quadro_subtypes[cs->subtyp],
445 readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ID));
448 printk(KERN_ERR "HiSax: bkm_a8 only supported on PCI Systems\n");
449 #endif /* CONFIG_PCI */