git.oblomov.eu Git - linux-2.6/blob - drivers/net/b44.c

   1 /* b44.c: Broadcom 4400 device driver.
   2  *
   3  * Copyright (C) 2002 David S. Miller (davem@redhat.com)
   4  * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
   5  *
   6  * Distribute under GPL.
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/moduleparam.h>
  12 #include <linux/types.h>
  13 #include <linux/netdevice.h>
  14 #include <linux/ethtool.h>
  15 #include <linux/mii.h>
  16 #include <linux/if_ether.h>
  17 #include <linux/etherdevice.h>
  18 #include <linux/pci.h>
  19 #include <linux/delay.h>
  20 #include <linux/init.h>
  21 #include <linux/version.h>
  22 #include <linux/dma-mapping.h>
  23
  24 #include <asm/uaccess.h>
  25 #include <asm/io.h>
  26 #include <asm/irq.h>
  27
  28 #include "b44.h"
  29
  30 #define DRV_MODULE_NAME         "b44"
  31 #define PFX DRV_MODULE_NAME     ": "
  32 #define DRV_MODULE_VERSION      "0.95"
  33 #define DRV_MODULE_RELDATE      "Aug 3, 2004"
  34
  35 #define B44_DEF_MSG_ENABLE        \
  36         (NETIF_MSG_DRV          | \
  37          NETIF_MSG_PROBE        | \
  38          NETIF_MSG_LINK         | \
  39          NETIF_MSG_TIMER        | \
  40          NETIF_MSG_IFDOWN       | \
  41          NETIF_MSG_IFUP         | \
  42          NETIF_MSG_RX_ERR       | \
  43          NETIF_MSG_TX_ERR)
  44
  45 /* length of time before we decide the hardware is borked,
  46  * and dev->tx_timeout() should be called to fix the problem
  47  */
  48 #define B44_TX_TIMEOUT                  (5 * HZ)
  49
  50 /* hardware minimum and maximum for a single frame's data payload */
  51 #define B44_MIN_MTU                     60
  52 #define B44_MAX_MTU                     1500
  53
  54 #define B44_RX_RING_SIZE                512
  55 #define B44_DEF_RX_RING_PENDING         200
  56 #define B44_RX_RING_BYTES       (sizeof(struct dma_desc) * \
  57                                  B44_RX_RING_SIZE)
  58 #define B44_TX_RING_SIZE                512
  59 #define B44_DEF_TX_RING_PENDING         (B44_TX_RING_SIZE - 1)
  60 #define B44_TX_RING_BYTES       (sizeof(struct dma_desc) * \
  61                                  B44_TX_RING_SIZE)
  62 #define B44_DMA_MASK 0x3fffffff
  63
  64 #define TX_RING_GAP(BP) \
  65         (B44_TX_RING_SIZE - (BP)->tx_pending)
  66 #define TX_BUFFS_AVAIL(BP)                                              \
  67         (((BP)->tx_cons <= (BP)->tx_prod) ?                             \
  68           (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod :            \
  69           (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
  70 #define NEXT_TX(N)              (((N) + 1) & (B44_TX_RING_SIZE - 1))
  71
  72 #define RX_PKT_BUF_SZ           (1536 + bp->rx_offset + 64)
  73 #define TX_PKT_BUF_SZ           (B44_MAX_MTU + ETH_HLEN + 8)
  74
  75 /* minimum number of free TX descriptors required to wake up TX process */
  76 #define B44_TX_WAKEUP_THRESH            (B44_TX_RING_SIZE / 4)
  77
  78 static char version[] __devinitdata =
  79         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  80
  81 MODULE_AUTHOR("Florian Schirmer, Pekka Pietikainen, David S. Miller");
  82 MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
  83 MODULE_LICENSE("GPL");
  84 MODULE_VERSION(DRV_MODULE_VERSION);
  85
  86 static int b44_debug = -1;      /* -1 == use B44_DEF_MSG_ENABLE as value */
  87 module_param(b44_debug, int, 0);
  88 MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
  89
  90 static struct pci_device_id b44_pci_tbl[] = {
  91         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401,
  92           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  93         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0,
  94           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  95         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1,
  96           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  97         { }     /* terminate list with empty entry */
  98 };
  99
 100 MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
 101
 102 static void b44_halt(struct b44 *);
 103 static void b44_init_rings(struct b44 *);
 104 static void b44_init_hw(struct b44 *);
 105 static int b44_poll(struct net_device *dev, int *budget);
 106 #ifdef CONFIG_NET_POLL_CONTROLLER
 107 static void b44_poll_controller(struct net_device *dev);
 108 #endif
 109
 110 static int dma_desc_align_mask;
 111 static int dma_desc_sync_size;
 112
 113 static inline void b44_sync_dma_desc_for_device(struct pci_dev *pdev,
 114                                                 dma_addr_t dma_base,
 115                                                 unsigned long offset,
 116                                                 enum dma_data_direction dir)
 117 {
 118         dma_sync_single_range_for_device(&pdev->dev, dma_base,
 119                                          offset & dma_desc_align_mask,
 120                                          dma_desc_sync_size, dir);
 121 }
 122
 123 static inline void b44_sync_dma_desc_for_cpu(struct pci_dev *pdev,
 124                                              dma_addr_t dma_base,
 125                                              unsigned long offset,
 126                                              enum dma_data_direction dir)
 127 {
 128         dma_sync_single_range_for_cpu(&pdev->dev, dma_base,
 129                                       offset & dma_desc_align_mask,
 130                                       dma_desc_sync_size, dir);
 131 }
 132
 133 static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
 134 {
 135         return readl(bp->regs + reg);
 136 }
 137
 138 static inline void bw32(const struct b44 *bp,
 139                         unsigned long reg, unsigned long val)
 140 {
 141         writel(val, bp->regs + reg);
 142 }
 143
 144 static int b44_wait_bit(struct b44 *bp, unsigned long reg,
 145                         u32 bit, unsigned long timeout, const int clear)
 146 {
 147         unsigned long i;
 148
 149         for (i = 0; i < timeout; i++) {
 150                 u32 val = br32(bp, reg);
 151
 152                 if (clear && !(val & bit))
 153                         break;
 154                 if (!clear && (val & bit))
 155                         break;
 156                 udelay(10);
 157         }
 158         if (i == timeout) {
 159                 printk(KERN_ERR PFX "%s: BUG!  Timeout waiting for bit %08x of register "
 160                        "%lx to %s.\n",
 161                        bp->dev->name,
 162                        bit, reg,
 163                        (clear ? "clear" : "set"));
 164                 return -ENODEV;
 165         }
 166         return 0;
 167 }
 168
 169 /* Sonics SiliconBackplane support routines.  ROFL, you should see all the
 170  * buzz words used on this company's website :-)
 171  *
 172  * All of these routines must be invoked with bp->lock held and
 173  * interrupts disabled.
 174  */
 175
 176 #define SB_PCI_DMA             0x40000000      /* Client Mode PCI memory access space (1 GB) */
 177 #define BCM4400_PCI_CORE_ADDR  0x18002000      /* Address of PCI core on BCM4400 cards */
 178
 179 static u32 ssb_get_core_rev(struct b44 *bp)
 180 {
 181         return (br32(bp, B44_SBIDHIGH) & SBIDHIGH_RC_MASK);
 182 }
 183
 184 static u32 ssb_pci_setup(struct b44 *bp, u32 cores)
 185 {
 186         u32 bar_orig, pci_rev, val;
 187
 188         pci_read_config_dword(bp->pdev, SSB_BAR0_WIN, &bar_orig);
 189         pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, BCM4400_PCI_CORE_ADDR);
 190         pci_rev = ssb_get_core_rev(bp);
 191
 192         val = br32(bp, B44_SBINTVEC);
 193         val |= cores;
 194         bw32(bp, B44_SBINTVEC, val);
 195
 196         val = br32(bp, SSB_PCI_TRANS_2);
 197         val |= SSB_PCI_PREF | SSB_PCI_BURST;
 198         bw32(bp, SSB_PCI_TRANS_2, val);
 199
 200         pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, bar_orig);
 201
 202         return pci_rev;
 203 }
 204
 205 static void ssb_core_disable(struct b44 *bp)
 206 {
 207         if (br32(bp, B44_SBTMSLOW) & SBTMSLOW_RESET)
 208                 return;
 209
 210         bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK));
 211         b44_wait_bit(bp, B44_SBTMSLOW, SBTMSLOW_REJECT, 100000, 0);
 212         b44_wait_bit(bp, B44_SBTMSHIGH, SBTMSHIGH_BUSY, 100000, 1);
 213         bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK |
 214                             SBTMSLOW_REJECT | SBTMSLOW_RESET));
 215         br32(bp, B44_SBTMSLOW);
 216         udelay(1);
 217         bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_RESET));
 218         br32(bp, B44_SBTMSLOW);
 219         udelay(1);
 220 }
 221
 222 static void ssb_core_reset(struct b44 *bp)
 223 {
 224         u32 val;
 225
 226         ssb_core_disable(bp);
 227         bw32(bp, B44_SBTMSLOW, (SBTMSLOW_RESET | SBTMSLOW_CLOCK | SBTMSLOW_FGC));
 228         br32(bp, B44_SBTMSLOW);
 229         udelay(1);
 230
 231         /* Clear SERR if set, this is a hw bug workaround.  */
 232         if (br32(bp, B44_SBTMSHIGH) & SBTMSHIGH_SERR)
 233                 bw32(bp, B44_SBTMSHIGH, 0);
 234
 235         val = br32(bp, B44_SBIMSTATE);
 236         if (val & (SBIMSTATE_IBE | SBIMSTATE_TO))
 237                 bw32(bp, B44_SBIMSTATE, val & ~(SBIMSTATE_IBE | SBIMSTATE_TO));
 238
 239         bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC));
 240         br32(bp, B44_SBTMSLOW);
 241         udelay(1);
 242
 243         bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK));
 244         br32(bp, B44_SBTMSLOW);
 245         udelay(1);
 246 }
 247
 248 static int ssb_core_unit(struct b44 *bp)
 249 {
 250 #if 0
 251         u32 val = br32(bp, B44_SBADMATCH0);
 252         u32 base;
 253
 254         type = val & SBADMATCH0_TYPE_MASK;
 255         switch (type) {
 256         case 0:
 257                 base = val & SBADMATCH0_BS0_MASK;
 258                 break;
 259
 260         case 1:
 261                 base = val & SBADMATCH0_BS1_MASK;
 262                 break;
 263
 264         case 2:
 265         default:
 266                 base = val & SBADMATCH0_BS2_MASK;
 267                 break;
 268         };
 269 #endif
 270         return 0;
 271 }
 272
 273 static int ssb_is_core_up(struct b44 *bp)
 274 {
 275         return ((br32(bp, B44_SBTMSLOW) & (SBTMSLOW_RESET | SBTMSLOW_REJECT | SBTMSLOW_CLOCK))
 276                 == SBTMSLOW_CLOCK);
 277 }
 278
 279 static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
 280 {
 281         u32 val;
 282
 283         val  = ((u32) data[2]) << 24;
 284         val |= ((u32) data[3]) << 16;
 285         val |= ((u32) data[4]) <<  8;
 286         val |= ((u32) data[5]) <<  0;
 287         bw32(bp, B44_CAM_DATA_LO, val);
 288         val = (CAM_DATA_HI_VALID |
 289                (((u32) data[0]) << 8) |
 290                (((u32) data[1]) << 0));
 291         bw32(bp, B44_CAM_DATA_HI, val);
 292         bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
 293                             (index << CAM_CTRL_INDEX_SHIFT)));
 294         b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
 295 }
 296
 297 static inline void __b44_disable_ints(struct b44 *bp)
 298 {
 299         bw32(bp, B44_IMASK, 0);
 300 }
 301
 302 static void b44_disable_ints(struct b44 *bp)
 303 {
 304         __b44_disable_ints(bp);
 305
 306         /* Flush posted writes. */
 307         br32(bp, B44_IMASK);
 308 }
 309
 310 static void b44_enable_ints(struct b44 *bp)
 311 {
 312         bw32(bp, B44_IMASK, bp->imask);
 313 }
 314
 315 static int b44_readphy(struct b44 *bp, int reg, u32 *val)
 316 {
 317         int err;
 318
 319         bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
 320         bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
 321                              (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
 322                              (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
 323                              (reg << MDIO_DATA_RA_SHIFT) |
 324                              (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
 325         err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
 326         *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
 327
 328         return err;
 329 }
 330
 331 static int b44_writephy(struct b44 *bp, int reg, u32 val)
 332 {
 333         bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
 334         bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
 335                              (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
 336                              (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
 337                              (reg << MDIO_DATA_RA_SHIFT) |
 338                              (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
 339                              (val & MDIO_DATA_DATA)));
 340         return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
 341 }
 342
 343 /* miilib interface */
 344 /* FIXME FIXME: phy_id is ignored, bp->phy_addr use is unconditional
 345  * due to code existing before miilib use was added to this driver.
 346  * Someone should remove this artificial driver limitation in
 347  * b44_{read,write}phy.  bp->phy_addr itself is fine (and needed).
 348  */
 349 static int b44_mii_read(struct net_device *dev, int phy_id, int location)
 350 {
 351         u32 val;
 352         struct b44 *bp = netdev_priv(dev);
 353         int rc = b44_readphy(bp, location, &val);
 354         if (rc)
 355                 return 0xffffffff;
 356         return val;
 357 }
 358
 359 static void b44_mii_write(struct net_device *dev, int phy_id, int location,
 360                          int val)
 361 {
 362         struct b44 *bp = netdev_priv(dev);
 363         b44_writephy(bp, location, val);
 364 }
 365
 366 static int b44_phy_reset(struct b44 *bp)
 367 {
 368         u32 val;
 369         int err;
 370
 371         err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
 372         if (err)
 373                 return err;
 374         udelay(100);
 375         err = b44_readphy(bp, MII_BMCR, &val);
 376         if (!err) {
 377                 if (val & BMCR_RESET) {
 378                         printk(KERN_ERR PFX "%s: PHY Reset would not complete.\n",
 379                                bp->dev->name);
 380                         err = -ENODEV;
 381                 }
 382         }
 383
 384         return 0;
 385 }
 386
 387 static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
 388 {
 389         u32 val;
 390
 391         bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
 392         bp->flags |= pause_flags;
 393
 394         val = br32(bp, B44_RXCONFIG);
 395         if (pause_flags & B44_FLAG_RX_PAUSE)
 396                 val |= RXCONFIG_FLOW;
 397         else
 398                 val &= ~RXCONFIG_FLOW;
 399         bw32(bp, B44_RXCONFIG, val);
 400
 401         val = br32(bp, B44_MAC_FLOW);
 402         if (pause_flags & B44_FLAG_TX_PAUSE)
 403                 val |= (MAC_FLOW_PAUSE_ENAB |
 404                         (0xc0 & MAC_FLOW_RX_HI_WATER));
 405         else
 406                 val &= ~MAC_FLOW_PAUSE_ENAB;
 407         bw32(bp, B44_MAC_FLOW, val);
 408 }
 409
 410 static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
 411 {
 412         u32 pause_enab = bp->flags & (B44_FLAG_TX_PAUSE |
 413                                       B44_FLAG_RX_PAUSE);
 414
 415         if (local & ADVERTISE_PAUSE_CAP) {
 416                 if (local & ADVERTISE_PAUSE_ASYM) {
 417                         if (remote & LPA_PAUSE_CAP)
 418                                 pause_enab |= (B44_FLAG_TX_PAUSE |
 419                                                B44_FLAG_RX_PAUSE);
 420                         else if (remote & LPA_PAUSE_ASYM)
 421                                 pause_enab |= B44_FLAG_RX_PAUSE;
 422                 } else {
 423                         if (remote & LPA_PAUSE_CAP)
 424                                 pause_enab |= (B44_FLAG_TX_PAUSE |
 425                                                B44_FLAG_RX_PAUSE);
 426                 }
 427         } else if (local & ADVERTISE_PAUSE_ASYM) {
 428                 if ((remote & LPA_PAUSE_CAP) &&
 429                     (remote & LPA_PAUSE_ASYM))
 430                         pause_enab |= B44_FLAG_TX_PAUSE;
 431         }
 432
 433         __b44_set_flow_ctrl(bp, pause_enab);
 434 }
 435
 436 static int b44_setup_phy(struct b44 *bp)
 437 {
 438         u32 val;
 439         int err;
 440
 441         if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
 442                 goto out;
 443         if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
 444                                 val & MII_ALEDCTRL_ALLMSK)) != 0)
 445                 goto out;
 446         if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0)
 447                 goto out;
 448         if ((err = b44_writephy(bp, B44_MII_TLEDCTRL,
 449                                 val | MII_TLEDCTRL_ENABLE)) != 0)
 450                 goto out;
 451
 452         if (!(bp->flags & B44_FLAG_FORCE_LINK)) {
 453                 u32 adv = ADVERTISE_CSMA;
 454
 455                 if (bp->flags & B44_FLAG_ADV_10HALF)
 456                         adv |= ADVERTISE_10HALF;
 457                 if (bp->flags & B44_FLAG_ADV_10FULL)
 458                         adv |= ADVERTISE_10FULL;
 459                 if (bp->flags & B44_FLAG_ADV_100HALF)
 460                         adv |= ADVERTISE_100HALF;
 461                 if (bp->flags & B44_FLAG_ADV_100FULL)
 462                         adv |= ADVERTISE_100FULL;
 463
 464                 if (bp->flags & B44_FLAG_PAUSE_AUTO)
 465                         adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 466
 467                 if ((err = b44_writephy(bp, MII_ADVERTISE, adv)) != 0)
 468                         goto out;
 469                 if ((err = b44_writephy(bp, MII_BMCR, (BMCR_ANENABLE |
 470                                                        BMCR_ANRESTART))) != 0)
 471                         goto out;
 472         } else {
 473                 u32 bmcr;
 474
 475                 if ((err = b44_readphy(bp, MII_BMCR, &bmcr)) != 0)
 476                         goto out;
 477                 bmcr &= ~(BMCR_FULLDPLX | BMCR_ANENABLE | BMCR_SPEED100);
 478                 if (bp->flags & B44_FLAG_100_BASE_T)
 479                         bmcr |= BMCR_SPEED100;
 480                 if (bp->flags & B44_FLAG_FULL_DUPLEX)
 481                         bmcr |= BMCR_FULLDPLX;
 482                 if ((err = b44_writephy(bp, MII_BMCR, bmcr)) != 0)
 483                         goto out;
 484
 485                 /* Since we will not be negotiating there is no safe way
 486                  * to determine if the link partner supports flow control
 487                  * or not.  So just disable it completely in this case.
 488                  */
 489                 b44_set_flow_ctrl(bp, 0, 0);
 490         }
 491
 492 out:
 493         return err;
 494 }
 495
 496 static void b44_stats_update(struct b44 *bp)
 497 {
 498         unsigned long reg;
 499         u32 *val;
 500
 501         val = &bp->hw_stats.tx_good_octets;
 502         for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
 503                 *val++ += br32(bp, reg);
 504         }
 505         val = &bp->hw_stats.rx_good_octets;
 506         for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
 507                 *val++ += br32(bp, reg);
 508         }
 509 }
 510
 511 static void b44_link_report(struct b44 *bp)
 512 {
 513         if (!netif_carrier_ok(bp->dev)) {
 514                 printk(KERN_INFO PFX "%s: Link is down.\n", bp->dev->name);
 515         } else {
 516                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
 517                        bp->dev->name,
 518                        (bp->flags & B44_FLAG_100_BASE_T) ? 100 : 10,
 519                        (bp->flags & B44_FLAG_FULL_DUPLEX) ? "full" : "half");
 520
 521                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
 522                        "%s for RX.\n",
 523                        bp->dev->name,
 524                        (bp->flags & B44_FLAG_TX_PAUSE) ? "on" : "off",
 525                        (bp->flags & B44_FLAG_RX_PAUSE) ? "on" : "off");
 526         }
 527 }
 528
 529 static void b44_check_phy(struct b44 *bp)
 530 {
 531         u32 bmsr, aux;
 532
 533         if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
 534             !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
 535             (bmsr != 0xffff)) {
 536                 if (aux & MII_AUXCTRL_SPEED)
 537                         bp->flags |= B44_FLAG_100_BASE_T;
 538                 else
 539                         bp->flags &= ~B44_FLAG_100_BASE_T;
 540                 if (aux & MII_AUXCTRL_DUPLEX)
 541                         bp->flags |= B44_FLAG_FULL_DUPLEX;
 542                 else
 543                         bp->flags &= ~B44_FLAG_FULL_DUPLEX;
 544
 545                 if (!netif_carrier_ok(bp->dev) &&
 546                     (bmsr & BMSR_LSTATUS)) {
 547                         u32 val = br32(bp, B44_TX_CTRL);
 548                         u32 local_adv, remote_adv;
 549
 550                         if (bp->flags & B44_FLAG_FULL_DUPLEX)
 551                                 val |= TX_CTRL_DUPLEX;
 552                         else
 553                                 val &= ~TX_CTRL_DUPLEX;
 554                         bw32(bp, B44_TX_CTRL, val);
 555
 556                         if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
 557                             !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
 558                             !b44_readphy(bp, MII_LPA, &remote_adv))
 559                                 b44_set_flow_ctrl(bp, local_adv, remote_adv);
 560
 561                         /* Link now up */
 562                         netif_carrier_on(bp->dev);
 563                         b44_link_report(bp);
 564                 } else if (netif_carrier_ok(bp->dev) && !(bmsr & BMSR_LSTATUS)) {
 565                         /* Link now down */
 566                         netif_carrier_off(bp->dev);
 567                         b44_link_report(bp);
 568                 }
 569
 570                 if (bmsr & BMSR_RFAULT)
 571                         printk(KERN_WARNING PFX "%s: Remote fault detected in PHY\n",
 572                                bp->dev->name);
 573                 if (bmsr & BMSR_JCD)
 574                         printk(KERN_WARNING PFX "%s: Jabber detected in PHY\n",
 575                                bp->dev->name);
 576         }
 577 }
 578
 579 static void b44_timer(unsigned long __opaque)
 580 {
 581         struct b44 *bp = (struct b44 *) __opaque;
 582
 583         spin_lock_irq(&bp->lock);
 584
 585         b44_check_phy(bp);
 586
 587         b44_stats_update(bp);
 588
 589         spin_unlock_irq(&bp->lock);
 590
 591         bp->timer.expires = jiffies + HZ;
 592         add_timer(&bp->timer);
 593 }
 594
 595 static void b44_tx(struct b44 *bp)
 596 {
 597         u32 cur, cons;
 598
 599         cur  = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
 600         cur /= sizeof(struct dma_desc);
 601
 602         /* XXX needs updating when NETIF_F_SG is supported */
 603         for (cons = bp->tx_cons; cons != cur; cons = NEXT_TX(cons)) {
 604                 struct ring_info *rp = &bp->tx_buffers[cons];
 605                 struct sk_buff *skb = rp->skb;
 606
 607                 if (unlikely(skb == NULL))
 608                         BUG();
 609
 610                 pci_unmap_single(bp->pdev,
 611                                  pci_unmap_addr(rp, mapping),
 612                                  skb->len,
 613                                  PCI_DMA_TODEVICE);
 614                 rp->skb = NULL;
 615                 dev_kfree_skb_irq(skb);
 616         }
 617
 618         bp->tx_cons = cons;
 619         if (netif_queue_stopped(bp->dev) &&
 620             TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
 621                 netif_wake_queue(bp->dev);
 622
 623         bw32(bp, B44_GPTIMER, 0);
 624 }
 625
 626 /* Works like this.  This chip writes a 'struct rx_header" 30 bytes
 627  * before the DMA address you give it.  So we allocate 30 more bytes
 628  * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
 629  * point the chip at 30 bytes past where the rx_header will go.
 630  */
 631 static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
 632 {
 633         struct dma_desc *dp;
 634         struct ring_info *src_map, *map;
 635         struct rx_header *rh;
 636         struct sk_buff *skb;
 637         dma_addr_t mapping;
 638         int dest_idx;
 639         u32 ctrl;
 640
 641         src_map = NULL;
 642         if (src_idx >= 0)
 643                 src_map = &bp->rx_buffers[src_idx];
 644         dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
 645         map = &bp->rx_buffers[dest_idx];
 646         skb = dev_alloc_skb(RX_PKT_BUF_SZ);
 647         if (skb == NULL)
 648                 return -ENOMEM;
 649
 650         mapping = pci_map_single(bp->pdev, skb->data,
 651                                  RX_PKT_BUF_SZ,
 652                                  PCI_DMA_FROMDEVICE);
 653
 654         /* Hardware bug work-around, the chip is unable to do PCI DMA
 655            to/from anything above 1GB :-( */
 656         if(mapping+RX_PKT_BUF_SZ > B44_DMA_MASK) {
 657                 /* Sigh... */
 658                 pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
 659                 dev_kfree_skb_any(skb);
 660                 skb = __dev_alloc_skb(RX_PKT_BUF_SZ,GFP_DMA);
 661                 if (skb == NULL)
 662                         return -ENOMEM;
 663                 mapping = pci_map_single(bp->pdev, skb->data,
 664                                          RX_PKT_BUF_SZ,
 665                                          PCI_DMA_FROMDEVICE);
 666                 if(mapping+RX_PKT_BUF_SZ > B44_DMA_MASK) {
 667                         pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
 668                         dev_kfree_skb_any(skb);
 669                         return -ENOMEM;
 670                 }
 671         }
 672
 673         skb->dev = bp->dev;
 674         skb_reserve(skb, bp->rx_offset);
 675
 676         rh = (struct rx_header *)
 677                 (skb->data - bp->rx_offset);
 678         rh->len = 0;
 679         rh->flags = 0;
 680
 681         map->skb = skb;
 682         pci_unmap_addr_set(map, mapping, mapping);
 683
 684         if (src_map != NULL)
 685                 src_map->skb = NULL;
 686
 687         ctrl  = (DESC_CTRL_LEN & (RX_PKT_BUF_SZ - bp->rx_offset));
 688         if (dest_idx == (B44_RX_RING_SIZE - 1))
 689                 ctrl |= DESC_CTRL_EOT;
 690
 691         dp = &bp->rx_ring[dest_idx];
 692         dp->ctrl = cpu_to_le32(ctrl);
 693         dp->addr = cpu_to_le32((u32) mapping + bp->rx_offset + bp->dma_offset);
 694
 695         if (bp->flags & B44_FLAG_RX_RING_HACK)
 696                 b44_sync_dma_desc_for_device(bp->pdev, bp->rx_ring_dma,
 697                                              dest_idx * sizeof(dp),
 698                                              DMA_BIDIRECTIONAL);
 699
 700         return RX_PKT_BUF_SZ;
 701 }
 702
 703 static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
 704 {
 705         struct dma_desc *src_desc, *dest_desc;
 706         struct ring_info *src_map, *dest_map;
 707         struct rx_header *rh;
 708         int dest_idx;
 709         u32 ctrl;
 710
 711         dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
 712         dest_desc = &bp->rx_ring[dest_idx];
 713         dest_map = &bp->rx_buffers[dest_idx];
 714         src_desc = &bp->rx_ring[src_idx];
 715         src_map = &bp->rx_buffers[src_idx];
 716
 717         dest_map->skb = src_map->skb;
 718         rh = (struct rx_header *) src_map->skb->data;
 719         rh->len = 0;
 720         rh->flags = 0;
 721         pci_unmap_addr_set(dest_map, mapping,
 722                            pci_unmap_addr(src_map, mapping));
 723
 724         if (bp->flags & B44_FLAG_RX_RING_HACK)
 725                 b44_sync_dma_desc_for_cpu(bp->pdev, bp->rx_ring_dma,
 726                                           src_idx * sizeof(src_desc),
 727                                           DMA_BIDIRECTIONAL);
 728
 729         ctrl = src_desc->ctrl;
 730         if (dest_idx == (B44_RX_RING_SIZE - 1))
 731                 ctrl |= cpu_to_le32(DESC_CTRL_EOT);
 732         else
 733                 ctrl &= cpu_to_le32(~DESC_CTRL_EOT);
 734
 735         dest_desc->ctrl = ctrl;
 736         dest_desc->addr = src_desc->addr;
 737
 738         src_map->skb = NULL;
 739
 740         if (bp->flags & B44_FLAG_RX_RING_HACK)
 741                 b44_sync_dma_desc_for_device(bp->pdev, bp->rx_ring_dma,
 742                                              dest_idx * sizeof(dest_desc),
 743                                              DMA_BIDIRECTIONAL);
 744
 745         pci_dma_sync_single_for_device(bp->pdev, src_desc->addr,
 746                                        RX_PKT_BUF_SZ,
 747                                        PCI_DMA_FROMDEVICE);
 748 }
 749
 750 static int b44_rx(struct b44 *bp, int budget)
 751 {
 752         int received;
 753         u32 cons, prod;
 754
 755         received = 0;
 756         prod  = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
 757         prod /= sizeof(struct dma_desc);
 758         cons = bp->rx_cons;
 759
 760         while (cons != prod && budget > 0) {
 761                 struct ring_info *rp = &bp->rx_buffers[cons];
 762                 struct sk_buff *skb = rp->skb;
 763                 dma_addr_t map = pci_unmap_addr(rp, mapping);
 764                 struct rx_header *rh;
 765                 u16 len;
 766
 767                 pci_dma_sync_single_for_cpu(bp->pdev, map,
 768                                             RX_PKT_BUF_SZ,
 769                                             PCI_DMA_FROMDEVICE);
 770                 rh = (struct rx_header *) skb->data;
 771                 len = cpu_to_le16(rh->len);
 772                 if ((len > (RX_PKT_BUF_SZ - bp->rx_offset)) ||
 773                     (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
 774                 drop_it:
 775                         b44_recycle_rx(bp, cons, bp->rx_prod);
 776                 drop_it_no_recycle:
 777                         bp->stats.rx_dropped++;
 778                         goto next_pkt;
 779                 }
 780
 781                 if (len == 0) {
 782                         int i = 0;
 783
 784                         do {
 785                                 udelay(2);
 786                                 barrier();
 787                                 len = cpu_to_le16(rh->len);
 788                         } while (len == 0 && i++ < 5);
 789                         if (len == 0)
 790                                 goto drop_it;
 791                 }
 792
 793                 /* Omit CRC. */
 794                 len -= 4;
 795
 796                 if (len > RX_COPY_THRESHOLD) {
 797                         int skb_size;
 798                         skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
 799                         if (skb_size < 0)
 800                                 goto drop_it;
 801                         pci_unmap_single(bp->pdev, map,
 802                                          skb_size, PCI_DMA_FROMDEVICE);
 803                         /* Leave out rx_header */
 804                         skb_put(skb, len+bp->rx_offset);
 805                         skb_pull(skb,bp->rx_offset);
 806                 } else {
 807                         struct sk_buff *copy_skb;
 808
 809                         b44_recycle_rx(bp, cons, bp->rx_prod);
 810                         copy_skb = dev_alloc_skb(len + 2);
 811                         if (copy_skb == NULL)
 812                                 goto drop_it_no_recycle;
 813
 814                         copy_skb->dev = bp->dev;
 815                         skb_reserve(copy_skb, 2);
 816                         skb_put(copy_skb, len);
 817                         /* DMA sync done above, copy just the actual packet */
 818                         memcpy(copy_skb->data, skb->data+bp->rx_offset, len);
 819
 820                         skb = copy_skb;
 821                 }
 822                 skb->ip_summed = CHECKSUM_NONE;
 823                 skb->protocol = eth_type_trans(skb, bp->dev);
 824                 netif_receive_skb(skb);
 825                 bp->dev->last_rx = jiffies;
 826                 received++;
 827                 budget--;
 828         next_pkt:
 829                 bp->rx_prod = (bp->rx_prod + 1) &
 830                         (B44_RX_RING_SIZE - 1);
 831                 cons = (cons + 1) & (B44_RX_RING_SIZE - 1);
 832         }
 833
 834         bp->rx_cons = cons;
 835         bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
 836
 837         return received;
 838 }
 839
 840 static int b44_poll(struct net_device *netdev, int *budget)
 841 {
 842         struct b44 *bp = netdev_priv(netdev);
 843         int done;
 844
 845         spin_lock_irq(&bp->lock);
 846
 847         if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
 848                 /* spin_lock(&bp->tx_lock); */
 849                 b44_tx(bp);
 850                 /* spin_unlock(&bp->tx_lock); */
 851         }
 852         spin_unlock_irq(&bp->lock);
 853
 854         done = 1;
 855         if (bp->istat & ISTAT_RX) {
 856                 int orig_budget = *budget;
 857                 int work_done;
 858
 859                 if (orig_budget > netdev->quota)
 860                         orig_budget = netdev->quota;
 861
 862                 work_done = b44_rx(bp, orig_budget);
 863
 864                 *budget -= work_done;
 865                 netdev->quota -= work_done;
 866
 867                 if (work_done >= orig_budget)
 868                         done = 0;
 869         }
 870
 871         if (bp->istat & ISTAT_ERRORS) {
 872                 spin_lock_irq(&bp->lock);
 873                 b44_halt(bp);
 874                 b44_init_rings(bp);
 875                 b44_init_hw(bp);
 876                 netif_wake_queue(bp->dev);
 877                 spin_unlock_irq(&bp->lock);
 878                 done = 1;
 879         }
 880
 881         if (done) {
 882                 netif_rx_complete(netdev);
 883                 b44_enable_ints(bp);
 884         }
 885
 886         return (done ? 0 : 1);
 887 }
 888
 889 static irqreturn_t b44_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 890 {
 891         struct net_device *dev = dev_id;
 892         struct b44 *bp = netdev_priv(dev);
 893         unsigned long flags;
 894         u32 istat, imask;
 895         int handled = 0;
 896
 897         spin_lock_irqsave(&bp->lock, flags);
 898
 899         istat = br32(bp, B44_ISTAT);
 900         imask = br32(bp, B44_IMASK);
 901
 902         /* ??? What the fuck is the purpose of the interrupt mask
 903          * ??? register if we have to mask it out by hand anyways?
 904          */
 905         istat &= imask;
 906         if (istat) {
 907                 handled = 1;
 908                 if (netif_rx_schedule_prep(dev)) {
 909                         /* NOTE: These writes are posted by the readback of
 910                          *       the ISTAT register below.
 911                          */
 912                         bp->istat = istat;
 913                         __b44_disable_ints(bp);
 914                         __netif_rx_schedule(dev);
 915                 } else {
 916                         printk(KERN_ERR PFX "%s: Error, poll already scheduled\n",
 917                                dev->name);
 918                 }
 919
 920                 bw32(bp, B44_ISTAT, istat);
 921                 br32(bp, B44_ISTAT);
 922         }
 923         spin_unlock_irqrestore(&bp->lock, flags);
 924         return IRQ_RETVAL(handled);
 925 }
 926
 927 static void b44_tx_timeout(struct net_device *dev)
 928 {
 929         struct b44 *bp = netdev_priv(dev);
 930
 931         printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
 932                dev->name);
 933
 934         spin_lock_irq(&bp->lock);
 935
 936         b44_halt(bp);
 937         b44_init_rings(bp);
 938         b44_init_hw(bp);
 939
 940         spin_unlock_irq(&bp->lock);
 941
 942         b44_enable_ints(bp);
 943
 944         netif_wake_queue(dev);
 945 }
 946
 947 static int b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
 948 {
 949         struct b44 *bp = netdev_priv(dev);
 950         struct sk_buff *bounce_skb;
 951         dma_addr_t mapping;
 952         u32 len, entry, ctrl;
 953
 954         len = skb->len;
 955         spin_lock_irq(&bp->lock);
 956
 957         /* This is a hard error, log it. */
 958         if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) {
 959                 netif_stop_queue(dev);
 960                 spin_unlock_irq(&bp->lock);
 961                 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
 962                        dev->name);
 963                 return 1;
 964         }
 965
 966         mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
 967         if(mapping+len > B44_DMA_MASK) {
 968                 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
 969                 pci_unmap_single(bp->pdev, mapping, len, PCI_DMA_TODEVICE);
 970
 971                 bounce_skb = __dev_alloc_skb(TX_PKT_BUF_SZ,
 972                                              GFP_ATOMIC|GFP_DMA);
 973                 if (!bounce_skb)
 974                         return NETDEV_TX_BUSY;
 975
 976                 mapping = pci_map_single(bp->pdev, bounce_skb->data,
 977                                          len, PCI_DMA_TODEVICE);
 978                 if(mapping+len > B44_DMA_MASK) {
 979                         pci_unmap_single(bp->pdev, mapping,
 980                                          len, PCI_DMA_TODEVICE);
 981                         dev_kfree_skb_any(bounce_skb);
 982                         return NETDEV_TX_BUSY;
 983                 }
 984
 985                 memcpy(skb_put(bounce_skb, len), skb->data, skb->len);
 986                 dev_kfree_skb_any(skb);
 987                 skb = bounce_skb;
 988         }
 989
 990         entry = bp->tx_prod;
 991         bp->tx_buffers[entry].skb = skb;
 992         pci_unmap_addr_set(&bp->tx_buffers[entry], mapping, mapping);
 993
 994         ctrl  = (len & DESC_CTRL_LEN);
 995         ctrl |= DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF;
 996         if (entry == (B44_TX_RING_SIZE - 1))
 997                 ctrl |= DESC_CTRL_EOT;
 998
 999         bp->tx_ring[entry].ctrl = cpu_to_le32(ctrl);
1000         bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
1001
1002         if (bp->flags & B44_FLAG_TX_RING_HACK)
1003                 b44_sync_dma_desc_for_device(bp->pdev, bp->tx_ring_dma,
1004                                              entry * sizeof(bp->tx_ring[0]),
1005                                              DMA_TO_DEVICE);
1006
1007         entry = NEXT_TX(entry);
1008
1009         bp->tx_prod = entry;
1010
1011         wmb();
1012
1013         bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1014         if (bp->flags & B44_FLAG_BUGGY_TXPTR)
1015                 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1016         if (bp->flags & B44_FLAG_REORDER_BUG)
1017                 br32(bp, B44_DMATX_PTR);
1018
1019         if (TX_BUFFS_AVAIL(bp) < 1)
1020                 netif_stop_queue(dev);
1021
1022         spin_unlock_irq(&bp->lock);
1023
1024         dev->trans_start = jiffies;
1025
1026         return 0;
1027 }
1028
1029 static int b44_change_mtu(struct net_device *dev, int new_mtu)
1030 {
1031         struct b44 *bp = netdev_priv(dev);
1032
1033         if (new_mtu < B44_MIN_MTU || new_mtu > B44_MAX_MTU)
1034                 return -EINVAL;
1035
1036         if (!netif_running(dev)) {
1037                 /* We'll just catch it later when the
1038                  * device is up'd.
1039                  */
1040                 dev->mtu = new_mtu;
1041                 return 0;
1042         }
1043
1044         spin_lock_irq(&bp->lock);
1045         b44_halt(bp);
1046         dev->mtu = new_mtu;
1047         b44_init_rings(bp);
1048         b44_init_hw(bp);
1049         spin_unlock_irq(&bp->lock);
1050
1051         b44_enable_ints(bp);
1052
1053         return 0;
1054 }
1055
1056 /* Free up pending packets in all rx/tx rings.
1057  *
1058  * The chip has been shut down and the driver detached from
1059  * the networking, so no interrupts or new tx packets will
1060  * end up in the driver.  bp->lock is not held and we are not
1061  * in an interrupt context and thus may sleep.
1062  */
1063 static void b44_free_rings(struct b44 *bp)
1064 {
1065         struct ring_info *rp;
1066         int i;
1067
1068         for (i = 0; i < B44_RX_RING_SIZE; i++) {
1069                 rp = &bp->rx_buffers[i];
1070
1071                 if (rp->skb == NULL)
1072                         continue;
1073                 pci_unmap_single(bp->pdev,
1074                                  pci_unmap_addr(rp, mapping),
1075                                  RX_PKT_BUF_SZ,
1076                                  PCI_DMA_FROMDEVICE);
1077                 dev_kfree_skb_any(rp->skb);
1078                 rp->skb = NULL;
1079         }
1080
1081         /* XXX needs changes once NETIF_F_SG is set... */
1082         for (i = 0; i < B44_TX_RING_SIZE; i++) {
1083                 rp = &bp->tx_buffers[i];
1084
1085                 if (rp->skb == NULL)
1086                         continue;
1087                 pci_unmap_single(bp->pdev,
1088                                  pci_unmap_addr(rp, mapping),
1089                                  rp->skb->len,
1090                                  PCI_DMA_TODEVICE);
1091                 dev_kfree_skb_any(rp->skb);
1092                 rp->skb = NULL;
1093         }
1094 }
1095
1096 /* Initialize tx/rx rings for packet processing.
1097  *
1098  * The chip has been shut down and the driver detached from
1099  * the networking, so no interrupts or new tx packets will
1100  * end up in the driver.  bp->lock is not held and we are not
1101  * in an interrupt context and thus may sleep.
1102  */
1103 static void b44_init_rings(struct b44 *bp)
1104 {
1105         int i;
1106
1107         b44_free_rings(bp);
1108
1109         memset(bp->rx_ring, 0, B44_RX_RING_BYTES);
1110         memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
1111
1112         if (bp->flags & B44_FLAG_RX_RING_HACK)
1113                 dma_sync_single_for_device(&bp->pdev->dev, bp->rx_ring_dma,
1114                                            DMA_TABLE_BYTES,
1115                                            PCI_DMA_BIDIRECTIONAL);
1116
1117         if (bp->flags & B44_FLAG_TX_RING_HACK)
1118                 dma_sync_single_for_device(&bp->pdev->dev, bp->tx_ring_dma,
1119                                            DMA_TABLE_BYTES,
1120                                            PCI_DMA_TODEVICE);
1121
1122         for (i = 0; i < bp->rx_pending; i++) {
1123                 if (b44_alloc_rx_skb(bp, -1, i) < 0)
1124                         break;
1125         }
1126 }
1127
1128 /*
1129  * Must not be invoked with interrupt sources disabled and
1130  * the hardware shutdown down.
1131  */
1132 static void b44_free_consistent(struct b44 *bp)
1133 {
1134         if (bp->rx_buffers) {
1135                 kfree(bp->rx_buffers);
1136                 bp->rx_buffers = NULL;
1137         }
1138         if (bp->tx_buffers) {
1139                 kfree(bp->tx_buffers);
1140                 bp->tx_buffers = NULL;
1141         }
1142         if (bp->rx_ring) {
1143                 if (bp->flags & B44_FLAG_RX_RING_HACK) {
1144                         dma_unmap_single(&bp->pdev->dev, bp->rx_ring_dma,
1145                                          DMA_TABLE_BYTES,
1146                                          DMA_BIDIRECTIONAL);
1147                         kfree(bp->rx_ring);
1148                 } else
1149                         pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
1150                                             bp->rx_ring, bp->rx_ring_dma);
1151                 bp->rx_ring = NULL;
1152                 bp->flags &= ~B44_FLAG_RX_RING_HACK;
1153         }
1154         if (bp->tx_ring) {
1155                 if (bp->flags & B44_FLAG_TX_RING_HACK) {
1156                         dma_unmap_single(&bp->pdev->dev, bp->tx_ring_dma,
1157                                          DMA_TABLE_BYTES,
1158                                          DMA_TO_DEVICE);
1159                         kfree(bp->tx_ring);
1160                 } else
1161                         pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
1162                                             bp->tx_ring, bp->tx_ring_dma);
1163                 bp->tx_ring = NULL;
1164                 bp->flags &= ~B44_FLAG_TX_RING_HACK;
1165         }
1166 }
1167
1168 /*
1169  * Must not be invoked with interrupt sources disabled and
1170  * the hardware shutdown down.  Can sleep.
1171  */
1172 static int b44_alloc_consistent(struct b44 *bp)
1173 {
1174         int size;
1175
1176         size  = B44_RX_RING_SIZE * sizeof(struct ring_info);
1177         bp->rx_buffers = kmalloc(size, GFP_KERNEL);
1178         if (!bp->rx_buffers)
1179                 goto out_err;
1180         memset(bp->rx_buffers, 0, size);
1181
1182         size = B44_TX_RING_SIZE * sizeof(struct ring_info);
1183         bp->tx_buffers = kmalloc(size, GFP_KERNEL);
1184         if (!bp->tx_buffers)
1185                 goto out_err;
1186         memset(bp->tx_buffers, 0, size);
1187
1188         size = DMA_TABLE_BYTES;
1189         bp->rx_ring = pci_alloc_consistent(bp->pdev, size, &bp->rx_ring_dma);
1190         if (!bp->rx_ring) {
1191                 /* Allocation may have failed due to pci_alloc_consistent
1192                    insisting on use of GFP_DMA, which is more restrictive
1193                    than necessary...  */
1194                 struct dma_desc *rx_ring;
1195                 dma_addr_t rx_ring_dma;
1196
1197                 if (!(rx_ring = (struct dma_desc *)kmalloc(size, GFP_KERNEL)))
1198                         goto out_err;
1199
1200                 memset(rx_ring, 0, size);
1201                 rx_ring_dma = dma_map_single(&bp->pdev->dev, rx_ring,
1202                                              DMA_TABLE_BYTES,
1203                                              DMA_BIDIRECTIONAL);
1204
1205                 if (rx_ring_dma + size > B44_DMA_MASK) {
1206                         kfree(rx_ring);
1207                         goto out_err;
1208                 }
1209
1210                 bp->rx_ring = rx_ring;
1211                 bp->rx_ring_dma = rx_ring_dma;
1212                 bp->flags |= B44_FLAG_RX_RING_HACK;
1213         }
1214
1215         bp->tx_ring = pci_alloc_consistent(bp->pdev, size, &bp->tx_ring_dma);
1216         if (!bp->tx_ring) {
1217                 /* Allocation may have failed due to pci_alloc_consistent
1218                    insisting on use of GFP_DMA, which is more restrictive
1219                    than necessary...  */
1220                 struct dma_desc *tx_ring;
1221                 dma_addr_t tx_ring_dma;
1222
1223                 if (!(tx_ring = (struct dma_desc *)kmalloc(size, GFP_KERNEL)))
1224                         goto out_err;
1225
1226                 memset(tx_ring, 0, size);
1227                 tx_ring_dma = dma_map_single(&bp->pdev->dev, tx_ring,
1228                                              DMA_TABLE_BYTES,
1229                                              DMA_TO_DEVICE);
1230
1231                 if (tx_ring_dma + size > B44_DMA_MASK) {
1232                         kfree(tx_ring);
1233                         goto out_err;
1234                 }
1235
1236                 bp->tx_ring = tx_ring;
1237                 bp->tx_ring_dma = tx_ring_dma;
1238                 bp->flags |= B44_FLAG_TX_RING_HACK;
1239         }
1240
1241         return 0;
1242
1243 out_err:
1244         b44_free_consistent(bp);
1245         return -ENOMEM;
1246 }
1247
1248 /* bp->lock is held. */
1249 static void b44_clear_stats(struct b44 *bp)
1250 {
1251         unsigned long reg;
1252
1253         bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1254         for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
1255                 br32(bp, reg);
1256         for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
1257                 br32(bp, reg);
1258 }
1259
1260 /* bp->lock is held. */
1261 static void b44_chip_reset(struct b44 *bp)
1262 {
1263         if (ssb_is_core_up(bp)) {
1264                 bw32(bp, B44_RCV_LAZY, 0);
1265                 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
1266                 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 100, 1);
1267                 bw32(bp, B44_DMATX_CTRL, 0);
1268                 bp->tx_prod = bp->tx_cons = 0;
1269                 if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
1270                         b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
1271                                      100, 0);
1272                 }
1273                 bw32(bp, B44_DMARX_CTRL, 0);
1274                 bp->rx_prod = bp->rx_cons = 0;
1275         } else {
1276                 ssb_pci_setup(bp, (bp->core_unit == 0 ?
1277                                    SBINTVEC_ENET0 :
1278                                    SBINTVEC_ENET1));
1279         }
1280
1281         ssb_core_reset(bp);
1282
1283         b44_clear_stats(bp);
1284
1285         /* Make PHY accessible. */
1286         bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1287                              (0x0d & MDIO_CTRL_MAXF_MASK)));
1288         br32(bp, B44_MDIO_CTRL);
1289
1290         if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
1291                 bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
1292                 br32(bp, B44_ENET_CTRL);
1293                 bp->flags &= ~B44_FLAG_INTERNAL_PHY;
1294         } else {
1295                 u32 val = br32(bp, B44_DEVCTRL);
1296
1297                 if (val & DEVCTRL_EPR) {
1298                         bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
1299                         br32(bp, B44_DEVCTRL);
1300                         udelay(100);
1301                 }
1302                 bp->flags |= B44_FLAG_INTERNAL_PHY;
1303         }
1304 }
1305
1306 /* bp->lock is held. */
1307 static void b44_halt(struct b44 *bp)
1308 {
1309         b44_disable_ints(bp);
1310         b44_chip_reset(bp);
1311 }
1312
1313 /* bp->lock is held. */
1314 static void __b44_set_mac_addr(struct b44 *bp)
1315 {
1316         bw32(bp, B44_CAM_CTRL, 0);
1317         if (!(bp->dev->flags & IFF_PROMISC)) {
1318                 u32 val;
1319
1320                 __b44_cam_write(bp, bp->dev->dev_addr, 0);
1321                 val = br32(bp, B44_CAM_CTRL);
1322                 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1323         }
1324 }
1325
1326 static int b44_set_mac_addr(struct net_device *dev, void *p)
1327 {
1328         struct b44 *bp = netdev_priv(dev);
1329         struct sockaddr *addr = p;
1330
1331         if (netif_running(dev))
1332                 return -EBUSY;
1333
1334         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1335
1336         spin_lock_irq(&bp->lock);
1337         __b44_set_mac_addr(bp);
1338         spin_unlock_irq(&bp->lock);
1339
1340         return 0;
1341 }
1342
1343 /* Called at device open time to get the chip ready for
1344  * packet processing.  Invoked with bp->lock held.
1345  */
1346 static void __b44_set_rx_mode(struct net_device *);
1347 static void b44_init_hw(struct b44 *bp)
1348 {
1349         u32 val;
1350
1351         b44_chip_reset(bp);
1352         b44_phy_reset(bp);
1353         b44_setup_phy(bp);
1354
1355         /* Enable CRC32, set proper LED modes and power on PHY */
1356         bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
1357         bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
1358
1359         /* This sets the MAC address too.  */
1360         __b44_set_rx_mode(bp->dev);
1361
1362         /* MTU + eth header + possible VLAN tag + struct rx_header */
1363         bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1364         bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1365
1366         bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
1367         bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
1368         bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
1369         bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1370                               (bp->rx_offset << DMARX_CTRL_ROSHIFT)));
1371         bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
1372
1373         bw32(bp, B44_DMARX_PTR, bp->rx_pending);
1374         bp->rx_prod = bp->rx_pending;
1375
1376         bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1377
1378         val = br32(bp, B44_ENET_CTRL);
1379         bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
1380 }
1381
1382 static int b44_open(struct net_device *dev)
1383 {
1384         struct b44 *bp = netdev_priv(dev);
1385         int err;
1386
1387         err = b44_alloc_consistent(bp);
1388         if (err)
1389                 return err;
1390
1391         err = request_irq(dev->irq, b44_interrupt, SA_SHIRQ, dev->name, dev);
1392         if (err)
1393                 goto err_out_free;
1394
1395         spin_lock_irq(&bp->lock);
1396
1397         b44_init_rings(bp);
1398         b44_init_hw(bp);
1399         bp->flags |= B44_FLAG_INIT_COMPLETE;
1400
1401         netif_carrier_off(dev);
1402         b44_check_phy(bp);
1403
1404         spin_unlock_irq(&bp->lock);
1405
1406         init_timer(&bp->timer);
1407         bp->timer.expires = jiffies + HZ;
1408         bp->timer.data = (unsigned long) bp;
1409         bp->timer.function = b44_timer;
1410         add_timer(&bp->timer);
1411
1412         b44_enable_ints(bp);
1413
1414         return 0;
1415
1416 err_out_free:
1417         b44_free_consistent(bp);
1418         return err;
1419 }
1420
1421 #if 0
1422 /*static*/ void b44_dump_state(struct b44 *bp)
1423 {
1424         u32 val32, val32_2, val32_3, val32_4, val32_5;
1425         u16 val16;
1426
1427         pci_read_config_word(bp->pdev, PCI_STATUS, &val16);
1428         printk("DEBUG: PCI status [%04x] \n", val16);
1429
1430 }
1431 #endif
1432
1433 #ifdef CONFIG_NET_POLL_CONTROLLER
1434 /*
1435  * Polling receive - used by netconsole and other diagnostic tools
1436  * to allow network i/o with interrupts disabled.
1437  */
1438 static void b44_poll_controller(struct net_device *dev)
1439 {
1440         disable_irq(dev->irq);
1441         b44_interrupt(dev->irq, dev, NULL);
1442         enable_irq(dev->irq);
1443 }
1444 #endif
1445
1446 static int b44_close(struct net_device *dev)
1447 {
1448         struct b44 *bp = netdev_priv(dev);
1449
1450         netif_stop_queue(dev);
1451
1452         del_timer_sync(&bp->timer);
1453
1454         spin_lock_irq(&bp->lock);
1455
1456 #if 0
1457         b44_dump_state(bp);
1458 #endif
1459         b44_halt(bp);
1460         b44_free_rings(bp);
1461         bp->flags &= ~B44_FLAG_INIT_COMPLETE;
1462         netif_carrier_off(bp->dev);
1463
1464         spin_unlock_irq(&bp->lock);
1465
1466         free_irq(dev->irq, dev);
1467
1468         b44_free_consistent(bp);
1469
1470         return 0;
1471 }
1472
1473 static struct net_device_stats *b44_get_stats(struct net_device *dev)
1474 {
1475         struct b44 *bp = netdev_priv(dev);
1476         struct net_device_stats *nstat = &bp->stats;
1477         struct b44_hw_stats *hwstat = &bp->hw_stats;
1478
1479         /* Convert HW stats into netdevice stats. */
1480         nstat->rx_packets = hwstat->rx_pkts;
1481         nstat->tx_packets = hwstat->tx_pkts;
1482         nstat->rx_bytes   = hwstat->rx_octets;
1483         nstat->tx_bytes   = hwstat->tx_octets;
1484         nstat->tx_errors  = (hwstat->tx_jabber_pkts +
1485                              hwstat->tx_oversize_pkts +
1486                              hwstat->tx_underruns +
1487                              hwstat->tx_excessive_cols +
1488                              hwstat->tx_late_cols);
1489         nstat->multicast  = hwstat->tx_multicast_pkts;
1490         nstat->collisions = hwstat->tx_total_cols;
1491
1492         nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1493                                    hwstat->rx_undersize);
1494         nstat->rx_over_errors   = hwstat->rx_missed_pkts;
1495         nstat->rx_frame_errors  = hwstat->rx_align_errs;
1496         nstat->rx_crc_errors    = hwstat->rx_crc_errs;
1497         nstat->rx_errors        = (hwstat->rx_jabber_pkts +
1498                                    hwstat->rx_oversize_pkts +
1499                                    hwstat->rx_missed_pkts +
1500                                    hwstat->rx_crc_align_errs +
1501                                    hwstat->rx_undersize +
1502                                    hwstat->rx_crc_errs +
1503                                    hwstat->rx_align_errs +
1504                                    hwstat->rx_symbol_errs);
1505
1506         nstat->tx_aborted_errors = hwstat->tx_underruns;
1507 #if 0
1508         /* Carrier lost counter seems to be broken for some devices */
1509         nstat->tx_carrier_errors = hwstat->tx_carrier_lost;
1510 #endif
1511
1512         return nstat;
1513 }
1514
1515 static int __b44_load_mcast(struct b44 *bp, struct net_device *dev)
1516 {
1517         struct dev_mc_list *mclist;
1518         int i, num_ents;
1519
1520         num_ents = min_t(int, dev->mc_count, B44_MCAST_TABLE_SIZE);
1521         mclist = dev->mc_list;
1522         for (i = 0; mclist && i < num_ents; i++, mclist = mclist->next) {
1523                 __b44_cam_write(bp, mclist->dmi_addr, i + 1);
1524         }
1525         return i+1;
1526 }
1527
1528 static void __b44_set_rx_mode(struct net_device *dev)
1529 {
1530         struct b44 *bp = netdev_priv(dev);
1531         u32 val;
1532         int i=0;
1533         unsigned char zero[6] = {0,0,0,0,0,0};
1534
1535         val = br32(bp, B44_RXCONFIG);
1536         val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
1537         if (dev->flags & IFF_PROMISC) {
1538                 val |= RXCONFIG_PROMISC;
1539                 bw32(bp, B44_RXCONFIG, val);
1540         } else {
1541                 __b44_set_mac_addr(bp);
1542
1543                 if (dev->flags & IFF_ALLMULTI)
1544                         val |= RXCONFIG_ALLMULTI;
1545                 else
1546                         i=__b44_load_mcast(bp, dev);
1547
1548                 for(;i<64;i++) {
1549                         __b44_cam_write(bp, zero, i);
1550                 }
1551                 bw32(bp, B44_RXCONFIG, val);
1552                 val = br32(bp, B44_CAM_CTRL);
1553                 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1554         }
1555 }
1556
1557 static void b44_set_rx_mode(struct net_device *dev)
1558 {
1559         struct b44 *bp = netdev_priv(dev);
1560
1561         spin_lock_irq(&bp->lock);
1562         __b44_set_rx_mode(dev);
1563         spin_unlock_irq(&bp->lock);
1564 }
1565
1566 static u32 b44_get_msglevel(struct net_device *dev)
1567 {
1568         struct b44 *bp = netdev_priv(dev);
1569         return bp->msg_enable;
1570 }
1571
1572 static void b44_set_msglevel(struct net_device *dev, u32 value)
1573 {
1574         struct b44 *bp = netdev_priv(dev);
1575         bp->msg_enable = value;
1576 }
1577
1578 static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1579 {
1580         struct b44 *bp = netdev_priv(dev);
1581         struct pci_dev *pci_dev = bp->pdev;
1582
1583         strcpy (info->driver, DRV_MODULE_NAME);
1584         strcpy (info->version, DRV_MODULE_VERSION);
1585         strcpy (info->bus_info, pci_name(pci_dev));
1586 }
1587
1588 static int b44_nway_reset(struct net_device *dev)
1589 {
1590         struct b44 *bp = netdev_priv(dev);
1591         u32 bmcr;
1592         int r;
1593
1594         spin_lock_irq(&bp->lock);
1595         b44_readphy(bp, MII_BMCR, &bmcr);
1596         b44_readphy(bp, MII_BMCR, &bmcr);
1597         r = -EINVAL;
1598         if (bmcr & BMCR_ANENABLE) {
1599                 b44_writephy(bp, MII_BMCR,
1600                              bmcr | BMCR_ANRESTART);
1601                 r = 0;
1602         }
1603         spin_unlock_irq(&bp->lock);
1604
1605         return r;
1606 }
1607
1608 static int b44_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1609 {
1610         struct b44 *bp = netdev_priv(dev);
1611
1612         if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
1613                 return -EAGAIN;
1614         cmd->supported = (SUPPORTED_Autoneg);
1615         cmd->supported |= (SUPPORTED_100baseT_Half |
1616                           SUPPORTED_100baseT_Full |
1617                           SUPPORTED_10baseT_Half |
1618                           SUPPORTED_10baseT_Full |
1619                           SUPPORTED_MII);
1620
1621         cmd->advertising = 0;
1622         if (bp->flags & B44_FLAG_ADV_10HALF)
1623                 cmd->advertising |= ADVERTISED_10baseT_Half;
1624         if (bp->flags & B44_FLAG_ADV_10FULL)
1625                 cmd->advertising |= ADVERTISED_10baseT_Full;
1626         if (bp->flags & B44_FLAG_ADV_100HALF)
1627                 cmd->advertising |= ADVERTISED_100baseT_Half;
1628         if (bp->flags & B44_FLAG_ADV_100FULL)
1629                 cmd->advertising |= ADVERTISED_100baseT_Full;
1630         cmd->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
1631         cmd->speed = (bp->flags & B44_FLAG_100_BASE_T) ?
1632                 SPEED_100 : SPEED_10;
1633         cmd->duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
1634                 DUPLEX_FULL : DUPLEX_HALF;
1635         cmd->port = 0;
1636         cmd->phy_address = bp->phy_addr;
1637         cmd->transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
1638                 XCVR_INTERNAL : XCVR_EXTERNAL;
1639         cmd->autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
1640                 AUTONEG_DISABLE : AUTONEG_ENABLE;
1641         cmd->maxtxpkt = 0;
1642         cmd->maxrxpkt = 0;
1643         return 0;
1644 }
1645
1646 static int b44_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1647 {
1648         struct b44 *bp = netdev_priv(dev);
1649
1650         if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
1651                 return -EAGAIN;
1652
1653         /* We do not support gigabit. */
1654         if (cmd->autoneg == AUTONEG_ENABLE) {
1655                 if (cmd->advertising &
1656                     (ADVERTISED_1000baseT_Half |
1657                      ADVERTISED_1000baseT_Full))
1658                         return -EINVAL;
1659         } else if ((cmd->speed != SPEED_100 &&
1660                     cmd->speed != SPEED_10) ||
1661                    (cmd->duplex != DUPLEX_HALF &&
1662                     cmd->duplex != DUPLEX_FULL)) {
1663                         return -EINVAL;
1664         }
1665
1666         spin_lock_irq(&bp->lock);
1667
1668         if (cmd->autoneg == AUTONEG_ENABLE) {
1669                 bp->flags &= ~B44_FLAG_FORCE_LINK;
1670                 bp->flags &= ~(B44_FLAG_ADV_10HALF |
1671                                B44_FLAG_ADV_10FULL |
1672                                B44_FLAG_ADV_100HALF |
1673                                B44_FLAG_ADV_100FULL);
1674                 if (cmd->advertising & ADVERTISE_10HALF)
1675                         bp->flags |= B44_FLAG_ADV_10HALF;
1676                 if (cmd->advertising & ADVERTISE_10FULL)
1677                         bp->flags |= B44_FLAG_ADV_10FULL;
1678                 if (cmd->advertising & ADVERTISE_100HALF)
1679                         bp->flags |= B44_FLAG_ADV_100HALF;
1680                 if (cmd->advertising & ADVERTISE_100FULL)
1681                         bp->flags |= B44_FLAG_ADV_100FULL;
1682         } else {
1683                 bp->flags |= B44_FLAG_FORCE_LINK;
1684                 if (cmd->speed == SPEED_100)
1685                         bp->flags |= B44_FLAG_100_BASE_T;
1686                 if (cmd->duplex == DUPLEX_FULL)
1687                         bp->flags |= B44_FLAG_FULL_DUPLEX;
1688         }
1689
1690         b44_setup_phy(bp);
1691
1692         spin_unlock_irq(&bp->lock);
1693
1694         return 0;
1695 }
1696
1697 static void b44_get_ringparam(struct net_device *dev,
1698                               struct ethtool_ringparam *ering)
1699 {
1700         struct b44 *bp = netdev_priv(dev);
1701
1702         ering->rx_max_pending = B44_RX_RING_SIZE - 1;
1703         ering->rx_pending = bp->rx_pending;
1704
1705         /* XXX ethtool lacks a tx_max_pending, oops... */
1706 }
1707
1708 static int b44_set_ringparam(struct net_device *dev,
1709                              struct ethtool_ringparam *ering)
1710 {
1711         struct b44 *bp = netdev_priv(dev);
1712
1713         if ((ering->rx_pending > B44_RX_RING_SIZE - 1) ||
1714             (ering->rx_mini_pending != 0) ||
1715             (ering->rx_jumbo_pending != 0) ||
1716             (ering->tx_pending > B44_TX_RING_SIZE - 1))
1717                 return -EINVAL;
1718
1719         spin_lock_irq(&bp->lock);
1720
1721         bp->rx_pending = ering->rx_pending;
1722         bp->tx_pending = ering->tx_pending;
1723
1724         b44_halt(bp);
1725         b44_init_rings(bp);
1726         b44_init_hw(bp);
1727         netif_wake_queue(bp->dev);
1728         spin_unlock_irq(&bp->lock);
1729
1730         b44_enable_ints(bp);
1731
1732         return 0;
1733 }
1734
1735 static void b44_get_pauseparam(struct net_device *dev,
1736                                 struct ethtool_pauseparam *epause)
1737 {
1738         struct b44 *bp = netdev_priv(dev);
1739
1740         epause->autoneg =
1741                 (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
1742         epause->rx_pause =
1743                 (bp->flags & B44_FLAG_RX_PAUSE) != 0;
1744         epause->tx_pause =
1745                 (bp->flags & B44_FLAG_TX_PAUSE) != 0;
1746 }
1747
1748 static int b44_set_pauseparam(struct net_device *dev,
1749                                 struct ethtool_pauseparam *epause)
1750 {
1751         struct b44 *bp = netdev_priv(dev);
1752
1753         spin_lock_irq(&bp->lock);
1754         if (epause->autoneg)
1755                 bp->flags |= B44_FLAG_PAUSE_AUTO;
1756         else
1757                 bp->flags &= ~B44_FLAG_PAUSE_AUTO;
1758         if (epause->rx_pause)
1759                 bp->flags |= B44_FLAG_RX_PAUSE;
1760         else
1761                 bp->flags &= ~B44_FLAG_RX_PAUSE;
1762         if (epause->tx_pause)
1763                 bp->flags |= B44_FLAG_TX_PAUSE;
1764         else
1765                 bp->flags &= ~B44_FLAG_TX_PAUSE;
1766         if (bp->flags & B44_FLAG_PAUSE_AUTO) {
1767                 b44_halt(bp);
1768                 b44_init_rings(bp);
1769                 b44_init_hw(bp);
1770         } else {
1771                 __b44_set_flow_ctrl(bp, bp->flags);
1772         }
1773         spin_unlock_irq(&bp->lock);
1774
1775         b44_enable_ints(bp);
1776
1777         return 0;
1778 }
1779
1780 static struct ethtool_ops b44_ethtool_ops = {
1781         .get_drvinfo            = b44_get_drvinfo,
1782         .get_settings           = b44_get_settings,
1783         .set_settings           = b44_set_settings,
1784         .nway_reset             = b44_nway_reset,
1785         .get_link               = ethtool_op_get_link,
1786         .get_ringparam          = b44_get_ringparam,
1787         .set_ringparam          = b44_set_ringparam,
1788         .get_pauseparam         = b44_get_pauseparam,
1789         .set_pauseparam         = b44_set_pauseparam,
1790         .get_msglevel           = b44_get_msglevel,
1791         .set_msglevel           = b44_set_msglevel,
1792         .get_perm_addr          = ethtool_op_get_perm_addr,
1793 };
1794
1795 static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1796 {
1797         struct mii_ioctl_data *data = if_mii(ifr);
1798         struct b44 *bp = netdev_priv(dev);
1799         int err;
1800
1801         spin_lock_irq(&bp->lock);
1802         err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
1803         spin_unlock_irq(&bp->lock);
1804
1805         return err;
1806 }
1807
1808 /* Read 128-bytes of EEPROM. */
1809 static int b44_read_eeprom(struct b44 *bp, u8 *data)
1810 {
1811         long i;
1812         u16 *ptr = (u16 *) data;
1813
1814         for (i = 0; i < 128; i += 2)
1815                 ptr[i / 2] = readw(bp->regs + 4096 + i);
1816
1817         return 0;
1818 }
1819
1820 static int __devinit b44_get_invariants(struct b44 *bp)
1821 {
1822         u8 eeprom[128];
1823         int err;
1824
1825         err = b44_read_eeprom(bp, &eeprom[0]);
1826         if (err)
1827                 goto out;
1828
1829         bp->dev->dev_addr[0] = eeprom[79];
1830         bp->dev->dev_addr[1] = eeprom[78];
1831         bp->dev->dev_addr[2] = eeprom[81];
1832         bp->dev->dev_addr[3] = eeprom[80];
1833         bp->dev->dev_addr[4] = eeprom[83];
1834         bp->dev->dev_addr[5] = eeprom[82];
1835         memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
1836
1837         bp->phy_addr = eeprom[90] & 0x1f;
1838
1839         /* With this, plus the rx_header prepended to the data by the
1840          * hardware, we'll land the ethernet header on a 2-byte boundary.
1841          */
1842         bp->rx_offset = 30;
1843
1844         bp->imask = IMASK_DEF;
1845
1846         bp->core_unit = ssb_core_unit(bp);
1847         bp->dma_offset = SB_PCI_DMA;
1848
1849         /* XXX - really required?
1850            bp->flags |= B44_FLAG_BUGGY_TXPTR;
1851          */
1852 out:
1853         return err;
1854 }
1855
1856 static int __devinit b44_init_one(struct pci_dev *pdev,
1857                                   const struct pci_device_id *ent)
1858 {
1859         static int b44_version_printed = 0;
1860         unsigned long b44reg_base, b44reg_len;
1861         struct net_device *dev;
1862         struct b44 *bp;
1863         int err, i;
1864
1865         if (b44_version_printed++ == 0)
1866                 printk(KERN_INFO "%s", version);
1867
1868         err = pci_enable_device(pdev);
1869         if (err) {
1870                 printk(KERN_ERR PFX "Cannot enable PCI device, "
1871                        "aborting.\n");
1872                 return err;
1873         }
1874
1875         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1876                 printk(KERN_ERR PFX "Cannot find proper PCI device "
1877                        "base address, aborting.\n");
1878                 err = -ENODEV;
1879                 goto err_out_disable_pdev;
1880         }
1881
1882         err = pci_request_regions(pdev, DRV_MODULE_NAME);
1883         if (err) {
1884                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
1885                        "aborting.\n");
1886                 goto err_out_disable_pdev;
1887         }
1888
1889         pci_set_master(pdev);
1890
1891         err = pci_set_dma_mask(pdev, (u64) B44_DMA_MASK);
1892         if (err) {
1893                 printk(KERN_ERR PFX "No usable DMA configuration, "
1894                        "aborting.\n");
1895                 goto err_out_free_res;
1896         }
1897
1898         err = pci_set_consistent_dma_mask(pdev, (u64) B44_DMA_MASK);
1899         if (err) {
1900           printk(KERN_ERR PFX "No usable DMA configuration, "
1901                  "aborting.\n");
1902           goto err_out_free_res;
1903         }
1904
1905         b44reg_base = pci_resource_start(pdev, 0);
1906         b44reg_len = pci_resource_len(pdev, 0);
1907
1908         dev = alloc_etherdev(sizeof(*bp));
1909         if (!dev) {
1910                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
1911                 err = -ENOMEM;
1912                 goto err_out_free_res;
1913         }
1914
1915         SET_MODULE_OWNER(dev);
1916         SET_NETDEV_DEV(dev,&pdev->dev);
1917
1918         /* No interesting netdevice features in this card... */
1919         dev->features |= 0;
1920
1921         bp = netdev_priv(dev);
1922         bp->pdev = pdev;
1923         bp->dev = dev;
1924         if (b44_debug >= 0)
1925                 bp->msg_enable = (1 << b44_debug) - 1;
1926         else
1927                 bp->msg_enable = B44_DEF_MSG_ENABLE;
1928
1929         spin_lock_init(&bp->lock);
1930
1931         bp->regs = ioremap(b44reg_base, b44reg_len);
1932         if (bp->regs == 0UL) {
1933                 printk(KERN_ERR PFX "Cannot map device registers, "
1934                        "aborting.\n");
1935                 err = -ENOMEM;
1936                 goto err_out_free_dev;
1937         }
1938
1939         bp->rx_pending = B44_DEF_RX_RING_PENDING;
1940         bp->tx_pending = B44_DEF_TX_RING_PENDING;
1941
1942         dev->open = b44_open;
1943         dev->stop = b44_close;
1944         dev->hard_start_xmit = b44_start_xmit;
1945         dev->get_stats = b44_get_stats;
1946         dev->set_multicast_list = b44_set_rx_mode;
1947         dev->set_mac_address = b44_set_mac_addr;
1948         dev->do_ioctl = b44_ioctl;
1949         dev->tx_timeout = b44_tx_timeout;
1950         dev->poll = b44_poll;
1951         dev->weight = 64;
1952         dev->watchdog_timeo = B44_TX_TIMEOUT;
1953 #ifdef CONFIG_NET_POLL_CONTROLLER
1954         dev->poll_controller = b44_poll_controller;
1955 #endif
1956         dev->change_mtu = b44_change_mtu;
1957         dev->irq = pdev->irq;
1958         SET_ETHTOOL_OPS(dev, &b44_ethtool_ops);
1959
1960         err = b44_get_invariants(bp);
1961         if (err) {
1962                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
1963                        "aborting.\n");
1964                 goto err_out_iounmap;
1965         }
1966
1967         bp->mii_if.dev = dev;
1968         bp->mii_if.mdio_read = b44_mii_read;
1969         bp->mii_if.mdio_write = b44_mii_write;
1970         bp->mii_if.phy_id = bp->phy_addr;
1971         bp->mii_if.phy_id_mask = 0x1f;
1972         bp->mii_if.reg_num_mask = 0x1f;
1973
1974         /* By default, advertise all speed/duplex settings. */
1975         bp->flags |= (B44_FLAG_ADV_10HALF | B44_FLAG_ADV_10FULL |
1976                       B44_FLAG_ADV_100HALF | B44_FLAG_ADV_100FULL);
1977
1978         /* By default, auto-negotiate PAUSE. */
1979         bp->flags |= B44_FLAG_PAUSE_AUTO;
1980
1981         err = register_netdev(dev);
1982         if (err) {
1983                 printk(KERN_ERR PFX "Cannot register net device, "
1984                        "aborting.\n");
1985                 goto err_out_iounmap;
1986         }
1987
1988         pci_set_drvdata(pdev, dev);
1989
1990         pci_save_state(bp->pdev);
1991
1992         printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
1993         for (i = 0; i < 6; i++)
1994                 printk("%2.2x%c", dev->dev_addr[i],
1995                        i == 5 ? '\n' : ':');
1996
1997         return 0;
1998
1999 err_out_iounmap:
2000         iounmap(bp->regs);
2001
2002 err_out_free_dev:
2003         free_netdev(dev);
2004
2005 err_out_free_res:
2006         pci_release_regions(pdev);
2007
2008 err_out_disable_pdev:
2009         pci_disable_device(pdev);
2010         pci_set_drvdata(pdev, NULL);
2011         return err;
2012 }
2013
2014 static void __devexit b44_remove_one(struct pci_dev *pdev)
2015 {
2016         struct net_device *dev = pci_get_drvdata(pdev);
2017
2018         if (dev) {
2019                 struct b44 *bp = netdev_priv(dev);
2020
2021                 unregister_netdev(dev);
2022                 iounmap(bp->regs);
2023                 free_netdev(dev);
2024                 pci_release_regions(pdev);
2025                 pci_disable_device(pdev);
2026                 pci_set_drvdata(pdev, NULL);
2027         }
2028 }
2029
2030 static int b44_suspend(struct pci_dev *pdev, pm_message_t state)
2031 {
2032         struct net_device *dev = pci_get_drvdata(pdev);
2033         struct b44 *bp = netdev_priv(dev);
2034
2035         if (!netif_running(dev))
2036                  return 0;
2037
2038         del_timer_sync(&bp->timer);
2039
2040         spin_lock_irq(&bp->lock);
2041
2042         b44_halt(bp);
2043         netif_carrier_off(bp->dev);
2044         netif_device_detach(bp->dev);
2045         b44_free_rings(bp);
2046
2047         spin_unlock_irq(&bp->lock);
2048         pci_disable_device(pdev);
2049         return 0;
2050 }
2051
2052 static int b44_resume(struct pci_dev *pdev)
2053 {
2054         struct net_device *dev = pci_get_drvdata(pdev);
2055         struct b44 *bp = netdev_priv(dev);
2056
2057         pci_restore_state(pdev);
2058         pci_enable_device(pdev);
2059         pci_set_master(pdev);
2060
2061         if (!netif_running(dev))
2062                 return 0;
2063
2064         spin_lock_irq(&bp->lock);
2065
2066         b44_init_rings(bp);
2067         b44_init_hw(bp);
2068         netif_device_attach(bp->dev);
2069         spin_unlock_irq(&bp->lock);
2070
2071         bp->timer.expires = jiffies + HZ;
2072         add_timer(&bp->timer);
2073
2074         b44_enable_ints(bp);
2075         return 0;
2076 }
2077
2078 static struct pci_driver b44_driver = {
2079         .name           = DRV_MODULE_NAME,
2080         .id_table       = b44_pci_tbl,
2081         .probe          = b44_init_one,
2082         .remove         = __devexit_p(b44_remove_one),
2083         .suspend        = b44_suspend,
2084         .resume         = b44_resume,
2085 };
2086
2087 static int __init b44_init(void)
2088 {
2089         unsigned int dma_desc_align_size = dma_get_cache_alignment();
2090
2091         /* Setup paramaters for syncing RX/TX DMA descriptors */
2092         dma_desc_align_mask = ~(dma_desc_align_size - 1);
2093         dma_desc_sync_size = max(dma_desc_align_size, sizeof(struct dma_desc));
2094
2095         return pci_module_init(&b44_driver);
2096 }
2097
2098 static void __exit b44_cleanup(void)
2099 {
2100         pci_unregister_driver(&b44_driver);
2101 }
2102
2103 module_init(b44_init);
2104 module_exit(b44_cleanup);
2105