1 #include <asm-generic/pgtable-nopud.h>
4 #define PTE_INDEX_SIZE 12
5 #define PMD_INDEX_SIZE 12
6 #define PUD_INDEX_SIZE 0
7 #define PGD_INDEX_SIZE 4
9 #define PTE_TABLE_SIZE (sizeof(real_pte_t) << PTE_INDEX_SIZE)
10 #define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE)
11 #define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
13 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
14 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
15 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
17 /* PMD_SHIFT determines what a second-level page table entry can map */
18 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
19 #define PMD_SIZE (1UL << PMD_SHIFT)
20 #define PMD_MASK (~(PMD_SIZE-1))
22 /* PGDIR_SHIFT determines what a third-level page table entry can map */
23 #define PGDIR_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
24 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
25 #define PGDIR_MASK (~(PGDIR_SIZE-1))
27 /* Additional PTE bits (don't change without checking asm in hash_low.S) */
28 #define _PAGE_HPTE_SUB 0x0ffff000 /* combo only: sub pages HPTE bits */
29 #define _PAGE_HPTE_SUB0 0x08000000 /* combo only: first sub page */
30 #define _PAGE_COMBO 0x10000000 /* this is a combo 4k page */
31 #define _PAGE_F_SECOND 0x00008000 /* full page: hidx bits */
32 #define _PAGE_F_GIX 0x00007000 /* full page: hidx bits */
34 /* PTE flags to conserve for HPTE identification */
35 #define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | _PAGE_HPTE_SUB |\
38 /* Shift to put page number into pte.
40 * That gives us a max RPN of 32 bits, which means a max of 48 bits
41 * of addressable physical space.
42 * We could get 3 more bits here by setting PTE_RPN_SHIFT to 29 but
43 * 32 makes PTEs more readable for debugging for now :)
45 #define PTE_RPN_SHIFT (32)
46 #define PTE_RPN_MAX (1UL << (64 - PTE_RPN_SHIFT))
47 #define PTE_RPN_MASK (~((1UL<<PTE_RPN_SHIFT)-1))
49 /* _PAGE_CHG_MASK masks of bits that are to be preserved accross
52 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
55 /* Bits to mask out from a PMD to get to the PTE page */
56 #define PMD_MASKED_BITS 0x1ff
57 /* Bits to mask out from a PGD/PUD to get to the PMD page */
58 #define PUD_MASKED_BITS 0x1ff
62 /* Manipulate "rpte" values */
63 #define __real_pte(e,p) ((real_pte_t) { \
64 (e), pte_val(*((p) + PTRS_PER_PTE)) })
65 #define __rpte_to_hidx(r,index) ((pte_val((r).pte) & _PAGE_COMBO) ? \
66 (((r).hidx >> ((index)<<2)) & 0xf) : ((pte_val((r).pte) >> 12) & 0xf))
67 #define __rpte_to_pte(r) ((r).pte)
68 #define __rpte_sub_valid(rpte, index) \
69 (pte_val(rpte.pte) & (_PAGE_HPTE_SUB0 >> (index)))
72 /* Trick: we set __end to va + 64k, which happens works for
73 * a 16M page as well as we want only one iteration
75 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
77 unsigned long __end = va + PAGE_SIZE; \
78 unsigned __split = (psize == MMU_PAGE_4K || \
79 psize == MMU_PAGE_64K_AP); \
80 shift = mmu_psize_defs[psize].shift; \
81 for (index = 0; va < __end; index++, va += (1 << shift)) { \
82 if (!__split || __rpte_sub_valid(rpte, index)) do { \
84 #define pte_iterate_hashed_end() } while(0); } } while(0)
87 #endif /* __ASSEMBLY__ */