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   1 /*
   2  * SH7723 Setup
   3  *
   4  *  Copyright (C) 2008  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 #include <linux/mm.h>
  14 #include <linux/serial_sci.h>
  15 #include <linux/uio_driver.h>
  16 #include <linux/sh_timer.h>
  17 #include <linux/io.h>
  18 #include <asm/clock.h>
  19 #include <asm/mmzone.h>
  20
  21 static struct uio_info vpu_platform_data = {
  22         .name = "VPU5",
  23         .version = "0",
  24         .irq = 60,
  25 };
  26
  27 static struct resource vpu_resources[] = {
  28         [0] = {
  29                 .name   = "VPU",
  30                 .start  = 0xfe900000,
  31                 .end    = 0xfe902807,
  32                 .flags  = IORESOURCE_MEM,
  33         },
  34         [1] = {
  35                 /* place holder for contiguous memory */
  36         },
  37 };
  38
  39 static struct platform_device vpu_device = {
  40         .name           = "uio_pdrv_genirq",
  41         .id             = 0,
  42         .dev = {
  43                 .platform_data  = &vpu_platform_data,
  44         },
  45         .resource       = vpu_resources,
  46         .num_resources  = ARRAY_SIZE(vpu_resources),
  47 };
  48
  49 static struct uio_info veu0_platform_data = {
  50         .name = "VEU2H",
  51         .version = "0",
  52         .irq = 54,
  53 };
  54
  55 static struct resource veu0_resources[] = {
  56         [0] = {
  57                 .name   = "VEU2H0",
  58                 .start  = 0xfe920000,
  59                 .end    = 0xfe92027b,
  60                 .flags  = IORESOURCE_MEM,
  61         },
  62         [1] = {
  63                 /* place holder for contiguous memory */
  64         },
  65 };
  66
  67 static struct platform_device veu0_device = {
  68         .name           = "uio_pdrv_genirq",
  69         .id             = 1,
  70         .dev = {
  71                 .platform_data  = &veu0_platform_data,
  72         },
  73         .resource       = veu0_resources,
  74         .num_resources  = ARRAY_SIZE(veu0_resources),
  75 };
  76
  77 static struct uio_info veu1_platform_data = {
  78         .name = "VEU2H",
  79         .version = "0",
  80         .irq = 27,
  81 };
  82
  83 static struct resource veu1_resources[] = {
  84         [0] = {
  85                 .name   = "VEU2H1",
  86                 .start  = 0xfe924000,
  87                 .end    = 0xfe92427b,
  88                 .flags  = IORESOURCE_MEM,
  89         },
  90         [1] = {
  91                 /* place holder for contiguous memory */
  92         },
  93 };
  94
  95 static struct platform_device veu1_device = {
  96         .name           = "uio_pdrv_genirq",
  97         .id             = 2,
  98         .dev = {
  99                 .platform_data  = &veu1_platform_data,
 100         },
 101         .resource       = veu1_resources,
 102         .num_resources  = ARRAY_SIZE(veu1_resources),
 103 };
 104
 105 static struct sh_timer_config cmt_platform_data = {
 106         .name = "CMT",
 107         .channel_offset = 0x60,
 108         .timer_bit = 5,
 109         .clk = "cmt0",
 110         .clockevent_rating = 125,
 111         .clocksource_rating = 125,
 112 };
 113
 114 static struct resource cmt_resources[] = {
 115         [0] = {
 116                 .name   = "CMT",
 117                 .start  = 0x044a0060,
 118                 .end    = 0x044a006b,
 119                 .flags  = IORESOURCE_MEM,
 120         },
 121         [1] = {
 122                 .start  = 104,
 123                 .flags  = IORESOURCE_IRQ,
 124         },
 125 };
 126
 127 static struct platform_device cmt_device = {
 128         .name           = "sh_cmt",
 129         .id             = 0,
 130         .dev = {
 131                 .platform_data  = &cmt_platform_data,
 132         },
 133         .resource       = cmt_resources,
 134         .num_resources  = ARRAY_SIZE(cmt_resources),
 135 };
 136
 137 static struct sh_timer_config tmu0_platform_data = {
 138         .name = "TMU0",
 139         .channel_offset = 0x04,
 140         .timer_bit = 0,
 141         .clk = "tmu0",
 142         .clockevent_rating = 200,
 143 };
 144
 145 static struct resource tmu0_resources[] = {
 146         [0] = {
 147                 .name   = "TMU0",
 148                 .start  = 0xffd80008,
 149                 .end    = 0xffd80013,
 150                 .flags  = IORESOURCE_MEM,
 151         },
 152         [1] = {
 153                 .start  = 16,
 154                 .flags  = IORESOURCE_IRQ,
 155         },
 156 };
 157
 158 static struct platform_device tmu0_device = {
 159         .name           = "sh_tmu",
 160         .id             = 0,
 161         .dev = {
 162                 .platform_data  = &tmu0_platform_data,
 163         },
 164         .resource       = tmu0_resources,
 165         .num_resources  = ARRAY_SIZE(tmu0_resources),
 166 };
 167
 168 static struct sh_timer_config tmu1_platform_data = {
 169         .name = "TMU1",
 170         .channel_offset = 0x10,
 171         .timer_bit = 1,
 172         .clk = "tmu0",
 173         .clocksource_rating = 200,
 174 };
 175
 176 static struct resource tmu1_resources[] = {
 177         [0] = {
 178                 .name   = "TMU1",
 179                 .start  = 0xffd80014,
 180                 .end    = 0xffd8001f,
 181                 .flags  = IORESOURCE_MEM,
 182         },
 183         [1] = {
 184                 .start  = 17,
 185                 .flags  = IORESOURCE_IRQ,
 186         },
 187 };
 188
 189 static struct platform_device tmu1_device = {
 190         .name           = "sh_tmu",
 191         .id             = 1,
 192         .dev = {
 193                 .platform_data  = &tmu1_platform_data,
 194         },
 195         .resource       = tmu1_resources,
 196         .num_resources  = ARRAY_SIZE(tmu1_resources),
 197 };
 198
 199 static struct sh_timer_config tmu2_platform_data = {
 200         .name = "TMU2",
 201         .channel_offset = 0x1c,
 202         .timer_bit = 2,
 203         .clk = "tmu0",
 204 };
 205
 206 static struct resource tmu2_resources[] = {
 207         [0] = {
 208                 .name   = "TMU2",
 209                 .start  = 0xffd80020,
 210                 .end    = 0xffd8002b,
 211                 .flags  = IORESOURCE_MEM,
 212         },
 213         [1] = {
 214                 .start  = 18,
 215                 .flags  = IORESOURCE_IRQ,
 216         },
 217 };
 218
 219 static struct platform_device tmu2_device = {
 220         .name           = "sh_tmu",
 221         .id             = 2,
 222         .dev = {
 223                 .platform_data  = &tmu2_platform_data,
 224         },
 225         .resource       = tmu2_resources,
 226         .num_resources  = ARRAY_SIZE(tmu2_resources),
 227 };
 228
 229 static struct sh_timer_config tmu3_platform_data = {
 230         .name = "TMU3",
 231         .channel_offset = 0x04,
 232         .timer_bit = 0,
 233         .clk = "tmu1",
 234 };
 235
 236 static struct resource tmu3_resources[] = {
 237         [0] = {
 238                 .name   = "TMU3",
 239                 .start  = 0xffd90008,
 240                 .end    = 0xffd90013,
 241                 .flags  = IORESOURCE_MEM,
 242         },
 243         [1] = {
 244                 .start  = 57,
 245                 .flags  = IORESOURCE_IRQ,
 246         },
 247 };
 248
 249 static struct platform_device tmu3_device = {
 250         .name           = "sh_tmu",
 251         .id             = 3,
 252         .dev = {
 253                 .platform_data  = &tmu3_platform_data,
 254         },
 255         .resource       = tmu3_resources,
 256         .num_resources  = ARRAY_SIZE(tmu3_resources),
 257 };
 258
 259 static struct sh_timer_config tmu4_platform_data = {
 260         .name = "TMU4",
 261         .channel_offset = 0x10,
 262         .timer_bit = 1,
 263         .clk = "tmu1",
 264 };
 265
 266 static struct resource tmu4_resources[] = {
 267         [0] = {
 268                 .name   = "TMU4",
 269                 .start  = 0xffd90014,
 270                 .end    = 0xffd9001f,
 271                 .flags  = IORESOURCE_MEM,
 272         },
 273         [1] = {
 274                 .start  = 58,
 275                 .flags  = IORESOURCE_IRQ,
 276         },
 277 };
 278
 279 static struct platform_device tmu4_device = {
 280         .name           = "sh_tmu",
 281         .id             = 4,
 282         .dev = {
 283                 .platform_data  = &tmu4_platform_data,
 284         },
 285         .resource       = tmu4_resources,
 286         .num_resources  = ARRAY_SIZE(tmu4_resources),
 287 };
 288
 289 static struct sh_timer_config tmu5_platform_data = {
 290         .name = "TMU5",
 291         .channel_offset = 0x1c,
 292         .timer_bit = 2,
 293         .clk = "tmu1",
 294 };
 295
 296 static struct resource tmu5_resources[] = {
 297         [0] = {
 298                 .name   = "TMU5",
 299                 .start  = 0xffd90020,
 300                 .end    = 0xffd9002b,
 301                 .flags  = IORESOURCE_MEM,
 302         },
 303         [1] = {
 304                 .start  = 57,
 305                 .flags  = IORESOURCE_IRQ,
 306         },
 307 };
 308
 309 static struct platform_device tmu5_device = {
 310         .name           = "sh_tmu",
 311         .id             = 5,
 312         .dev = {
 313                 .platform_data  = &tmu5_platform_data,
 314         },
 315         .resource       = tmu5_resources,
 316         .num_resources  = ARRAY_SIZE(tmu5_resources),
 317 };
 318
 319 static struct plat_sci_port sci_platform_data[] = {
 320         {
 321                 .mapbase        = 0xffe00000,
 322                 .flags          = UPF_BOOT_AUTOCONF,
 323                 .type           = PORT_SCIF,
 324                 .irqs           = { 80, 80, 80, 80 },
 325                 .clk            = "scif0",
 326         },{
 327                 .mapbase        = 0xffe10000,
 328                 .flags          = UPF_BOOT_AUTOCONF,
 329                 .type           = PORT_SCIF,
 330                 .irqs           = { 81, 81, 81, 81 },
 331                 .clk            = "scif1",
 332         },{
 333                 .mapbase        = 0xffe20000,
 334                 .flags          = UPF_BOOT_AUTOCONF,
 335                 .type           = PORT_SCIF,
 336                 .irqs           = { 82, 82, 82, 82 },
 337                 .clk            = "scif2",
 338         },{
 339                 .mapbase        = 0xa4e30000,
 340                 .flags          = UPF_BOOT_AUTOCONF,
 341                 .type           = PORT_SCIFA,
 342                 .irqs           = { 56, 56, 56, 56 },
 343                 .clk            = "scif3",
 344         },{
 345                 .mapbase        = 0xa4e40000,
 346                 .flags          = UPF_BOOT_AUTOCONF,
 347                 .type           = PORT_SCIFA,
 348                 .irqs           = { 88, 88, 88, 88 },
 349                 .clk            = "scif4",
 350         },{
 351                 .mapbase        = 0xa4e50000,
 352                 .flags          = UPF_BOOT_AUTOCONF,
 353                 .type           = PORT_SCIFA,
 354                 .irqs           = { 109, 109, 109, 109 },
 355                 .clk            = "scif5",
 356         }, {
 357                 .flags = 0,
 358         }
 359 };
 360
 361 static struct platform_device sci_device = {
 362         .name           = "sh-sci",
 363         .id             = -1,
 364         .dev            = {
 365                 .platform_data  = sci_platform_data,
 366         },
 367 };
 368
 369 static struct resource rtc_resources[] = {
 370         [0] = {
 371                 .start  = 0xa465fec0,
 372                 .end    = 0xa465fec0 + 0x58 - 1,
 373                 .flags  = IORESOURCE_IO,
 374         },
 375         [1] = {
 376                 /* Period IRQ */
 377                 .start  = 69,
 378                 .flags  = IORESOURCE_IRQ,
 379         },
 380         [2] = {
 381                 /* Carry IRQ */
 382                 .start  = 70,
 383                 .flags  = IORESOURCE_IRQ,
 384         },
 385         [3] = {
 386                 /* Alarm IRQ */
 387                 .start  = 68,
 388                 .flags  = IORESOURCE_IRQ,
 389         },
 390 };
 391
 392 static struct platform_device rtc_device = {
 393         .name           = "sh-rtc",
 394         .id             = -1,
 395         .num_resources  = ARRAY_SIZE(rtc_resources),
 396         .resource       = rtc_resources,
 397 };
 398
 399 static struct resource sh7723_usb_host_resources[] = {
 400         [0] = {
 401                 .name   = "r8a66597_hcd",
 402                 .start  = 0xa4d80000,
 403                 .end    = 0xa4d800ff,
 404                 .flags  = IORESOURCE_MEM,
 405         },
 406         [1] = {
 407                 .start  = 65,
 408                 .end    = 65,
 409                 .flags  = IORESOURCE_IRQ,
 410         },
 411 };
 412
 413 static struct platform_device sh7723_usb_host_device = {
 414         .name           = "r8a66597_hcd",
 415         .id             = 0,
 416         .dev = {
 417                 .dma_mask               = NULL,         /*  not use dma */
 418                 .coherent_dma_mask      = 0xffffffff,
 419         },
 420         .num_resources  = ARRAY_SIZE(sh7723_usb_host_resources),
 421         .resource       = sh7723_usb_host_resources,
 422 };
 423
 424 static struct resource iic_resources[] = {
 425         [0] = {
 426                 .name   = "IIC",
 427                 .start  = 0x04470000,
 428                 .end    = 0x04470017,
 429                 .flags  = IORESOURCE_MEM,
 430         },
 431         [1] = {
 432                 .start  = 96,
 433                 .end    = 99,
 434                 .flags  = IORESOURCE_IRQ,
 435        },
 436 };
 437
 438 static struct platform_device iic_device = {
 439         .name           = "i2c-sh_mobile",
 440         .id             = 0, /* "i2c0" clock */
 441         .num_resources  = ARRAY_SIZE(iic_resources),
 442         .resource       = iic_resources,
 443 };
 444
 445 static struct platform_device *sh7723_devices[] __initdata = {
 446         &cmt_device,
 447         &tmu0_device,
 448         &tmu1_device,
 449         &tmu2_device,
 450         &tmu3_device,
 451         &tmu4_device,
 452         &tmu5_device,
 453         &sci_device,
 454         &rtc_device,
 455         &iic_device,
 456         &sh7723_usb_host_device,
 457         &vpu_device,
 458         &veu0_device,
 459         &veu1_device,
 460 };
 461
 462 static int __init sh7723_devices_setup(void)
 463 {
 464         platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
 465         platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
 466         platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
 467
 468         return platform_add_devices(sh7723_devices,
 469                                     ARRAY_SIZE(sh7723_devices));
 470 }
 471 __initcall(sh7723_devices_setup);
 472
 473 static struct platform_device *sh7723_early_devices[] __initdata = {
 474         &cmt_device,
 475         &tmu0_device,
 476         &tmu1_device,
 477         &tmu2_device,
 478         &tmu3_device,
 479         &tmu4_device,
 480         &tmu5_device,
 481 };
 482
 483 void __init plat_early_device_setup(void)
 484 {
 485         early_platform_add_devices(sh7723_early_devices,
 486                                    ARRAY_SIZE(sh7723_early_devices));
 487 }
 488
 489 #define RAMCR_CACHE_L2FC        0x0002
 490 #define RAMCR_CACHE_L2E         0x0001
 491 #define L2_CACHE_ENABLE         (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
 492 void __uses_jump_to_uncached l2_cache_init(void)
 493 {
 494         /* Enable L2 cache */
 495         ctrl_outl(L2_CACHE_ENABLE, RAMCR);
 496 }
 497
 498 enum {
 499         UNUSED=0,
 500
 501         /* interrupt sources */
 502         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 503         HUDI,
 504         DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3,
 505         _2DG_TRI,_2DG_INI,_2DG_CEI,
 506         DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3,
 507         VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI,
 508         SCIFA_SCIFA0,
 509         VPU_VPUI,
 510         TPU_TPUI,
 511         ADC_ADI,
 512         USB_USI0,
 513         RTC_ATI,RTC_PRI,RTC_CUI,
 514         DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR,
 515         DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR,
 516         KEYSC_KEYI,
 517         SCIF_SCIF0,SCIF_SCIF1,SCIF_SCIF2,
 518         MSIOF_MSIOFI0,MSIOF_MSIOFI1,
 519         SCIFA_SCIFA1,
 520         FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I,
 521         I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI,
 522         SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2,
 523         CMT_CMTI,
 524         TSIF_TSIFI,
 525         SIU_SIUI,
 526         SCIFA_SCIFA2,
 527         TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
 528         IRDA_IRDAI,
 529         ATAPI_ATAPII,
 530         SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2,
 531         VEU2H1_VEU2HI,
 532         LCDC_LCDCI,
 533         TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2,
 534
 535         /* interrupt groups */
 536         DMAC1A, DMAC0A, VIO, DMAC0B, FLCTL, I2C, _2DG,
 537         SDHI1, RTC, DMAC1B, SDHI0,
 538 };
 539
 540 static struct intc_vect vectors[] __initdata = {
 541         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
 542         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
 543         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
 544         INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
 545
 546         INTC_VECT(DMAC1A_DEI0,0x700),
 547         INTC_VECT(DMAC1A_DEI1,0x720),
 548         INTC_VECT(DMAC1A_DEI2,0x740),
 549         INTC_VECT(DMAC1A_DEI3,0x760),
 550
 551         INTC_VECT(_2DG_TRI, 0x780),
 552         INTC_VECT(_2DG_INI, 0x7A0),
 553         INTC_VECT(_2DG_CEI, 0x7C0),
 554
 555         INTC_VECT(DMAC0A_DEI0,0x800),
 556         INTC_VECT(DMAC0A_DEI1,0x820),
 557         INTC_VECT(DMAC0A_DEI2,0x840),
 558         INTC_VECT(DMAC0A_DEI3,0x860),
 559
 560         INTC_VECT(VIO_CEUI,0x880),
 561         INTC_VECT(VIO_BEUI,0x8A0),
 562         INTC_VECT(VIO_VEU2HI,0x8C0),
 563         INTC_VECT(VIO_VOUI,0x8E0),
 564
 565         INTC_VECT(SCIFA_SCIFA0,0x900),
 566         INTC_VECT(VPU_VPUI,0x980),
 567         INTC_VECT(TPU_TPUI,0x9A0),
 568         INTC_VECT(ADC_ADI,0x9E0),
 569         INTC_VECT(USB_USI0,0xA20),
 570
 571         INTC_VECT(RTC_ATI,0xA80),
 572         INTC_VECT(RTC_PRI,0xAA0),
 573         INTC_VECT(RTC_CUI,0xAC0),
 574
 575         INTC_VECT(DMAC1B_DEI4,0xB00),
 576         INTC_VECT(DMAC1B_DEI5,0xB20),
 577         INTC_VECT(DMAC1B_DADERR,0xB40),
 578
 579         INTC_VECT(DMAC0B_DEI4,0xB80),
 580         INTC_VECT(DMAC0B_DEI5,0xBA0),
 581         INTC_VECT(DMAC0B_DADERR,0xBC0),
 582
 583         INTC_VECT(KEYSC_KEYI,0xBE0),
 584         INTC_VECT(SCIF_SCIF0,0xC00),
 585         INTC_VECT(SCIF_SCIF1,0xC20),
 586         INTC_VECT(SCIF_SCIF2,0xC40),
 587         INTC_VECT(MSIOF_MSIOFI0,0xC80),
 588         INTC_VECT(MSIOF_MSIOFI1,0xCA0),
 589         INTC_VECT(SCIFA_SCIFA1,0xD00),
 590
 591         INTC_VECT(FLCTL_FLSTEI,0xD80),
 592         INTC_VECT(FLCTL_FLTENDI,0xDA0),
 593         INTC_VECT(FLCTL_FLTREQ0I,0xDC0),
 594         INTC_VECT(FLCTL_FLTREQ1I,0xDE0),
 595
 596         INTC_VECT(I2C_ALI,0xE00),
 597         INTC_VECT(I2C_TACKI,0xE20),
 598         INTC_VECT(I2C_WAITI,0xE40),
 599         INTC_VECT(I2C_DTEI,0xE60),
 600
 601         INTC_VECT(SDHI0_SDHII0,0xE80),
 602         INTC_VECT(SDHI0_SDHII1,0xEA0),
 603         INTC_VECT(SDHI0_SDHII2,0xEC0),
 604
 605         INTC_VECT(CMT_CMTI,0xF00),
 606         INTC_VECT(TSIF_TSIFI,0xF20),
 607         INTC_VECT(SIU_SIUI,0xF80),
 608         INTC_VECT(SCIFA_SCIFA2,0xFA0),
 609
 610         INTC_VECT(TMU0_TUNI0,0x400),
 611         INTC_VECT(TMU0_TUNI1,0x420),
 612         INTC_VECT(TMU0_TUNI2,0x440),
 613
 614         INTC_VECT(IRDA_IRDAI,0x480),
 615         INTC_VECT(ATAPI_ATAPII,0x4A0),
 616
 617         INTC_VECT(SDHI1_SDHII0,0x4E0),
 618         INTC_VECT(SDHI1_SDHII1,0x500),
 619         INTC_VECT(SDHI1_SDHII2,0x520),
 620
 621         INTC_VECT(VEU2H1_VEU2HI,0x560),
 622         INTC_VECT(LCDC_LCDCI,0x580),
 623
 624         INTC_VECT(TMU1_TUNI0,0x920),
 625         INTC_VECT(TMU1_TUNI1,0x940),
 626         INTC_VECT(TMU1_TUNI2,0x960),
 627
 628 };
 629
 630 static struct intc_group groups[] __initdata = {
 631         INTC_GROUP(DMAC1A,DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3),
 632         INTC_GROUP(DMAC0A,DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3),
 633         INTC_GROUP(VIO, VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI),
 634         INTC_GROUP(DMAC0B, DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR),
 635         INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I),
 636         INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI),
 637         INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI),
 638         INTC_GROUP(SDHI1, SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2),
 639         INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI),
 640         INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR),
 641         INTC_GROUP(SDHI0,SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2),
 642 };
 643
 644 static struct intc_mask_reg mask_registers[] __initdata = {
 645         { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
 646           { 0,  TMU1_TUNI2,TMU1_TUNI1,TMU1_TUNI0,0,SDHI1_SDHII2,SDHI1_SDHII1,SDHI1_SDHII0} },
 647         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
 648           { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } },
 649         { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
 650           { 0, 0, 0, VPU_VPUI,0,0,0,SCIFA_SCIFA0 } },
 651         { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
 652           { DMAC1A_DEI3,DMAC1A_DEI2,DMAC1A_DEI1,DMAC1A_DEI0,0,0,0,IRDA_IRDAI } },
 653         { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
 654           { 0,TMU0_TUNI2,TMU0_TUNI1,TMU0_TUNI0,VEU2H1_VEU2HI,0,0,LCDC_LCDCI } },
 655         { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
 656           { KEYSC_KEYI,DMAC0B_DADERR,DMAC0B_DEI5,DMAC0B_DEI4,0,SCIF_SCIF2,SCIF_SCIF1,SCIF_SCIF0 } },
 657         { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
 658           { 0,0,0,SCIFA_SCIFA1,ADC_ADI,0,MSIOF_MSIOFI1,MSIOF_MSIOFI0 } },
 659         { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
 660           { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
 661             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
 662         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
 663           { 0,SDHI0_SDHII2,SDHI0_SDHII1,SDHI0_SDHII0,0,0,SCIFA_SCIFA2,SIU_SIUI } },
 664         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
 665           { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } },
 666         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
 667           { 0, DMAC1B_DADERR,DMAC1B_DEI5,DMAC1B_DEI4,0,RTC_ATI,RTC_PRI,RTC_CUI } },
 668         { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
 669           { 0,_2DG_CEI,_2DG_INI,_2DG_TRI,0,TPU_TPUI,0,TSIF_TSIFI } },
 670         { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
 671           { 0,0,0,0,0,0,0,ATAPI_ATAPII } },
 672         { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
 673           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 674 };
 675
 676 static struct intc_prio_reg prio_registers[] __initdata = {
 677         { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI } },
 678         { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2H1_VEU2HI, LCDC_LCDCI, DMAC1A, 0} },
 679         { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 0} },
 680         { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
 681         { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA_SCIFA0, VPU_VPUI } },
 682         { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, USB_USI0, CMT_CMTI } },
 683         { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,0 } },
 684         { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0,MSIOF_MSIOFI1, FLCTL, I2C } },
 685         { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA_SCIFA1,0,TSIF_TSIFI,_2DG } },
 686         { 0xa4080024, 0, 16, 4, /* IPRJ */ { ADC_ADI,0,SIU_SIUI,SDHI1 } },
 687         { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC,DMAC1B,0,SDHI0 } },
 688         { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA_SCIFA2,0,TPU_TPUI,ATAPI_ATAPII } },
 689         { 0xa4140010, 0, 32, 4, /* INTPRI00 */
 690           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 691 };
 692
 693 static struct intc_sense_reg sense_registers[] __initdata = {
 694         { 0xa414001c, 16, 2, /* ICR1 */
 695           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 696 };
 697
 698 static struct intc_mask_reg ack_registers[] __initdata = {
 699         { 0xa4140024, 0, 8, /* INTREQ00 */
 700           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 701 };
 702
 703 static DECLARE_INTC_DESC_ACK(intc_desc, "sh7723", vectors, groups,
 704                              mask_registers, prio_registers, sense_registers,
 705                              ack_registers);
 706
 707 void __init plat_irq_setup(void)
 708 {
 709         register_intc_controller(&intc_desc);
 710 }