1 /* starfire.c: Linux device driver for the Adaptec Starfire network adapter. */
3 Written 1998-2000 by Donald Becker.
5 Current maintainer is Ion Badulescu <ionut ta badula tod org>. Please
6 send all bug reports to me, and not to Donald Becker, as this code
7 has been heavily modified from Donald's original version.
9 This software may be used and distributed according to the terms of
10 the GNU General Public License (GPL), incorporated herein by reference.
11 Drivers based on or derived from this code fall under the GPL and must
12 retain the authorship, copyright and license notice. This file is not
13 a complete program and may only be used when the entire operating
14 system is licensed under the GPL.
16 The information below comes from Donald Becker's original driver:
18 The author may be reached as becker@scyld.com, or C/O
19 Scyld Computing Corporation
20 410 Severn Ave., Suite 210
23 Support and updates available at
24 http://www.scyld.com/network/starfire.html
25 [link no longer provides useful info -jgarzik]
29 #define DRV_NAME "starfire"
30 #define DRV_VERSION "2.0"
31 #define DRV_RELDATE "June 27, 2006"
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/pci.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/init.h>
39 #include <linux/delay.h>
40 #include <linux/crc32.h>
41 #include <linux/ethtool.h>
42 #include <linux/mii.h>
43 #include <linux/if_vlan.h>
45 #include <asm/processor.h> /* Processor type for cache alignment. */
46 #include <asm/uaccess.h>
49 #include "starfire_firmware.h"
51 * The current frame processor firmware fails to checksum a fragment
52 * of length 1. If and when this is fixed, the #define below can be removed.
54 #define HAS_BROKEN_FIRMWARE
57 * If using the broken firmware, data must be padded to the next 32-bit boundary.
59 #ifdef HAS_BROKEN_FIRMWARE
60 #define PADDING_MASK 3
64 * Define this if using the driver with the zero-copy patch
68 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
72 #ifndef CONFIG_ADAPTEC_STARFIRE_NAPI
73 #undef HAVE_NETDEV_POLL
76 /* The user-configurable values.
77 These may be modified when a driver module is loaded.*/
79 /* Used for tuning interrupt latency vs. overhead. */
80 static int intr_latency;
81 static int small_frames;
83 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
84 static int max_interrupt_work = 20;
86 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
87 The Starfire has a 512 element hash table based on the Ethernet CRC. */
88 static const int multicast_filter_limit = 512;
89 /* Whether to do TCP/UDP checksums in hardware */
90 static int enable_hw_cksum = 1;
92 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
94 * Set the copy breakpoint for the copy-only-tiny-frames scheme.
95 * Setting to > 1518 effectively disables this feature.
98 * The ia64 doesn't allow for unaligned loads even of integers being
99 * misaligned on a 2 byte boundary. Thus always force copying of
100 * packets as the starfire doesn't allow for misaligned DMAs ;-(
103 * The Alpha and the Sparc don't like unaligned loads, either. On Sparc64,
104 * at least, having unaligned frames leads to a rather serious performance
107 #if defined(__ia64__) || defined(__alpha__) || defined(__sparc__)
108 static int rx_copybreak = PKT_BUF_SZ;
110 static int rx_copybreak /* = 0 */;
113 /* PCI DMA burst size -- on sparc64 we want to force it to 64 bytes, on the others the default of 128 is fine. */
115 #define DMA_BURST_SIZE 64
117 #define DMA_BURST_SIZE 128
120 /* Used to pass the media type, etc.
121 Both 'options[]' and 'full_duplex[]' exist for driver interoperability.
122 The media type is usually passed in 'options[]'.
123 These variables are deprecated, use ethtool instead. -Ion
125 #define MAX_UNITS 8 /* More are supported, limit only on options */
126 static int options[MAX_UNITS] = {0, };
127 static int full_duplex[MAX_UNITS] = {0, };
129 /* Operational parameters that are set at compile time. */
131 /* The "native" ring sizes are either 256 or 2048.
132 However in some modes a descriptor may be marked to wrap the ring earlier.
134 #define RX_RING_SIZE 256
135 #define TX_RING_SIZE 32
136 /* The completion queues are fixed at 1024 entries i.e. 4K or 8KB. */
137 #define DONE_Q_SIZE 1024
138 /* All queues must be aligned on a 256-byte boundary */
139 #define QUEUE_ALIGN 256
141 #if RX_RING_SIZE > 256
142 #define RX_Q_ENTRIES Rx2048QEntries
144 #define RX_Q_ENTRIES Rx256QEntries
147 /* Operational parameters that usually are not changed. */
148 /* Time in jiffies before concluding the transmitter is hung. */
149 #define TX_TIMEOUT (2 * HZ)
153 * We need a much better method to determine if dma_addr_t is 64-bit.
155 #if (defined(__i386__) && defined(CONFIG_HIGHMEM64G)) || defined(__x86_64__) || defined (__ia64__) || defined(__alpha__) || defined(__mips64__) || (defined(__mips__) && defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR))
156 /* 64-bit dma_addr_t */
157 #define ADDR_64BITS /* This chip uses 64 bit addresses. */
158 #define netdrv_addr_t __le64
159 #define cpu_to_dma(x) cpu_to_le64(x)
160 #define dma_to_cpu(x) le64_to_cpu(x)
161 #define RX_DESC_Q_ADDR_SIZE RxDescQAddr64bit
162 #define TX_DESC_Q_ADDR_SIZE TxDescQAddr64bit
163 #define RX_COMPL_Q_ADDR_SIZE RxComplQAddr64bit
164 #define TX_COMPL_Q_ADDR_SIZE TxComplQAddr64bit
165 #define RX_DESC_ADDR_SIZE RxDescAddr64bit
166 #else /* 32-bit dma_addr_t */
167 #define netdrv_addr_t __le32
168 #define cpu_to_dma(x) cpu_to_le32(x)
169 #define dma_to_cpu(x) le32_to_cpu(x)
170 #define RX_DESC_Q_ADDR_SIZE RxDescQAddr32bit
171 #define TX_DESC_Q_ADDR_SIZE TxDescQAddr32bit
172 #define RX_COMPL_Q_ADDR_SIZE RxComplQAddr32bit
173 #define TX_COMPL_Q_ADDR_SIZE TxComplQAddr32bit
174 #define RX_DESC_ADDR_SIZE RxDescAddr32bit
177 #define skb_first_frag_len(skb) skb_headlen(skb)
178 #define skb_num_frags(skb) (skb_shinfo(skb)->nr_frags + 1)
180 #ifdef HAVE_NETDEV_POLL
181 #define init_poll(dev, np) \
182 netif_napi_add(dev, &np->napi, netdev_poll, max_interrupt_work)
183 #define netdev_rx(dev, np, ioaddr) \
186 if (netif_rx_schedule_prep(dev, &np->napi)) { \
187 __netif_rx_schedule(dev, &np->napi); \
188 intr_enable = readl(ioaddr + IntrEnable); \
189 intr_enable &= ~(IntrRxDone | IntrRxEmpty); \
190 writel(intr_enable, ioaddr + IntrEnable); \
191 readl(ioaddr + IntrEnable); /* flush PCI posting buffers */ \
193 /* Paranoia check */ \
194 intr_enable = readl(ioaddr + IntrEnable); \
195 if (intr_enable & (IntrRxDone | IntrRxEmpty)) { \
196 printk(KERN_INFO "%s: interrupt while in polling mode!\n", dev->name); \
197 intr_enable &= ~(IntrRxDone | IntrRxEmpty); \
198 writel(intr_enable, ioaddr + IntrEnable); \
202 #define netdev_receive_skb(skb) netif_receive_skb(skb)
203 #define vlan_netdev_receive_skb(skb, vlgrp, vlid) vlan_hwaccel_receive_skb(skb, vlgrp, vlid)
204 static int netdev_poll(struct napi_struct *napi, int budget);
205 #else /* not HAVE_NETDEV_POLL */
206 #define init_poll(dev, np)
207 #define netdev_receive_skb(skb) netif_rx(skb)
208 #define vlan_netdev_receive_skb(skb, vlgrp, vlid) vlan_hwaccel_rx(skb, vlgrp, vlid)
209 #define netdev_rx(dev, np, ioaddr) \
211 int quota = np->dirty_rx + RX_RING_SIZE - np->cur_rx; \
212 __netdev_rx(dev, "a);\
214 #endif /* not HAVE_NETDEV_POLL */
215 /* end of compatibility code */
218 /* These identify the driver base version and may not be removed. */
219 static const char version[] __devinitdata =
220 KERN_INFO "starfire.c:v1.03 7/26/2000 Written by Donald Becker <becker@scyld.com>\n"
221 KERN_INFO " (unofficial 2.2/2.4 kernel port, version " DRV_VERSION ", " DRV_RELDATE ")\n";
223 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
224 MODULE_DESCRIPTION("Adaptec Starfire Ethernet driver");
225 MODULE_LICENSE("GPL");
226 MODULE_VERSION(DRV_VERSION);
228 module_param(max_interrupt_work, int, 0);
229 module_param(mtu, int, 0);
230 module_param(debug, int, 0);
231 module_param(rx_copybreak, int, 0);
232 module_param(intr_latency, int, 0);
233 module_param(small_frames, int, 0);
234 module_param_array(options, int, NULL, 0);
235 module_param_array(full_duplex, int, NULL, 0);
236 module_param(enable_hw_cksum, int, 0);
237 MODULE_PARM_DESC(max_interrupt_work, "Maximum events handled per interrupt");
238 MODULE_PARM_DESC(mtu, "MTU (all boards)");
239 MODULE_PARM_DESC(debug, "Debug level (0-6)");
240 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
241 MODULE_PARM_DESC(intr_latency, "Maximum interrupt latency, in microseconds");
242 MODULE_PARM_DESC(small_frames, "Maximum size of receive frames that bypass interrupt latency (0,64,128,256,512)");
243 MODULE_PARM_DESC(options, "Deprecated: Bits 0-3: media type, bit 17: full duplex");
244 MODULE_PARM_DESC(full_duplex, "Deprecated: Forced full-duplex setting (0/1)");
245 MODULE_PARM_DESC(enable_hw_cksum, "Enable/disable hardware cksum support (0/1)");
250 I. Board Compatibility
252 This driver is for the Adaptec 6915 "Starfire" 64 bit PCI Ethernet adapter.
254 II. Board-specific settings
256 III. Driver operation
260 The Starfire hardware uses multiple fixed-size descriptor queues/rings. The
261 ring sizes are set fixed by the hardware, but may optionally be wrapped
262 earlier by the END bit in the descriptor.
263 This driver uses that hardware queue size for the Rx ring, where a large
264 number of entries has no ill effect beyond increases the potential backlog.
265 The Tx ring is wrapped with the END bit, since a large hardware Tx queue
266 disables the queue layer priority ordering and we have no mechanism to
267 utilize the hardware two-level priority queue. When modifying the
268 RX/TX_RING_SIZE pay close attention to page sizes and the ring-empty warning
271 IIIb/c. Transmit/Receive Structure
273 See the Adaptec manual for the many possible structures, and options for
274 each structure. There are far too many to document all of them here.
276 For transmit this driver uses type 0/1 transmit descriptors (depending
277 on the 32/64 bitness of the architecture), and relies on automatic
278 minimum-length padding. It does not use the completion queue
279 consumer index, but instead checks for non-zero status entries.
281 For receive this driver uses type 2/3 receive descriptors. The driver
282 allocates full frame size skbuffs for the Rx ring buffers, so all frames
283 should fit in a single descriptor. The driver does not use the completion
284 queue consumer index, but instead checks for non-zero status entries.
286 When an incoming frame is less than RX_COPYBREAK bytes long, a fresh skbuff
287 is allocated and the frame is copied to the new skbuff. When the incoming
288 frame is larger, the skbuff is passed directly up the protocol stack.
289 Buffers consumed this way are replaced by newly allocated skbuffs in a later
292 A notable aspect of operation is that unaligned buffers are not permitted by
293 the Starfire hardware. Thus the IP header at offset 14 in an ethernet frame
294 isn't longword aligned, which may cause problems on some machine
295 e.g. Alphas and IA64. For these architectures, the driver is forced to copy
296 the frame into a new skbuff unconditionally. Copied frames are put into the
297 skbuff at an offset of "+2", thus 16-byte aligning the IP header.
299 IIId. Synchronization
301 The driver runs as two independent, single-threaded flows of control. One
302 is the send-packet routine, which enforces single-threaded use by the
303 dev->tbusy flag. The other thread is the interrupt handler, which is single
304 threaded by the hardware and interrupt handling software.
306 The send packet thread has partial control over the Tx ring and the netif_queue
307 status. If the number of free Tx slots in the ring falls below a certain number
308 (currently hardcoded to 4), it signals the upper layer to stop the queue.
310 The interrupt handler has exclusive control over the Rx ring and records stats
311 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
312 empty by incrementing the dirty_tx mark. Iff the netif_queue is stopped and the
313 number of free Tx slow is above the threshold, it signals the upper layer to
320 The Adaptec Starfire manuals, available only from Adaptec.
321 http://www.scyld.com/expert/100mbps.html
322 http://www.scyld.com/expert/NWay.html
326 - StopOnPerr is broken, don't enable
327 - Hardware ethernet padding exposes random data, perform software padding
328 instead (unverified -- works correctly for all the hardware I have)
334 enum chip_capability_flags {CanHaveMII=1, };
340 static struct pci_device_id starfire_pci_tbl[] = {
341 { 0x9004, 0x6915, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_6915 },
344 MODULE_DEVICE_TABLE(pci, starfire_pci_tbl);
346 /* A chip capabilities table, matching the CH_xxx entries in xxx_pci_tbl[] above. */
347 static const struct chip_info {
350 } netdrv_tbl[] __devinitdata = {
351 { "Adaptec Starfire 6915", CanHaveMII },
355 /* Offsets to the device registers.
356 Unlike software-only systems, device drivers interact with complex hardware.
357 It's not useful to define symbolic names for every register bit in the
358 device. The name can only partially document the semantics and make
359 the driver longer and more difficult to read.
360 In general, only the important configuration values or bits changed
361 multiple times should be defined symbolically.
363 enum register_offsets {
364 PCIDeviceConfig=0x50040, GenCtrl=0x50070, IntrTimerCtrl=0x50074,
365 IntrClear=0x50080, IntrStatus=0x50084, IntrEnable=0x50088,
366 MIICtrl=0x52000, TxStationAddr=0x50120, EEPROMCtrl=0x51000,
367 GPIOCtrl=0x5008C, TxDescCtrl=0x50090,
368 TxRingPtr=0x50098, HiPriTxRingPtr=0x50094, /* Low and High priority. */
369 TxRingHiAddr=0x5009C, /* 64 bit address extension. */
370 TxProducerIdx=0x500A0, TxConsumerIdx=0x500A4,
372 CompletionHiAddr=0x500B4, TxCompletionAddr=0x500B8,
373 RxCompletionAddr=0x500BC, RxCompletionQ2Addr=0x500C0,
374 CompletionQConsumerIdx=0x500C4, RxDMACtrl=0x500D0,
375 RxDescQCtrl=0x500D4, RxDescQHiAddr=0x500DC, RxDescQAddr=0x500E0,
376 RxDescQIdx=0x500E8, RxDMAStatus=0x500F0, RxFilterMode=0x500F4,
377 TxMode=0x55000, VlanType=0x55064,
378 PerfFilterTable=0x56000, HashTable=0x56100,
379 TxGfpMem=0x58000, RxGfpMem=0x5a000,
383 * Bits in the interrupt status/mask registers.
384 * Warning: setting Intr[Ab]NormalSummary in the IntrEnable register
385 * enables all the interrupt sources that are or'ed into those status bits.
387 enum intr_status_bits {
388 IntrLinkChange=0xf0000000, IntrStatsMax=0x08000000,
389 IntrAbnormalSummary=0x02000000, IntrGeneralTimer=0x01000000,
390 IntrSoftware=0x800000, IntrRxComplQ1Low=0x400000,
391 IntrTxComplQLow=0x200000, IntrPCI=0x100000,
392 IntrDMAErr=0x080000, IntrTxDataLow=0x040000,
393 IntrRxComplQ2Low=0x020000, IntrRxDescQ1Low=0x010000,
394 IntrNormalSummary=0x8000, IntrTxDone=0x4000,
395 IntrTxDMADone=0x2000, IntrTxEmpty=0x1000,
396 IntrEarlyRxQ2=0x0800, IntrEarlyRxQ1=0x0400,
397 IntrRxQ2Done=0x0200, IntrRxQ1Done=0x0100,
398 IntrRxGFPDead=0x80, IntrRxDescQ2Low=0x40,
399 IntrNoTxCsum=0x20, IntrTxBadID=0x10,
400 IntrHiPriTxBadID=0x08, IntrRxGfp=0x04,
401 IntrTxGfp=0x02, IntrPCIPad=0x01,
403 IntrRxDone=IntrRxQ2Done | IntrRxQ1Done,
404 IntrRxEmpty=IntrRxDescQ1Low | IntrRxDescQ2Low,
405 IntrNormalMask=0xff00, IntrAbnormalMask=0x3ff00fe,
408 /* Bits in the RxFilterMode register. */
410 AcceptBroadcast=0x04, AcceptAllMulticast=0x02, AcceptAll=0x01,
411 AcceptMulticast=0x10, PerfectFilter=0x40, HashFilter=0x30,
412 PerfectFilterVlan=0x80, MinVLANPrio=0xE000, VlanMode=0x0200,
416 /* Bits in the TxMode register */
418 MiiSoftReset=0x8000, MIILoopback=0x4000,
419 TxFlowEnable=0x0800, RxFlowEnable=0x0400,
420 PadEnable=0x04, FullDuplex=0x02, HugeFrame=0x01,
423 /* Bits in the TxDescCtrl register. */
425 TxDescSpaceUnlim=0x00, TxDescSpace32=0x10, TxDescSpace64=0x20,
426 TxDescSpace128=0x30, TxDescSpace256=0x40,
427 TxDescType0=0x00, TxDescType1=0x01, TxDescType2=0x02,
428 TxDescType3=0x03, TxDescType4=0x04,
429 TxNoDMACompletion=0x08,
430 TxDescQAddr64bit=0x80, TxDescQAddr32bit=0,
431 TxHiPriFIFOThreshShift=24, TxPadLenShift=16,
432 TxDMABurstSizeShift=8,
435 /* Bits in the RxDescQCtrl register. */
437 RxBufferLenShift=16, RxMinDescrThreshShift=0,
438 RxPrefetchMode=0x8000, RxVariableQ=0x2000,
439 Rx2048QEntries=0x4000, Rx256QEntries=0,
440 RxDescAddr64bit=0x1000, RxDescAddr32bit=0,
441 RxDescQAddr64bit=0x0100, RxDescQAddr32bit=0,
442 RxDescSpace4=0x000, RxDescSpace8=0x100,
443 RxDescSpace16=0x200, RxDescSpace32=0x300,
444 RxDescSpace64=0x400, RxDescSpace128=0x500,
448 /* Bits in the RxDMACtrl register. */
449 enum rx_dmactrl_bits {
450 RxReportBadFrames=0x80000000, RxDMAShortFrames=0x40000000,
451 RxDMABadFrames=0x20000000, RxDMACrcErrorFrames=0x10000000,
452 RxDMAControlFrame=0x08000000, RxDMAPauseFrame=0x04000000,
453 RxChecksumIgnore=0, RxChecksumRejectTCPUDP=0x02000000,
454 RxChecksumRejectTCPOnly=0x01000000,
455 RxCompletionQ2Enable=0x800000,
456 RxDMAQ2Disable=0, RxDMAQ2FPOnly=0x100000,
457 RxDMAQ2SmallPkt=0x200000, RxDMAQ2HighPrio=0x300000,
458 RxDMAQ2NonIP=0x400000,
459 RxUseBackupQueue=0x080000, RxDMACRC=0x040000,
460 RxEarlyIntThreshShift=12, RxHighPrioThreshShift=8,
464 /* Bits in the RxCompletionAddr register */
466 RxComplQAddr64bit=0x80, RxComplQAddr32bit=0,
467 RxComplProducerWrEn=0x40,
468 RxComplType0=0x00, RxComplType1=0x10,
469 RxComplType2=0x20, RxComplType3=0x30,
470 RxComplThreshShift=0,
473 /* Bits in the TxCompletionAddr register */
475 TxComplQAddr64bit=0x80, TxComplQAddr32bit=0,
476 TxComplProducerWrEn=0x40,
477 TxComplIntrStatus=0x20,
478 CommonQueueMode=0x10,
479 TxComplThreshShift=0,
482 /* Bits in the GenCtrl register */
484 RxEnable=0x05, TxEnable=0x0a,
485 RxGFPEnable=0x10, TxGFPEnable=0x20,
488 /* Bits in the IntrTimerCtrl register */
489 enum intr_ctrl_bits {
490 Timer10X=0x800, EnableIntrMasking=0x60, SmallFrameBypass=0x100,
491 SmallFrame64=0, SmallFrame128=0x200, SmallFrame256=0x400, SmallFrame512=0x600,
492 IntrLatencyMask=0x1f,
495 /* The Rx and Tx buffer descriptors. */
496 struct starfire_rx_desc {
497 netdrv_addr_t rxaddr;
500 RxDescValid=1, RxDescEndRing=2,
503 /* Completion queue entry. */
504 struct short_rx_done_desc {
505 __le32 status; /* Low 16 bits is length. */
507 struct basic_rx_done_desc {
508 __le32 status; /* Low 16 bits is length. */
512 struct csum_rx_done_desc {
513 __le32 status; /* Low 16 bits is length. */
514 __le16 csum; /* Partial checksum */
517 struct full_rx_done_desc {
518 __le32 status; /* Low 16 bits is length. */
522 __le16 csum; /* partial checksum */
525 /* XXX: this is ugly and I'm not sure it's worth the trouble -Ion */
527 typedef struct full_rx_done_desc rx_done_desc;
528 #define RxComplType RxComplType3
529 #else /* not VLAN_SUPPORT */
530 typedef struct csum_rx_done_desc rx_done_desc;
531 #define RxComplType RxComplType2
532 #endif /* not VLAN_SUPPORT */
535 RxOK=0x20000000, RxFIFOErr=0x10000000, RxBufQ2=0x08000000,
538 /* Type 1 Tx descriptor. */
539 struct starfire_tx_desc_1 {
540 __le32 status; /* Upper bits are status, lower 16 length. */
544 /* Type 2 Tx descriptor. */
545 struct starfire_tx_desc_2 {
546 __le32 status; /* Upper bits are status, lower 16 length. */
552 typedef struct starfire_tx_desc_2 starfire_tx_desc;
553 #define TX_DESC_TYPE TxDescType2
554 #else /* not ADDR_64BITS */
555 typedef struct starfire_tx_desc_1 starfire_tx_desc;
556 #define TX_DESC_TYPE TxDescType1
557 #endif /* not ADDR_64BITS */
558 #define TX_DESC_SPACING TxDescSpaceUnlim
562 TxCRCEn=0x01000000, TxDescIntr=0x08000000,
563 TxRingWrap=0x04000000, TxCalTCP=0x02000000,
565 struct tx_done_desc {
566 __le32 status; /* timestamp, index. */
568 __le32 intrstatus; /* interrupt status */
572 struct rx_ring_info {
576 struct tx_ring_info {
579 unsigned int used_slots;
583 struct netdev_private {
584 /* Descriptor rings first for alignment. */
585 struct starfire_rx_desc *rx_ring;
586 starfire_tx_desc *tx_ring;
587 dma_addr_t rx_ring_dma;
588 dma_addr_t tx_ring_dma;
589 /* The addresses of rx/tx-in-place skbuffs. */
590 struct rx_ring_info rx_info[RX_RING_SIZE];
591 struct tx_ring_info tx_info[TX_RING_SIZE];
592 /* Pointers to completion queues (full pages). */
593 rx_done_desc *rx_done_q;
594 dma_addr_t rx_done_q_dma;
595 unsigned int rx_done;
596 struct tx_done_desc *tx_done_q;
597 dma_addr_t tx_done_q_dma;
598 unsigned int tx_done;
599 struct napi_struct napi;
600 struct net_device *dev;
601 struct net_device_stats stats;
602 struct pci_dev *pci_dev;
604 struct vlan_group *vlgrp;
607 dma_addr_t queue_mem_dma;
608 size_t queue_mem_size;
610 /* Frequently used values: keep some adjacent for cache effect. */
612 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
613 unsigned int cur_tx, dirty_tx, reap_tx;
614 unsigned int rx_buf_sz; /* Based on MTU+slack. */
615 /* These values keep track of the transceiver/media in use. */
616 int speed100; /* Set if speed == 100MBit. */
620 /* MII transceiver section. */
621 struct mii_if_info mii_if; /* MII lib hooks/info */
622 int phy_cnt; /* MII device addresses. */
623 unsigned char phys[PHY_CNT]; /* MII device addresses. */
628 static int mdio_read(struct net_device *dev, int phy_id, int location);
629 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
630 static int netdev_open(struct net_device *dev);
631 static void check_duplex(struct net_device *dev);
632 static void tx_timeout(struct net_device *dev);
633 static void init_ring(struct net_device *dev);
634 static int start_tx(struct sk_buff *skb, struct net_device *dev);
635 static irqreturn_t intr_handler(int irq, void *dev_instance);
636 static void netdev_error(struct net_device *dev, int intr_status);
637 static int __netdev_rx(struct net_device *dev, int *quota);
638 static void refill_rx_ring(struct net_device *dev);
639 static void netdev_error(struct net_device *dev, int intr_status);
640 static void set_rx_mode(struct net_device *dev);
641 static struct net_device_stats *get_stats(struct net_device *dev);
642 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
643 static int netdev_close(struct net_device *dev);
644 static void netdev_media_change(struct net_device *dev);
645 static const struct ethtool_ops ethtool_ops;
649 static void netdev_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
651 struct netdev_private *np = netdev_priv(dev);
653 spin_lock(&np->lock);
655 printk("%s: Setting vlgrp to %p\n", dev->name, grp);
658 spin_unlock(&np->lock);
661 static void netdev_vlan_rx_add_vid(struct net_device *dev, unsigned short vid)
663 struct netdev_private *np = netdev_priv(dev);
665 spin_lock(&np->lock);
667 printk("%s: Adding vlanid %d to vlan filter\n", dev->name, vid);
669 spin_unlock(&np->lock);
672 static void netdev_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
674 struct netdev_private *np = netdev_priv(dev);
676 spin_lock(&np->lock);
678 printk("%s: removing vlanid %d from vlan filter\n", dev->name, vid);
679 vlan_group_set_device(np->vlgrp, vid, NULL);
681 spin_unlock(&np->lock);
683 #endif /* VLAN_SUPPORT */
686 static int __devinit starfire_init_one(struct pci_dev *pdev,
687 const struct pci_device_id *ent)
689 struct netdev_private *np;
690 int i, irq, option, chip_idx = ent->driver_data;
691 struct net_device *dev;
692 static int card_idx = -1;
695 int drv_flags, io_size;
697 DECLARE_MAC_BUF(mac);
699 /* when built into the kernel, we only print version if device is found */
701 static int printed_version;
702 if (!printed_version++)
708 if (pci_enable_device (pdev))
711 ioaddr = pci_resource_start(pdev, 0);
712 io_size = pci_resource_len(pdev, 0);
713 if (!ioaddr || ((pci_resource_flags(pdev, 0) & IORESOURCE_MEM) == 0)) {
714 printk(KERN_ERR DRV_NAME " %d: no PCI MEM resources, aborting\n", card_idx);
718 dev = alloc_etherdev(sizeof(*np));
720 printk(KERN_ERR DRV_NAME " %d: cannot alloc etherdev, aborting\n", card_idx);
723 SET_NETDEV_DEV(dev, &pdev->dev);
727 if (pci_request_regions (pdev, DRV_NAME)) {
728 printk(KERN_ERR DRV_NAME " %d: cannot reserve PCI resources, aborting\n", card_idx);
729 goto err_out_free_netdev;
732 base = ioremap(ioaddr, io_size);
734 printk(KERN_ERR DRV_NAME " %d: cannot remap %#x @ %#lx, aborting\n",
735 card_idx, io_size, ioaddr);
736 goto err_out_free_res;
739 pci_set_master(pdev);
741 /* enable MWI -- it vastly improves Rx performance on sparc64 */
742 pci_try_set_mwi(pdev);
745 /* Starfire can do TCP/UDP checksumming */
747 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
748 #endif /* ZEROCOPY */
750 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER;
751 dev->vlan_rx_register = netdev_vlan_rx_register;
752 dev->vlan_rx_add_vid = netdev_vlan_rx_add_vid;
753 dev->vlan_rx_kill_vid = netdev_vlan_rx_kill_vid;
754 #endif /* VLAN_RX_KILL_VID */
756 dev->features |= NETIF_F_HIGHDMA;
757 #endif /* ADDR_64BITS */
759 /* Serial EEPROM reads are hidden by the hardware. */
760 for (i = 0; i < 6; i++)
761 dev->dev_addr[i] = readb(base + EEPROMCtrl + 20 - i);
763 #if ! defined(final_version) /* Dump the EEPROM contents during development. */
765 for (i = 0; i < 0x20; i++)
767 (unsigned int)readb(base + EEPROMCtrl + i),
768 i % 16 != 15 ? " " : "\n");
771 /* Issue soft reset */
772 writel(MiiSoftReset, base + TxMode);
774 writel(0, base + TxMode);
776 /* Reset the chip to erase previous misconfiguration. */
777 writel(1, base + PCIDeviceConfig);
779 while (--boguscnt > 0) {
781 if ((readl(base + PCIDeviceConfig) & 1) == 0)
785 printk("%s: chipset reset never completed!\n", dev->name);
786 /* wait a little longer */
789 dev->base_addr = (unsigned long)base;
792 np = netdev_priv(dev);
795 spin_lock_init(&np->lock);
796 pci_set_drvdata(pdev, dev);
800 np->mii_if.dev = dev;
801 np->mii_if.mdio_read = mdio_read;
802 np->mii_if.mdio_write = mdio_write;
803 np->mii_if.phy_id_mask = 0x1f;
804 np->mii_if.reg_num_mask = 0x1f;
806 drv_flags = netdrv_tbl[chip_idx].drv_flags;
808 option = card_idx < MAX_UNITS ? options[card_idx] : 0;
810 option = dev->mem_start;
812 /* The lower four bits are the media type. */
814 np->mii_if.full_duplex = 1;
816 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
817 np->mii_if.full_duplex = 1;
819 if (np->mii_if.full_duplex)
820 np->mii_if.force_media = 1;
822 np->mii_if.force_media = 0;
825 /* timer resolution is 128 * 0.8us */
826 np->intr_timer_ctrl = (((intr_latency * 10) / 1024) & IntrLatencyMask) |
827 Timer10X | EnableIntrMasking;
829 if (small_frames > 0) {
830 np->intr_timer_ctrl |= SmallFrameBypass;
831 switch (small_frames) {
833 np->intr_timer_ctrl |= SmallFrame64;
836 np->intr_timer_ctrl |= SmallFrame128;
839 np->intr_timer_ctrl |= SmallFrame256;
842 np->intr_timer_ctrl |= SmallFrame512;
843 if (small_frames > 512)
844 printk("Adjusting small_frames down to 512\n");
849 /* The chip-specific entries in the device structure. */
850 dev->open = &netdev_open;
851 dev->hard_start_xmit = &start_tx;
852 dev->tx_timeout = tx_timeout;
853 dev->watchdog_timeo = TX_TIMEOUT;
855 dev->stop = &netdev_close;
856 dev->get_stats = &get_stats;
857 dev->set_multicast_list = &set_rx_mode;
858 dev->do_ioctl = &netdev_ioctl;
859 SET_ETHTOOL_OPS(dev, ðtool_ops);
864 if (register_netdev(dev))
865 goto err_out_cleardev;
867 printk(KERN_INFO "%s: %s at %p, %s, IRQ %d.\n",
868 dev->name, netdrv_tbl[chip_idx].name, base,
869 print_mac(mac, dev->dev_addr), irq);
871 if (drv_flags & CanHaveMII) {
872 int phy, phy_idx = 0;
874 for (phy = 0; phy < 32 && phy_idx < PHY_CNT; phy++) {
875 mdio_write(dev, phy, MII_BMCR, BMCR_RESET);
878 while (--boguscnt > 0)
879 if ((mdio_read(dev, phy, MII_BMCR) & BMCR_RESET) == 0)
882 printk("%s: PHY#%d reset never completed!\n", dev->name, phy);
885 mii_status = mdio_read(dev, phy, MII_BMSR);
886 if (mii_status != 0) {
887 np->phys[phy_idx++] = phy;
888 np->mii_if.advertising = mdio_read(dev, phy, MII_ADVERTISE);
889 printk(KERN_INFO "%s: MII PHY found at address %d, status "
890 "%#4.4x advertising %#4.4x.\n",
891 dev->name, phy, mii_status, np->mii_if.advertising);
892 /* there can be only one PHY on-board */
896 np->phy_cnt = phy_idx;
898 np->mii_if.phy_id = np->phys[0];
900 memset(&np->mii_if, 0, sizeof(np->mii_if));
903 printk(KERN_INFO "%s: scatter-gather and hardware TCP cksumming %s.\n",
904 dev->name, enable_hw_cksum ? "enabled" : "disabled");
908 pci_set_drvdata(pdev, NULL);
911 pci_release_regions (pdev);
918 /* Read the MII Management Data I/O (MDIO) interfaces. */
919 static int mdio_read(struct net_device *dev, int phy_id, int location)
921 struct netdev_private *np = netdev_priv(dev);
922 void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2);
923 int result, boguscnt=1000;
924 /* ??? Should we add a busy-wait here? */
926 result = readl(mdio_addr);
927 while ((result & 0xC0000000) != 0x80000000 && --boguscnt > 0);
930 if ((result & 0xffff) == 0xffff)
932 return result & 0xffff;
936 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
938 struct netdev_private *np = netdev_priv(dev);
939 void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2);
940 writel(value, mdio_addr);
941 /* The busy-wait will occur before a read. */
945 static int netdev_open(struct net_device *dev)
947 struct netdev_private *np = netdev_priv(dev);
948 void __iomem *ioaddr = np->base;
950 size_t tx_done_q_size, rx_done_q_size, tx_ring_size, rx_ring_size;
952 /* Do we ever need to reset the chip??? */
954 retval = request_irq(dev->irq, &intr_handler, IRQF_SHARED, dev->name, dev);
958 /* Disable the Rx and Tx, and reset the chip. */
959 writel(0, ioaddr + GenCtrl);
960 writel(1, ioaddr + PCIDeviceConfig);
962 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
963 dev->name, dev->irq);
965 /* Allocate the various queues. */
966 if (!np->queue_mem) {
967 tx_done_q_size = ((sizeof(struct tx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
968 rx_done_q_size = ((sizeof(rx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
969 tx_ring_size = ((sizeof(starfire_tx_desc) * TX_RING_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
970 rx_ring_size = sizeof(struct starfire_rx_desc) * RX_RING_SIZE;
971 np->queue_mem_size = tx_done_q_size + rx_done_q_size + tx_ring_size + rx_ring_size;
972 np->queue_mem = pci_alloc_consistent(np->pci_dev, np->queue_mem_size, &np->queue_mem_dma);
973 if (np->queue_mem == NULL) {
974 free_irq(dev->irq, dev);
978 np->tx_done_q = np->queue_mem;
979 np->tx_done_q_dma = np->queue_mem_dma;
980 np->rx_done_q = (void *) np->tx_done_q + tx_done_q_size;
981 np->rx_done_q_dma = np->tx_done_q_dma + tx_done_q_size;
982 np->tx_ring = (void *) np->rx_done_q + rx_done_q_size;
983 np->tx_ring_dma = np->rx_done_q_dma + rx_done_q_size;
984 np->rx_ring = (void *) np->tx_ring + tx_ring_size;
985 np->rx_ring_dma = np->tx_ring_dma + tx_ring_size;
988 /* Start with no carrier, it gets adjusted later */
989 netif_carrier_off(dev);
991 /* Set the size of the Rx buffers. */
992 writel((np->rx_buf_sz << RxBufferLenShift) |
993 (0 << RxMinDescrThreshShift) |
994 RxPrefetchMode | RxVariableQ |
996 RX_DESC_Q_ADDR_SIZE | RX_DESC_ADDR_SIZE |
998 ioaddr + RxDescQCtrl);
1000 /* Set up the Rx DMA controller. */
1001 writel(RxChecksumIgnore |
1002 (0 << RxEarlyIntThreshShift) |
1003 (6 << RxHighPrioThreshShift) |
1004 ((DMA_BURST_SIZE / 32) << RxBurstSizeShift),
1005 ioaddr + RxDMACtrl);
1007 /* Set Tx descriptor */
1008 writel((2 << TxHiPriFIFOThreshShift) |
1009 (0 << TxPadLenShift) |
1010 ((DMA_BURST_SIZE / 32) << TxDMABurstSizeShift) |
1011 TX_DESC_Q_ADDR_SIZE |
1012 TX_DESC_SPACING | TX_DESC_TYPE,
1013 ioaddr + TxDescCtrl);
1015 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + RxDescQHiAddr);
1016 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + TxRingHiAddr);
1017 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + CompletionHiAddr);
1018 writel(np->rx_ring_dma, ioaddr + RxDescQAddr);
1019 writel(np->tx_ring_dma, ioaddr + TxRingPtr);
1021 writel(np->tx_done_q_dma, ioaddr + TxCompletionAddr);
1022 writel(np->rx_done_q_dma |
1024 (0 << RxComplThreshShift),
1025 ioaddr + RxCompletionAddr);
1028 printk(KERN_DEBUG "%s: Filling in the station address.\n", dev->name);
1030 /* Fill both the Tx SA register and the Rx perfect filter. */
1031 for (i = 0; i < 6; i++)
1032 writeb(dev->dev_addr[i], ioaddr + TxStationAddr + 5 - i);
1033 /* The first entry is special because it bypasses the VLAN filter.
1035 writew(0, ioaddr + PerfFilterTable);
1036 writew(0, ioaddr + PerfFilterTable + 4);
1037 writew(0, ioaddr + PerfFilterTable + 8);
1038 for (i = 1; i < 16; i++) {
1039 __be16 *eaddrs = (__be16 *)dev->dev_addr;
1040 void __iomem *setup_frm = ioaddr + PerfFilterTable + i * 16;
1041 writew(be16_to_cpu(eaddrs[2]), setup_frm); setup_frm += 4;
1042 writew(be16_to_cpu(eaddrs[1]), setup_frm); setup_frm += 4;
1043 writew(be16_to_cpu(eaddrs[0]), setup_frm); setup_frm += 8;
1046 /* Initialize other registers. */
1047 /* Configure the PCI bus bursts and FIFO thresholds. */
1048 np->tx_mode = TxFlowEnable|RxFlowEnable|PadEnable; /* modified when link is up. */
1049 writel(MiiSoftReset | np->tx_mode, ioaddr + TxMode);
1051 writel(np->tx_mode, ioaddr + TxMode);
1052 np->tx_threshold = 4;
1053 writel(np->tx_threshold, ioaddr + TxThreshold);
1055 writel(np->intr_timer_ctrl, ioaddr + IntrTimerCtrl);
1057 #ifdef HAVE_NETDEV_POLL
1058 napi_enable(&np->napi);
1060 netif_start_queue(dev);
1063 printk(KERN_DEBUG "%s: Setting the Rx and Tx modes.\n", dev->name);
1066 np->mii_if.advertising = mdio_read(dev, np->phys[0], MII_ADVERTISE);
1069 /* Enable GPIO interrupts on link change */
1070 writel(0x0f00ff00, ioaddr + GPIOCtrl);
1072 /* Set the interrupt mask */
1073 writel(IntrRxDone | IntrRxEmpty | IntrDMAErr |
1074 IntrTxDMADone | IntrStatsMax | IntrLinkChange |
1075 IntrRxGFPDead | IntrNoTxCsum | IntrTxBadID,
1076 ioaddr + IntrEnable);
1077 /* Enable PCI interrupts. */
1078 writel(0x00800000 | readl(ioaddr + PCIDeviceConfig),
1079 ioaddr + PCIDeviceConfig);
1082 /* Set VLAN type to 802.1q */
1083 writel(ETH_P_8021Q, ioaddr + VlanType);
1084 #endif /* VLAN_SUPPORT */
1086 /* Load Rx/Tx firmware into the frame processors */
1087 for (i = 0; i < FIRMWARE_RX_SIZE * 2; i++)
1088 writel(firmware_rx[i], ioaddr + RxGfpMem + i * 4);
1089 for (i = 0; i < FIRMWARE_TX_SIZE * 2; i++)
1090 writel(firmware_tx[i], ioaddr + TxGfpMem + i * 4);
1091 if (enable_hw_cksum)
1092 /* Enable the Rx and Tx units, and the Rx/Tx frame processors. */
1093 writel(TxEnable|TxGFPEnable|RxEnable|RxGFPEnable, ioaddr + GenCtrl);
1095 /* Enable the Rx and Tx units only. */
1096 writel(TxEnable|RxEnable, ioaddr + GenCtrl);
1099 printk(KERN_DEBUG "%s: Done netdev_open().\n",
1106 static void check_duplex(struct net_device *dev)
1108 struct netdev_private *np = netdev_priv(dev);
1110 int silly_count = 1000;
1112 mdio_write(dev, np->phys[0], MII_ADVERTISE, np->mii_if.advertising);
1113 mdio_write(dev, np->phys[0], MII_BMCR, BMCR_RESET);
1115 while (--silly_count && mdio_read(dev, np->phys[0], MII_BMCR) & BMCR_RESET)
1118 printk("%s: MII reset failed!\n", dev->name);
1122 reg0 = mdio_read(dev, np->phys[0], MII_BMCR);
1124 if (!np->mii_if.force_media) {
1125 reg0 |= BMCR_ANENABLE | BMCR_ANRESTART;
1127 reg0 &= ~(BMCR_ANENABLE | BMCR_ANRESTART);
1129 reg0 |= BMCR_SPEED100;
1130 if (np->mii_if.full_duplex)
1131 reg0 |= BMCR_FULLDPLX;
1132 printk(KERN_DEBUG "%s: Link forced to %sMbit %s-duplex\n",
1134 np->speed100 ? "100" : "10",
1135 np->mii_if.full_duplex ? "full" : "half");
1137 mdio_write(dev, np->phys[0], MII_BMCR, reg0);
1141 static void tx_timeout(struct net_device *dev)
1143 struct netdev_private *np = netdev_priv(dev);
1144 void __iomem *ioaddr = np->base;
1147 printk(KERN_WARNING "%s: Transmit timed out, status %#8.8x, "
1148 "resetting...\n", dev->name, (int) readl(ioaddr + IntrStatus));
1150 /* Perhaps we should reinitialize the hardware here. */
1153 * Stop and restart the interface.
1154 * Cheat and increase the debug level temporarily.
1162 /* Trigger an immediate transmit demand. */
1164 dev->trans_start = jiffies;
1165 np->stats.tx_errors++;
1166 netif_wake_queue(dev);
1170 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1171 static void init_ring(struct net_device *dev)
1173 struct netdev_private *np = netdev_priv(dev);
1176 np->cur_rx = np->cur_tx = np->reap_tx = 0;
1177 np->dirty_rx = np->dirty_tx = np->rx_done = np->tx_done = 0;
1179 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1181 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
1182 for (i = 0; i < RX_RING_SIZE; i++) {
1183 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
1184 np->rx_info[i].skb = skb;
1187 np->rx_info[i].mapping = pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1188 skb->dev = dev; /* Mark as being used by this device. */
1189 /* Grrr, we cannot offset to correctly align the IP header. */
1190 np->rx_ring[i].rxaddr = cpu_to_dma(np->rx_info[i].mapping | RxDescValid);
1192 writew(i - 1, np->base + RxDescQIdx);
1193 np->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1195 /* Clear the remainder of the Rx buffer ring. */
1196 for ( ; i < RX_RING_SIZE; i++) {
1197 np->rx_ring[i].rxaddr = 0;
1198 np->rx_info[i].skb = NULL;
1199 np->rx_info[i].mapping = 0;
1201 /* Mark the last entry as wrapping the ring. */
1202 np->rx_ring[RX_RING_SIZE - 1].rxaddr |= cpu_to_dma(RxDescEndRing);
1204 /* Clear the completion rings. */
1205 for (i = 0; i < DONE_Q_SIZE; i++) {
1206 np->rx_done_q[i].status = 0;
1207 np->tx_done_q[i].status = 0;
1210 for (i = 0; i < TX_RING_SIZE; i++)
1211 memset(&np->tx_info[i], 0, sizeof(np->tx_info[i]));
1217 static int start_tx(struct sk_buff *skb, struct net_device *dev)
1219 struct netdev_private *np = netdev_priv(dev);
1225 * be cautious here, wrapping the queue has weird semantics
1226 * and we may not have enough slots even when it seems we do.
1228 if ((np->cur_tx - np->dirty_tx) + skb_num_frags(skb) * 2 > TX_RING_SIZE) {
1229 netif_stop_queue(dev);
1233 #if defined(ZEROCOPY) && defined(HAS_BROKEN_FIRMWARE)
1234 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1235 if (skb_padto(skb, (skb->len + PADDING_MASK) & ~PADDING_MASK))
1236 return NETDEV_TX_OK;
1238 #endif /* ZEROCOPY && HAS_BROKEN_FIRMWARE */
1240 entry = np->cur_tx % TX_RING_SIZE;
1241 for (i = 0; i < skb_num_frags(skb); i++) {
1246 np->tx_info[entry].skb = skb;
1248 if (entry >= TX_RING_SIZE - skb_num_frags(skb)) {
1249 status |= TxRingWrap;
1253 status |= TxDescIntr;
1256 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1258 np->stats.tx_compressed++;
1260 status |= skb_first_frag_len(skb) | (skb_num_frags(skb) << 16);
1262 np->tx_info[entry].mapping =
1263 pci_map_single(np->pci_dev, skb->data, skb_first_frag_len(skb), PCI_DMA_TODEVICE);
1265 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[i - 1];
1266 status |= this_frag->size;
1267 np->tx_info[entry].mapping =
1268 pci_map_single(np->pci_dev, page_address(this_frag->page) + this_frag->page_offset, this_frag->size, PCI_DMA_TODEVICE);
1271 np->tx_ring[entry].addr = cpu_to_dma(np->tx_info[entry].mapping);
1272 np->tx_ring[entry].status = cpu_to_le32(status);
1274 printk(KERN_DEBUG "%s: Tx #%d/#%d slot %d status %#8.8x.\n",
1275 dev->name, np->cur_tx, np->dirty_tx,
1278 np->tx_info[entry].used_slots = TX_RING_SIZE - entry;
1279 np->cur_tx += np->tx_info[entry].used_slots;
1282 np->tx_info[entry].used_slots = 1;
1283 np->cur_tx += np->tx_info[entry].used_slots;
1286 /* scavenge the tx descriptors twice per TX_RING_SIZE */
1287 if (np->cur_tx % (TX_RING_SIZE / 2) == 0)
1291 /* Non-x86: explicitly flush descriptor cache lines here. */
1292 /* Ensure all descriptors are written back before the transmit is
1296 /* Update the producer index. */
1297 writel(entry * (sizeof(starfire_tx_desc) / 8), np->base + TxProducerIdx);
1299 /* 4 is arbitrary, but should be ok */
1300 if ((np->cur_tx - np->dirty_tx) + 4 > TX_RING_SIZE)
1301 netif_stop_queue(dev);
1303 dev->trans_start = jiffies;
1309 /* The interrupt handler does all of the Rx thread work and cleans up
1310 after the Tx thread. */
1311 static irqreturn_t intr_handler(int irq, void *dev_instance)
1313 struct net_device *dev = dev_instance;
1314 struct netdev_private *np = netdev_priv(dev);
1315 void __iomem *ioaddr = np->base;
1316 int boguscnt = max_interrupt_work;
1322 u32 intr_status = readl(ioaddr + IntrClear);
1325 printk(KERN_DEBUG "%s: Interrupt status %#8.8x.\n",
1326 dev->name, intr_status);
1328 if (intr_status == 0 || intr_status == (u32) -1)
1333 if (intr_status & (IntrRxDone | IntrRxEmpty))
1334 netdev_rx(dev, np, ioaddr);
1336 /* Scavenge the skbuff list based on the Tx-done queue.
1337 There are redundant checks here that may be cleaned up
1338 after the driver has proven to be reliable. */
1339 consumer = readl(ioaddr + TxConsumerIdx);
1341 printk(KERN_DEBUG "%s: Tx Consumer index is %d.\n",
1342 dev->name, consumer);
1344 while ((tx_status = le32_to_cpu(np->tx_done_q[np->tx_done].status)) != 0) {
1346 printk(KERN_DEBUG "%s: Tx completion #%d entry %d is %#8.8x.\n",
1347 dev->name, np->dirty_tx, np->tx_done, tx_status);
1348 if ((tx_status & 0xe0000000) == 0xa0000000) {
1349 np->stats.tx_packets++;
1350 } else if ((tx_status & 0xe0000000) == 0x80000000) {
1351 u16 entry = (tx_status & 0x7fff) / sizeof(starfire_tx_desc);
1352 struct sk_buff *skb = np->tx_info[entry].skb;
1353 np->tx_info[entry].skb = NULL;
1354 pci_unmap_single(np->pci_dev,
1355 np->tx_info[entry].mapping,
1356 skb_first_frag_len(skb),
1358 np->tx_info[entry].mapping = 0;
1359 np->dirty_tx += np->tx_info[entry].used_slots;
1360 entry = (entry + np->tx_info[entry].used_slots) % TX_RING_SIZE;
1363 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1364 pci_unmap_single(np->pci_dev,
1365 np->tx_info[entry].mapping,
1366 skb_shinfo(skb)->frags[i].size,
1373 dev_kfree_skb_irq(skb);
1375 np->tx_done_q[np->tx_done].status = 0;
1376 np->tx_done = (np->tx_done + 1) % DONE_Q_SIZE;
1378 writew(np->tx_done, ioaddr + CompletionQConsumerIdx + 2);
1380 if (netif_queue_stopped(dev) &&
1381 (np->cur_tx - np->dirty_tx + 4 < TX_RING_SIZE)) {
1382 /* The ring is no longer full, wake the queue. */
1383 netif_wake_queue(dev);
1386 /* Stats overflow */
1387 if (intr_status & IntrStatsMax)
1390 /* Media change interrupt. */
1391 if (intr_status & IntrLinkChange)
1392 netdev_media_change(dev);
1394 /* Abnormal error summary/uncommon events handlers. */
1395 if (intr_status & IntrAbnormalSummary)
1396 netdev_error(dev, intr_status);
1398 if (--boguscnt < 0) {
1400 printk(KERN_WARNING "%s: Too much work at interrupt, "
1402 dev->name, intr_status);
1408 printk(KERN_DEBUG "%s: exiting interrupt, status=%#8.8x.\n",
1409 dev->name, (int) readl(ioaddr + IntrStatus));
1410 return IRQ_RETVAL(handled);
1414 /* This routine is logically part of the interrupt/poll handler, but separated
1415 for clarity, code sharing between NAPI/non-NAPI, and better register allocation. */
1416 static int __netdev_rx(struct net_device *dev, int *quota)
1418 struct netdev_private *np = netdev_priv(dev);
1422 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1423 while ((desc_status = le32_to_cpu(np->rx_done_q[np->rx_done].status)) != 0) {
1424 struct sk_buff *skb;
1427 rx_done_desc *desc = &np->rx_done_q[np->rx_done];
1430 printk(KERN_DEBUG " netdev_rx() status of %d was %#8.8x.\n", np->rx_done, desc_status);
1431 if (!(desc_status & RxOK)) {
1432 /* There was an error. */
1434 printk(KERN_DEBUG " netdev_rx() Rx error was %#8.8x.\n", desc_status);
1435 np->stats.rx_errors++;
1436 if (desc_status & RxFIFOErr)
1437 np->stats.rx_fifo_errors++;
1441 if (*quota <= 0) { /* out of rx quota */
1447 pkt_len = desc_status; /* Implicitly Truncate */
1448 entry = (desc_status >> 16) & 0x7ff;
1451 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d, quota %d.\n", pkt_len, *quota);
1452 /* Check if the packet is long enough to accept without copying
1453 to a minimally-sized skbuff. */
1454 if (pkt_len < rx_copybreak
1455 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1456 skb_reserve(skb, 2); /* 16 byte align the IP header */
1457 pci_dma_sync_single_for_cpu(np->pci_dev,
1458 np->rx_info[entry].mapping,
1459 pkt_len, PCI_DMA_FROMDEVICE);
1460 skb_copy_to_linear_data(skb, np->rx_info[entry].skb->data, pkt_len);
1461 pci_dma_sync_single_for_device(np->pci_dev,
1462 np->rx_info[entry].mapping,
1463 pkt_len, PCI_DMA_FROMDEVICE);
1464 skb_put(skb, pkt_len);
1466 pci_unmap_single(np->pci_dev, np->rx_info[entry].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1467 skb = np->rx_info[entry].skb;
1468 skb_put(skb, pkt_len);
1469 np->rx_info[entry].skb = NULL;
1470 np->rx_info[entry].mapping = 0;
1472 #ifndef final_version /* Remove after testing. */
1473 /* You will want this info for the initial debug. */
1475 DECLARE_MAC_BUF(mac);
1476 DECLARE_MAC_BUF(mac2);
1478 printk(KERN_DEBUG " Rx data %s %s"
1480 print_mac(mac, &skb->data[0]),
1481 print_mac(mac2, &skb->data[6]),
1482 skb->data[12], skb->data[13]);
1486 skb->protocol = eth_type_trans(skb, dev);
1489 printk(KERN_DEBUG " netdev_rx() status2 of %d was %#4.4x.\n", np->rx_done, le16_to_cpu(desc->status2));
1491 if (le16_to_cpu(desc->status2) & 0x0100) {
1492 skb->ip_summed = CHECKSUM_UNNECESSARY;
1493 np->stats.rx_compressed++;
1496 * This feature doesn't seem to be working, at least
1497 * with the two firmware versions I have. If the GFP sees
1498 * an IP fragment, it either ignores it completely, or reports
1499 * "bad checksum" on it.
1501 * Maybe I missed something -- corrections are welcome.
1502 * Until then, the printk stays. :-) -Ion
1504 else if (le16_to_cpu(desc->status2) & 0x0040) {
1505 skb->ip_summed = CHECKSUM_COMPLETE;
1506 skb->csum = le16_to_cpu(desc->csum);
1507 printk(KERN_DEBUG "%s: checksum_hw, status2 = %#x\n", dev->name, le16_to_cpu(desc->status2));
1510 if (np->vlgrp && le16_to_cpu(desc->status2) & 0x0200) {
1512 printk(KERN_DEBUG " netdev_rx() vlanid = %d\n", le16_to_cpu(desc->vlanid));
1513 /* vlan_netdev_receive_skb() expects a packet with the VLAN tag stripped out */
1514 vlan_netdev_receive_skb(skb, np->vlgrp, le16_to_cpu(desc->vlanid) & VLAN_VID_MASK);
1516 #endif /* VLAN_SUPPORT */
1517 netdev_receive_skb(skb);
1518 dev->last_rx = jiffies;
1519 np->stats.rx_packets++;
1524 np->rx_done = (np->rx_done + 1) % DONE_Q_SIZE;
1526 writew(np->rx_done, np->base + CompletionQConsumerIdx);
1529 refill_rx_ring(dev);
1531 printk(KERN_DEBUG " exiting netdev_rx(): %d, status of %d was %#8.8x.\n",
1532 retcode, np->rx_done, desc_status);
1537 #ifdef HAVE_NETDEV_POLL
1538 static int netdev_poll(struct napi_struct *napi, int budget)
1540 struct netdev_private *np = container_of(napi, struct netdev_private, napi);
1541 struct net_device *dev = np->dev;
1543 void __iomem *ioaddr = np->base;
1547 writel(IntrRxDone | IntrRxEmpty, ioaddr + IntrClear);
1549 if (__netdev_rx(dev, "a))
1552 intr_status = readl(ioaddr + IntrStatus);
1553 } while (intr_status & (IntrRxDone | IntrRxEmpty));
1555 netif_rx_complete(dev, napi);
1556 intr_status = readl(ioaddr + IntrEnable);
1557 intr_status |= IntrRxDone | IntrRxEmpty;
1558 writel(intr_status, ioaddr + IntrEnable);
1562 printk(KERN_DEBUG " exiting netdev_poll(): %d.\n",
1565 /* Restart Rx engine if stopped. */
1566 return budget - quota;
1568 #endif /* HAVE_NETDEV_POLL */
1571 static void refill_rx_ring(struct net_device *dev)
1573 struct netdev_private *np = netdev_priv(dev);
1574 struct sk_buff *skb;
1577 /* Refill the Rx ring buffers. */
1578 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1579 entry = np->dirty_rx % RX_RING_SIZE;
1580 if (np->rx_info[entry].skb == NULL) {
1581 skb = dev_alloc_skb(np->rx_buf_sz);
1582 np->rx_info[entry].skb = skb;
1584 break; /* Better luck next round. */
1585 np->rx_info[entry].mapping =
1586 pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1587 skb->dev = dev; /* Mark as being used by this device. */
1588 np->rx_ring[entry].rxaddr =
1589 cpu_to_dma(np->rx_info[entry].mapping | RxDescValid);
1591 if (entry == RX_RING_SIZE - 1)
1592 np->rx_ring[entry].rxaddr |= cpu_to_dma(RxDescEndRing);
1595 writew(entry, np->base + RxDescQIdx);
1599 static void netdev_media_change(struct net_device *dev)
1601 struct netdev_private *np = netdev_priv(dev);
1602 void __iomem *ioaddr = np->base;
1603 u16 reg0, reg1, reg4, reg5;
1605 u32 new_intr_timer_ctrl;
1607 /* reset status first */
1608 mdio_read(dev, np->phys[0], MII_BMCR);
1609 mdio_read(dev, np->phys[0], MII_BMSR);
1611 reg0 = mdio_read(dev, np->phys[0], MII_BMCR);
1612 reg1 = mdio_read(dev, np->phys[0], MII_BMSR);
1614 if (reg1 & BMSR_LSTATUS) {
1616 if (reg0 & BMCR_ANENABLE) {
1617 /* autonegotiation is enabled */
1618 reg4 = mdio_read(dev, np->phys[0], MII_ADVERTISE);
1619 reg5 = mdio_read(dev, np->phys[0], MII_LPA);
1620 if (reg4 & ADVERTISE_100FULL && reg5 & LPA_100FULL) {
1622 np->mii_if.full_duplex = 1;
1623 } else if (reg4 & ADVERTISE_100HALF && reg5 & LPA_100HALF) {
1625 np->mii_if.full_duplex = 0;
1626 } else if (reg4 & ADVERTISE_10FULL && reg5 & LPA_10FULL) {
1628 np->mii_if.full_duplex = 1;
1631 np->mii_if.full_duplex = 0;
1634 /* autonegotiation is disabled */
1635 if (reg0 & BMCR_SPEED100)
1639 if (reg0 & BMCR_FULLDPLX)
1640 np->mii_if.full_duplex = 1;
1642 np->mii_if.full_duplex = 0;
1644 netif_carrier_on(dev);
1645 printk(KERN_DEBUG "%s: Link is up, running at %sMbit %s-duplex\n",
1647 np->speed100 ? "100" : "10",
1648 np->mii_if.full_duplex ? "full" : "half");
1650 new_tx_mode = np->tx_mode & ~FullDuplex; /* duplex setting */
1651 if (np->mii_if.full_duplex)
1652 new_tx_mode |= FullDuplex;
1653 if (np->tx_mode != new_tx_mode) {
1654 np->tx_mode = new_tx_mode;
1655 writel(np->tx_mode | MiiSoftReset, ioaddr + TxMode);
1657 writel(np->tx_mode, ioaddr + TxMode);
1660 new_intr_timer_ctrl = np->intr_timer_ctrl & ~Timer10X;
1662 new_intr_timer_ctrl |= Timer10X;
1663 if (np->intr_timer_ctrl != new_intr_timer_ctrl) {
1664 np->intr_timer_ctrl = new_intr_timer_ctrl;
1665 writel(new_intr_timer_ctrl, ioaddr + IntrTimerCtrl);
1668 netif_carrier_off(dev);
1669 printk(KERN_DEBUG "%s: Link is down\n", dev->name);
1674 static void netdev_error(struct net_device *dev, int intr_status)
1676 struct netdev_private *np = netdev_priv(dev);
1678 /* Came close to underrunning the Tx FIFO, increase threshold. */
1679 if (intr_status & IntrTxDataLow) {
1680 if (np->tx_threshold <= PKT_BUF_SZ / 16) {
1681 writel(++np->tx_threshold, np->base + TxThreshold);
1682 printk(KERN_NOTICE "%s: PCI bus congestion, increasing Tx FIFO threshold to %d bytes\n",
1683 dev->name, np->tx_threshold * 16);
1685 printk(KERN_WARNING "%s: PCI Tx underflow -- adapter is probably malfunctioning\n", dev->name);
1687 if (intr_status & IntrRxGFPDead) {
1688 np->stats.rx_fifo_errors++;
1689 np->stats.rx_errors++;
1691 if (intr_status & (IntrNoTxCsum | IntrDMAErr)) {
1692 np->stats.tx_fifo_errors++;
1693 np->stats.tx_errors++;
1695 if ((intr_status & ~(IntrNormalMask | IntrAbnormalSummary | IntrLinkChange | IntrStatsMax | IntrTxDataLow | IntrRxGFPDead | IntrNoTxCsum | IntrPCIPad)) && debug)
1696 printk(KERN_ERR "%s: Something Wicked happened! %#8.8x.\n",
1697 dev->name, intr_status);
1701 static struct net_device_stats *get_stats(struct net_device *dev)
1703 struct netdev_private *np = netdev_priv(dev);
1704 void __iomem *ioaddr = np->base;
1706 /* This adapter architecture needs no SMP locks. */
1707 np->stats.tx_bytes = readl(ioaddr + 0x57010);
1708 np->stats.rx_bytes = readl(ioaddr + 0x57044);
1709 np->stats.tx_packets = readl(ioaddr + 0x57000);
1710 np->stats.tx_aborted_errors =
1711 readl(ioaddr + 0x57024) + readl(ioaddr + 0x57028);
1712 np->stats.tx_window_errors = readl(ioaddr + 0x57018);
1713 np->stats.collisions =
1714 readl(ioaddr + 0x57004) + readl(ioaddr + 0x57008);
1716 /* The chip only need report frame silently dropped. */
1717 np->stats.rx_dropped += readw(ioaddr + RxDMAStatus);
1718 writew(0, ioaddr + RxDMAStatus);
1719 np->stats.rx_crc_errors = readl(ioaddr + 0x5703C);
1720 np->stats.rx_frame_errors = readl(ioaddr + 0x57040);
1721 np->stats.rx_length_errors = readl(ioaddr + 0x57058);
1722 np->stats.rx_missed_errors = readl(ioaddr + 0x5707C);
1728 static void set_rx_mode(struct net_device *dev)
1730 struct netdev_private *np = netdev_priv(dev);
1731 void __iomem *ioaddr = np->base;
1732 u32 rx_mode = MinVLANPrio;
1733 struct dev_mc_list *mclist;
1737 rx_mode |= VlanMode;
1740 void __iomem *filter_addr = ioaddr + HashTable + 8;
1741 for (i = 0; i < VLAN_VID_MASK; i++) {
1742 if (vlan_group_get_device(np->vlgrp, i)) {
1743 if (vlan_count >= 32)
1745 writew(i, filter_addr);
1750 if (i == VLAN_VID_MASK) {
1751 rx_mode |= PerfectFilterVlan;
1752 while (vlan_count < 32) {
1753 writew(0, filter_addr);
1759 #endif /* VLAN_SUPPORT */
1761 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1762 rx_mode |= AcceptAll;
1763 } else if ((dev->mc_count > multicast_filter_limit)
1764 || (dev->flags & IFF_ALLMULTI)) {
1765 /* Too many to match, or accept all multicasts. */
1766 rx_mode |= AcceptBroadcast|AcceptAllMulticast|PerfectFilter;
1767 } else if (dev->mc_count <= 14) {
1768 /* Use the 16 element perfect filter, skip first two entries. */
1769 void __iomem *filter_addr = ioaddr + PerfFilterTable + 2 * 16;
1771 for (i = 2, mclist = dev->mc_list; mclist && i < dev->mc_count + 2;
1772 i++, mclist = mclist->next) {
1773 eaddrs = (__be16 *)mclist->dmi_addr;
1774 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 4;
1775 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1776 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 8;
1778 eaddrs = (__be16 *)dev->dev_addr;
1780 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 4;
1781 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1782 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 8;
1784 rx_mode |= AcceptBroadcast|PerfectFilter;
1786 /* Must use a multicast hash table. */
1787 void __iomem *filter_addr;
1789 __le16 mc_filter[32] __attribute__ ((aligned(sizeof(long)))); /* Multicast hash filter */
1791 memset(mc_filter, 0, sizeof(mc_filter));
1792 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1793 i++, mclist = mclist->next) {
1794 /* The chip uses the upper 9 CRC bits
1795 as index into the hash table */
1796 int bit_nr = ether_crc_le(ETH_ALEN, mclist->dmi_addr) >> 23;
1797 __le32 *fptr = (__le32 *) &mc_filter[(bit_nr >> 4) & ~1];
1799 *fptr |= cpu_to_le32(1 << (bit_nr & 31));
1801 /* Clear the perfect filter list, skip first two entries. */
1802 filter_addr = ioaddr + PerfFilterTable + 2 * 16;
1803 eaddrs = (__be16 *)dev->dev_addr;
1804 for (i = 2; i < 16; i++) {
1805 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 4;
1806 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1807 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 8;
1809 for (filter_addr = ioaddr + HashTable, i = 0; i < 32; filter_addr+= 16, i++)
1810 writew(mc_filter[i], filter_addr);
1811 rx_mode |= AcceptBroadcast|PerfectFilter|HashFilter;
1813 writel(rx_mode, ioaddr + RxFilterMode);
1816 static int check_if_running(struct net_device *dev)
1818 if (!netif_running(dev))
1823 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1825 struct netdev_private *np = netdev_priv(dev);
1826 strcpy(info->driver, DRV_NAME);
1827 strcpy(info->version, DRV_VERSION);
1828 strcpy(info->bus_info, pci_name(np->pci_dev));
1831 static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1833 struct netdev_private *np = netdev_priv(dev);
1834 spin_lock_irq(&np->lock);
1835 mii_ethtool_gset(&np->mii_if, ecmd);
1836 spin_unlock_irq(&np->lock);
1840 static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1842 struct netdev_private *np = netdev_priv(dev);
1844 spin_lock_irq(&np->lock);
1845 res = mii_ethtool_sset(&np->mii_if, ecmd);
1846 spin_unlock_irq(&np->lock);
1851 static int nway_reset(struct net_device *dev)
1853 struct netdev_private *np = netdev_priv(dev);
1854 return mii_nway_restart(&np->mii_if);
1857 static u32 get_link(struct net_device *dev)
1859 struct netdev_private *np = netdev_priv(dev);
1860 return mii_link_ok(&np->mii_if);
1863 static u32 get_msglevel(struct net_device *dev)
1868 static void set_msglevel(struct net_device *dev, u32 val)
1873 static const struct ethtool_ops ethtool_ops = {
1874 .begin = check_if_running,
1875 .get_drvinfo = get_drvinfo,
1876 .get_settings = get_settings,
1877 .set_settings = set_settings,
1878 .nway_reset = nway_reset,
1879 .get_link = get_link,
1880 .get_msglevel = get_msglevel,
1881 .set_msglevel = set_msglevel,
1884 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1886 struct netdev_private *np = netdev_priv(dev);
1887 struct mii_ioctl_data *data = if_mii(rq);
1890 if (!netif_running(dev))
1893 spin_lock_irq(&np->lock);
1894 rc = generic_mii_ioctl(&np->mii_if, data, cmd, NULL);
1895 spin_unlock_irq(&np->lock);
1897 if ((cmd == SIOCSMIIREG) && (data->phy_id == np->phys[0]))
1903 static int netdev_close(struct net_device *dev)
1905 struct netdev_private *np = netdev_priv(dev);
1906 void __iomem *ioaddr = np->base;
1909 netif_stop_queue(dev);
1910 #ifdef HAVE_NETDEV_POLL
1911 napi_disable(&np->napi);
1915 printk(KERN_DEBUG "%s: Shutting down ethercard, Intr status %#8.8x.\n",
1916 dev->name, (int) readl(ioaddr + IntrStatus));
1917 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1918 dev->name, np->cur_tx, np->dirty_tx,
1919 np->cur_rx, np->dirty_rx);
1922 /* Disable interrupts by clearing the interrupt mask. */
1923 writel(0, ioaddr + IntrEnable);
1925 /* Stop the chip's Tx and Rx processes. */
1926 writel(0, ioaddr + GenCtrl);
1927 readl(ioaddr + GenCtrl);
1930 printk(KERN_DEBUG" Tx ring at %#llx:\n",
1931 (long long) np->tx_ring_dma);
1932 for (i = 0; i < 8 /* TX_RING_SIZE is huge! */; i++)
1933 printk(KERN_DEBUG " #%d desc. %#8.8x %#llx -> %#8.8x.\n",
1934 i, le32_to_cpu(np->tx_ring[i].status),
1935 (long long) dma_to_cpu(np->tx_ring[i].addr),
1936 le32_to_cpu(np->tx_done_q[i].status));
1937 printk(KERN_DEBUG " Rx ring at %#llx -> %p:\n",
1938 (long long) np->rx_ring_dma, np->rx_done_q);
1940 for (i = 0; i < 8 /* RX_RING_SIZE */; i++) {
1941 printk(KERN_DEBUG " #%d desc. %#llx -> %#8.8x\n",
1942 i, (long long) dma_to_cpu(np->rx_ring[i].rxaddr), le32_to_cpu(np->rx_done_q[i].status));
1946 free_irq(dev->irq, dev);
1948 /* Free all the skbuffs in the Rx queue. */
1949 for (i = 0; i < RX_RING_SIZE; i++) {
1950 np->rx_ring[i].rxaddr = cpu_to_dma(0xBADF00D0); /* An invalid address. */
1951 if (np->rx_info[i].skb != NULL) {
1952 pci_unmap_single(np->pci_dev, np->rx_info[i].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1953 dev_kfree_skb(np->rx_info[i].skb);
1955 np->rx_info[i].skb = NULL;
1956 np->rx_info[i].mapping = 0;
1958 for (i = 0; i < TX_RING_SIZE; i++) {
1959 struct sk_buff *skb = np->tx_info[i].skb;
1962 pci_unmap_single(np->pci_dev,
1963 np->tx_info[i].mapping,
1964 skb_first_frag_len(skb), PCI_DMA_TODEVICE);
1965 np->tx_info[i].mapping = 0;
1967 np->tx_info[i].skb = NULL;
1974 static int starfire_suspend(struct pci_dev *pdev, pm_message_t state)
1976 struct net_device *dev = pci_get_drvdata(pdev);
1978 if (netif_running(dev)) {
1979 netif_device_detach(dev);
1983 pci_save_state(pdev);
1984 pci_set_power_state(pdev, pci_choose_state(pdev,state));
1989 static int starfire_resume(struct pci_dev *pdev)
1991 struct net_device *dev = pci_get_drvdata(pdev);
1993 pci_set_power_state(pdev, PCI_D0);
1994 pci_restore_state(pdev);
1996 if (netif_running(dev)) {
1998 netif_device_attach(dev);
2003 #endif /* CONFIG_PM */
2006 static void __devexit starfire_remove_one (struct pci_dev *pdev)
2008 struct net_device *dev = pci_get_drvdata(pdev);
2009 struct netdev_private *np = netdev_priv(dev);
2013 unregister_netdev(dev);
2016 pci_free_consistent(pdev, np->queue_mem_size, np->queue_mem, np->queue_mem_dma);
2019 /* XXX: add wakeup code -- requires firmware for MagicPacket */
2020 pci_set_power_state(pdev, PCI_D3hot); /* go to sleep in D3 mode */
2021 pci_disable_device(pdev);
2024 pci_release_regions(pdev);
2026 pci_set_drvdata(pdev, NULL);
2027 free_netdev(dev); /* Will also free np!! */
2031 static struct pci_driver starfire_driver = {
2033 .probe = starfire_init_one,
2034 .remove = __devexit_p(starfire_remove_one),
2036 .suspend = starfire_suspend,
2037 .resume = starfire_resume,
2038 #endif /* CONFIG_PM */
2039 .id_table = starfire_pci_tbl,
2043 static int __init starfire_init (void)
2045 /* when a module, this is printed whether or not devices are found in probe */
2048 #ifdef HAVE_NETDEV_POLL
2049 printk(KERN_INFO DRV_NAME ": polling (NAPI) enabled\n");
2051 printk(KERN_INFO DRV_NAME ": polling (NAPI) disabled\n");
2055 /* we can do this test only at run-time... sigh */
2056 if (sizeof(dma_addr_t) != sizeof(netdrv_addr_t)) {
2057 printk("This driver has dma_addr_t issues, please send email to maintainer\n");
2061 return pci_register_driver(&starfire_driver);
2065 static void __exit starfire_cleanup (void)
2067 pci_unregister_driver (&starfire_driver);
2071 module_init(starfire_init);
2072 module_exit(starfire_cleanup);