2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/cpu.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmi.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
37 #include <asm/arch_hooks.h>
39 #include <asm/i8253.h>
42 #include <mach_apic.h>
43 #include <mach_apicdef.h>
49 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
50 # error SPURIOUS_APIC_VECTOR definition error
53 unsigned long mp_lapic_addr;
55 DEFINE_PER_CPU(u16, x86_bios_cpu_apicid) = BAD_APICID;
56 EXPORT_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
59 * Knob to control our willingness to enable the local APIC.
61 * -1=force-disable, +1=force-enable
63 static int enable_local_apic __initdata;
65 /* Local APIC timer verification ok */
66 static int local_apic_timer_verify_ok;
67 /* Disable local APIC timer from the kernel commandline or via dmi quirk
68 or using CPU MSR check */
69 int local_apic_timer_disabled;
70 /* Local APIC timer works in C2 */
71 int local_apic_timer_c2_ok;
72 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
75 * Debug level, exported for io_apic.c
79 static unsigned int calibration_result;
81 static int lapic_next_event(unsigned long delta,
82 struct clock_event_device *evt);
83 static void lapic_timer_setup(enum clock_event_mode mode,
84 struct clock_event_device *evt);
85 static void lapic_timer_broadcast(cpumask_t mask);
86 static void apic_pm_activate(void);
89 * The local apic timer can be used for any function which is CPU local.
91 static struct clock_event_device lapic_clockevent = {
93 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
94 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
96 .set_mode = lapic_timer_setup,
97 .set_next_event = lapic_next_event,
98 .broadcast = lapic_timer_broadcast,
102 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
104 /* Local APIC was disabled by the BIOS and enabled by the kernel */
105 static int enabled_via_apicbase;
107 static unsigned long apic_phys;
110 * Get the LAPIC version
112 static inline int lapic_get_version(void)
114 return GET_APIC_VERSION(apic_read(APIC_LVR));
118 * Check, if the APIC is integrated or a separate chip
120 static inline int lapic_is_integrated(void)
122 return APIC_INTEGRATED(lapic_get_version());
126 * Check, whether this is a modern or a first generation APIC
128 static int modern_apic(void)
130 /* AMD systems use old APIC versions, so check the CPU */
131 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
132 boot_cpu_data.x86 >= 0xf)
134 return lapic_get_version() >= 0x14;
137 void apic_wait_icr_idle(void)
139 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
143 u32 safe_apic_wait_icr_idle(void)
150 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
154 } while (timeout++ < 1000);
160 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
162 void __cpuinit enable_NMI_through_LVT0(void)
164 unsigned int v = APIC_DM_NMI;
166 /* Level triggered for 82489DX */
167 if (!lapic_is_integrated())
168 v |= APIC_LVT_LEVEL_TRIGGER;
169 apic_write_around(APIC_LVT0, v);
173 * get_physical_broadcast - Get number of physical broadcast IDs
175 int get_physical_broadcast(void)
177 return modern_apic() ? 0xff : 0xf;
181 * lapic_get_maxlvt - get the maximum number of local vector table entries
183 int lapic_get_maxlvt(void)
185 unsigned int v = apic_read(APIC_LVR);
187 /* 82489DXs do not report # of LVT entries. */
188 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
195 /* Clock divisor is set to 16 */
196 #define APIC_DIVISOR 16
199 * This function sets up the local APIC timer, with a timeout of
200 * 'clocks' APIC bus clock. During calibration we actually call
201 * this function twice on the boot CPU, once with a bogus timeout
202 * value, second time for real. The other (noncalibrating) CPUs
203 * call this function only once, with the real, calibrated value.
205 * We do reads before writes even if unnecessary, to get around the
206 * P5 APIC double write bug.
208 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
210 unsigned int lvtt_value, tmp_value;
212 lvtt_value = LOCAL_TIMER_VECTOR;
214 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
215 if (!lapic_is_integrated())
216 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
219 lvtt_value |= APIC_LVT_MASKED;
221 apic_write_around(APIC_LVTT, lvtt_value);
226 tmp_value = apic_read(APIC_TDCR);
227 apic_write_around(APIC_TDCR, (tmp_value
228 & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
232 apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
236 * Program the next event, relative to now
238 static int lapic_next_event(unsigned long delta,
239 struct clock_event_device *evt)
241 apic_write_around(APIC_TMICT, delta);
246 * Setup the lapic timer in periodic or oneshot mode
248 static void lapic_timer_setup(enum clock_event_mode mode,
249 struct clock_event_device *evt)
254 /* Lapic used for broadcast ? */
255 if (!local_apic_timer_verify_ok)
258 local_irq_save(flags);
261 case CLOCK_EVT_MODE_PERIODIC:
262 case CLOCK_EVT_MODE_ONESHOT:
263 __setup_APIC_LVTT(calibration_result,
264 mode != CLOCK_EVT_MODE_PERIODIC, 1);
266 case CLOCK_EVT_MODE_UNUSED:
267 case CLOCK_EVT_MODE_SHUTDOWN:
268 v = apic_read(APIC_LVTT);
269 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
270 apic_write_around(APIC_LVTT, v);
272 case CLOCK_EVT_MODE_RESUME:
273 /* Nothing to do here */
277 local_irq_restore(flags);
281 * Local APIC timer broadcast function
283 static void lapic_timer_broadcast(cpumask_t mask)
286 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
291 * Setup the local APIC timer for this CPU. Copy the initilized values
292 * of the boot CPU and register the clock event in the framework.
294 static void __devinit setup_APIC_timer(void)
296 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
298 memcpy(levt, &lapic_clockevent, sizeof(*levt));
299 levt->cpumask = cpumask_of_cpu(smp_processor_id());
301 clockevents_register_device(levt);
305 * In this functions we calibrate APIC bus clocks to the external timer.
307 * We want to do the calibration only once since we want to have local timer
308 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
311 * This was previously done by reading the PIT/HPET and waiting for a wrap
312 * around to find out, that a tick has elapsed. I have a box, where the PIT
313 * readout is broken, so it never gets out of the wait loop again. This was
314 * also reported by others.
316 * Monitoring the jiffies value is inaccurate and the clockevents
317 * infrastructure allows us to do a simple substitution of the interrupt
320 * The calibration routine also uses the pm_timer when possible, as the PIT
321 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
322 * back to normal later in the boot process).
325 #define LAPIC_CAL_LOOPS (HZ/10)
327 static __initdata int lapic_cal_loops = -1;
328 static __initdata long lapic_cal_t1, lapic_cal_t2;
329 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
330 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
331 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
334 * Temporary interrupt handler.
336 static void __init lapic_cal_handler(struct clock_event_device *dev)
338 unsigned long long tsc = 0;
339 long tapic = apic_read(APIC_TMCCT);
340 unsigned long pm = acpi_pm_read_early();
345 switch (lapic_cal_loops++) {
347 lapic_cal_t1 = tapic;
348 lapic_cal_tsc1 = tsc;
350 lapic_cal_j1 = jiffies;
353 case LAPIC_CAL_LOOPS:
354 lapic_cal_t2 = tapic;
355 lapic_cal_tsc2 = tsc;
356 if (pm < lapic_cal_pm1)
357 pm += ACPI_PM_OVRRUN;
359 lapic_cal_j2 = jiffies;
365 * Setup the boot APIC
367 * Calibrate and verify the result.
369 void __init setup_boot_APIC_clock(void)
371 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
372 const long pm_100ms = PMTMR_TICKS_PER_SEC/10;
373 const long pm_thresh = pm_100ms/100;
374 void (*real_handler)(struct clock_event_device *dev);
375 unsigned long deltaj;
377 int pm_referenced = 0;
380 * The local apic timer can be disabled via the kernel
381 * commandline or from the CPU detection code. Register the lapic
382 * timer as a dummy clock event source on SMP systems, so the
383 * broadcast mechanism is used. On UP systems simply ignore it.
385 if (local_apic_timer_disabled) {
386 /* No broadcast on UP ! */
387 if (num_possible_cpus() > 1) {
388 lapic_clockevent.mult = 1;
394 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
395 "calibrating APIC timer ...\n");
399 /* Replace the global interrupt handler */
400 real_handler = global_clock_event->event_handler;
401 global_clock_event->event_handler = lapic_cal_handler;
404 * Setup the APIC counter to 1e9. There is no way the lapic
405 * can underflow in the 100ms detection time frame
407 __setup_APIC_LVTT(1000000000, 0, 0);
409 /* Let the interrupts run */
412 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
417 /* Restore the real event handler */
418 global_clock_event->event_handler = real_handler;
420 /* Build delta t1-t2 as apic timer counts down */
421 delta = lapic_cal_t1 - lapic_cal_t2;
422 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
424 /* Check, if the PM timer is available */
425 deltapm = lapic_cal_pm2 - lapic_cal_pm1;
426 apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm);
432 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
434 if (deltapm > (pm_100ms - pm_thresh) &&
435 deltapm < (pm_100ms + pm_thresh)) {
436 apic_printk(APIC_VERBOSE, "... PM timer result ok\n");
438 res = (((u64) deltapm) * mult) >> 22;
439 do_div(res, 1000000);
440 printk(KERN_WARNING "APIC calibration not consistent "
441 "with PM Timer: %ldms instead of 100ms\n",
443 /* Correct the lapic counter value */
444 res = (((u64) delta) * pm_100ms);
445 do_div(res, deltapm);
446 printk(KERN_INFO "APIC delta adjusted to PM-Timer: "
447 "%lu (%ld)\n", (unsigned long) res, delta);
453 /* Calculate the scaled math multiplication factor */
454 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
455 lapic_clockevent.shift);
456 lapic_clockevent.max_delta_ns =
457 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
458 lapic_clockevent.min_delta_ns =
459 clockevent_delta2ns(0xF, &lapic_clockevent);
461 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
463 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
464 apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult);
465 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
469 delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
470 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
472 (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ),
473 (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ));
476 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
478 calibration_result / (1000000 / HZ),
479 calibration_result % (1000000 / HZ));
481 local_apic_timer_verify_ok = 1;
484 * Do a sanity check on the APIC calibration result
486 if (calibration_result < (1000000 / HZ)) {
489 "APIC frequency too slow, disabling apic timer\n");
490 /* No broadcast on UP ! */
491 if (num_possible_cpus() > 1)
496 /* We trust the pm timer based calibration */
497 if (!pm_referenced) {
498 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
501 * Setup the apic timer manually
503 levt->event_handler = lapic_cal_handler;
504 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
505 lapic_cal_loops = -1;
507 /* Let the interrupts run */
510 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
515 /* Stop the lapic timer */
516 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
521 deltaj = lapic_cal_j2 - lapic_cal_j1;
522 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
524 /* Check, if the jiffies result is consistent */
525 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
526 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
528 local_apic_timer_verify_ok = 0;
532 if (!local_apic_timer_verify_ok) {
534 "APIC timer disabled due to verification failure.\n");
535 /* No broadcast on UP ! */
536 if (num_possible_cpus() == 1)
540 * If nmi_watchdog is set to IO_APIC, we need the
541 * PIT/HPET going. Otherwise register lapic as a dummy
544 if (nmi_watchdog != NMI_IO_APIC)
545 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
547 printk(KERN_WARNING "APIC timer registered as dummy,"
548 " due to nmi_watchdog=1!\n");
551 /* Setup the lapic or request the broadcast */
555 void __devinit setup_secondary_APIC_clock(void)
561 * The guts of the apic timer interrupt
563 static void local_apic_timer_interrupt(void)
565 int cpu = smp_processor_id();
566 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
569 * Normally we should not be here till LAPIC has been initialized but
570 * in some cases like kdump, its possible that there is a pending LAPIC
571 * timer interrupt from previous kernel's context and is delivered in
572 * new kernel the moment interrupts are enabled.
574 * Interrupts are enabled early and LAPIC is setup much later, hence
575 * its possible that when we get here evt->event_handler is NULL.
576 * Check for event_handler being NULL and discard the interrupt as
579 if (!evt->event_handler) {
581 "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
583 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
588 * the NMI deadlock-detector uses this.
590 per_cpu(irq_stat, cpu).apic_timer_irqs++;
592 evt->event_handler(evt);
596 * Local APIC timer interrupt. This is the most natural way for doing
597 * local interrupts, but local timer interrupts can be emulated by
598 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
600 * [ if a single-CPU system runs an SMP kernel then we call the local
601 * interrupt as well. Thus we cannot inline the local irq ... ]
603 void smp_apic_timer_interrupt(struct pt_regs *regs)
605 struct pt_regs *old_regs = set_irq_regs(regs);
608 * NOTE! We'd better ACK the irq immediately,
609 * because timer handling can be slow.
613 * update_process_times() expects us to have done irq_enter().
614 * Besides, if we don't timer interrupts ignore the global
615 * interrupt lock, which is the WrongThing (tm) to do.
618 local_apic_timer_interrupt();
621 set_irq_regs(old_regs);
624 int setup_profiling_timer(unsigned int multiplier)
630 * Setup extended LVT, AMD specific (K8, family 10h)
632 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
633 * MCE interrupts are supported. Thus MCE offset must be set to 0.
636 #define APIC_EILVT_LVTOFF_MCE 0
637 #define APIC_EILVT_LVTOFF_IBS 1
639 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
641 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
642 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
646 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
648 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
649 return APIC_EILVT_LVTOFF_MCE;
652 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
654 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
655 return APIC_EILVT_LVTOFF_IBS;
659 * Local APIC start and shutdown
663 * clear_local_APIC - shutdown the local APIC
665 * This is called, when a CPU is disabled and before rebooting, so the state of
666 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
667 * leftovers during boot.
669 void clear_local_APIC(void)
674 /* APIC hasn't been mapped yet */
678 maxlvt = lapic_get_maxlvt();
680 * Masking an LVT entry can trigger a local APIC error
681 * if the vector is zero. Mask LVTERR first to prevent this.
684 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
685 apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
688 * Careful: we have to set masks only first to deassert
689 * any level-triggered sources.
691 v = apic_read(APIC_LVTT);
692 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
693 v = apic_read(APIC_LVT0);
694 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
695 v = apic_read(APIC_LVT1);
696 apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
698 v = apic_read(APIC_LVTPC);
699 apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
702 /* lets not touch this if we didn't frob it */
703 #ifdef CONFIG_X86_MCE_P4THERMAL
705 v = apic_read(APIC_LVTTHMR);
706 apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED);
710 * Clean APIC state for other OSs:
712 apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
713 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
714 apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
716 apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
718 apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
720 #ifdef CONFIG_X86_MCE_P4THERMAL
722 apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED);
724 /* Integrated APIC (!82489DX) ? */
725 if (lapic_is_integrated()) {
727 /* Clear ESR due to Pentium errata 3AP and 11AP */
728 apic_write(APIC_ESR, 0);
734 * disable_local_APIC - clear and disable the local APIC
736 void disable_local_APIC(void)
743 * Disable APIC (implies clearing of registers
746 value = apic_read(APIC_SPIV);
747 value &= ~APIC_SPIV_APIC_ENABLED;
748 apic_write_around(APIC_SPIV, value);
751 * When LAPIC was disabled by the BIOS and enabled by the kernel,
752 * restore the disabled state.
754 if (enabled_via_apicbase) {
757 rdmsr(MSR_IA32_APICBASE, l, h);
758 l &= ~MSR_IA32_APICBASE_ENABLE;
759 wrmsr(MSR_IA32_APICBASE, l, h);
764 * If Linux enabled the LAPIC against the BIOS default disable it down before
765 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
766 * not power-off. Additionally clear all LVT entries before disable_local_APIC
767 * for the case where Linux didn't enable the LAPIC.
769 void lapic_shutdown(void)
776 local_irq_save(flags);
779 if (enabled_via_apicbase)
780 disable_local_APIC();
782 local_irq_restore(flags);
786 * This is to verify that we're looking at a real local APIC.
787 * Check these against your board if the CPUs aren't getting
788 * started for no apparent reason.
790 int __init verify_local_APIC(void)
792 unsigned int reg0, reg1;
795 * The version register is read-only in a real APIC.
797 reg0 = apic_read(APIC_LVR);
798 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
799 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
800 reg1 = apic_read(APIC_LVR);
801 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
804 * The two version reads above should print the same
805 * numbers. If the second one is different, then we
806 * poke at a non-APIC.
812 * Check if the version looks reasonably.
814 reg1 = GET_APIC_VERSION(reg0);
815 if (reg1 == 0x00 || reg1 == 0xff)
817 reg1 = lapic_get_maxlvt();
818 if (reg1 < 0x02 || reg1 == 0xff)
822 * The ID register is read/write in a real APIC.
824 reg0 = apic_read(APIC_ID);
825 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
828 * The next two are just to see if we have sane values.
829 * They're only really relevant if we're in Virtual Wire
830 * compatibility mode, but most boxes are anymore.
832 reg0 = apic_read(APIC_LVT0);
833 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
834 reg1 = apic_read(APIC_LVT1);
835 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
841 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
843 void __init sync_Arb_IDs(void)
846 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
849 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
854 apic_wait_icr_idle();
856 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
857 apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
862 * An initial setup of the virtual wire mode.
864 void __init init_bsp_APIC(void)
869 * Don't do the setup now if we have a SMP BIOS as the
870 * through-I/O-APIC virtual wire mode might be active.
872 if (smp_found_config || !cpu_has_apic)
876 * Do not trust the local APIC being empty at bootup.
883 value = apic_read(APIC_SPIV);
884 value &= ~APIC_VECTOR_MASK;
885 value |= APIC_SPIV_APIC_ENABLED;
887 /* This bit is reserved on P4/Xeon and should be cleared */
888 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
889 (boot_cpu_data.x86 == 15))
890 value &= ~APIC_SPIV_FOCUS_DISABLED;
892 value |= APIC_SPIV_FOCUS_DISABLED;
893 value |= SPURIOUS_APIC_VECTOR;
894 apic_write_around(APIC_SPIV, value);
897 * Set up the virtual wire mode.
899 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
901 if (!lapic_is_integrated()) /* 82489DX */
902 value |= APIC_LVT_LEVEL_TRIGGER;
903 apic_write_around(APIC_LVT1, value);
906 static void __cpuinit lapic_setup_esr(void)
908 unsigned long oldvalue, value, maxlvt;
909 if (lapic_is_integrated() && !esr_disable) {
911 maxlvt = lapic_get_maxlvt();
912 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
913 apic_write(APIC_ESR, 0);
914 oldvalue = apic_read(APIC_ESR);
916 /* enables sending errors */
917 value = ERROR_APIC_VECTOR;
918 apic_write_around(APIC_LVTERR, value);
920 * spec says clear errors after enabling vector.
923 apic_write(APIC_ESR, 0);
924 value = apic_read(APIC_ESR);
925 if (value != oldvalue)
926 apic_printk(APIC_VERBOSE, "ESR value before enabling "
927 "vector: 0x%08lx after: 0x%08lx\n",
932 * Something untraceable is creating bad interrupts on
933 * secondary quads ... for the moment, just leave the
934 * ESR disabled - we can't do anything useful with the
935 * errors anyway - mbligh
937 printk(KERN_INFO "Leaving ESR disabled.\n");
939 printk(KERN_INFO "No ESR for 82489DX.\n");
945 * setup_local_APIC - setup the local APIC
947 void __cpuinit setup_local_APIC(void)
949 unsigned long value, integrated;
952 /* Pound the ESR really hard over the head with a big hammer - mbligh */
954 apic_write(APIC_ESR, 0);
955 apic_write(APIC_ESR, 0);
956 apic_write(APIC_ESR, 0);
957 apic_write(APIC_ESR, 0);
960 integrated = lapic_is_integrated();
963 * Double-check whether this APIC is really registered.
965 if (!apic_id_registered())
969 * Intel recommends to set DFR, LDR and TPR before enabling
970 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
971 * document number 292116). So here it goes...
976 * Set Task Priority to 'accept all'. We never change this
979 value = apic_read(APIC_TASKPRI);
980 value &= ~APIC_TPRI_MASK;
981 apic_write_around(APIC_TASKPRI, value);
984 * After a crash, we no longer service the interrupts and a pending
985 * interrupt from previous kernel might still have ISR bit set.
987 * Most probably by now CPU has serviced that pending interrupt and
988 * it might not have done the ack_APIC_irq() because it thought,
989 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
990 * does not clear the ISR bit and cpu thinks it has already serivced
991 * the interrupt. Hence a vector might get locked. It was noticed
992 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
994 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
995 value = apic_read(APIC_ISR + i*0x10);
996 for (j = 31; j >= 0; j--) {
1003 * Now that we are all set up, enable the APIC
1005 value = apic_read(APIC_SPIV);
1006 value &= ~APIC_VECTOR_MASK;
1010 value |= APIC_SPIV_APIC_ENABLED;
1013 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1014 * certain networking cards. If high frequency interrupts are
1015 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1016 * entry is masked/unmasked at a high rate as well then sooner or
1017 * later IOAPIC line gets 'stuck', no more interrupts are received
1018 * from the device. If focus CPU is disabled then the hang goes
1021 * [ This bug can be reproduced easily with a level-triggered
1022 * PCI Ne2000 networking cards and PII/PIII processors, dual
1026 * Actually disabling the focus CPU check just makes the hang less
1027 * frequent as it makes the interrupt distributon model be more
1028 * like LRU than MRU (the short-term load is more even across CPUs).
1029 * See also the comment in end_level_ioapic_irq(). --macro
1032 /* Enable focus processor (bit==0) */
1033 value &= ~APIC_SPIV_FOCUS_DISABLED;
1036 * Set spurious IRQ vector
1038 value |= SPURIOUS_APIC_VECTOR;
1039 apic_write_around(APIC_SPIV, value);
1042 * Set up LVT0, LVT1:
1044 * set up through-local-APIC on the BP's LINT0. This is not
1045 * strictly necessary in pure symmetric-IO mode, but sometimes
1046 * we delegate interrupts to the 8259A.
1049 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1051 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1052 if (!smp_processor_id() && (pic_mode || !value)) {
1053 value = APIC_DM_EXTINT;
1054 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
1055 smp_processor_id());
1057 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1058 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
1059 smp_processor_id());
1061 apic_write_around(APIC_LVT0, value);
1064 * only the BP should see the LINT1 NMI signal, obviously.
1066 if (!smp_processor_id())
1067 value = APIC_DM_NMI;
1069 value = APIC_DM_NMI | APIC_LVT_MASKED;
1070 if (!integrated) /* 82489DX */
1071 value |= APIC_LVT_LEVEL_TRIGGER;
1072 apic_write_around(APIC_LVT1, value);
1075 void __cpuinit end_local_APIC_setup(void)
1077 unsigned long value;
1080 /* Disable the local apic timer */
1081 value = apic_read(APIC_LVTT);
1082 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1083 apic_write_around(APIC_LVTT, value);
1085 setup_apic_nmi_watchdog(NULL);
1090 * Detect and initialize APIC
1092 static int __init detect_init_APIC(void)
1096 /* Disabled by kernel option? */
1097 if (enable_local_apic < 0)
1100 switch (boot_cpu_data.x86_vendor) {
1101 case X86_VENDOR_AMD:
1102 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1103 (boot_cpu_data.x86 == 15))
1106 case X86_VENDOR_INTEL:
1107 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1108 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1115 if (!cpu_has_apic) {
1117 * Over-ride BIOS and try to enable the local APIC only if
1118 * "lapic" specified.
1120 if (enable_local_apic <= 0) {
1121 printk(KERN_INFO "Local APIC disabled by BIOS -- "
1122 "you can enable it with \"lapic\"\n");
1126 * Some BIOSes disable the local APIC in the APIC_BASE
1127 * MSR. This can only be done in software for Intel P6 or later
1128 * and AMD K7 (Model > 1) or later.
1130 rdmsr(MSR_IA32_APICBASE, l, h);
1131 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1133 "Local APIC disabled by BIOS -- reenabling.\n");
1134 l &= ~MSR_IA32_APICBASE_BASE;
1135 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
1136 wrmsr(MSR_IA32_APICBASE, l, h);
1137 enabled_via_apicbase = 1;
1141 * The APIC feature bit should now be enabled
1144 features = cpuid_edx(1);
1145 if (!(features & (1 << X86_FEATURE_APIC))) {
1146 printk(KERN_WARNING "Could not enable APIC!\n");
1149 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1150 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1152 /* The BIOS may have set up the APIC at some other address */
1153 rdmsr(MSR_IA32_APICBASE, l, h);
1154 if (l & MSR_IA32_APICBASE_ENABLE)
1155 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1157 if (nmi_watchdog != NMI_NONE && nmi_watchdog != NMI_DISABLED)
1158 nmi_watchdog = NMI_LOCAL_APIC;
1160 printk(KERN_INFO "Found and enabled local APIC!\n");
1167 printk(KERN_INFO "No local APIC present or hardware disabled\n");
1172 * init_apic_mappings - initialize APIC mappings
1174 void __init init_apic_mappings(void)
1177 * If no local APIC can be found then set up a fake all
1178 * zeroes page to simulate the local APIC and another
1179 * one for the IO-APIC.
1181 if (!smp_found_config && detect_init_APIC()) {
1182 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
1183 apic_phys = __pa(apic_phys);
1185 apic_phys = mp_lapic_addr;
1187 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1188 printk(KERN_DEBUG "mapped APIC to %08lx (%08lx)\n", APIC_BASE,
1192 * Fetch the APIC ID of the BSP in case we have a
1193 * default configuration (or the MP table is broken).
1195 if (boot_cpu_physical_apicid == -1U)
1196 boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id());
1198 #ifdef CONFIG_X86_IO_APIC
1200 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
1203 for (i = 0; i < nr_ioapics; i++) {
1204 if (smp_found_config) {
1205 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
1208 "WARNING: bogus zero IO-APIC "
1209 "address found in MPTABLE, "
1210 "disabling IO/APIC support!\n");
1211 smp_found_config = 0;
1212 skip_ioapic_setup = 1;
1213 goto fake_ioapic_page;
1217 ioapic_phys = (unsigned long)
1218 alloc_bootmem_pages(PAGE_SIZE);
1219 ioapic_phys = __pa(ioapic_phys);
1221 set_fixmap_nocache(idx, ioapic_phys);
1222 printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n",
1223 __fix_to_virt(idx), ioapic_phys);
1231 * This initializes the IO-APIC and APIC hardware if this is
1235 int apic_version[MAX_APICS];
1237 int __init APIC_init_uniprocessor(void)
1239 if (enable_local_apic < 0)
1240 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1242 if (!smp_found_config && !cpu_has_apic)
1246 * Complain if the BIOS pretends there is one.
1248 if (!cpu_has_apic &&
1249 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1250 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1251 boot_cpu_physical_apicid);
1252 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1256 verify_local_APIC();
1261 * Hack: In case of kdump, after a crash, kernel might be booting
1262 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1263 * might be zero if read from MP tables. Get it from LAPIC.
1265 #ifdef CONFIG_CRASH_DUMP
1266 boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id());
1268 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
1272 end_local_APIC_setup();
1273 #ifdef CONFIG_X86_IO_APIC
1274 if (smp_found_config)
1275 if (!skip_ioapic_setup && nr_ioapics)
1284 * Local APIC interrupts
1288 * This interrupt should _never_ happen with our APIC/SMP architecture
1290 void smp_spurious_interrupt(struct pt_regs *regs)
1296 * Check if this really is a spurious interrupt and ACK it
1297 * if it is a vectored one. Just in case...
1298 * Spurious interrupts should not be ACKed.
1300 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1301 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1304 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1305 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, "
1306 "should never happen.\n", smp_processor_id());
1307 __get_cpu_var(irq_stat).irq_spurious_count++;
1312 * This interrupt should never happen with our APIC/SMP architecture
1314 void smp_error_interrupt(struct pt_regs *regs)
1316 unsigned long v, v1;
1319 /* First tickle the hardware, only then report what went on. -- REW */
1320 v = apic_read(APIC_ESR);
1321 apic_write(APIC_ESR, 0);
1322 v1 = apic_read(APIC_ESR);
1324 atomic_inc(&irq_err_count);
1326 /* Here is what the APIC error bits mean:
1329 2: Send accept error
1330 3: Receive accept error
1332 5: Send illegal vector
1333 6: Received illegal vector
1334 7: Illegal register address
1336 printk(KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n",
1337 smp_processor_id(), v , v1);
1342 void __init smp_intr_init(void)
1345 * IRQ0 must be given a fixed assignment and initialized,
1346 * because it's used before the IO-APIC is set up.
1348 set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
1351 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
1352 * IPI, driven by wakeup.
1354 set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
1356 /* IPI for invalidation */
1357 set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
1359 /* IPI for generic function call */
1360 set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
1365 * Initialize APIC interrupts
1367 void __init apic_intr_init(void)
1372 /* self generated IPI for local APIC timer */
1373 set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
1375 /* IPI vectors for APIC spurious and error interrupts */
1376 set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
1377 set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
1379 /* thermal monitor LVT interrupt */
1380 #ifdef CONFIG_X86_MCE_P4THERMAL
1381 set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
1386 * connect_bsp_APIC - attach the APIC to the interrupt system
1388 void __init connect_bsp_APIC(void)
1392 * Do not trust the local APIC being empty at bootup.
1396 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1397 * local APIC to INT and NMI lines.
1399 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1400 "enabling APIC mode.\n");
1408 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1409 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1411 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1414 void disconnect_bsp_APIC(int virt_wire_setup)
1418 * Put the board back into PIC mode (has an effect only on
1419 * certain older boards). Note that APIC interrupts, including
1420 * IPIs, won't work beyond this point! The only exception are
1423 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1424 "entering PIC mode.\n");
1428 /* Go back to Virtual Wire compatibility mode */
1429 unsigned long value;
1431 /* For the spurious interrupt use vector F, and enable it */
1432 value = apic_read(APIC_SPIV);
1433 value &= ~APIC_VECTOR_MASK;
1434 value |= APIC_SPIV_APIC_ENABLED;
1436 apic_write_around(APIC_SPIV, value);
1438 if (!virt_wire_setup) {
1440 * For LVT0 make it edge triggered, active high,
1441 * external and enabled
1443 value = apic_read(APIC_LVT0);
1444 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1445 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1446 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1447 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1448 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1449 apic_write_around(APIC_LVT0, value);
1452 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
1456 * For LVT1 make it edge triggered, active high, nmi and
1459 value = apic_read(APIC_LVT1);
1461 APIC_MODE_MASK | APIC_SEND_PENDING |
1462 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1463 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1464 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1465 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1466 apic_write_around(APIC_LVT1, value);
1470 unsigned int __cpuinitdata maxcpus = NR_CPUS;
1472 void __cpuinit generic_processor_info(int apicid, int version)
1476 physid_mask_t phys_cpu;
1481 if (version == 0x0) {
1482 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
1483 "fixing up to 0x10. (tell your hw vendor)\n",
1487 apic_version[apicid] = version;
1489 phys_cpu = apicid_to_cpu_present(apicid);
1490 physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
1492 if (num_processors >= NR_CPUS) {
1493 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
1494 " Processor ignored.\n", NR_CPUS);
1498 if (num_processors >= maxcpus) {
1499 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
1500 " Processor ignored.\n", maxcpus);
1505 cpus_complement(tmp_map, cpu_present_map);
1506 cpu = first_cpu(tmp_map);
1508 if (apicid == boot_cpu_physical_apicid)
1510 * x86_bios_cpu_apicid is required to have processors listed
1511 * in same order as logical cpu numbers. Hence the first
1512 * entry is BSP, and so on.
1517 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1518 * but we need to work other dependencies like SMP_SUSPEND etc
1519 * before this can be done without some confusion.
1520 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1521 * - Ashok Raj <ashok.raj@intel.com>
1523 if (num_processors > 8) {
1524 switch (boot_cpu_data.x86_vendor) {
1525 case X86_VENDOR_INTEL:
1526 if (!APIC_XAPIC(version)) {
1530 /* If P4 and above fall through */
1531 case X86_VENDOR_AMD:
1536 /* are we being called early in kernel startup? */
1537 if (x86_cpu_to_apicid_early_ptr) {
1538 u16 *cpu_to_apicid = x86_cpu_to_apicid_early_ptr;
1539 u16 *bios_cpu_apicid = x86_bios_cpu_apicid_early_ptr;
1541 cpu_to_apicid[cpu] = apicid;
1542 bios_cpu_apicid[cpu] = apicid;
1544 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1545 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1548 cpu_set(cpu, cpu_possible_map);
1549 cpu_set(cpu, cpu_present_map);
1559 /* r/w apic fields */
1560 unsigned int apic_id;
1561 unsigned int apic_taskpri;
1562 unsigned int apic_ldr;
1563 unsigned int apic_dfr;
1564 unsigned int apic_spiv;
1565 unsigned int apic_lvtt;
1566 unsigned int apic_lvtpc;
1567 unsigned int apic_lvt0;
1568 unsigned int apic_lvt1;
1569 unsigned int apic_lvterr;
1570 unsigned int apic_tmict;
1571 unsigned int apic_tdcr;
1572 unsigned int apic_thmr;
1575 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1577 unsigned long flags;
1580 if (!apic_pm_state.active)
1583 maxlvt = lapic_get_maxlvt();
1585 apic_pm_state.apic_id = apic_read(APIC_ID);
1586 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1587 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1588 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1589 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1590 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1592 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1593 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1594 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1595 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1596 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1597 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1598 #ifdef CONFIG_X86_MCE_P4THERMAL
1600 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1603 local_irq_save(flags);
1604 disable_local_APIC();
1605 local_irq_restore(flags);
1609 static int lapic_resume(struct sys_device *dev)
1612 unsigned long flags;
1615 if (!apic_pm_state.active)
1618 maxlvt = lapic_get_maxlvt();
1620 local_irq_save(flags);
1623 * Make sure the APICBASE points to the right address
1625 * FIXME! This will be wrong if we ever support suspend on
1626 * SMP! We'll need to do this as part of the CPU restore!
1628 rdmsr(MSR_IA32_APICBASE, l, h);
1629 l &= ~MSR_IA32_APICBASE_BASE;
1630 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
1631 wrmsr(MSR_IA32_APICBASE, l, h);
1633 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
1634 apic_write(APIC_ID, apic_pm_state.apic_id);
1635 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
1636 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
1637 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
1638 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
1639 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
1640 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
1641 #ifdef CONFIG_X86_MCE_P4THERMAL
1643 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
1646 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
1647 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
1648 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
1649 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
1650 apic_write(APIC_ESR, 0);
1651 apic_read(APIC_ESR);
1652 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
1653 apic_write(APIC_ESR, 0);
1654 apic_read(APIC_ESR);
1655 local_irq_restore(flags);
1660 * This device has no shutdown method - fully functioning local APICs
1661 * are needed on every CPU up until machine_halt/restart/poweroff.
1664 static struct sysdev_class lapic_sysclass = {
1666 .resume = lapic_resume,
1667 .suspend = lapic_suspend,
1670 static struct sys_device device_lapic = {
1672 .cls = &lapic_sysclass,
1675 static void __devinit apic_pm_activate(void)
1677 apic_pm_state.active = 1;
1680 static int __init init_lapic_sysfs(void)
1686 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1688 error = sysdev_class_register(&lapic_sysclass);
1690 error = sysdev_register(&device_lapic);
1693 device_initcall(init_lapic_sysfs);
1695 #else /* CONFIG_PM */
1697 static void apic_pm_activate(void) { }
1699 #endif /* CONFIG_PM */
1702 * APIC command line parameters
1704 static int __init parse_lapic(char *arg)
1706 enable_local_apic = 1;
1709 early_param("lapic", parse_lapic);
1711 static int __init parse_nolapic(char *arg)
1713 enable_local_apic = -1;
1714 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1717 early_param("nolapic", parse_nolapic);
1719 static int __init parse_disable_lapic_timer(char *arg)
1721 local_apic_timer_disabled = 1;
1724 early_param("nolapic_timer", parse_disable_lapic_timer);
1726 static int __init parse_lapic_timer_c2_ok(char *arg)
1728 local_apic_timer_c2_ok = 1;
1731 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
1733 static int __init apic_set_verbosity(char *str)
1735 if (strcmp("debug", str) == 0)
1736 apic_verbosity = APIC_DEBUG;
1737 else if (strcmp("verbose", str) == 0)
1738 apic_verbosity = APIC_VERBOSE;
1741 __setup("apic=", apic_set_verbosity);