git.oblomov.eu Git - linux-2.6/blob - drivers/regulator/wm8350-regulator.c

   1 /*
   2  * wm8350.c  --  Voltage and current regulation for the Wolfson WM8350 PMIC
   3  *
   4  * Copyright 2007, 2008 Wolfson Microelectronics PLC.
   5  *
   6  * Author: Liam Girdwood
   7  *         linux@wolfsonmicro.com
   8  *
   9  *  This program is free software; you can redistribute  it and/or modify it
  10  *  under  the terms of  the GNU General  Public License as published by the
  11  *  Free Software Foundation;  either version 2 of the  License, or (at your
  12  *  option) any later version.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/moduleparam.h>
  17 #include <linux/init.h>
  18 #include <linux/bitops.h>
  19 #include <linux/err.h>
  20 #include <linux/i2c.h>
  21 #include <linux/mfd/wm8350/core.h>
  22 #include <linux/mfd/wm8350/pmic.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/regulator/driver.h>
  25 #include <linux/regulator/machine.h>
  26
  27 /* Microamps */
  28 static const int isink_cur[] = {
  29         4,
  30         5,
  31         6,
  32         7,
  33         8,
  34         10,
  35         11,
  36         14,
  37         16,
  38         19,
  39         23,
  40         27,
  41         32,
  42         39,
  43         46,
  44         54,
  45         65,
  46         77,
  47         92,
  48         109,
  49         130,
  50         154,
  51         183,
  52         218,
  53         259,
  54         308,
  55         367,
  56         436,
  57         518,
  58         616,
  59         733,
  60         872,
  61         1037,
  62         1233,
  63         1466,
  64         1744,
  65         2073,
  66         2466,
  67         2933,
  68         3487,
  69         4147,
  70         4932,
  71         5865,
  72         6975,
  73         8294,
  74         9864,
  75         11730,
  76         13949,
  77         16589,
  78         19728,
  79         23460,
  80         27899,
  81         33178,
  82         39455,
  83         46920,
  84         55798,
  85         66355,
  86         78910,
  87         93840,
  88         111596,
  89         132710,
  90         157820,
  91         187681,
  92         223191
  93 };
  94
  95 static int get_isink_val(int min_uA, int max_uA, u16 *setting)
  96 {
  97         int i;
  98
  99         for (i = ARRAY_SIZE(isink_cur) - 1; i >= 0; i--) {
 100                 if (min_uA <= isink_cur[i] && max_uA >= isink_cur[i]) {
 101                         *setting = i;
 102                         return 0;
 103                 }
 104         }
 105         return -EINVAL;
 106 }
 107
 108 static inline int wm8350_ldo_val_to_mvolts(unsigned int val)
 109 {
 110         if (val < 16)
 111                 return (val * 50) + 900;
 112         else
 113                 return ((val - 16) * 100) + 1800;
 114
 115 }
 116
 117 static inline unsigned int wm8350_ldo_mvolts_to_val(int mV)
 118 {
 119         if (mV < 1800)
 120                 return (mV - 900) / 50;
 121         else
 122                 return ((mV - 1800) / 100) + 16;
 123 }
 124
 125 static inline int wm8350_dcdc_val_to_mvolts(unsigned int val)
 126 {
 127         return (val * 25) + 850;
 128 }
 129
 130 static inline unsigned int wm8350_dcdc_mvolts_to_val(int mV)
 131 {
 132         return (mV - 850) / 25;
 133 }
 134
 135 static int wm8350_isink_set_current(struct regulator_dev *rdev, int min_uA,
 136         int max_uA)
 137 {
 138         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 139         int isink = rdev_get_id(rdev);
 140         u16 val, setting;
 141         int ret;
 142
 143         ret = get_isink_val(min_uA, max_uA, &setting);
 144         if (ret != 0)
 145                 return ret;
 146
 147         switch (isink) {
 148         case WM8350_ISINK_A:
 149                 val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) &
 150                     ~WM8350_CS1_ISEL_MASK;
 151                 wm8350_reg_write(wm8350, WM8350_CURRENT_SINK_DRIVER_A,
 152                                  val | setting);
 153                 break;
 154         case WM8350_ISINK_B:
 155                 val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) &
 156                     ~WM8350_CS1_ISEL_MASK;
 157                 wm8350_reg_write(wm8350, WM8350_CURRENT_SINK_DRIVER_B,
 158                                  val | setting);
 159                 break;
 160         default:
 161                 return -EINVAL;
 162         }
 163
 164         return 0;
 165 }
 166
 167 static int wm8350_isink_get_current(struct regulator_dev *rdev)
 168 {
 169         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 170         int isink = rdev_get_id(rdev);
 171         u16 val;
 172
 173         switch (isink) {
 174         case WM8350_ISINK_A:
 175                 val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) &
 176                     WM8350_CS1_ISEL_MASK;
 177                 break;
 178         case WM8350_ISINK_B:
 179                 val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) &
 180                     WM8350_CS1_ISEL_MASK;
 181                 break;
 182         default:
 183                 return 0;
 184         }
 185
 186         return (isink_cur[val] + 50) / 100;
 187 }
 188
 189 /* turn on ISINK followed by DCDC */
 190 static int wm8350_isink_enable(struct regulator_dev *rdev)
 191 {
 192         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 193         int isink = rdev_get_id(rdev);
 194
 195         switch (isink) {
 196         case WM8350_ISINK_A:
 197                 switch (wm8350->pmic.isink_A_dcdc) {
 198                 case WM8350_DCDC_2:
 199                 case WM8350_DCDC_5:
 200                         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_7,
 201                                         WM8350_CS1_ENA);
 202                         wm8350_set_bits(wm8350, WM8350_CSA_FLASH_CONTROL,
 203                                         WM8350_CS1_DRIVE);
 204                         wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
 205                                         1 << (wm8350->pmic.isink_A_dcdc -
 206                                               WM8350_DCDC_1));
 207                         break;
 208                 default:
 209                         return -EINVAL;
 210                 }
 211                 break;
 212         case WM8350_ISINK_B:
 213                 switch (wm8350->pmic.isink_B_dcdc) {
 214                 case WM8350_DCDC_2:
 215                 case WM8350_DCDC_5:
 216                         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_7,
 217                                         WM8350_CS2_ENA);
 218                         wm8350_set_bits(wm8350, WM8350_CSB_FLASH_CONTROL,
 219                                         WM8350_CS2_DRIVE);
 220                         wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
 221                                         1 << (wm8350->pmic.isink_B_dcdc -
 222                                               WM8350_DCDC_1));
 223                         break;
 224                 default:
 225                         return -EINVAL;
 226                 }
 227                 break;
 228         default:
 229                 return -EINVAL;
 230         }
 231         return 0;
 232 }
 233
 234 static int wm8350_isink_disable(struct regulator_dev *rdev)
 235 {
 236         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 237         int isink = rdev_get_id(rdev);
 238
 239         switch (isink) {
 240         case WM8350_ISINK_A:
 241                 switch (wm8350->pmic.isink_A_dcdc) {
 242                 case WM8350_DCDC_2:
 243                 case WM8350_DCDC_5:
 244                         wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
 245                                           1 << (wm8350->pmic.isink_A_dcdc -
 246                                                 WM8350_DCDC_1));
 247                         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_7,
 248                                           WM8350_CS1_ENA);
 249                         break;
 250                 default:
 251                         return -EINVAL;
 252                 }
 253                 break;
 254         case WM8350_ISINK_B:
 255                 switch (wm8350->pmic.isink_B_dcdc) {
 256                 case WM8350_DCDC_2:
 257                 case WM8350_DCDC_5:
 258                         wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
 259                                           1 << (wm8350->pmic.isink_B_dcdc -
 260                                                 WM8350_DCDC_1));
 261                         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_7,
 262                                           WM8350_CS2_ENA);
 263                         break;
 264                 default:
 265                         return -EINVAL;
 266                 }
 267                 break;
 268         default:
 269                 return -EINVAL;
 270         }
 271         return 0;
 272 }
 273
 274 static int wm8350_isink_is_enabled(struct regulator_dev *rdev)
 275 {
 276         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 277         int isink = rdev_get_id(rdev);
 278
 279         switch (isink) {
 280         case WM8350_ISINK_A:
 281                 return wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) &
 282                     0x8000;
 283         case WM8350_ISINK_B:
 284                 return wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) &
 285                     0x8000;
 286         }
 287         return -EINVAL;
 288 }
 289
 290 int wm8350_isink_set_flash(struct wm8350 *wm8350, int isink, u16 mode,
 291                            u16 trigger, u16 duration, u16 on_ramp, u16 off_ramp,
 292                            u16 drive)
 293 {
 294         switch (isink) {
 295         case WM8350_ISINK_A:
 296                 wm8350_reg_write(wm8350, WM8350_CSA_FLASH_CONTROL,
 297                                  (mode ? WM8350_CS1_FLASH_MODE : 0) |
 298                                  (trigger ? WM8350_CS1_TRIGSRC : 0) |
 299                                  duration | on_ramp | off_ramp | drive);
 300                 break;
 301         case WM8350_ISINK_B:
 302                 wm8350_reg_write(wm8350, WM8350_CSB_FLASH_CONTROL,
 303                                  (mode ? WM8350_CS2_FLASH_MODE : 0) |
 304                                  (trigger ? WM8350_CS2_TRIGSRC : 0) |
 305                                  duration | on_ramp | off_ramp | drive);
 306                 break;
 307         default:
 308                 return -EINVAL;
 309         }
 310         return 0;
 311 }
 312 EXPORT_SYMBOL_GPL(wm8350_isink_set_flash);
 313
 314 static int wm8350_dcdc_set_voltage(struct regulator_dev *rdev, int min_uV,
 315         int max_uV)
 316 {
 317         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 318         int volt_reg, dcdc = rdev_get_id(rdev), mV,
 319                 min_mV = min_uV / 1000, max_mV = max_uV / 1000;
 320         u16 val;
 321
 322         if (min_mV < 850 || min_mV > 4025)
 323                 return -EINVAL;
 324         if (max_mV < 850 || max_mV > 4025)
 325                 return -EINVAL;
 326
 327         /* step size is 25mV */
 328         mV = (min_mV - 826) / 25;
 329         if (wm8350_dcdc_val_to_mvolts(mV) > max_mV)
 330                 return -EINVAL;
 331         BUG_ON(wm8350_dcdc_val_to_mvolts(mV) < min_mV);
 332
 333         switch (dcdc) {
 334         case WM8350_DCDC_1:
 335                 volt_reg = WM8350_DCDC1_CONTROL;
 336                 break;
 337         case WM8350_DCDC_3:
 338                 volt_reg = WM8350_DCDC3_CONTROL;
 339                 break;
 340         case WM8350_DCDC_4:
 341                 volt_reg = WM8350_DCDC4_CONTROL;
 342                 break;
 343         case WM8350_DCDC_6:
 344                 volt_reg = WM8350_DCDC6_CONTROL;
 345                 break;
 346         case WM8350_DCDC_2:
 347         case WM8350_DCDC_5:
 348         default:
 349                 return -EINVAL;
 350         }
 351
 352         /* all DCDCs have same mV bits */
 353         val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_DC1_VSEL_MASK;
 354         wm8350_reg_write(wm8350, volt_reg, val | mV);
 355         return 0;
 356 }
 357
 358 static int wm8350_dcdc_get_voltage(struct regulator_dev *rdev)
 359 {
 360         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 361         int volt_reg, dcdc = rdev_get_id(rdev);
 362         u16 val;
 363
 364         switch (dcdc) {
 365         case WM8350_DCDC_1:
 366                 volt_reg = WM8350_DCDC1_CONTROL;
 367                 break;
 368         case WM8350_DCDC_3:
 369                 volt_reg = WM8350_DCDC3_CONTROL;
 370                 break;
 371         case WM8350_DCDC_4:
 372                 volt_reg = WM8350_DCDC4_CONTROL;
 373                 break;
 374         case WM8350_DCDC_6:
 375                 volt_reg = WM8350_DCDC6_CONTROL;
 376                 break;
 377         case WM8350_DCDC_2:
 378         case WM8350_DCDC_5:
 379         default:
 380                 return -EINVAL;
 381         }
 382
 383         /* all DCDCs have same mV bits */
 384         val = wm8350_reg_read(wm8350, volt_reg) & WM8350_DC1_VSEL_MASK;
 385         return wm8350_dcdc_val_to_mvolts(val) * 1000;
 386 }
 387
 388 static int wm8350_dcdc_set_suspend_voltage(struct regulator_dev *rdev, int uV)
 389 {
 390         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 391         int volt_reg, mV = uV / 1000, dcdc = rdev_get_id(rdev);
 392         u16 val;
 393
 394         dev_dbg(wm8350->dev, "%s %d mV %d\n", __func__, dcdc, mV);
 395
 396         if (mV && (mV < 850 || mV > 4025)) {
 397                 dev_err(wm8350->dev,
 398                         "DCDC%d suspend voltage %d mV out of range\n",
 399                         dcdc, mV);
 400                 return -EINVAL;
 401         }
 402         if (mV == 0)
 403                 mV = 850;
 404
 405         switch (dcdc) {
 406         case WM8350_DCDC_1:
 407                 volt_reg = WM8350_DCDC1_LOW_POWER;
 408                 break;
 409         case WM8350_DCDC_3:
 410                 volt_reg = WM8350_DCDC3_LOW_POWER;
 411                 break;
 412         case WM8350_DCDC_4:
 413                 volt_reg = WM8350_DCDC4_LOW_POWER;
 414                 break;
 415         case WM8350_DCDC_6:
 416                 volt_reg = WM8350_DCDC6_LOW_POWER;
 417                 break;
 418         case WM8350_DCDC_2:
 419         case WM8350_DCDC_5:
 420         default:
 421                 return -EINVAL;
 422         }
 423
 424         /* all DCDCs have same mV bits */
 425         val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_DC1_VSEL_MASK;
 426         wm8350_reg_write(wm8350, volt_reg,
 427                          val | wm8350_dcdc_mvolts_to_val(mV));
 428         return 0;
 429 }
 430
 431 static int wm8350_dcdc_set_suspend_enable(struct regulator_dev *rdev)
 432 {
 433         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 434         int dcdc = rdev_get_id(rdev);
 435         u16 val;
 436
 437         switch (dcdc) {
 438         case WM8350_DCDC_1:
 439                 val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER)
 440                         & ~WM8350_DCDC_HIB_MODE_MASK;
 441                 wm8350_reg_write(wm8350, WM8350_DCDC1_LOW_POWER,
 442                         wm8350->pmic.dcdc1_hib_mode);
 443                 break;
 444         case WM8350_DCDC_3:
 445                 val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER)
 446                         & ~WM8350_DCDC_HIB_MODE_MASK;
 447                 wm8350_reg_write(wm8350, WM8350_DCDC3_LOW_POWER,
 448                         wm8350->pmic.dcdc3_hib_mode);
 449                 break;
 450         case WM8350_DCDC_4:
 451                 val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER)
 452                         & ~WM8350_DCDC_HIB_MODE_MASK;
 453                 wm8350_reg_write(wm8350, WM8350_DCDC4_LOW_POWER,
 454                         wm8350->pmic.dcdc4_hib_mode);
 455                 break;
 456         case WM8350_DCDC_6:
 457                 val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER)
 458                         & ~WM8350_DCDC_HIB_MODE_MASK;
 459                 wm8350_reg_write(wm8350, WM8350_DCDC6_LOW_POWER,
 460                         wm8350->pmic.dcdc6_hib_mode);
 461                 break;
 462         case WM8350_DCDC_2:
 463         case WM8350_DCDC_5:
 464         default:
 465                 return -EINVAL;
 466         }
 467
 468         return 0;
 469 }
 470
 471 static int wm8350_dcdc_set_suspend_disable(struct regulator_dev *rdev)
 472 {
 473         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 474         int dcdc = rdev_get_id(rdev);
 475         u16 val;
 476
 477         switch (dcdc) {
 478         case WM8350_DCDC_1:
 479                 val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER);
 480                 wm8350->pmic.dcdc1_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
 481                 wm8350_reg_write(wm8350, WM8350_DCDC1_LOW_POWER,
 482                         WM8350_DCDC_HIB_MODE_DIS);
 483                 break;
 484         case WM8350_DCDC_3:
 485                 val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER);
 486                 wm8350->pmic.dcdc3_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
 487                 wm8350_reg_write(wm8350, WM8350_DCDC3_LOW_POWER,
 488                         WM8350_DCDC_HIB_MODE_DIS);
 489                 break;
 490         case WM8350_DCDC_4:
 491                 val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER);
 492                 wm8350->pmic.dcdc4_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
 493                 wm8350_reg_write(wm8350, WM8350_DCDC4_LOW_POWER,
 494                         WM8350_DCDC_HIB_MODE_DIS);
 495                 break;
 496         case WM8350_DCDC_6:
 497                 val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER);
 498                 wm8350->pmic.dcdc6_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
 499                 wm8350_reg_write(wm8350, WM8350_DCDC6_LOW_POWER,
 500                         WM8350_DCDC_HIB_MODE_DIS);
 501                 break;
 502         case WM8350_DCDC_2:
 503         case WM8350_DCDC_5:
 504         default:
 505                 return -EINVAL;
 506         }
 507
 508         return 0;
 509 }
 510
 511 static int wm8350_dcdc25_set_suspend_enable(struct regulator_dev *rdev)
 512 {
 513         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 514         int dcdc = rdev_get_id(rdev);
 515         u16 val;
 516
 517         switch (dcdc) {
 518         case WM8350_DCDC_2:
 519                 val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
 520                     & ~WM8350_DC2_HIB_MODE_MASK;
 521                 wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
 522                                  WM8350_DC2_HIB_MODE_ACTIVE);
 523                 break;
 524         case WM8350_DCDC_5:
 525                 val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
 526                     & ~WM8350_DC2_HIB_MODE_MASK;
 527                 wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
 528                                  WM8350_DC5_HIB_MODE_ACTIVE);
 529                 break;
 530         default:
 531                 return -EINVAL;
 532         }
 533         return 0;
 534 }
 535
 536 static int wm8350_dcdc25_set_suspend_disable(struct regulator_dev *rdev)
 537 {
 538         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 539         int dcdc = rdev_get_id(rdev);
 540         u16 val;
 541
 542         switch (dcdc) {
 543         case WM8350_DCDC_2:
 544                 val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
 545                     & ~WM8350_DC2_HIB_MODE_MASK;
 546                 wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
 547                                  WM8350_DC2_HIB_MODE_DISABLE);
 548                 break;
 549         case WM8350_DCDC_5:
 550                 val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
 551                     & ~WM8350_DC2_HIB_MODE_MASK;
 552                 wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
 553                                  WM8350_DC2_HIB_MODE_DISABLE);
 554                 break;
 555         default:
 556                 return -EINVAL;
 557         }
 558         return 0;
 559 }
 560
 561 static int wm8350_dcdc_set_suspend_mode(struct regulator_dev *rdev,
 562         unsigned int mode)
 563 {
 564         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 565         int dcdc = rdev_get_id(rdev);
 566         u16 *hib_mode;
 567
 568         switch (dcdc) {
 569         case WM8350_DCDC_1:
 570                 hib_mode = &wm8350->pmic.dcdc1_hib_mode;
 571                 break;
 572         case WM8350_DCDC_3:
 573                 hib_mode = &wm8350->pmic.dcdc3_hib_mode;
 574                 break;
 575         case WM8350_DCDC_4:
 576                 hib_mode = &wm8350->pmic.dcdc4_hib_mode;
 577                 break;
 578         case WM8350_DCDC_6:
 579                 hib_mode = &wm8350->pmic.dcdc6_hib_mode;
 580                 break;
 581         case WM8350_DCDC_2:
 582         case WM8350_DCDC_5:
 583         default:
 584                 return -EINVAL;
 585         }
 586
 587         switch (mode) {
 588         case REGULATOR_MODE_NORMAL:
 589                 *hib_mode = WM8350_DCDC_HIB_MODE_IMAGE;
 590                 break;
 591         case REGULATOR_MODE_IDLE:
 592                 *hib_mode = WM8350_DCDC_HIB_MODE_STANDBY;
 593                 break;
 594         case REGULATOR_MODE_STANDBY:
 595                 *hib_mode = WM8350_DCDC_HIB_MODE_LDO_IM;
 596                 break;
 597         default:
 598                 return -EINVAL;
 599         }
 600
 601         return 0;
 602 }
 603
 604 static int wm8350_ldo_set_suspend_voltage(struct regulator_dev *rdev, int uV)
 605 {
 606         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 607         int volt_reg, mV = uV / 1000, ldo = rdev_get_id(rdev);
 608         u16 val;
 609
 610         dev_dbg(wm8350->dev, "%s %d mV %d\n", __func__, ldo, mV);
 611
 612         if (mV < 900 || mV > 3300) {
 613                 dev_err(wm8350->dev, "LDO%d voltage %d mV out of range\n",
 614                         ldo, mV);
 615                 return -EINVAL;
 616         }
 617
 618         switch (ldo) {
 619         case WM8350_LDO_1:
 620                 volt_reg = WM8350_LDO1_LOW_POWER;
 621                 break;
 622         case WM8350_LDO_2:
 623                 volt_reg = WM8350_LDO2_LOW_POWER;
 624                 break;
 625         case WM8350_LDO_3:
 626                 volt_reg = WM8350_LDO3_LOW_POWER;
 627                 break;
 628         case WM8350_LDO_4:
 629                 volt_reg = WM8350_LDO4_LOW_POWER;
 630                 break;
 631         default:
 632                 return -EINVAL;
 633         }
 634
 635         /* all LDOs have same mV bits */
 636         val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_VSEL_MASK;
 637         wm8350_reg_write(wm8350, volt_reg,
 638                          val | wm8350_ldo_mvolts_to_val(mV));
 639         return 0;
 640 }
 641
 642 static int wm8350_ldo_set_suspend_enable(struct regulator_dev *rdev)
 643 {
 644         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 645         int volt_reg, ldo = rdev_get_id(rdev);
 646         u16 val;
 647
 648         switch (ldo) {
 649         case WM8350_LDO_1:
 650                 volt_reg = WM8350_LDO1_LOW_POWER;
 651                 break;
 652         case WM8350_LDO_2:
 653                 volt_reg = WM8350_LDO2_LOW_POWER;
 654                 break;
 655         case WM8350_LDO_3:
 656                 volt_reg = WM8350_LDO3_LOW_POWER;
 657                 break;
 658         case WM8350_LDO_4:
 659                 volt_reg = WM8350_LDO4_LOW_POWER;
 660                 break;
 661         default:
 662                 return -EINVAL;
 663         }
 664
 665         /* all LDOs have same mV bits */
 666         val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_HIB_MODE_MASK;
 667         wm8350_reg_write(wm8350, volt_reg, val);
 668         return 0;
 669 }
 670
 671 static int wm8350_ldo_set_suspend_disable(struct regulator_dev *rdev)
 672 {
 673         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 674         int volt_reg, ldo = rdev_get_id(rdev);
 675         u16 val;
 676
 677         switch (ldo) {
 678         case WM8350_LDO_1:
 679                 volt_reg = WM8350_LDO1_LOW_POWER;
 680                 break;
 681         case WM8350_LDO_2:
 682                 volt_reg = WM8350_LDO2_LOW_POWER;
 683                 break;
 684         case WM8350_LDO_3:
 685                 volt_reg = WM8350_LDO3_LOW_POWER;
 686                 break;
 687         case WM8350_LDO_4:
 688                 volt_reg = WM8350_LDO4_LOW_POWER;
 689                 break;
 690         default:
 691                 return -EINVAL;
 692         }
 693
 694         /* all LDOs have same mV bits */
 695         val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_HIB_MODE_MASK;
 696         wm8350_reg_write(wm8350, volt_reg, WM8350_LDO1_HIB_MODE_DIS);
 697         return 0;
 698 }
 699
 700 static int wm8350_ldo_set_voltage(struct regulator_dev *rdev, int min_uV,
 701         int max_uV)
 702 {
 703         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 704         int volt_reg, ldo = rdev_get_id(rdev), mV, min_mV = min_uV / 1000,
 705                 max_mV = max_uV / 1000;
 706         u16 val;
 707
 708         if (min_mV < 900 || min_mV > 3300)
 709                 return -EINVAL;
 710         if (max_mV < 900 || max_mV > 3300)
 711                 return -EINVAL;
 712
 713         if (min_mV < 1800) {
 714                 /* step size is 50mV < 1800mV */
 715                 mV = (min_mV - 851) / 50;
 716                 if (wm8350_ldo_val_to_mvolts(mV) > max_mV)
 717                         return -EINVAL;
 718                 BUG_ON(wm8350_ldo_val_to_mvolts(mV) < min_mV);
 719         } else {
 720                 /* step size is 100mV > 1800mV */
 721                 mV = ((min_mV - 1701) / 100) + 16;
 722                 if (wm8350_ldo_val_to_mvolts(mV) > max_mV)
 723                         return -EINVAL;
 724                 BUG_ON(wm8350_ldo_val_to_mvolts(mV) < min_mV);
 725         }
 726
 727         switch (ldo) {
 728         case WM8350_LDO_1:
 729                 volt_reg = WM8350_LDO1_CONTROL;
 730                 break;
 731         case WM8350_LDO_2:
 732                 volt_reg = WM8350_LDO2_CONTROL;
 733                 break;
 734         case WM8350_LDO_3:
 735                 volt_reg = WM8350_LDO3_CONTROL;
 736                 break;
 737         case WM8350_LDO_4:
 738                 volt_reg = WM8350_LDO4_CONTROL;
 739                 break;
 740         default:
 741                 return -EINVAL;
 742         }
 743
 744         /* all LDOs have same mV bits */
 745         val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_VSEL_MASK;
 746         wm8350_reg_write(wm8350, volt_reg, val | mV);
 747         return 0;
 748 }
 749
 750 static int wm8350_ldo_get_voltage(struct regulator_dev *rdev)
 751 {
 752         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 753         int volt_reg, ldo = rdev_get_id(rdev);
 754         u16 val;
 755
 756         switch (ldo) {
 757         case WM8350_LDO_1:
 758                 volt_reg = WM8350_LDO1_CONTROL;
 759                 break;
 760         case WM8350_LDO_2:
 761                 volt_reg = WM8350_LDO2_CONTROL;
 762                 break;
 763         case WM8350_LDO_3:
 764                 volt_reg = WM8350_LDO3_CONTROL;
 765                 break;
 766         case WM8350_LDO_4:
 767                 volt_reg = WM8350_LDO4_CONTROL;
 768                 break;
 769         default:
 770                 return -EINVAL;
 771         }
 772
 773         /* all LDOs have same mV bits */
 774         val = wm8350_reg_read(wm8350, volt_reg) & WM8350_LDO1_VSEL_MASK;
 775         return wm8350_ldo_val_to_mvolts(val) * 1000;
 776 }
 777
 778 int wm8350_dcdc_set_slot(struct wm8350 *wm8350, int dcdc, u16 start,
 779                          u16 stop, u16 fault)
 780 {
 781         int slot_reg;
 782         u16 val;
 783
 784         dev_dbg(wm8350->dev, "%s %d start %d stop %d\n",
 785                 __func__, dcdc, start, stop);
 786
 787         /* slot valid ? */
 788         if (start > 15 || stop > 15)
 789                 return -EINVAL;
 790
 791         switch (dcdc) {
 792         case WM8350_DCDC_1:
 793                 slot_reg = WM8350_DCDC1_TIMEOUTS;
 794                 break;
 795         case WM8350_DCDC_2:
 796                 slot_reg = WM8350_DCDC2_TIMEOUTS;
 797                 break;
 798         case WM8350_DCDC_3:
 799                 slot_reg = WM8350_DCDC3_TIMEOUTS;
 800                 break;
 801         case WM8350_DCDC_4:
 802                 slot_reg = WM8350_DCDC4_TIMEOUTS;
 803                 break;
 804         case WM8350_DCDC_5:
 805                 slot_reg = WM8350_DCDC5_TIMEOUTS;
 806                 break;
 807         case WM8350_DCDC_6:
 808                 slot_reg = WM8350_DCDC6_TIMEOUTS;
 809                 break;
 810         default:
 811                 return -EINVAL;
 812         }
 813
 814         val = wm8350_reg_read(wm8350, slot_reg) &
 815             ~(WM8350_DC1_ENSLOT_MASK | WM8350_DC1_SDSLOT_MASK |
 816               WM8350_DC1_ERRACT_MASK);
 817         wm8350_reg_write(wm8350, slot_reg,
 818                          val | (start << WM8350_DC1_ENSLOT_SHIFT) |
 819                          (stop << WM8350_DC1_SDSLOT_SHIFT) |
 820                          (fault << WM8350_DC1_ERRACT_SHIFT));
 821
 822         return 0;
 823 }
 824 EXPORT_SYMBOL_GPL(wm8350_dcdc_set_slot);
 825
 826 int wm8350_ldo_set_slot(struct wm8350 *wm8350, int ldo, u16 start, u16 stop)
 827 {
 828         int slot_reg;
 829         u16 val;
 830
 831         dev_dbg(wm8350->dev, "%s %d start %d stop %d\n",
 832                 __func__, ldo, start, stop);
 833
 834         /* slot valid ? */
 835         if (start > 15 || stop > 15)
 836                 return -EINVAL;
 837
 838         switch (ldo) {
 839         case WM8350_LDO_1:
 840                 slot_reg = WM8350_LDO1_TIMEOUTS;
 841                 break;
 842         case WM8350_LDO_2:
 843                 slot_reg = WM8350_LDO2_TIMEOUTS;
 844                 break;
 845         case WM8350_LDO_3:
 846                 slot_reg = WM8350_LDO3_TIMEOUTS;
 847                 break;
 848         case WM8350_LDO_4:
 849                 slot_reg = WM8350_LDO4_TIMEOUTS;
 850                 break;
 851         default:
 852                 return -EINVAL;
 853         }
 854
 855         val = wm8350_reg_read(wm8350, slot_reg) & ~WM8350_LDO1_SDSLOT_MASK;
 856         wm8350_reg_write(wm8350, slot_reg, val | ((start << 10) | (stop << 6)));
 857         return 0;
 858 }
 859 EXPORT_SYMBOL_GPL(wm8350_ldo_set_slot);
 860
 861 int wm8350_dcdc25_set_mode(struct wm8350 *wm8350, int dcdc, u16 mode,
 862                            u16 ilim, u16 ramp, u16 feedback)
 863 {
 864         u16 val;
 865
 866         dev_dbg(wm8350->dev, "%s %d mode: %s %s\n", __func__, dcdc,
 867                 mode ? "normal" : "boost", ilim ? "low" : "normal");
 868
 869         switch (dcdc) {
 870         case WM8350_DCDC_2:
 871                 val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
 872                     & ~(WM8350_DC2_MODE_MASK | WM8350_DC2_ILIM_MASK |
 873                         WM8350_DC2_RMP_MASK | WM8350_DC2_FBSRC_MASK);
 874                 wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
 875                                  (mode << WM8350_DC2_MODE_SHIFT) |
 876                                  (ilim << WM8350_DC2_ILIM_SHIFT) |
 877                                  (ramp << WM8350_DC2_RMP_SHIFT) |
 878                                  (feedback << WM8350_DC2_FBSRC_SHIFT));
 879                 break;
 880         case WM8350_DCDC_5:
 881                 val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
 882                     & ~(WM8350_DC5_MODE_MASK | WM8350_DC5_ILIM_MASK |
 883                         WM8350_DC5_RMP_MASK | WM8350_DC5_FBSRC_MASK);
 884                 wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
 885                                  (mode << WM8350_DC5_MODE_SHIFT) |
 886                                  (ilim << WM8350_DC5_ILIM_SHIFT) |
 887                                  (ramp << WM8350_DC5_RMP_SHIFT) |
 888                                  (feedback << WM8350_DC5_FBSRC_SHIFT));
 889                 break;
 890         default:
 891                 return -EINVAL;
 892         }
 893
 894         return 0;
 895 }
 896 EXPORT_SYMBOL_GPL(wm8350_dcdc25_set_mode);
 897
 898 static int wm8350_dcdc_enable(struct regulator_dev *rdev)
 899 {
 900         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 901         int dcdc = rdev_get_id(rdev);
 902         u16 shift;
 903
 904         if (dcdc < WM8350_DCDC_1 || dcdc > WM8350_DCDC_6)
 905                 return -EINVAL;
 906
 907         shift = dcdc - WM8350_DCDC_1;
 908         wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED, 1 << shift);
 909         return 0;
 910 }
 911
 912 static int wm8350_dcdc_disable(struct regulator_dev *rdev)
 913 {
 914         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 915         int dcdc = rdev_get_id(rdev);
 916         u16 shift;
 917
 918         if (dcdc < WM8350_DCDC_1 || dcdc > WM8350_DCDC_6)
 919                 return -EINVAL;
 920
 921         shift = dcdc - WM8350_DCDC_1;
 922         wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED, 1 << shift);
 923
 924         return 0;
 925 }
 926
 927 static int wm8350_ldo_enable(struct regulator_dev *rdev)
 928 {
 929         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 930         int ldo = rdev_get_id(rdev);
 931         u16 shift;
 932
 933         if (ldo < WM8350_LDO_1 || ldo > WM8350_LDO_4)
 934                 return -EINVAL;
 935
 936         shift = (ldo - WM8350_LDO_1) + 8;
 937         wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED, 1 << shift);
 938         return 0;
 939 }
 940
 941 static int wm8350_ldo_disable(struct regulator_dev *rdev)
 942 {
 943         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 944         int ldo = rdev_get_id(rdev);
 945         u16 shift;
 946
 947         if (ldo < WM8350_LDO_1 || ldo > WM8350_LDO_4)
 948                 return -EINVAL;
 949
 950         shift = (ldo - WM8350_LDO_1) + 8;
 951         wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED, 1 << shift);
 952         return 0;
 953 }
 954
 955 static int force_continuous_enable(struct wm8350 *wm8350, int dcdc, int enable)
 956 {
 957         int reg = 0, ret;
 958
 959         switch (dcdc) {
 960         case WM8350_DCDC_1:
 961                 reg = WM8350_DCDC1_FORCE_PWM;
 962                 break;
 963         case WM8350_DCDC_3:
 964                 reg = WM8350_DCDC3_FORCE_PWM;
 965                 break;
 966         case WM8350_DCDC_4:
 967                 reg = WM8350_DCDC4_FORCE_PWM;
 968                 break;
 969         case WM8350_DCDC_6:
 970                 reg = WM8350_DCDC6_FORCE_PWM;
 971                 break;
 972         default:
 973                 return -EINVAL;
 974         }
 975
 976         if (enable)
 977                 ret = wm8350_set_bits(wm8350, reg,
 978                         WM8350_DCDC1_FORCE_PWM_ENA);
 979         else
 980                 ret = wm8350_clear_bits(wm8350, reg,
 981                         WM8350_DCDC1_FORCE_PWM_ENA);
 982         return ret;
 983 }
 984
 985 static int wm8350_dcdc_set_mode(struct regulator_dev *rdev, unsigned int mode)
 986 {
 987         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 988         int dcdc = rdev_get_id(rdev);
 989         u16 val;
 990
 991         if (dcdc < WM8350_DCDC_1 || dcdc > WM8350_DCDC_6)
 992                 return -EINVAL;
 993
 994         if (dcdc == WM8350_DCDC_2 || dcdc == WM8350_DCDC_5)
 995                 return -EINVAL;
 996
 997         val = 1 << (dcdc - WM8350_DCDC_1);
 998
 999         switch (mode) {
1000         case REGULATOR_MODE_FAST:
1001                 /* force continuous mode */
1002                 wm8350_set_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val);
1003                 wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
1004                 force_continuous_enable(wm8350, dcdc, 1);
1005                 break;
1006         case REGULATOR_MODE_NORMAL:
1007                 /* active / pulse skipping */
1008                 wm8350_set_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val);
1009                 wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
1010                 force_continuous_enable(wm8350, dcdc, 0);
1011                 break;
1012         case REGULATOR_MODE_IDLE:
1013                 /* standby mode */
1014                 force_continuous_enable(wm8350, dcdc, 0);
1015                 wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
1016                 wm8350_clear_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val);
1017                 break;
1018         case REGULATOR_MODE_STANDBY:
1019                 /* LDO mode */
1020                 force_continuous_enable(wm8350, dcdc, 0);
1021                 wm8350_set_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
1022                 break;
1023         }
1024
1025         return 0;
1026 }
1027
1028 static unsigned int wm8350_dcdc_get_mode(struct regulator_dev *rdev)
1029 {
1030         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
1031         int dcdc = rdev_get_id(rdev);
1032         u16 mask, sleep, active, force;
1033         int mode = REGULATOR_MODE_NORMAL;
1034
1035         if (dcdc < WM8350_DCDC_1 || dcdc > WM8350_DCDC_6)
1036                 return -EINVAL;
1037
1038         if (dcdc == WM8350_DCDC_2 || dcdc == WM8350_DCDC_5)
1039                 return -EINVAL;
1040
1041         mask = 1 << (dcdc - WM8350_DCDC_1);
1042         active = wm8350_reg_read(wm8350, WM8350_DCDC_ACTIVE_OPTIONS) & mask;
1043         sleep = wm8350_reg_read(wm8350, WM8350_DCDC_SLEEP_OPTIONS) & mask;
1044         force = wm8350_reg_read(wm8350, WM8350_DCDC1_FORCE_PWM)
1045             & WM8350_DCDC1_FORCE_PWM_ENA;
1046         dev_dbg(wm8350->dev, "mask %x active %x sleep %x force %x",
1047                 mask, active, sleep, force);
1048
1049         if (active && !sleep) {
1050                 if (force)
1051                         mode = REGULATOR_MODE_FAST;
1052                 else
1053                         mode = REGULATOR_MODE_NORMAL;
1054         } else if (!active && !sleep)
1055                 mode = REGULATOR_MODE_IDLE;
1056         else if (!sleep)
1057                 mode = REGULATOR_MODE_STANDBY;
1058
1059         return mode;
1060 }
1061
1062 static unsigned int wm8350_ldo_get_mode(struct regulator_dev *rdev)
1063 {
1064         return REGULATOR_MODE_NORMAL;
1065 }
1066
1067 struct wm8350_dcdc_efficiency {
1068         int uA_load_min;
1069         int uA_load_max;
1070         unsigned int mode;
1071 };
1072
1073 static const struct wm8350_dcdc_efficiency dcdc1_6_efficiency[] = {
1074         {0, 10000, REGULATOR_MODE_STANDBY},       /* 0 - 10mA - LDO */
1075         {10000, 100000, REGULATOR_MODE_IDLE},     /* 10mA - 100mA - Standby */
1076         {100000, 1000000, REGULATOR_MODE_NORMAL}, /* > 100mA - Active */
1077         {-1, -1, REGULATOR_MODE_NORMAL},
1078 };
1079
1080 static const struct wm8350_dcdc_efficiency dcdc3_4_efficiency[] = {
1081         {0, 10000, REGULATOR_MODE_STANDBY},      /* 0 - 10mA - LDO */
1082         {10000, 100000, REGULATOR_MODE_IDLE},    /* 10mA - 100mA - Standby */
1083         {100000, 800000, REGULATOR_MODE_NORMAL}, /* > 100mA - Active */
1084         {-1, -1, REGULATOR_MODE_NORMAL},
1085 };
1086
1087 static unsigned int get_mode(int uA, const struct wm8350_dcdc_efficiency *eff)
1088 {
1089         int i = 0;
1090
1091         while (eff[i].uA_load_min != -1) {
1092                 if (uA >= eff[i].uA_load_min && uA <= eff[i].uA_load_max)
1093                         return eff[i].mode;
1094         }
1095         return REGULATOR_MODE_NORMAL;
1096 }
1097
1098 /* Query the regulator for it's most efficient mode @ uV,uA
1099  * WM8350 regulator efficiency is pretty similar over
1100  * different input and output uV.
1101  */
1102 static unsigned int wm8350_dcdc_get_optimum_mode(struct regulator_dev *rdev,
1103                                                  int input_uV, int output_uV,
1104                                                  int output_uA)
1105 {
1106         int dcdc = rdev_get_id(rdev), mode;
1107
1108         switch (dcdc) {
1109         case WM8350_DCDC_1:
1110         case WM8350_DCDC_6:
1111                 mode = get_mode(output_uA, dcdc1_6_efficiency);
1112                 break;
1113         case WM8350_DCDC_3:
1114         case WM8350_DCDC_4:
1115                 mode = get_mode(output_uA, dcdc3_4_efficiency);
1116                 break;
1117         default:
1118                 mode = REGULATOR_MODE_NORMAL;
1119                 break;
1120         }
1121         return mode;
1122 }
1123
1124 static int wm8350_dcdc_is_enabled(struct regulator_dev *rdev)
1125 {
1126         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
1127         int dcdc = rdev_get_id(rdev), shift;
1128
1129         if (dcdc < WM8350_DCDC_1 || dcdc > WM8350_DCDC_6)
1130                 return -EINVAL;
1131
1132         shift = dcdc - WM8350_DCDC_1;
1133         return wm8350_reg_read(wm8350, WM8350_DCDC_LDO_REQUESTED)
1134             & (1 << shift);
1135 }
1136
1137 static int wm8350_ldo_is_enabled(struct regulator_dev *rdev)
1138 {
1139         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
1140         int ldo = rdev_get_id(rdev), shift;
1141
1142         if (ldo < WM8350_LDO_1 || ldo > WM8350_LDO_4)
1143                 return -EINVAL;
1144
1145         shift = (ldo - WM8350_LDO_1) + 8;
1146         return wm8350_reg_read(wm8350, WM8350_DCDC_LDO_REQUESTED)
1147             & (1 << shift);
1148 }
1149
1150 static struct regulator_ops wm8350_dcdc_ops = {
1151         .set_voltage = wm8350_dcdc_set_voltage,
1152         .get_voltage = wm8350_dcdc_get_voltage,
1153         .enable = wm8350_dcdc_enable,
1154         .disable = wm8350_dcdc_disable,
1155         .get_mode = wm8350_dcdc_get_mode,
1156         .set_mode = wm8350_dcdc_set_mode,
1157         .get_optimum_mode = wm8350_dcdc_get_optimum_mode,
1158         .is_enabled = wm8350_dcdc_is_enabled,
1159         .set_suspend_voltage = wm8350_dcdc_set_suspend_voltage,
1160         .set_suspend_enable = wm8350_dcdc_set_suspend_enable,
1161         .set_suspend_disable = wm8350_dcdc_set_suspend_disable,
1162         .set_suspend_mode = wm8350_dcdc_set_suspend_mode,
1163 };
1164
1165 static struct regulator_ops wm8350_dcdc2_5_ops = {
1166         .enable = wm8350_dcdc_enable,
1167         .disable = wm8350_dcdc_disable,
1168         .is_enabled = wm8350_dcdc_is_enabled,
1169         .set_suspend_enable = wm8350_dcdc25_set_suspend_enable,
1170         .set_suspend_disable = wm8350_dcdc25_set_suspend_disable,
1171 };
1172
1173 static struct regulator_ops wm8350_ldo_ops = {
1174         .set_voltage = wm8350_ldo_set_voltage,
1175         .get_voltage = wm8350_ldo_get_voltage,
1176         .enable = wm8350_ldo_enable,
1177         .disable = wm8350_ldo_disable,
1178         .is_enabled = wm8350_ldo_is_enabled,
1179         .get_mode = wm8350_ldo_get_mode,
1180         .set_suspend_voltage = wm8350_ldo_set_suspend_voltage,
1181         .set_suspend_enable = wm8350_ldo_set_suspend_enable,
1182         .set_suspend_disable = wm8350_ldo_set_suspend_disable,
1183 };
1184
1185 static struct regulator_ops wm8350_isink_ops = {
1186         .set_current_limit = wm8350_isink_set_current,
1187         .get_current_limit = wm8350_isink_get_current,
1188         .enable = wm8350_isink_enable,
1189         .disable = wm8350_isink_disable,
1190         .is_enabled = wm8350_isink_is_enabled,
1191 };
1192
1193 static struct regulator_desc wm8350_reg[NUM_WM8350_REGULATORS] = {
1194         {
1195                 .name = "DCDC1",
1196                 .id = WM8350_DCDC_1,
1197                 .ops = &wm8350_dcdc_ops,
1198                 .irq = WM8350_IRQ_UV_DC1,
1199                 .type = REGULATOR_VOLTAGE,
1200                 .owner = THIS_MODULE,
1201         },
1202         {
1203                 .name = "DCDC2",
1204                 .id = WM8350_DCDC_2,
1205                 .ops = &wm8350_dcdc2_5_ops,
1206                 .irq = WM8350_IRQ_UV_DC2,
1207                 .type = REGULATOR_VOLTAGE,
1208                 .owner = THIS_MODULE,
1209         },
1210         {
1211                 .name = "DCDC3",
1212                 .id = WM8350_DCDC_3,
1213                 .ops = &wm8350_dcdc_ops,
1214                 .irq = WM8350_IRQ_UV_DC3,
1215                 .type = REGULATOR_VOLTAGE,
1216                 .owner = THIS_MODULE,
1217         },
1218         {
1219                 .name = "DCDC4",
1220                 .id = WM8350_DCDC_4,
1221                 .ops = &wm8350_dcdc_ops,
1222                 .irq = WM8350_IRQ_UV_DC4,
1223                 .type = REGULATOR_VOLTAGE,
1224                 .owner = THIS_MODULE,
1225         },
1226         {
1227                 .name = "DCDC5",
1228                 .id = WM8350_DCDC_5,
1229                 .ops = &wm8350_dcdc2_5_ops,
1230                 .irq = WM8350_IRQ_UV_DC5,
1231                 .type = REGULATOR_VOLTAGE,
1232                 .owner = THIS_MODULE,
1233          },
1234         {
1235                 .name = "DCDC6",
1236                 .id = WM8350_DCDC_6,
1237                 .ops = &wm8350_dcdc_ops,
1238                 .irq = WM8350_IRQ_UV_DC6,
1239                 .type = REGULATOR_VOLTAGE,
1240                 .owner = THIS_MODULE,
1241         },
1242         {
1243                 .name = "LDO1",
1244                 .id = WM8350_LDO_1,
1245                 .ops = &wm8350_ldo_ops,
1246                 .irq = WM8350_IRQ_UV_LDO1,
1247                 .type = REGULATOR_VOLTAGE,
1248                 .owner = THIS_MODULE,
1249         },
1250         {
1251                 .name = "LDO2",
1252                 .id = WM8350_LDO_2,
1253                 .ops = &wm8350_ldo_ops,
1254                 .irq = WM8350_IRQ_UV_LDO2,
1255                 .type = REGULATOR_VOLTAGE,
1256                 .owner = THIS_MODULE,
1257         },
1258         {
1259                 .name = "LDO3",
1260                 .id = WM8350_LDO_3,
1261                 .ops = &wm8350_ldo_ops,
1262                 .irq = WM8350_IRQ_UV_LDO3,
1263                 .type = REGULATOR_VOLTAGE,
1264                 .owner = THIS_MODULE,
1265         },
1266         {
1267                 .name = "LDO4",
1268                 .id = WM8350_LDO_4,
1269                 .ops = &wm8350_ldo_ops,
1270                 .irq = WM8350_IRQ_UV_LDO4,
1271                 .type = REGULATOR_VOLTAGE,
1272                 .owner = THIS_MODULE,
1273         },
1274         {
1275                 .name = "ISINKA",
1276                 .id = WM8350_ISINK_A,
1277                 .ops = &wm8350_isink_ops,
1278                 .irq = WM8350_IRQ_CS1,
1279                 .type = REGULATOR_CURRENT,
1280                 .owner = THIS_MODULE,
1281          },
1282         {
1283                 .name = "ISINKB",
1284                 .id = WM8350_ISINK_B,
1285                 .ops = &wm8350_isink_ops,
1286                 .irq = WM8350_IRQ_CS2,
1287                 .type = REGULATOR_CURRENT,
1288                 .owner = THIS_MODULE,
1289          },
1290 };
1291
1292 static void pmic_uv_handler(struct wm8350 *wm8350, int irq, void *data)
1293 {
1294         struct regulator_dev *rdev = (struct regulator_dev *)data;
1295
1296         if (irq == WM8350_IRQ_CS1 || irq == WM8350_IRQ_CS2)
1297                 regulator_notifier_call_chain(rdev,
1298                                               REGULATOR_EVENT_REGULATION_OUT,
1299                                               wm8350);
1300         else
1301                 regulator_notifier_call_chain(rdev,
1302                                               REGULATOR_EVENT_UNDER_VOLTAGE,
1303                                               wm8350);
1304 }
1305
1306 static int wm8350_regulator_probe(struct platform_device *pdev)
1307 {
1308         struct wm8350 *wm8350 = dev_get_drvdata(&pdev->dev);
1309         struct regulator_dev *rdev;
1310         int ret;
1311         u16 val;
1312
1313         if (pdev->id < WM8350_DCDC_1 || pdev->id > WM8350_ISINK_B)
1314                 return -ENODEV;
1315
1316         /* do any regulatior specific init */
1317         switch (pdev->id) {
1318         case WM8350_DCDC_1:
1319                 val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER);
1320                 wm8350->pmic.dcdc1_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1321                 break;
1322         case WM8350_DCDC_3:
1323                 val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER);
1324                 wm8350->pmic.dcdc3_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1325                 break;
1326         case WM8350_DCDC_4:
1327                 val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER);
1328                 wm8350->pmic.dcdc4_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1329                 break;
1330         case WM8350_DCDC_6:
1331                 val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER);
1332                 wm8350->pmic.dcdc6_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1333                 break;
1334         }
1335
1336
1337         /* register regulator */
1338         rdev = regulator_register(&wm8350_reg[pdev->id], &pdev->dev,
1339                                   dev_get_drvdata(&pdev->dev));
1340         if (IS_ERR(rdev)) {
1341                 dev_err(&pdev->dev, "failed to register %s\n",
1342                         wm8350_reg[pdev->id].name);
1343                 return PTR_ERR(rdev);
1344         }
1345
1346         /* register regulator IRQ */
1347         ret = wm8350_register_irq(wm8350, wm8350_reg[pdev->id].irq,
1348                                   pmic_uv_handler, rdev);
1349         if (ret < 0) {
1350                 regulator_unregister(rdev);
1351                 dev_err(&pdev->dev, "failed to register regulator %s IRQ\n",
1352                         wm8350_reg[pdev->id].name);
1353                 return ret;
1354         }
1355
1356         wm8350_unmask_irq(wm8350, wm8350_reg[pdev->id].irq);
1357
1358         return 0;
1359 }
1360
1361 static int wm8350_regulator_remove(struct platform_device *pdev)
1362 {
1363         struct regulator_dev *rdev = platform_get_drvdata(pdev);
1364         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
1365
1366         wm8350_mask_irq(wm8350, wm8350_reg[pdev->id].irq);
1367         wm8350_free_irq(wm8350, wm8350_reg[pdev->id].irq);
1368
1369         regulator_unregister(rdev);
1370
1371         return 0;
1372 }
1373
1374 int wm8350_register_regulator(struct wm8350 *wm8350, int reg,
1375                               struct regulator_init_data *initdata)
1376 {
1377         struct platform_device *pdev;
1378         int ret;
1379
1380         if (wm8350->pmic.pdev[reg])
1381                 return -EBUSY;
1382
1383         pdev = platform_device_alloc("wm8350-regulator", reg);
1384         if (!pdev)
1385                 return -ENOMEM;
1386
1387         wm8350->pmic.pdev[reg] = pdev;
1388
1389         initdata->driver_data = wm8350;
1390
1391         pdev->dev.platform_data = initdata;
1392         pdev->dev.parent = wm8350->dev;
1393         platform_set_drvdata(pdev, wm8350);
1394
1395         ret = platform_device_add(pdev);
1396
1397         if (ret != 0) {
1398                 dev_err(wm8350->dev, "Failed to register regulator %d: %d\n",
1399                         reg, ret);
1400                 platform_device_del(pdev);
1401                 wm8350->pmic.pdev[reg] = NULL;
1402         }
1403
1404         return ret;
1405 }
1406 EXPORT_SYMBOL_GPL(wm8350_register_regulator);
1407
1408 static struct platform_driver wm8350_regulator_driver = {
1409         .probe = wm8350_regulator_probe,
1410         .remove = wm8350_regulator_remove,
1411         .driver         = {
1412                 .name   = "wm8350-regulator",
1413         },
1414 };
1415
1416 static int __init wm8350_regulator_init(void)
1417 {
1418         return platform_driver_register(&wm8350_regulator_driver);
1419 }
1420 subsys_initcall(wm8350_regulator_init);
1421
1422 static void __exit wm8350_regulator_exit(void)
1423 {
1424         platform_driver_unregister(&wm8350_regulator_driver);
1425 }
1426 module_exit(wm8350_regulator_exit);
1427
1428 /* Module information */
1429 MODULE_AUTHOR("Liam Girdwood");
1430 MODULE_DESCRIPTION("WM8350 voltage and current regulator driver");
1431 MODULE_LICENSE("GPL");