4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
5 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
24 #include <linux/delay.h>
30 /* Struct to hold initial RF register values (RF Banks) */
32 u8 rf_bank; /* check out ath5k_reg.h */
33 u16 rf_register; /* register address */
34 u32 rf_value[5]; /* register value for different modes (above) */
38 * Mode-specific RF Gain table (64bytes) for RF5111/5112
39 * (RF5110 only comes with AR5210 and only supports a/turbo a mode so initial
40 * RF Gain values are included in AR5K_AR5210_INI)
42 struct ath5k_ini_rfgain {
43 u16 rfg_register; /* RF Gain register address */
44 u32 rfg_value[2]; /* [freq (see below)] */
47 struct ath5k_gain_opt {
50 const struct ath5k_gain_opt_step go_step[AR5K_GAIN_STEP_COUNT];
53 /* RF5111 mode-specific init registers */
54 static const struct ath5k_ini_rf rfregs_5111[] = {
56 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
57 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
59 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
61 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
63 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
65 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
67 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
69 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
71 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
73 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
75 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
77 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
79 { 0x00380000, 0x00380000, 0x00380000, 0x00380000, 0x00380000 } },
81 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
83 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
85 { 0x00000000, 0x00000000, 0x000000c0, 0x00000080, 0x00000080 } },
87 { 0x000400f9, 0x000400f9, 0x000400ff, 0x000400fd, 0x000400fd } },
89 { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } },
91 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
93 { 0x00000010, 0x00000014, 0x00000010, 0x00000010, 0x00000014 } },
95 { 0x00601068, 0x00601068, 0x00601068, 0x00601068, 0x00601068 } },
97 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
99 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
101 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
103 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
105 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
107 { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } },
109 { 0x04000000, 0x04000000, 0x04000000, 0x04000000, 0x04000000 } },
111 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
113 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
115 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
117 { 0x00000000, 0x00000000, 0x0a000000, 0x00000000, 0x00000000 } },
119 { 0x003800c0, 0x00380080, 0x023800c0, 0x003800c0, 0x003800c0 } },
121 { 0x00020006, 0x00020006, 0x00000006, 0x00020006, 0x00020006 } },
123 { 0x00000089, 0x00000089, 0x00000089, 0x00000089, 0x00000089 } },
125 { 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0 } },
127 { 0x00040007, 0x00040007, 0x00040007, 0x00040007, 0x00040007 } },
129 { 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a } },
131 { 0x00000040, 0x00000048, 0x00000040, 0x00000040, 0x00000040 } },
133 { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } },
135 { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } },
137 { 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f } },
139 { 0x000000f1, 0x000000f1, 0x00000061, 0x000000f1, 0x000000f1 } },
141 { 0x0000904f, 0x0000904f, 0x0000904c, 0x0000904f, 0x0000904f } },
143 { 0x0000125a, 0x0000125a, 0x0000129a, 0x0000125a, 0x0000125a } },
145 { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } },
148 /* Initial RF Gain settings for RF5111 */
149 static const struct ath5k_ini_rfgain rfgain_5111[] = {
151 { AR5K_RF_GAIN(0), { 0x000001a9, 0x00000000 } },
152 { AR5K_RF_GAIN(1), { 0x000001e9, 0x00000040 } },
153 { AR5K_RF_GAIN(2), { 0x00000029, 0x00000080 } },
154 { AR5K_RF_GAIN(3), { 0x00000069, 0x00000150 } },
155 { AR5K_RF_GAIN(4), { 0x00000199, 0x00000190 } },
156 { AR5K_RF_GAIN(5), { 0x000001d9, 0x000001d0 } },
157 { AR5K_RF_GAIN(6), { 0x00000019, 0x00000010 } },
158 { AR5K_RF_GAIN(7), { 0x00000059, 0x00000044 } },
159 { AR5K_RF_GAIN(8), { 0x00000099, 0x00000084 } },
160 { AR5K_RF_GAIN(9), { 0x000001a5, 0x00000148 } },
161 { AR5K_RF_GAIN(10), { 0x000001e5, 0x00000188 } },
162 { AR5K_RF_GAIN(11), { 0x00000025, 0x000001c8 } },
163 { AR5K_RF_GAIN(12), { 0x000001c8, 0x00000014 } },
164 { AR5K_RF_GAIN(13), { 0x00000008, 0x00000042 } },
165 { AR5K_RF_GAIN(14), { 0x00000048, 0x00000082 } },
166 { AR5K_RF_GAIN(15), { 0x00000088, 0x00000178 } },
167 { AR5K_RF_GAIN(16), { 0x00000198, 0x000001b8 } },
168 { AR5K_RF_GAIN(17), { 0x000001d8, 0x000001f8 } },
169 { AR5K_RF_GAIN(18), { 0x00000018, 0x00000012 } },
170 { AR5K_RF_GAIN(19), { 0x00000058, 0x00000052 } },
171 { AR5K_RF_GAIN(20), { 0x00000098, 0x00000092 } },
172 { AR5K_RF_GAIN(21), { 0x000001a4, 0x0000017c } },
173 { AR5K_RF_GAIN(22), { 0x000001e4, 0x000001bc } },
174 { AR5K_RF_GAIN(23), { 0x00000024, 0x000001fc } },
175 { AR5K_RF_GAIN(24), { 0x00000064, 0x0000000a } },
176 { AR5K_RF_GAIN(25), { 0x000000a4, 0x0000004a } },
177 { AR5K_RF_GAIN(26), { 0x000000e4, 0x0000008a } },
178 { AR5K_RF_GAIN(27), { 0x0000010a, 0x0000015a } },
179 { AR5K_RF_GAIN(28), { 0x0000014a, 0x0000019a } },
180 { AR5K_RF_GAIN(29), { 0x0000018a, 0x000001da } },
181 { AR5K_RF_GAIN(30), { 0x000001ca, 0x0000000e } },
182 { AR5K_RF_GAIN(31), { 0x0000000a, 0x0000004e } },
183 { AR5K_RF_GAIN(32), { 0x0000004a, 0x0000008e } },
184 { AR5K_RF_GAIN(33), { 0x0000008a, 0x0000015e } },
185 { AR5K_RF_GAIN(34), { 0x000001ba, 0x0000019e } },
186 { AR5K_RF_GAIN(35), { 0x000001fa, 0x000001de } },
187 { AR5K_RF_GAIN(36), { 0x0000003a, 0x00000009 } },
188 { AR5K_RF_GAIN(37), { 0x0000007a, 0x00000049 } },
189 { AR5K_RF_GAIN(38), { 0x00000186, 0x00000089 } },
190 { AR5K_RF_GAIN(39), { 0x000001c6, 0x00000179 } },
191 { AR5K_RF_GAIN(40), { 0x00000006, 0x000001b9 } },
192 { AR5K_RF_GAIN(41), { 0x00000046, 0x000001f9 } },
193 { AR5K_RF_GAIN(42), { 0x00000086, 0x00000039 } },
194 { AR5K_RF_GAIN(43), { 0x000000c6, 0x00000079 } },
195 { AR5K_RF_GAIN(44), { 0x000000c6, 0x000000b9 } },
196 { AR5K_RF_GAIN(45), { 0x000000c6, 0x000001bd } },
197 { AR5K_RF_GAIN(46), { 0x000000c6, 0x000001fd } },
198 { AR5K_RF_GAIN(47), { 0x000000c6, 0x0000003d } },
199 { AR5K_RF_GAIN(48), { 0x000000c6, 0x0000007d } },
200 { AR5K_RF_GAIN(49), { 0x000000c6, 0x000000bd } },
201 { AR5K_RF_GAIN(50), { 0x000000c6, 0x000000fd } },
202 { AR5K_RF_GAIN(51), { 0x000000c6, 0x000000fd } },
203 { AR5K_RF_GAIN(52), { 0x000000c6, 0x000000fd } },
204 { AR5K_RF_GAIN(53), { 0x000000c6, 0x000000fd } },
205 { AR5K_RF_GAIN(54), { 0x000000c6, 0x000000fd } },
206 { AR5K_RF_GAIN(55), { 0x000000c6, 0x000000fd } },
207 { AR5K_RF_GAIN(56), { 0x000000c6, 0x000000fd } },
208 { AR5K_RF_GAIN(57), { 0x000000c6, 0x000000fd } },
209 { AR5K_RF_GAIN(58), { 0x000000c6, 0x000000fd } },
210 { AR5K_RF_GAIN(59), { 0x000000c6, 0x000000fd } },
211 { AR5K_RF_GAIN(60), { 0x000000c6, 0x000000fd } },
212 { AR5K_RF_GAIN(61), { 0x000000c6, 0x000000fd } },
213 { AR5K_RF_GAIN(62), { 0x000000c6, 0x000000fd } },
214 { AR5K_RF_GAIN(63), { 0x000000c6, 0x000000fd } },
217 static const struct ath5k_gain_opt rfgain_opt_5111 = {
221 { { 4, 1, 1, 1 }, 6 },
222 { { 4, 0, 1, 1 }, 4 },
223 { { 3, 1, 1, 1 }, 3 },
224 { { 4, 0, 0, 1 }, 1 },
225 { { 4, 1, 1, 0 }, 0 },
226 { { 4, 0, 1, 0 }, -2 },
227 { { 3, 1, 1, 0 }, -3 },
228 { { 4, 0, 0, 0 }, -4 },
229 { { 2, 1, 1, 0 }, -6 }
233 /* RF5112 mode-specific init registers */
234 static const struct ath5k_ini_rf rfregs_5112[] = {
236 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
237 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
239 { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
241 { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
243 { 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000 } },
245 { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
247 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
249 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
251 { 0x00660000, 0x00660000, 0x00660000, 0x00660000, 0x00660000 } },
253 { 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000 } },
255 { 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000 } },
257 { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
259 { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
261 { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } },
263 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
265 { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
267 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
269 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
271 { 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000 } },
273 { 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000 } },
275 { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
277 { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },
279 { 0x00640000, 0x00640000, 0x00640000, 0x00640000, 0x00640000 } },
281 { 0x00200000, 0x00200000, 0x00200000, 0x00200000, 0x00200000 } },
283 { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
285 { 0x00250000, 0x00250000, 0x00250000, 0x00250000, 0x00250000 } },
287 { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
289 { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
291 { 0x00510000, 0x00510000, 0x00510000, 0x00510000, 0x00510000 } },
293 { 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000 } },
295 { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
297 { 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000 } },
299 { 0x00400000, 0x00400000, 0x00400000, 0x00400000, 0x00400000 } },
301 { 0x03090000, 0x03090000, 0x03090000, 0x03090000, 0x03090000 } },
303 { 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0x06000000 } },
305 { 0x000000b0, 0x000000b0, 0x000000a8, 0x000000a8, 0x000000a8 } },
307 { 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e } },
309 { 0x006c4a41, 0x006c4a41, 0x006c4af1, 0x006c4a61, 0x006c4a61 } },
311 { 0x0050892a, 0x0050892a, 0x0050892b, 0x0050892b, 0x0050892b } },
313 { 0x00842400, 0x00842400, 0x00842400, 0x00842400, 0x00842400 } },
315 { 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200 } },
317 { 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c } },
319 { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
321 { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
323 { 0x0000000a, 0x0000000a, 0x00000012, 0x00000012, 0x00000012 } },
325 { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
327 { 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1 } },
329 { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
331 { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
333 { 0x00000022, 0x00000022, 0x00000022, 0x00000022, 0x00000022 } },
335 { 0x00000092, 0x00000092, 0x00000092, 0x00000092, 0x00000092 } },
337 { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
339 { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
341 { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
343 { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
346 /* RF5112A mode-specific init registers */
347 static const struct ath5k_ini_rf rfregs_5112a[] = {
349 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
350 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
352 { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
354 { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
356 { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } },
358 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
360 { 0x00800000, 0x00800000, 0x00800000, 0x00800000, 0x00800000 } },
362 { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
364 { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } },
366 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
368 { 0x00180000, 0x00180000, 0x00180000, 0x00180000, 0x00180000 } },
370 { 0x00600000, 0x00600000, 0x006e0000, 0x006e0000, 0x006e0000 } },
372 { 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000 } },
374 { 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000 } },
376 { 0x04480000, 0x04480000, 0x04480000, 0x04480000, 0x04480000 } },
378 { 0x00220000, 0x00220000, 0x00220000, 0x00220000, 0x00220000 } },
380 { 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000 } },
382 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
384 { 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000 } },
386 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
388 { 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000 } },
390 { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
392 { 0x00190000, 0x00190000, 0x00190000, 0x00190000, 0x00190000 } },
394 { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
396 { 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000 } },
398 { 0x00990000, 0x00990000, 0x00990000, 0x00990000, 0x00990000 } },
400 { 0x00500000, 0x00500000, 0x00500000, 0x00500000, 0x00500000 } },
402 { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
404 { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
406 { 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000 } },
408 { 0x01740000, 0x01740000, 0x01740000, 0x01740000, 0x01740000 } },
410 { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
412 { 0x86280000, 0x86280000, 0x86280000, 0x86280000, 0x86280000 } },
414 { 0x31840000, 0x31840000, 0x31840000, 0x31840000, 0x31840000 } },
416 { 0x00020080, 0x00020080, 0x00020080, 0x00020080, 0x00020080 } },
418 { 0x00080009, 0x00080009, 0x00080009, 0x00080009, 0x00080009 } },
420 { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
422 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
424 { 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2 } },
426 { 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084 } },
428 { 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4 } },
430 { 0x00119220, 0x00119220, 0x00119220, 0x00119220, 0x00119220 } },
432 { 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800 } },
434 { 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230 } },
436 { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
438 { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
440 { 0x00000012, 0x00000012, 0x00000012, 0x00000012, 0x00000012 } },
442 { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
444 { 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9 } },
446 { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
448 { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
450 { 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2 } },
452 { 0x00000052, 0x00000052, 0x00000052, 0x00000052, 0x00000052 } },
454 { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
456 { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
458 { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
460 { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
464 static const struct ath5k_ini_rf rfregs_2112a[] = {
465 { 1, AR5K_RF_BUFFER_CONTROL_4,
466 /* mode b mode g mode gTurbo */
467 { 0x00000020, 0x00000020, 0x00000020 } },
468 { 2, AR5K_RF_BUFFER_CONTROL_3,
469 { 0x03060408, 0x03060408, 0x03070408 } },
470 { 3, AR5K_RF_BUFFER_CONTROL_6,
471 { 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
473 { 0x0a000000, 0x0a000000, 0x0a000000 } },
475 { 0x00000000, 0x00000000, 0x00000000 } },
477 { 0x00800000, 0x00800000, 0x00800000 } },
479 { 0x002a0000, 0x002a0000, 0x002a0000 } },
481 { 0x00010000, 0x00010000, 0x00010000 } },
483 { 0x00000000, 0x00000000, 0x00000000 } },
485 { 0x00180000, 0x00180000, 0x00180000 } },
487 { 0x006e0000, 0x006e0000, 0x006e0000 } },
489 { 0x00c70000, 0x00c70000, 0x00c70000 } },
491 { 0x004b0000, 0x004b0000, 0x004b0000 } },
493 { 0x04480000, 0x04480000, 0x04480000 } },
495 { 0x002a0000, 0x002a0000, 0x002a0000 } },
497 { 0x00e40000, 0x00e40000, 0x00e40000 } },
499 { 0x00000000, 0x00000000, 0x00000000 } },
501 { 0x00fc0000, 0x00fc0000, 0x00fc0000 } },
503 { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
505 { 0x043f0000, 0x043f0000, 0x043f0000 } },
507 { 0x0c0c0000, 0x0c0c0000, 0x0c0c0000 } },
509 { 0x02190000, 0x02190000, 0x02190000 } },
511 { 0x00240000, 0x00240000, 0x00240000 } },
513 { 0x00b40000, 0x00b40000, 0x00b40000 } },
515 { 0x00990000, 0x00990000, 0x00990000 } },
517 { 0x00500000, 0x00500000, 0x00500000 } },
519 { 0x002a0000, 0x002a0000, 0x002a0000 } },
521 { 0x00120000, 0x00120000, 0x00120000 } },
523 { 0xc0320000, 0xc0320000, 0xc0320000 } },
525 { 0x01740000, 0x01740000, 0x01740000 } },
527 { 0x00110000, 0x00110000, 0x00110000 } },
529 { 0x86280000, 0x86280000, 0x86280000 } },
531 { 0x31840000, 0x31840000, 0x31840000 } },
533 { 0x00f20080, 0x00f20080, 0x00f20080 } },
535 { 0x00070019, 0x00070019, 0x00070019 } },
537 { 0x00000000, 0x00000000, 0x00000000 } },
539 { 0x00000000, 0x00000000, 0x00000000 } },
541 { 0x000000b2, 0x000000b2, 0x000000b2 } },
543 { 0x00b02184, 0x00b02184, 0x00b02184 } },
545 { 0x004125a4, 0x004125a4, 0x004125a4 } },
547 { 0x00119220, 0x00119220, 0x00119220 } },
549 { 0x001a4800, 0x001a4800, 0x001a4800 } },
550 { 6, AR5K_RF_BUFFER_CONTROL_5,
551 { 0x000b0230, 0x000b0230, 0x000b0230 } },
553 { 0x00000094, 0x00000094, 0x00000094 } },
555 { 0x00000091, 0x00000091, 0x00000091 } },
557 { 0x00000012, 0x00000012, 0x00000012 } },
559 { 0x00000080, 0x00000080, 0x00000080 } },
561 { 0x000000d9, 0x000000d9, 0x000000d9 } },
563 { 0x00000060, 0x00000060, 0x00000060 } },
565 { 0x000000f0, 0x000000f0, 0x000000f0 } },
567 { 0x000000a2, 0x000000a2, 0x000000a2 } },
569 { 0x00000052, 0x00000052, 0x00000052 } },
571 { 0x000000d4, 0x000000d4, 0x000000d4 } },
573 { 0x000014cc, 0x000014cc, 0x000014cc } },
575 { 0x0000048c, 0x0000048c, 0x0000048c } },
576 { 7, AR5K_RF_BUFFER_CONTROL_1,
577 { 0x00000003, 0x00000003, 0x00000003 } },
580 /* RF5413/5414 mode-specific init registers */
581 static const struct ath5k_ini_rf rfregs_5413[] = {
583 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
584 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
586 { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } },
588 { 0x00a000c0, 0x00a000c0, 0x00e000c0, 0x00e000c0, 0x00e000c0 } },
590 { 0x33000000, 0x33000000, 0x33000000, 0x33000000, 0x33000000 } },
592 { 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000 } },
594 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
596 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
598 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
600 { 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000 } },
602 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
604 { 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000 } },
606 { 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000 } },
608 { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },
610 { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } },
612 { 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000 } },
614 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
616 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
618 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
620 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
622 { 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000 } },
624 { 0x00610000, 0x00610000, 0x00610000, 0x00610000, 0x00610000 } },
626 { 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000 } },
628 { 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000 } },
630 { 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000 } },
632 { 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000 } },
634 { 0x00770000, 0x00770000, 0x00770000, 0x00770000, 0x00770000 } },
636 { 0x00440000, 0x00440000, 0x00440000, 0x00440000, 0x00440000 } },
638 { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } },
640 { 0x00100080, 0x00100080, 0x00100080, 0x00100080, 0x00100080 } },
642 { 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034 } },
644 { 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0 } },
646 { 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f } },
648 { 0x00510040, 0x00510040, 0x005100a0, 0x005100a0, 0x005100a0 } },
650 { 0x0050006a, 0x0050006a, 0x005000dd, 0x005000dd, 0x005000dd } },
652 { 0x00000001, 0x00000001, 0x00000000, 0x00000000, 0x00000000 } },
654 { 0x00004044, 0x00004044, 0x00004044, 0x00004044, 0x00004044 } },
656 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
658 { 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0 } },
660 { 0x00002c00, 0x00002c00, 0x00003600, 0x00003600, 0x00003600 } },
662 { 0x00000403, 0x00000403, 0x00040403, 0x00040403, 0x00040403 } },
664 { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
666 { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
668 { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
671 /* RF2413/2414 mode-specific init registers */
672 static const struct ath5k_ini_rf rfregs_2413[] = {
673 { 1, AR5K_RF_BUFFER_CONTROL_4,
674 /* mode b mode g mode gTurbo */
675 { 0x00000020, 0x00000020, 0x00000020 } },
676 { 2, AR5K_RF_BUFFER_CONTROL_3,
677 { 0x02001408, 0x02001408, 0x02001408 } },
678 { 3, AR5K_RF_BUFFER_CONTROL_6,
679 { 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
681 { 0xf0000000, 0xf0000000, 0xf0000000 } },
683 { 0x00000000, 0x00000000, 0x00000000 } },
685 { 0x03000000, 0x03000000, 0x03000000 } },
687 { 0x00000000, 0x00000000, 0x00000000 } },
689 { 0x00000000, 0x00000000, 0x00000000 } },
691 { 0x00000000, 0x00000000, 0x00000000 } },
693 { 0x00000000, 0x00000000, 0x00000000 } },
695 { 0x00000000, 0x00000000, 0x00000000 } },
697 { 0x40400000, 0x40400000, 0x40400000 } },
699 { 0x65050000, 0x65050000, 0x65050000 } },
701 { 0x00000000, 0x00000000, 0x00000000 } },
703 { 0x00000000, 0x00000000, 0x00000000 } },
705 { 0x00420000, 0x00420000, 0x00420000 } },
707 { 0x00b50000, 0x00b50000, 0x00b50000 } },
709 { 0x00030000, 0x00030000, 0x00030000 } },
711 { 0x00f70000, 0x00f70000, 0x00f70000 } },
713 { 0x009d0000, 0x009d0000, 0x009d0000 } },
715 { 0x00220000, 0x00220000, 0x00220000 } },
717 { 0x04220000, 0x04220000, 0x04220000 } },
719 { 0x00230018, 0x00230018, 0x00230018 } },
721 { 0x00280050, 0x00280050, 0x00280050 } },
723 { 0x005000c3, 0x005000c3, 0x005000c3 } },
725 { 0x0004007f, 0x0004007f, 0x0004007f } },
727 { 0x00000458, 0x00000458, 0x00000458 } },
729 { 0x00000000, 0x00000000, 0x00000000 } },
731 { 0x0000c000, 0x0000c000, 0x0000c000 } },
732 { 6, AR5K_RF_BUFFER_CONTROL_5,
733 { 0x00400230, 0x00400230, 0x00400230 } },
735 { 0x00006400, 0x00006400, 0x00006400 } },
737 { 0x00000800, 0x00000800, 0x00000800 } },
738 { 7, AR5K_RF_BUFFER_CONTROL_2,
739 { 0x0000000e, 0x0000000e, 0x0000000e } },
742 /* RF2425 mode-specific init registers */
743 static const struct ath5k_ini_rf rfregs_2425[] = {
744 { 1, AR5K_RF_BUFFER_CONTROL_4,
745 /* mode g mode gTurbo */
746 { 0x00000020, 0x00000020 } },
747 { 2, AR5K_RF_BUFFER_CONTROL_3,
748 { 0x02001408, 0x02001408 } },
749 { 3, AR5K_RF_BUFFER_CONTROL_6,
750 { 0x00e020c0, 0x00e020c0 } },
752 { 0x10000000, 0x10000000 } },
754 { 0x00000000, 0x00000000 } },
756 { 0x00000000, 0x00000000 } },
758 { 0x00000000, 0x00000000 } },
760 { 0x00000000, 0x00000000 } },
762 { 0x00000000, 0x00000000 } },
764 { 0x00000000, 0x00000000 } },
766 { 0x00000000, 0x00000000 } },
768 { 0x00000000, 0x00000000 } },
770 { 0x00000000, 0x00000000 } },
772 { 0x00000000, 0x00000000 } },
774 { 0x002a0000, 0x002a0000 } },
776 { 0x00000000, 0x00000000 } },
778 { 0x00000000, 0x00000000 } },
780 { 0x00100000, 0x00100000 } },
782 { 0x00020000, 0x00020000 } },
784 { 0x00730000, 0x00730000 } },
786 { 0x00f80000, 0x00f80000 } },
788 { 0x00e70000, 0x00e70000 } },
790 { 0x00140000, 0x00140000 } },
792 { 0x00910040, 0x00910040 } },
794 { 0x0007001a, 0x0007001a } },
796 { 0x00410000, 0x00410000 } },
798 { 0x00810060, 0x00810060 } },
800 { 0x00020803, 0x00020803 } },
802 { 0x00000000, 0x00000000 } },
804 { 0x00000000, 0x00000000 } },
806 { 0x00001660, 0x00001660 } },
808 { 0x00001688, 0x00001688 } },
809 { 6, AR5K_RF_BUFFER_CONTROL_1,
810 { 0x00000001, 0x00000001 } },
812 { 0x00006400, 0x00006400 } },
814 { 0x00000800, 0x00000800 } },
815 { 7, AR5K_RF_BUFFER_CONTROL_2,
816 { 0x0000000e, 0x0000000e } },
819 /* Initial RF Gain settings for RF5112 */
820 static const struct ath5k_ini_rfgain rfgain_5112[] = {
822 { AR5K_RF_GAIN(0), { 0x00000007, 0x00000007 } },
823 { AR5K_RF_GAIN(1), { 0x00000047, 0x00000047 } },
824 { AR5K_RF_GAIN(2), { 0x00000087, 0x00000087 } },
825 { AR5K_RF_GAIN(3), { 0x000001a0, 0x000001a0 } },
826 { AR5K_RF_GAIN(4), { 0x000001e0, 0x000001e0 } },
827 { AR5K_RF_GAIN(5), { 0x00000020, 0x00000020 } },
828 { AR5K_RF_GAIN(6), { 0x00000060, 0x00000060 } },
829 { AR5K_RF_GAIN(7), { 0x000001a1, 0x000001a1 } },
830 { AR5K_RF_GAIN(8), { 0x000001e1, 0x000001e1 } },
831 { AR5K_RF_GAIN(9), { 0x00000021, 0x00000021 } },
832 { AR5K_RF_GAIN(10), { 0x00000061, 0x00000061 } },
833 { AR5K_RF_GAIN(11), { 0x00000162, 0x00000162 } },
834 { AR5K_RF_GAIN(12), { 0x000001a2, 0x000001a2 } },
835 { AR5K_RF_GAIN(13), { 0x000001e2, 0x000001e2 } },
836 { AR5K_RF_GAIN(14), { 0x00000022, 0x00000022 } },
837 { AR5K_RF_GAIN(15), { 0x00000062, 0x00000062 } },
838 { AR5K_RF_GAIN(16), { 0x00000163, 0x00000163 } },
839 { AR5K_RF_GAIN(17), { 0x000001a3, 0x000001a3 } },
840 { AR5K_RF_GAIN(18), { 0x000001e3, 0x000001e3 } },
841 { AR5K_RF_GAIN(19), { 0x00000023, 0x00000023 } },
842 { AR5K_RF_GAIN(20), { 0x00000063, 0x00000063 } },
843 { AR5K_RF_GAIN(21), { 0x00000184, 0x00000184 } },
844 { AR5K_RF_GAIN(22), { 0x000001c4, 0x000001c4 } },
845 { AR5K_RF_GAIN(23), { 0x00000004, 0x00000004 } },
846 { AR5K_RF_GAIN(24), { 0x000001ea, 0x0000000b } },
847 { AR5K_RF_GAIN(25), { 0x0000002a, 0x0000004b } },
848 { AR5K_RF_GAIN(26), { 0x0000006a, 0x0000008b } },
849 { AR5K_RF_GAIN(27), { 0x000000aa, 0x000001ac } },
850 { AR5K_RF_GAIN(28), { 0x000001ab, 0x000001ec } },
851 { AR5K_RF_GAIN(29), { 0x000001eb, 0x0000002c } },
852 { AR5K_RF_GAIN(30), { 0x0000002b, 0x00000012 } },
853 { AR5K_RF_GAIN(31), { 0x0000006b, 0x00000052 } },
854 { AR5K_RF_GAIN(32), { 0x000000ab, 0x00000092 } },
855 { AR5K_RF_GAIN(33), { 0x000001ac, 0x00000193 } },
856 { AR5K_RF_GAIN(34), { 0x000001ec, 0x000001d3 } },
857 { AR5K_RF_GAIN(35), { 0x0000002c, 0x00000013 } },
858 { AR5K_RF_GAIN(36), { 0x0000003a, 0x00000053 } },
859 { AR5K_RF_GAIN(37), { 0x0000007a, 0x00000093 } },
860 { AR5K_RF_GAIN(38), { 0x000000ba, 0x00000194 } },
861 { AR5K_RF_GAIN(39), { 0x000001bb, 0x000001d4 } },
862 { AR5K_RF_GAIN(40), { 0x000001fb, 0x00000014 } },
863 { AR5K_RF_GAIN(41), { 0x0000003b, 0x0000003a } },
864 { AR5K_RF_GAIN(42), { 0x0000007b, 0x0000007a } },
865 { AR5K_RF_GAIN(43), { 0x000000bb, 0x000000ba } },
866 { AR5K_RF_GAIN(44), { 0x000001bc, 0x000001bb } },
867 { AR5K_RF_GAIN(45), { 0x000001fc, 0x000001fb } },
868 { AR5K_RF_GAIN(46), { 0x0000003c, 0x0000003b } },
869 { AR5K_RF_GAIN(47), { 0x0000007c, 0x0000007b } },
870 { AR5K_RF_GAIN(48), { 0x000000bc, 0x000000bb } },
871 { AR5K_RF_GAIN(49), { 0x000000fc, 0x000001bc } },
872 { AR5K_RF_GAIN(50), { 0x000000fc, 0x000001fc } },
873 { AR5K_RF_GAIN(51), { 0x000000fc, 0x0000003c } },
874 { AR5K_RF_GAIN(52), { 0x000000fc, 0x0000007c } },
875 { AR5K_RF_GAIN(53), { 0x000000fc, 0x000000bc } },
876 { AR5K_RF_GAIN(54), { 0x000000fc, 0x000000fc } },
877 { AR5K_RF_GAIN(55), { 0x000000fc, 0x000000fc } },
878 { AR5K_RF_GAIN(56), { 0x000000fc, 0x000000fc } },
879 { AR5K_RF_GAIN(57), { 0x000000fc, 0x000000fc } },
880 { AR5K_RF_GAIN(58), { 0x000000fc, 0x000000fc } },
881 { AR5K_RF_GAIN(59), { 0x000000fc, 0x000000fc } },
882 { AR5K_RF_GAIN(60), { 0x000000fc, 0x000000fc } },
883 { AR5K_RF_GAIN(61), { 0x000000fc, 0x000000fc } },
884 { AR5K_RF_GAIN(62), { 0x000000fc, 0x000000fc } },
885 { AR5K_RF_GAIN(63), { 0x000000fc, 0x000000fc } },
888 /* Initial RF Gain settings for RF5413 */
889 static const struct ath5k_ini_rfgain rfgain_5413[] = {
891 { AR5K_RF_GAIN(0), { 0x00000000, 0x00000000 } },
892 { AR5K_RF_GAIN(1), { 0x00000040, 0x00000040 } },
893 { AR5K_RF_GAIN(2), { 0x00000080, 0x00000080 } },
894 { AR5K_RF_GAIN(3), { 0x000001a1, 0x00000161 } },
895 { AR5K_RF_GAIN(4), { 0x000001e1, 0x000001a1 } },
896 { AR5K_RF_GAIN(5), { 0x00000021, 0x000001e1 } },
897 { AR5K_RF_GAIN(6), { 0x00000061, 0x00000021 } },
898 { AR5K_RF_GAIN(7), { 0x00000188, 0x00000061 } },
899 { AR5K_RF_GAIN(8), { 0x000001c8, 0x00000188 } },
900 { AR5K_RF_GAIN(9), { 0x00000008, 0x000001c8 } },
901 { AR5K_RF_GAIN(10), { 0x00000048, 0x00000008 } },
902 { AR5K_RF_GAIN(11), { 0x00000088, 0x00000048 } },
903 { AR5K_RF_GAIN(12), { 0x000001a9, 0x00000088 } },
904 { AR5K_RF_GAIN(13), { 0x000001e9, 0x00000169 } },
905 { AR5K_RF_GAIN(14), { 0x00000029, 0x000001a9 } },
906 { AR5K_RF_GAIN(15), { 0x00000069, 0x000001e9 } },
907 { AR5K_RF_GAIN(16), { 0x000001d0, 0x00000029 } },
908 { AR5K_RF_GAIN(17), { 0x00000010, 0x00000069 } },
909 { AR5K_RF_GAIN(18), { 0x00000050, 0x00000190 } },
910 { AR5K_RF_GAIN(19), { 0x00000090, 0x000001d0 } },
911 { AR5K_RF_GAIN(20), { 0x000001b1, 0x00000010 } },
912 { AR5K_RF_GAIN(21), { 0x000001f1, 0x00000050 } },
913 { AR5K_RF_GAIN(22), { 0x00000031, 0x00000090 } },
914 { AR5K_RF_GAIN(23), { 0x00000071, 0x00000171 } },
915 { AR5K_RF_GAIN(24), { 0x000001b8, 0x000001b1 } },
916 { AR5K_RF_GAIN(25), { 0x000001f8, 0x000001f1 } },
917 { AR5K_RF_GAIN(26), { 0x00000038, 0x00000031 } },
918 { AR5K_RF_GAIN(27), { 0x00000078, 0x00000071 } },
919 { AR5K_RF_GAIN(28), { 0x00000199, 0x00000198 } },
920 { AR5K_RF_GAIN(29), { 0x000001d9, 0x000001d8 } },
921 { AR5K_RF_GAIN(30), { 0x00000019, 0x00000018 } },
922 { AR5K_RF_GAIN(31), { 0x00000059, 0x00000058 } },
923 { AR5K_RF_GAIN(32), { 0x00000099, 0x00000098 } },
924 { AR5K_RF_GAIN(33), { 0x000000d9, 0x00000179 } },
925 { AR5K_RF_GAIN(34), { 0x000000f9, 0x000001b9 } },
926 { AR5K_RF_GAIN(35), { 0x000000f9, 0x000001f9 } },
927 { AR5K_RF_GAIN(36), { 0x000000f9, 0x00000039 } },
928 { AR5K_RF_GAIN(37), { 0x000000f9, 0x00000079 } },
929 { AR5K_RF_GAIN(38), { 0x000000f9, 0x000000b9 } },
930 { AR5K_RF_GAIN(39), { 0x000000f9, 0x000000f9 } },
931 { AR5K_RF_GAIN(40), { 0x000000f9, 0x000000f9 } },
932 { AR5K_RF_GAIN(41), { 0x000000f9, 0x000000f9 } },
933 { AR5K_RF_GAIN(42), { 0x000000f9, 0x000000f9 } },
934 { AR5K_RF_GAIN(43), { 0x000000f9, 0x000000f9 } },
935 { AR5K_RF_GAIN(44), { 0x000000f9, 0x000000f9 } },
936 { AR5K_RF_GAIN(45), { 0x000000f9, 0x000000f9 } },
937 { AR5K_RF_GAIN(46), { 0x000000f9, 0x000000f9 } },
938 { AR5K_RF_GAIN(47), { 0x000000f9, 0x000000f9 } },
939 { AR5K_RF_GAIN(48), { 0x000000f9, 0x000000f9 } },
940 { AR5K_RF_GAIN(49), { 0x000000f9, 0x000000f9 } },
941 { AR5K_RF_GAIN(50), { 0x000000f9, 0x000000f9 } },
942 { AR5K_RF_GAIN(51), { 0x000000f9, 0x000000f9 } },
943 { AR5K_RF_GAIN(52), { 0x000000f9, 0x000000f9 } },
944 { AR5K_RF_GAIN(53), { 0x000000f9, 0x000000f9 } },
945 { AR5K_RF_GAIN(54), { 0x000000f9, 0x000000f9 } },
946 { AR5K_RF_GAIN(55), { 0x000000f9, 0x000000f9 } },
947 { AR5K_RF_GAIN(56), { 0x000000f9, 0x000000f9 } },
948 { AR5K_RF_GAIN(57), { 0x000000f9, 0x000000f9 } },
949 { AR5K_RF_GAIN(58), { 0x000000f9, 0x000000f9 } },
950 { AR5K_RF_GAIN(59), { 0x000000f9, 0x000000f9 } },
951 { AR5K_RF_GAIN(60), { 0x000000f9, 0x000000f9 } },
952 { AR5K_RF_GAIN(61), { 0x000000f9, 0x000000f9 } },
953 { AR5K_RF_GAIN(62), { 0x000000f9, 0x000000f9 } },
954 { AR5K_RF_GAIN(63), { 0x000000f9, 0x000000f9 } },
957 /* Initial RF Gain settings for RF2413 */
958 static const struct ath5k_ini_rfgain rfgain_2413[] = {
959 { AR5K_RF_GAIN(0), { 0x00000000 } },
960 { AR5K_RF_GAIN(1), { 0x00000040 } },
961 { AR5K_RF_GAIN(2), { 0x00000080 } },
962 { AR5K_RF_GAIN(3), { 0x00000181 } },
963 { AR5K_RF_GAIN(4), { 0x000001c1 } },
964 { AR5K_RF_GAIN(5), { 0x00000001 } },
965 { AR5K_RF_GAIN(6), { 0x00000041 } },
966 { AR5K_RF_GAIN(7), { 0x00000081 } },
967 { AR5K_RF_GAIN(8), { 0x00000168 } },
968 { AR5K_RF_GAIN(9), { 0x000001a8 } },
969 { AR5K_RF_GAIN(10), { 0x000001e8 } },
970 { AR5K_RF_GAIN(11), { 0x00000028 } },
971 { AR5K_RF_GAIN(12), { 0x00000068 } },
972 { AR5K_RF_GAIN(13), { 0x00000189 } },
973 { AR5K_RF_GAIN(14), { 0x000001c9 } },
974 { AR5K_RF_GAIN(15), { 0x00000009 } },
975 { AR5K_RF_GAIN(16), { 0x00000049 } },
976 { AR5K_RF_GAIN(17), { 0x00000089 } },
977 { AR5K_RF_GAIN(18), { 0x00000190 } },
978 { AR5K_RF_GAIN(19), { 0x000001d0 } },
979 { AR5K_RF_GAIN(20), { 0x00000010 } },
980 { AR5K_RF_GAIN(21), { 0x00000050 } },
981 { AR5K_RF_GAIN(22), { 0x00000090 } },
982 { AR5K_RF_GAIN(23), { 0x00000191 } },
983 { AR5K_RF_GAIN(24), { 0x000001d1 } },
984 { AR5K_RF_GAIN(25), { 0x00000011 } },
985 { AR5K_RF_GAIN(26), { 0x00000051 } },
986 { AR5K_RF_GAIN(27), { 0x00000091 } },
987 { AR5K_RF_GAIN(28), { 0x00000178 } },
988 { AR5K_RF_GAIN(29), { 0x000001b8 } },
989 { AR5K_RF_GAIN(30), { 0x000001f8 } },
990 { AR5K_RF_GAIN(31), { 0x00000038 } },
991 { AR5K_RF_GAIN(32), { 0x00000078 } },
992 { AR5K_RF_GAIN(33), { 0x00000199 } },
993 { AR5K_RF_GAIN(34), { 0x000001d9 } },
994 { AR5K_RF_GAIN(35), { 0x00000019 } },
995 { AR5K_RF_GAIN(36), { 0x00000059 } },
996 { AR5K_RF_GAIN(37), { 0x00000099 } },
997 { AR5K_RF_GAIN(38), { 0x000000d9 } },
998 { AR5K_RF_GAIN(39), { 0x000000f9 } },
999 { AR5K_RF_GAIN(40), { 0x000000f9 } },
1000 { AR5K_RF_GAIN(41), { 0x000000f9 } },
1001 { AR5K_RF_GAIN(42), { 0x000000f9 } },
1002 { AR5K_RF_GAIN(43), { 0x000000f9 } },
1003 { AR5K_RF_GAIN(44), { 0x000000f9 } },
1004 { AR5K_RF_GAIN(45), { 0x000000f9 } },
1005 { AR5K_RF_GAIN(46), { 0x000000f9 } },
1006 { AR5K_RF_GAIN(47), { 0x000000f9 } },
1007 { AR5K_RF_GAIN(48), { 0x000000f9 } },
1008 { AR5K_RF_GAIN(49), { 0x000000f9 } },
1009 { AR5K_RF_GAIN(50), { 0x000000f9 } },
1010 { AR5K_RF_GAIN(51), { 0x000000f9 } },
1011 { AR5K_RF_GAIN(52), { 0x000000f9 } },
1012 { AR5K_RF_GAIN(53), { 0x000000f9 } },
1013 { AR5K_RF_GAIN(54), { 0x000000f9 } },
1014 { AR5K_RF_GAIN(55), { 0x000000f9 } },
1015 { AR5K_RF_GAIN(56), { 0x000000f9 } },
1016 { AR5K_RF_GAIN(57), { 0x000000f9 } },
1017 { AR5K_RF_GAIN(58), { 0x000000f9 } },
1018 { AR5K_RF_GAIN(59), { 0x000000f9 } },
1019 { AR5K_RF_GAIN(60), { 0x000000f9 } },
1020 { AR5K_RF_GAIN(61), { 0x000000f9 } },
1021 { AR5K_RF_GAIN(62), { 0x000000f9 } },
1022 { AR5K_RF_GAIN(63), { 0x000000f9 } },
1025 /* Initial RF Gain settings for RF2425 */
1026 static const struct ath5k_ini_rfgain rfgain_2425[] = {
1027 { AR5K_RF_GAIN(0), { 0x00000000 } },
1028 { AR5K_RF_GAIN(1), { 0x00000040 } },
1029 { AR5K_RF_GAIN(2), { 0x00000080 } },
1030 { AR5K_RF_GAIN(3), { 0x00000181 } },
1031 { AR5K_RF_GAIN(4), { 0x000001c1 } },
1032 { AR5K_RF_GAIN(5), { 0x00000001 } },
1033 { AR5K_RF_GAIN(6), { 0x00000041 } },
1034 { AR5K_RF_GAIN(7), { 0x00000081 } },
1035 { AR5K_RF_GAIN(8), { 0x00000188 } },
1036 { AR5K_RF_GAIN(9), { 0x000001c8 } },
1037 { AR5K_RF_GAIN(10), { 0x00000008 } },
1038 { AR5K_RF_GAIN(11), { 0x00000048 } },
1039 { AR5K_RF_GAIN(12), { 0x00000088 } },
1040 { AR5K_RF_GAIN(13), { 0x00000189 } },
1041 { AR5K_RF_GAIN(14), { 0x000001c9 } },
1042 { AR5K_RF_GAIN(15), { 0x00000009 } },
1043 { AR5K_RF_GAIN(16), { 0x00000049 } },
1044 { AR5K_RF_GAIN(17), { 0x00000089 } },
1045 { AR5K_RF_GAIN(18), { 0x000001b0 } },
1046 { AR5K_RF_GAIN(19), { 0x000001f0 } },
1047 { AR5K_RF_GAIN(20), { 0x00000030 } },
1048 { AR5K_RF_GAIN(21), { 0x00000070 } },
1049 { AR5K_RF_GAIN(22), { 0x00000171 } },
1050 { AR5K_RF_GAIN(23), { 0x000001b1 } },
1051 { AR5K_RF_GAIN(24), { 0x000001f1 } },
1052 { AR5K_RF_GAIN(25), { 0x00000031 } },
1053 { AR5K_RF_GAIN(26), { 0x00000071 } },
1054 { AR5K_RF_GAIN(27), { 0x000001b8 } },
1055 { AR5K_RF_GAIN(28), { 0x000001f8 } },
1056 { AR5K_RF_GAIN(29), { 0x00000038 } },
1057 { AR5K_RF_GAIN(30), { 0x00000078 } },
1058 { AR5K_RF_GAIN(31), { 0x000000b8 } },
1059 { AR5K_RF_GAIN(32), { 0x000001b9 } },
1060 { AR5K_RF_GAIN(33), { 0x000001f9 } },
1061 { AR5K_RF_GAIN(34), { 0x00000039 } },
1062 { AR5K_RF_GAIN(35), { 0x00000079 } },
1063 { AR5K_RF_GAIN(36), { 0x000000b9 } },
1064 { AR5K_RF_GAIN(37), { 0x000000f9 } },
1065 { AR5K_RF_GAIN(38), { 0x000000f9 } },
1066 { AR5K_RF_GAIN(39), { 0x000000f9 } },
1067 { AR5K_RF_GAIN(40), { 0x000000f9 } },
1068 { AR5K_RF_GAIN(41), { 0x000000f9 } },
1069 { AR5K_RF_GAIN(42), { 0x000000f9 } },
1070 { AR5K_RF_GAIN(43), { 0x000000f9 } },
1071 { AR5K_RF_GAIN(44), { 0x000000f9 } },
1072 { AR5K_RF_GAIN(45), { 0x000000f9 } },
1073 { AR5K_RF_GAIN(46), { 0x000000f9 } },
1074 { AR5K_RF_GAIN(47), { 0x000000f9 } },
1075 { AR5K_RF_GAIN(48), { 0x000000f9 } },
1076 { AR5K_RF_GAIN(49), { 0x000000f9 } },
1077 { AR5K_RF_GAIN(50), { 0x000000f9 } },
1078 { AR5K_RF_GAIN(51), { 0x000000f9 } },
1079 { AR5K_RF_GAIN(52), { 0x000000f9 } },
1080 { AR5K_RF_GAIN(53), { 0x000000f9 } },
1081 { AR5K_RF_GAIN(54), { 0x000000f9 } },
1082 { AR5K_RF_GAIN(55), { 0x000000f9 } },
1083 { AR5K_RF_GAIN(56), { 0x000000f9 } },
1084 { AR5K_RF_GAIN(57), { 0x000000f9 } },
1085 { AR5K_RF_GAIN(58), { 0x000000f9 } },
1086 { AR5K_RF_GAIN(59), { 0x000000f9 } },
1087 { AR5K_RF_GAIN(60), { 0x000000f9 } },
1088 { AR5K_RF_GAIN(61), { 0x000000f9 } },
1089 { AR5K_RF_GAIN(62), { 0x000000f9 } },
1090 { AR5K_RF_GAIN(63), { 0x000000f9 } },
1093 static const struct ath5k_gain_opt rfgain_opt_5112 = {
1097 { { 3, 0, 0, 0, 0, 0, 0 }, 6 },
1098 { { 2, 0, 0, 0, 0, 0, 0 }, 0 },
1099 { { 1, 0, 0, 0, 0, 0, 0 }, -3 },
1100 { { 0, 0, 0, 0, 0, 0, 0 }, -6 },
1101 { { 0, 1, 1, 0, 0, 0, 0 }, -8 },
1102 { { 0, 1, 1, 0, 1, 1, 0 }, -10 },
1103 { { 0, 1, 0, 1, 1, 1, 0 }, -13 },
1104 { { 0, 1, 0, 1, 1, 0, 1 }, -16 },
1109 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
1111 static unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits,
1112 u32 first, u32 col, bool set)
1114 u32 mask, entry, last, data, shift, position;
1121 /* should not happen */
1124 if (!(col <= 3 && bits <= 32 && first + bits <= 319)) {
1125 ATH5K_PRINTF("invalid values at offset %u\n", offset);
1129 entry = ((first - 1) / 8) + offset;
1130 position = (first - 1) % 8;
1133 data = ath5k_hw_bitswap(reg, bits);
1135 for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) {
1136 last = (position + left > 8) ? 8 : position + left;
1137 mask = (((1 << last) - 1) ^ ((1 << position) - 1)) << (col * 8);
1141 rf[entry] |= ((data << position) << (col * 8)) & mask;
1142 data >>= (8 - position);
1144 data = (((rf[entry] & mask) >> (col * 8)) >> position)
1146 shift += last - position;
1149 left -= 8 - position;
1152 data = set ? 1 : ath5k_hw_bitswap(data, bits);
1157 static u32 ath5k_hw_rfregs_gainf_corr(struct ath5k_hw *ah)
1162 if (ah->ah_rf_banks == NULL)
1165 rf = ah->ah_rf_banks;
1166 ah->ah_gain.g_f_corr = 0;
1168 if (ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 1, 36, 0, false) != 1)
1171 step = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 4, 32, 0, false);
1172 mix = ah->ah_gain.g_step->gos_param[0];
1176 ah->ah_gain.g_f_corr = step * 2;
1179 ah->ah_gain.g_f_corr = (step - 5) * 2;
1182 ah->ah_gain.g_f_corr = step;
1185 ah->ah_gain.g_f_corr = 0;
1189 return ah->ah_gain.g_f_corr;
1192 static bool ath5k_hw_rfregs_gain_readback(struct ath5k_hw *ah)
1194 u32 step, mix, level[4];
1197 if (ah->ah_rf_banks == NULL)
1200 rf = ah->ah_rf_banks;
1202 if (ah->ah_radio == AR5K_RF5111) {
1203 step = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 6, 37, 0,
1206 level[1] = (step == 0x3f) ? 0x32 : step + 4;
1207 level[2] = (step != 0x3f) ? 0x40 : level[0];
1208 level[3] = level[2] + 0x32;
1210 ah->ah_gain.g_high = level[3] -
1211 (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
1212 ah->ah_gain.g_low = level[0] +
1213 (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
1215 mix = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 1, 36, 0,
1217 level[0] = level[2] = 0;
1220 level[1] = level[3] = 83;
1222 level[1] = level[3] = 107;
1223 ah->ah_gain.g_high = 55;
1227 return (ah->ah_gain.g_current >= level[0] &&
1228 ah->ah_gain.g_current <= level[1]) ||
1229 (ah->ah_gain.g_current >= level[2] &&
1230 ah->ah_gain.g_current <= level[3]);
1233 static s32 ath5k_hw_rfregs_gain_adjust(struct ath5k_hw *ah)
1235 const struct ath5k_gain_opt *go;
1238 switch (ah->ah_radio) {
1240 go = &rfgain_opt_5111;
1243 go = &rfgain_opt_5112;
1249 ah->ah_gain.g_step = &go->go_step[ah->ah_gain.g_step_idx];
1251 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {
1252 if (ah->ah_gain.g_step_idx == 0)
1254 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
1255 ah->ah_gain.g_target >= ah->ah_gain.g_high &&
1256 ah->ah_gain.g_step_idx > 0;
1257 ah->ah_gain.g_step =
1258 &go->go_step[ah->ah_gain.g_step_idx])
1259 ah->ah_gain.g_target -= 2 *
1260 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -
1261 ah->ah_gain.g_step->gos_gain);
1267 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {
1268 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))
1270 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
1271 ah->ah_gain.g_target <= ah->ah_gain.g_low &&
1272 ah->ah_gain.g_step_idx < go->go_steps_count-1;
1273 ah->ah_gain.g_step =
1274 &go->go_step[ah->ah_gain.g_step_idx])
1275 ah->ah_gain.g_target -= 2 *
1276 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
1277 ah->ah_gain.g_step->gos_gain);
1284 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1285 "ret %d, gain step %u, current gain %u, target gain %u\n",
1286 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current,
1287 ah->ah_gain.g_target);
1293 * Read EEPROM Calibration data, modify RF Banks and Initialize RF5111
1295 static int ath5k_hw_rf5111_rfregs(struct ath5k_hw *ah,
1296 struct ieee80211_channel *channel, unsigned int mode)
1298 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1300 const unsigned int rf_size = ARRAY_SIZE(rfregs_5111);
1302 int obdb = -1, bank = -1;
1305 AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
1307 rf = ah->ah_rf_banks;
1309 /* Copy values to modify them */
1310 for (i = 0; i < rf_size; i++) {
1311 if (rfregs_5111[i].rf_bank >= AR5K_RF5111_INI_RF_MAX_BANKS) {
1312 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
1316 if (bank != rfregs_5111[i].rf_bank) {
1317 bank = rfregs_5111[i].rf_bank;
1318 ah->ah_offset[bank] = i;
1321 rf[i] = rfregs_5111[i].rf_value[mode];
1325 if (channel->hw_value & CHANNEL_2GHZ) {
1326 if (channel->hw_value & CHANNEL_CCK)
1327 ee_mode = AR5K_EEPROM_MODE_11B;
1329 ee_mode = AR5K_EEPROM_MODE_11G;
1332 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[0],
1333 ee->ee_ob[ee_mode][obdb], 3, 119, 0, true))
1336 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[0],
1337 ee->ee_ob[ee_mode][obdb], 3, 122, 0, true))
1343 /* For 11a, Turbo and XR */
1344 ee_mode = AR5K_EEPROM_MODE_11A;
1345 obdb = channel->center_freq >= 5725 ? 3 :
1346 (channel->center_freq >= 5500 ? 2 :
1347 (channel->center_freq >= 5260 ? 1 :
1348 (channel->center_freq > 4000 ? 0 : -1)));
1350 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1351 ee->ee_pwd_84, 1, 51, 3, true))
1354 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1355 ee->ee_pwd_90, 1, 45, 3, true))
1359 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1360 !ee->ee_xpd[ee_mode], 1, 95, 0, true))
1363 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1364 ee->ee_x_gain[ee_mode], 4, 96, 0, true))
1367 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6], obdb >= 0 ?
1368 ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, true))
1371 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6], obdb >= 0 ?
1372 ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, true))
1376 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
1377 ee->ee_i_gain[ee_mode], 6, 29, 0, true))
1380 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
1381 ee->ee_xpd[ee_mode], 1, 4, 0, true))
1384 /* Write RF values */
1385 for (i = 0; i < rf_size; i++) {
1387 ath5k_hw_reg_write(ah, rf[i], rfregs_5111[i].rf_register);
1394 * Read EEPROM Calibration data, modify RF Banks and Initialize RF5112
1396 static int ath5k_hw_rf5112_rfregs(struct ath5k_hw *ah,
1397 struct ieee80211_channel *channel, unsigned int mode)
1399 const struct ath5k_ini_rf *rf_ini;
1400 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1402 unsigned int rf_size, i;
1403 int obdb = -1, bank = -1;
1406 AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
1408 rf = ah->ah_rf_banks;
1410 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_2112A
1411 && !test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) {
1412 rf_ini = rfregs_2112a;
1413 rf_size = ARRAY_SIZE(rfregs_5112a);
1415 ATH5K_ERR(ah->ah_sc,"invalid channel mode: %i\n",mode);
1418 mode = mode - 2; /*no a/turboa modes for 2112*/
1419 } else if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
1420 rf_ini = rfregs_5112a;
1421 rf_size = ARRAY_SIZE(rfregs_5112a);
1423 rf_ini = rfregs_5112;
1424 rf_size = ARRAY_SIZE(rfregs_5112);
1427 /* Copy values to modify them */
1428 for (i = 0; i < rf_size; i++) {
1429 if (rf_ini[i].rf_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) {
1430 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
1434 if (bank != rf_ini[i].rf_bank) {
1435 bank = rf_ini[i].rf_bank;
1436 ah->ah_offset[bank] = i;
1439 rf[i] = rf_ini[i].rf_value[mode];
1443 if (channel->hw_value & CHANNEL_2GHZ) {
1444 if (channel->hw_value & CHANNEL_OFDM)
1445 ee_mode = AR5K_EEPROM_MODE_11G;
1447 ee_mode = AR5K_EEPROM_MODE_11B;
1450 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1451 ee->ee_ob[ee_mode][obdb], 3, 287, 0, true))
1454 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1455 ee->ee_ob[ee_mode][obdb], 3, 290, 0, true))
1458 /* For 11a, Turbo and XR */
1459 ee_mode = AR5K_EEPROM_MODE_11A;
1460 obdb = channel->center_freq >= 5725 ? 3 :
1461 (channel->center_freq >= 5500 ? 2 :
1462 (channel->center_freq >= 5260 ? 1 :
1463 (channel->center_freq > 4000 ? 0 : -1)));
1468 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1469 ee->ee_ob[ee_mode][obdb], 3, 279, 0, true))
1472 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1473 ee->ee_ob[ee_mode][obdb], 3, 282, 0, true))
1477 ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1478 ee->ee_x_gain[ee_mode], 2, 270, 0, true);
1479 ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1480 ee->ee_x_gain[ee_mode], 2, 257, 0, true);
1482 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1483 ee->ee_xpd[ee_mode], 1, 302, 0, true))
1487 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
1488 ee->ee_i_gain[ee_mode], 6, 14, 0, true))
1491 /* Write RF values */
1492 for (i = 0; i < rf_size; i++)
1493 ath5k_hw_reg_write(ah, rf[i], rf_ini[i].rf_register);
1499 * Initialize RF5413/5414 and future chips
1500 * (until we come up with a better solution)
1502 static int ath5k_hw_rf5413_rfregs(struct ath5k_hw *ah,
1503 struct ieee80211_channel *channel, unsigned int mode)
1505 const struct ath5k_ini_rf *rf_ini;
1507 unsigned int rf_size, i;
1510 AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
1512 rf = ah->ah_rf_banks;
1514 switch (ah->ah_radio) {
1516 rf_ini = rfregs_5413;
1517 rf_size = ARRAY_SIZE(rfregs_5413);
1520 rf_ini = rfregs_2413;
1521 rf_size = ARRAY_SIZE(rfregs_2413);
1524 ATH5K_ERR(ah->ah_sc,
1525 "invalid channel mode: %i\n", mode);
1532 rf_ini = rfregs_2425;
1533 rf_size = ARRAY_SIZE(rfregs_2425);
1536 ATH5K_ERR(ah->ah_sc,
1537 "invalid channel mode: %i\n", mode);
1552 /* Copy values to modify them */
1553 for (i = 0; i < rf_size; i++) {
1554 if (rf_ini[i].rf_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) {
1555 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
1559 if (bank != rf_ini[i].rf_bank) {
1560 bank = rf_ini[i].rf_bank;
1561 ah->ah_offset[bank] = i;
1564 rf[i] = rf_ini[i].rf_value[mode];
1568 * After compairing dumps from different cards
1569 * we get the same RF_BUFFER settings (diff returns
1570 * 0 lines). It seems that RF_BUFFER settings are static
1571 * and are written unmodified (no EEPROM stuff
1572 * is used because calibration data would be
1573 * different between different cards and would result
1574 * different RF_BUFFER settings)
1577 /* Write RF values */
1578 for (i = 0; i < rf_size; i++)
1579 ath5k_hw_reg_write(ah, rf[i], rf_ini[i].rf_register);
1587 int ath5k_hw_rfregs(struct ath5k_hw *ah, struct ieee80211_channel *channel,
1590 int (*func)(struct ath5k_hw *, struct ieee80211_channel *, unsigned int);
1593 switch (ah->ah_radio) {
1595 ah->ah_rf_banks_size = sizeof(rfregs_5111);
1596 func = ath5k_hw_rf5111_rfregs;
1599 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
1600 ah->ah_rf_banks_size = sizeof(rfregs_5112a);
1602 ah->ah_rf_banks_size = sizeof(rfregs_5112);
1603 func = ath5k_hw_rf5112_rfregs;
1606 ah->ah_rf_banks_size = sizeof(rfregs_5413);
1607 func = ath5k_hw_rf5413_rfregs;
1610 ah->ah_rf_banks_size = sizeof(rfregs_2413);
1611 func = ath5k_hw_rf5413_rfregs;
1614 ah->ah_rf_banks_size = sizeof(rfregs_2425);
1615 func = ath5k_hw_rf5413_rfregs;
1621 if (ah->ah_rf_banks == NULL) {
1622 /* XXX do extra checks? */
1623 ah->ah_rf_banks = kmalloc(ah->ah_rf_banks_size, GFP_KERNEL);
1624 if (ah->ah_rf_banks == NULL) {
1625 ATH5K_ERR(ah->ah_sc, "out of memory\n");
1630 ret = func(ah, channel, mode);
1632 ah->ah_rf_gain = AR5K_RFGAIN_INACTIVE;
1637 int ath5k_hw_rfgain(struct ath5k_hw *ah, unsigned int freq)
1639 const struct ath5k_ini_rfgain *ath5k_rfg;
1640 unsigned int i, size;
1642 switch (ah->ah_radio) {
1644 ath5k_rfg = rfgain_5111;
1645 size = ARRAY_SIZE(rfgain_5111);
1648 ath5k_rfg = rfgain_5112;
1649 size = ARRAY_SIZE(rfgain_5112);
1652 ath5k_rfg = rfgain_5413;
1653 size = ARRAY_SIZE(rfgain_5413);
1656 ath5k_rfg = rfgain_2413;
1657 size = ARRAY_SIZE(rfgain_2413);
1658 freq = 0; /* only 2Ghz */
1661 ath5k_rfg = rfgain_2425;
1662 size = ARRAY_SIZE(rfgain_2425);
1663 freq = 0; /* only 2Ghz */
1670 case AR5K_INI_RFGAIN_2GHZ:
1671 case AR5K_INI_RFGAIN_5GHZ:
1677 for (i = 0; i < size; i++) {
1679 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq],
1680 (u32)ath5k_rfg[i].rfg_register);
1686 enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath5k_hw *ah)
1690 ATH5K_TRACE(ah->ah_sc);
1692 if (ah->ah_rf_banks == NULL || !ah->ah_gain.g_active ||
1693 ah->ah_version <= AR5K_AR5211)
1694 return AR5K_RFGAIN_INACTIVE;
1696 if (ah->ah_rf_gain != AR5K_RFGAIN_READ_REQUESTED)
1699 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
1701 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
1702 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
1703 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
1705 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK)
1706 ah->ah_gain.g_current += AR5K_GAIN_CCK_PROBE_CORR;
1708 if (ah->ah_radio >= AR5K_RF5112) {
1709 ath5k_hw_rfregs_gainf_corr(ah);
1710 ah->ah_gain.g_current =
1711 ah->ah_gain.g_current>=ah->ah_gain.g_f_corr ?
1712 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) :
1716 if (ath5k_hw_rfregs_gain_readback(ah) &&
1717 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
1718 ath5k_hw_rfregs_gain_adjust(ah))
1719 ah->ah_rf_gain = AR5K_RFGAIN_NEED_CHANGE;
1723 return ah->ah_rf_gain;
1726 int ath5k_hw_set_rfgain_opt(struct ath5k_hw *ah)
1728 /* Initialize the gain optimization values */
1729 switch (ah->ah_radio) {
1731 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
1732 ah->ah_gain.g_step =
1733 &rfgain_opt_5111.go_step[ah->ah_gain.g_step_idx];
1734 ah->ah_gain.g_low = 20;
1735 ah->ah_gain.g_high = 35;
1736 ah->ah_gain.g_active = 1;
1739 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
1740 ah->ah_gain.g_step =
1741 &rfgain_opt_5112.go_step[ah->ah_gain.g_step_idx];
1742 ah->ah_gain.g_low = 20;
1743 ah->ah_gain.g_high = 85;
1744 ah->ah_gain.g_active = 1;
1753 /**************************\
1754 PHY/RF channel functions
1755 \**************************/
1758 * Check if a channel is supported
1760 bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
1762 /* Check if the channel is in our supported range */
1763 if (flags & CHANNEL_2GHZ) {
1764 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
1765 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
1767 } else if (flags & CHANNEL_5GHZ)
1768 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
1769 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
1776 * Convertion needed for RF5110
1778 static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
1783 * Convert IEEE channel/MHz to an internal channel value used
1784 * by the AR5210 chipset. This has not been verified with
1785 * newer chipsets like the AR5212A who have a completely
1786 * different RF/PHY part.
1788 athchan = (ath5k_hw_bitswap(
1789 (ieee80211_frequency_to_channel(
1790 channel->center_freq) - 24) / 2, 5)
1791 << 1) | (1 << 6) | 0x1;
1796 * Set channel on RF5110
1798 static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
1799 struct ieee80211_channel *channel)
1804 * Set the channel and wait
1806 data = ath5k_hw_rf5110_chan2athchan(channel);
1807 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
1808 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
1815 * Convertion needed for 5111
1817 static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
1818 struct ath5k_athchan_2ghz *athchan)
1822 /* Cast this value to catch negative channel numbers (>= -19) */
1823 channel = (int)ieee;
1826 * Map 2GHz IEEE channel to 5GHz Atheros channel
1828 if (channel <= 13) {
1829 athchan->a2_athchan = 115 + channel;
1830 athchan->a2_flags = 0x46;
1831 } else if (channel == 14) {
1832 athchan->a2_athchan = 124;
1833 athchan->a2_flags = 0x44;
1834 } else if (channel >= 15 && channel <= 26) {
1835 athchan->a2_athchan = ((channel - 14) * 4) + 132;
1836 athchan->a2_flags = 0x46;
1844 * Set channel on 5111
1846 static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
1847 struct ieee80211_channel *channel)
1849 struct ath5k_athchan_2ghz ath5k_channel_2ghz;
1850 unsigned int ath5k_channel =
1851 ieee80211_frequency_to_channel(channel->center_freq);
1852 u32 data0, data1, clock;
1856 * Set the channel on the RF5111 radio
1860 if (channel->hw_value & CHANNEL_2GHZ) {
1861 /* Map 2GHz channel to 5GHz Atheros channel ID */
1862 ret = ath5k_hw_rf5111_chan2athchan(
1863 ieee80211_frequency_to_channel(channel->center_freq),
1864 &ath5k_channel_2ghz);
1868 ath5k_channel = ath5k_channel_2ghz.a2_athchan;
1869 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
1873 if (ath5k_channel < 145 || !(ath5k_channel & 1)) {
1875 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) |
1876 (clock << 1) | (1 << 10) | 1;
1879 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff)
1880 << 2) | (clock << 1) | (1 << 10) | 1;
1883 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
1885 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
1886 AR5K_RF_BUFFER_CONTROL_3);
1892 * Set channel on 5112 and newer
1894 static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
1895 struct ieee80211_channel *channel)
1897 u32 data, data0, data1, data2;
1900 data = data0 = data1 = data2 = 0;
1901 c = channel->center_freq;
1904 if (!((c - 2224) % 5)) {
1905 data0 = ((2 * (c - 704)) - 3040) / 10;
1907 } else if (!((c - 2192) % 5)) {
1908 data0 = ((2 * (c - 672)) - 3040) / 10;
1913 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
1914 } else if ((c - (c % 5)) != 2 || c > 5435) {
1915 if (!(c % 20) && c >= 5120) {
1916 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1917 data2 = ath5k_hw_bitswap(3, 2);
1918 } else if (!(c % 10)) {
1919 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1920 data2 = ath5k_hw_bitswap(2, 2);
1921 } else if (!(c % 5)) {
1922 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1923 data2 = ath5k_hw_bitswap(1, 2);
1927 data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8);
1928 data2 = ath5k_hw_bitswap(0, 2);
1931 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
1933 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1934 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1940 * Set the channel on the RF2425
1942 static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
1943 struct ieee80211_channel *channel)
1945 u32 data, data0, data2;
1948 data = data0 = data2 = 0;
1949 c = channel->center_freq;
1952 data0 = ath5k_hw_bitswap((c - 2272), 8);
1955 } else if ((c - (c % 5)) != 2 || c > 5435) {
1956 if (!(c % 20) && c < 5120)
1957 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1959 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1961 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1964 data2 = ath5k_hw_bitswap(1, 2);
1966 data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8);
1967 data2 = ath5k_hw_bitswap(0, 2);
1970 data = (data0 << 4) | data2 << 2 | 0x1001;
1972 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1973 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1979 * Set a channel on the radio chip
1981 int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel)
1985 * Check bounds supported by the PHY (we don't care about regultory
1986 * restrictions at this point). Note: hw_value already has the band
1987 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
1988 * of the band by that */
1989 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
1990 ATH5K_ERR(ah->ah_sc,
1991 "channel frequency (%u MHz) out of supported "
1993 channel->center_freq);
1998 * Set the channel and wait
2000 switch (ah->ah_radio) {
2002 ret = ath5k_hw_rf5110_channel(ah, channel);
2005 ret = ath5k_hw_rf5111_channel(ah, channel);
2008 ret = ath5k_hw_rf2425_channel(ah, channel);
2011 ret = ath5k_hw_rf5112_channel(ah, channel);
2018 /* Set JAPAN setting for channel 14 */
2019 if (channel->center_freq == 2484) {
2020 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
2021 AR5K_PHY_CCKTXCTL_JAPAN);
2023 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
2024 AR5K_PHY_CCKTXCTL_WORLD);
2027 ah->ah_current_channel.center_freq = channel->center_freq;
2028 ah->ah_current_channel.hw_value = channel->hw_value;
2029 ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false;
2039 * ath5k_hw_noise_floor_calibration - perform PHY noise floor calibration
2041 * @ah: struct ath5k_hw pointer we are operating on
2042 * @freq: the channel frequency, just used for error logging
2044 * This function performs a noise floor calibration of the PHY and waits for
2045 * it to complete. Then the noise floor value is compared to some maximum
2046 * noise floor we consider valid.
2048 * Note that this is different from what the madwifi HAL does: it reads the
2049 * noise floor and afterwards initiates the calibration. Since the noise floor
2050 * calibration can take some time to finish, depending on the current channel
2051 * use, that avoids the occasional timeout warnings we are seeing now.
2053 * See the following link for an Atheros patent on noise floor calibration:
2054 * http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL \
2055 * &p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7245893.PN.&OS=PN/7
2057 * XXX: Since during noise floor calibration antennas are detached according to
2058 * the patent, we should stop tx queues here.
2061 ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq)
2068 * Enable noise floor calibration
2070 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
2071 AR5K_PHY_AGCCTL_NF);
2073 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
2074 AR5K_PHY_AGCCTL_NF, 0, false);
2076 ATH5K_ERR(ah->ah_sc,
2077 "noise floor calibration timeout (%uMHz)\n", freq);
2081 /* Wait until the noise floor is calibrated and read the value */
2082 for (i = 20; i > 0; i--) {
2084 noise_floor = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
2085 noise_floor = AR5K_PHY_NF_RVAL(noise_floor);
2086 if (noise_floor & AR5K_PHY_NF_ACTIVE) {
2087 noise_floor = AR5K_PHY_NF_AVAL(noise_floor);
2089 if (noise_floor <= AR5K_TUNE_NOISE_FLOOR)
2094 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
2095 "noise floor %d\n", noise_floor);
2097 if (noise_floor > AR5K_TUNE_NOISE_FLOOR) {
2098 ATH5K_ERR(ah->ah_sc,
2099 "noise floor calibration failed (%uMHz)\n", freq);
2103 ah->ah_noise_floor = noise_floor;
2109 * Perform a PHY calibration on RF5110
2110 * -Fix BPSK/QAM Constellation (I/Q correction)
2111 * -Calculate Noise Floor
2113 static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
2114 struct ieee80211_channel *channel)
2116 u32 phy_sig, phy_agc, phy_sat, beacon;
2120 * Disable beacons and RX/TX queues, wait
2122 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
2123 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
2124 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
2125 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
2130 * Set the channel (with AGC turned off)
2132 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
2134 ret = ath5k_hw_channel(ah, channel);
2137 * Activate PHY and wait
2139 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
2142 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
2148 * Calibrate the radio chip
2151 /* Remember normal state */
2152 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
2153 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
2154 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
2156 /* Update radio registers */
2157 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
2158 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
2160 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
2161 AR5K_PHY_AGCCOARSE_LO)) |
2162 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
2163 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
2165 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
2166 AR5K_PHY_ADCSAT_THR)) |
2167 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
2168 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
2172 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
2174 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
2175 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
2180 * Enable calibration and wait until completion
2182 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
2184 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
2185 AR5K_PHY_AGCCTL_CAL, 0, false);
2187 /* Reset to normal state */
2188 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG);
2189 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE);
2190 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT);
2193 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
2194 channel->center_freq);
2198 ret = ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
2203 * Re-enable RX/TX and beacons
2205 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
2206 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
2207 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
2213 * Perform a PHY calibration on RF5111/5112 and newer chips
2215 static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah,
2216 struct ieee80211_channel *channel)
2219 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
2221 ATH5K_TRACE(ah->ah_sc);
2223 if (!ah->ah_calibration ||
2224 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
2227 /* Calibration has finished, get the results and re-run */
2228 for (i = 0; i <= 10; i++) {
2229 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
2230 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
2231 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
2234 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
2235 q_coffd = q_pwr >> 7;
2238 if (i_coffd == 0 || q_coffd == 0)
2241 i_coff = ((-iq_corr) / i_coffd) & 0x3f;
2243 /* Boundary check */
2249 q_coff = (((s32)i_pwr / q_coffd) - 128) & 0x1f;
2251 /* Boundary check */
2257 /* Commit new I/Q value */
2258 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE |
2259 ((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S));
2261 /* Re-enable calibration -if we don't we'll commit
2262 * the same values again and again */
2263 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
2264 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
2265 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN);
2269 /* TODO: Separate noise floor calibration from I/Q calibration
2270 * since noise floor calibration interrupts rx path while I/Q
2271 * calibration doesn't. We don't need to run noise floor calibration
2272 * as often as I/Q calibration.*/
2273 ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
2275 /* Request RF gain */
2276 if (channel->hw_value & CHANNEL_5GHZ) {
2277 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_max,
2278 AR5K_PHY_PAPD_PROBE_TXPOWER) |
2279 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
2280 ah->ah_rf_gain = AR5K_RFGAIN_READ_REQUESTED;
2287 * Perform a PHY calibration
2289 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
2290 struct ieee80211_channel *channel)
2294 if (ah->ah_radio == AR5K_RF5110)
2295 ret = ath5k_hw_rf5110_calibrate(ah, channel);
2297 ret = ath5k_hw_rf511x_calibrate(ah, channel);
2302 int ath5k_hw_phy_disable(struct ath5k_hw *ah)
2304 ATH5K_TRACE(ah->ah_sc);
2306 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
2311 /********************\
2313 \********************/
2316 * Get the PHY Chip revision
2318 u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
2324 ATH5K_TRACE(ah->ah_sc);
2327 * Set the radio chip access register
2331 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
2334 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
2342 /* ...wait until PHY is ready and read the selected radio revision */
2343 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
2345 for (i = 0; i < 8; i++)
2346 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
2348 if (ah->ah_version == AR5K_AR5210) {
2349 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
2350 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
2352 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
2353 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
2354 ((srev & 0x0f) << 4), 8);
2357 /* Reset to the 5GHz mode */
2358 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
2363 void /*TODO:Boundary check*/
2364 ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant)
2366 ATH5K_TRACE(ah->ah_sc);
2368 if (ah->ah_version != AR5K_AR5210)
2369 ath5k_hw_reg_write(ah, ant, AR5K_DEFAULT_ANTENNA);
2372 unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah)
2374 ATH5K_TRACE(ah->ah_sc);
2376 if (ah->ah_version != AR5K_AR5210)
2377 return ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
2379 return false; /*XXX: What do we return for 5210 ?*/
2387 * Initialize the tx power table (not fully implemented)
2389 static void ath5k_txpower_table(struct ath5k_hw *ah,
2390 struct ieee80211_channel *channel, s16 max_power)
2392 unsigned int i, min, max, n;
2393 u16 txpower, *rates;
2395 rates = ah->ah_txpower.txp_rates;
2397 txpower = AR5K_TUNE_DEFAULT_TXPOWER * 2;
2398 if (max_power > txpower)
2399 txpower = max_power > AR5K_TUNE_MAX_TXPOWER ?
2400 AR5K_TUNE_MAX_TXPOWER : max_power;
2402 for (i = 0; i < AR5K_MAX_RATES; i++)
2405 /* XXX setup target powers by rate */
2407 ah->ah_txpower.txp_min = rates[7];
2408 ah->ah_txpower.txp_max = rates[0];
2409 ah->ah_txpower.txp_ofdm = rates[0];
2411 /* Calculate the power table */
2412 n = ARRAY_SIZE(ah->ah_txpower.txp_pcdac);
2413 min = AR5K_EEPROM_PCDAC_START;
2414 max = AR5K_EEPROM_PCDAC_STOP;
2415 for (i = 0; i < n; i += AR5K_EEPROM_PCDAC_STEP)
2416 ah->ah_txpower.txp_pcdac[i] =
2418 min + ((i * (max - min)) / n);
2425 * Set transmition power
2427 int /*O.K. - txpower_table is unimplemented so this doesn't work*/
2428 ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
2429 unsigned int txpower)
2431 bool tpc = ah->ah_txpower.txp_tpc;
2434 ATH5K_TRACE(ah->ah_sc);
2435 if (txpower > AR5K_TUNE_MAX_TXPOWER) {
2436 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower);
2441 * RF2413 for some reason can't
2442 * transmit anything if we call
2443 * this funtion, so we skip it
2444 * until we fix txpower.
2446 * XXX: Assume same for RF2425
2449 if ((ah->ah_radio == AR5K_RF2413) || (ah->ah_radio == AR5K_RF2425))
2452 /* Reset TX power values */
2453 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
2454 ah->ah_txpower.txp_tpc = tpc;
2456 /* Initialize TX power table */
2457 ath5k_txpower_table(ah, channel, txpower);
2460 * Write TX power values
2462 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2463 ath5k_hw_reg_write(ah,
2464 ((((ah->ah_txpower.txp_pcdac[(i << 1) + 1] << 8) | 0xff) & 0xffff) << 16) |
2465 (((ah->ah_txpower.txp_pcdac[(i << 1) ] << 8) | 0xff) & 0xffff),
2466 AR5K_PHY_PCDAC_TXPOWER(i));
2469 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) |
2470 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
2471 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
2473 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) |
2474 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
2475 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
2477 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) |
2478 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
2479 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
2481 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) |
2482 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
2483 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
2485 if (ah->ah_txpower.txp_tpc)
2486 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
2487 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
2489 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX |
2490 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
2495 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, unsigned int power)
2498 struct ieee80211_channel *channel = &ah->ah_current_channel;
2500 ATH5K_TRACE(ah->ah_sc);
2501 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
2502 "changing txpower to %d\n", power);
2504 return ath5k_hw_txpower(ah, channel, power);
projects / linux-2.6 / blob