Merge branches 'release', 'bugzilla-11880', 'bugzilla-12037' and 'bugzilla-12257...
[linux-2.6] / drivers / net / wireless / ath5k / phy.c
1 /*
2  * PHY functions
3  *
4  * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
5  * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
6  * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7  *
8  * Permission to use, copy, modify, and distribute this software for any
9  * purpose with or without fee is hereby granted, provided that the above
10  * copyright notice and this permission notice appear in all copies.
11  *
12  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19  *
20  */
21
22 #define _ATH5K_PHY
23
24 #include <linux/delay.h>
25
26 #include "ath5k.h"
27 #include "reg.h"
28 #include "base.h"
29
30 /* Struct to hold initial RF register values (RF Banks) */
31 struct ath5k_ini_rf {
32         u8      rf_bank;        /* check out ath5k_reg.h */
33         u16     rf_register;    /* register address */
34         u32     rf_value[5];    /* register value for different modes (above) */
35 };
36
37 /*
38  * Mode-specific RF Gain table (64bytes) for RF5111/5112
39  * (RF5110 only comes with AR5210 and only supports a/turbo a mode so initial
40  * RF Gain values are included in AR5K_AR5210_INI)
41  */
42 struct ath5k_ini_rfgain {
43         u16     rfg_register;   /* RF Gain register address */
44         u32     rfg_value[2];   /* [freq (see below)] */
45 };
46
47 struct ath5k_gain_opt {
48         u32                     go_default;
49         u32                     go_steps_count;
50         const struct ath5k_gain_opt_step        go_step[AR5K_GAIN_STEP_COUNT];
51 };
52
53 /* RF5111 mode-specific init registers */
54 static const struct ath5k_ini_rf rfregs_5111[] = {
55         { 0, 0x989c,
56         /*    mode a/XR   mode aTurbo mode b      mode g      mode gTurbo */
57             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
58         { 0, 0x989c,
59             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
60         { 0, 0x989c,
61             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
62         { 0, 0x989c,
63             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
64         { 0, 0x989c,
65             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
66         { 0, 0x989c,
67             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
68         { 0, 0x989c,
69             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
70         { 0, 0x989c,
71             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
72         { 0, 0x989c,
73             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
74         { 0, 0x989c,
75             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
76         { 0, 0x989c,
77             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
78         { 0, 0x989c,
79             { 0x00380000, 0x00380000, 0x00380000, 0x00380000, 0x00380000 } },
80         { 0, 0x989c,
81             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
82         { 0, 0x989c,
83             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
84         { 0, 0x989c,
85             { 0x00000000, 0x00000000, 0x000000c0, 0x00000080, 0x00000080 } },
86         { 0, 0x989c,
87             { 0x000400f9, 0x000400f9, 0x000400ff, 0x000400fd, 0x000400fd } },
88         { 0, 0x98d4,
89             { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } },
90         { 1, 0x98d4,
91             { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
92         { 2, 0x98d4,
93             { 0x00000010, 0x00000014, 0x00000010, 0x00000010, 0x00000014 } },
94         { 3, 0x98d8,
95             { 0x00601068, 0x00601068, 0x00601068, 0x00601068, 0x00601068 } },
96         { 6, 0x989c,
97             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
98         { 6, 0x989c,
99             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
100         { 6, 0x989c,
101             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
102         { 6, 0x989c,
103             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
104         { 6, 0x989c,
105             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
106         { 6, 0x989c,
107             { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } },
108         { 6, 0x989c,
109             { 0x04000000, 0x04000000, 0x04000000, 0x04000000, 0x04000000 } },
110         { 6, 0x989c,
111             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
112         { 6, 0x989c,
113             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
114         { 6, 0x989c,
115             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
116         { 6, 0x989c,
117             { 0x00000000, 0x00000000, 0x0a000000, 0x00000000, 0x00000000 } },
118         { 6, 0x989c,
119             { 0x003800c0, 0x00380080, 0x023800c0, 0x003800c0, 0x003800c0 } },
120         { 6, 0x989c,
121             { 0x00020006, 0x00020006, 0x00000006, 0x00020006, 0x00020006 } },
122         { 6, 0x989c,
123             { 0x00000089, 0x00000089, 0x00000089, 0x00000089, 0x00000089 } },
124         { 6, 0x989c,
125             { 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0 } },
126         { 6, 0x989c,
127             { 0x00040007, 0x00040007, 0x00040007, 0x00040007, 0x00040007 } },
128         { 6, 0x98d4,
129             { 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a } },
130         { 7, 0x989c,
131             { 0x00000040, 0x00000048, 0x00000040, 0x00000040, 0x00000040 } },
132         { 7, 0x989c,
133             { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } },
134         { 7, 0x989c,
135             { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } },
136         { 7, 0x989c,
137             { 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f } },
138         { 7, 0x989c,
139             { 0x000000f1, 0x000000f1, 0x00000061, 0x000000f1, 0x000000f1 } },
140         { 7, 0x989c,
141             { 0x0000904f, 0x0000904f, 0x0000904c, 0x0000904f, 0x0000904f } },
142         { 7, 0x989c,
143             { 0x0000125a, 0x0000125a, 0x0000129a, 0x0000125a, 0x0000125a } },
144         { 7, 0x98cc,
145             { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } },
146 };
147
148 /* Initial RF Gain settings for RF5111 */
149 static const struct ath5k_ini_rfgain rfgain_5111[] = {
150         /*                            5Ghz      2Ghz    */
151         { AR5K_RF_GAIN(0),      { 0x000001a9, 0x00000000 } },
152         { AR5K_RF_GAIN(1),      { 0x000001e9, 0x00000040 } },
153         { AR5K_RF_GAIN(2),      { 0x00000029, 0x00000080 } },
154         { AR5K_RF_GAIN(3),      { 0x00000069, 0x00000150 } },
155         { AR5K_RF_GAIN(4),      { 0x00000199, 0x00000190 } },
156         { AR5K_RF_GAIN(5),      { 0x000001d9, 0x000001d0 } },
157         { AR5K_RF_GAIN(6),      { 0x00000019, 0x00000010 } },
158         { AR5K_RF_GAIN(7),      { 0x00000059, 0x00000044 } },
159         { AR5K_RF_GAIN(8),      { 0x00000099, 0x00000084 } },
160         { AR5K_RF_GAIN(9),      { 0x000001a5, 0x00000148 } },
161         { AR5K_RF_GAIN(10),     { 0x000001e5, 0x00000188 } },
162         { AR5K_RF_GAIN(11),     { 0x00000025, 0x000001c8 } },
163         { AR5K_RF_GAIN(12),     { 0x000001c8, 0x00000014 } },
164         { AR5K_RF_GAIN(13),     { 0x00000008, 0x00000042 } },
165         { AR5K_RF_GAIN(14),     { 0x00000048, 0x00000082 } },
166         { AR5K_RF_GAIN(15),     { 0x00000088, 0x00000178 } },
167         { AR5K_RF_GAIN(16),     { 0x00000198, 0x000001b8 } },
168         { AR5K_RF_GAIN(17),     { 0x000001d8, 0x000001f8 } },
169         { AR5K_RF_GAIN(18),     { 0x00000018, 0x00000012 } },
170         { AR5K_RF_GAIN(19),     { 0x00000058, 0x00000052 } },
171         { AR5K_RF_GAIN(20),     { 0x00000098, 0x00000092 } },
172         { AR5K_RF_GAIN(21),     { 0x000001a4, 0x0000017c } },
173         { AR5K_RF_GAIN(22),     { 0x000001e4, 0x000001bc } },
174         { AR5K_RF_GAIN(23),     { 0x00000024, 0x000001fc } },
175         { AR5K_RF_GAIN(24),     { 0x00000064, 0x0000000a } },
176         { AR5K_RF_GAIN(25),     { 0x000000a4, 0x0000004a } },
177         { AR5K_RF_GAIN(26),     { 0x000000e4, 0x0000008a } },
178         { AR5K_RF_GAIN(27),     { 0x0000010a, 0x0000015a } },
179         { AR5K_RF_GAIN(28),     { 0x0000014a, 0x0000019a } },
180         { AR5K_RF_GAIN(29),     { 0x0000018a, 0x000001da } },
181         { AR5K_RF_GAIN(30),     { 0x000001ca, 0x0000000e } },
182         { AR5K_RF_GAIN(31),     { 0x0000000a, 0x0000004e } },
183         { AR5K_RF_GAIN(32),     { 0x0000004a, 0x0000008e } },
184         { AR5K_RF_GAIN(33),     { 0x0000008a, 0x0000015e } },
185         { AR5K_RF_GAIN(34),     { 0x000001ba, 0x0000019e } },
186         { AR5K_RF_GAIN(35),     { 0x000001fa, 0x000001de } },
187         { AR5K_RF_GAIN(36),     { 0x0000003a, 0x00000009 } },
188         { AR5K_RF_GAIN(37),     { 0x0000007a, 0x00000049 } },
189         { AR5K_RF_GAIN(38),     { 0x00000186, 0x00000089 } },
190         { AR5K_RF_GAIN(39),     { 0x000001c6, 0x00000179 } },
191         { AR5K_RF_GAIN(40),     { 0x00000006, 0x000001b9 } },
192         { AR5K_RF_GAIN(41),     { 0x00000046, 0x000001f9 } },
193         { AR5K_RF_GAIN(42),     { 0x00000086, 0x00000039 } },
194         { AR5K_RF_GAIN(43),     { 0x000000c6, 0x00000079 } },
195         { AR5K_RF_GAIN(44),     { 0x000000c6, 0x000000b9 } },
196         { AR5K_RF_GAIN(45),     { 0x000000c6, 0x000001bd } },
197         { AR5K_RF_GAIN(46),     { 0x000000c6, 0x000001fd } },
198         { AR5K_RF_GAIN(47),     { 0x000000c6, 0x0000003d } },
199         { AR5K_RF_GAIN(48),     { 0x000000c6, 0x0000007d } },
200         { AR5K_RF_GAIN(49),     { 0x000000c6, 0x000000bd } },
201         { AR5K_RF_GAIN(50),     { 0x000000c6, 0x000000fd } },
202         { AR5K_RF_GAIN(51),     { 0x000000c6, 0x000000fd } },
203         { AR5K_RF_GAIN(52),     { 0x000000c6, 0x000000fd } },
204         { AR5K_RF_GAIN(53),     { 0x000000c6, 0x000000fd } },
205         { AR5K_RF_GAIN(54),     { 0x000000c6, 0x000000fd } },
206         { AR5K_RF_GAIN(55),     { 0x000000c6, 0x000000fd } },
207         { AR5K_RF_GAIN(56),     { 0x000000c6, 0x000000fd } },
208         { AR5K_RF_GAIN(57),     { 0x000000c6, 0x000000fd } },
209         { AR5K_RF_GAIN(58),     { 0x000000c6, 0x000000fd } },
210         { AR5K_RF_GAIN(59),     { 0x000000c6, 0x000000fd } },
211         { AR5K_RF_GAIN(60),     { 0x000000c6, 0x000000fd } },
212         { AR5K_RF_GAIN(61),     { 0x000000c6, 0x000000fd } },
213         { AR5K_RF_GAIN(62),     { 0x000000c6, 0x000000fd } },
214         { AR5K_RF_GAIN(63),     { 0x000000c6, 0x000000fd } },
215 };
216
217 static const struct ath5k_gain_opt rfgain_opt_5111 = {
218         4,
219         9,
220         {
221                 { { 4, 1, 1, 1 }, 6 },
222                 { { 4, 0, 1, 1 }, 4 },
223                 { { 3, 1, 1, 1 }, 3 },
224                 { { 4, 0, 0, 1 }, 1 },
225                 { { 4, 1, 1, 0 }, 0 },
226                 { { 4, 0, 1, 0 }, -2 },
227                 { { 3, 1, 1, 0 }, -3 },
228                 { { 4, 0, 0, 0 }, -4 },
229                 { { 2, 1, 1, 0 }, -6 }
230         }
231 };
232
233 /* RF5112 mode-specific init registers */
234 static const struct ath5k_ini_rf rfregs_5112[] = {
235         { 1, 0x98d4,
236         /*    mode a/XR   mode aTurbo mode b      mode g      mode gTurbo */
237             { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
238         { 2, 0x98d0,
239             { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
240         { 3, 0x98dc,
241             { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
242         { 6, 0x989c,
243             { 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000 } },
244         { 6, 0x989c,
245             { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
246         { 6, 0x989c,
247             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
248         { 6, 0x989c,
249             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
250         { 6, 0x989c,
251             { 0x00660000, 0x00660000, 0x00660000, 0x00660000, 0x00660000 } },
252         { 6, 0x989c,
253             { 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000 } },
254         { 6, 0x989c,
255             { 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000 } },
256         { 6, 0x989c,
257             { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
258         { 6, 0x989c,
259             { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
260         { 6, 0x989c,
261             { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } },
262         { 6, 0x989c,
263             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
264         { 6, 0x989c,
265             { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
266         { 6, 0x989c,
267             { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
268         { 6, 0x989c,
269             { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
270         { 6, 0x989c,
271             { 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000 } },
272         { 6, 0x989c,
273             { 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000 } },
274         { 6, 0x989c,
275             { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
276         { 6, 0x989c,
277             { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },
278         { 6, 0x989c,
279             { 0x00640000, 0x00640000, 0x00640000, 0x00640000, 0x00640000 } },
280         { 6, 0x989c,
281             { 0x00200000, 0x00200000, 0x00200000, 0x00200000, 0x00200000 } },
282         { 6, 0x989c,
283             { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
284         { 6, 0x989c,
285             { 0x00250000, 0x00250000, 0x00250000, 0x00250000, 0x00250000 } },
286         { 6, 0x989c,
287             { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
288         { 6, 0x989c,
289             { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
290         { 6, 0x989c,
291             { 0x00510000, 0x00510000, 0x00510000, 0x00510000, 0x00510000 } },
292         { 6, 0x989c,
293             { 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000 } },
294         { 6, 0x989c,
295             { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
296         { 6, 0x989c,
297             { 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000 } },
298         { 6, 0x989c,
299             { 0x00400000, 0x00400000, 0x00400000, 0x00400000, 0x00400000 } },
300         { 6, 0x989c,
301             { 0x03090000, 0x03090000, 0x03090000, 0x03090000, 0x03090000 } },
302         { 6, 0x989c,
303             { 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0x06000000 } },
304         { 6, 0x989c,
305             { 0x000000b0, 0x000000b0, 0x000000a8, 0x000000a8, 0x000000a8 } },
306         { 6, 0x989c,
307             { 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e } },
308         { 6, 0x989c,
309             { 0x006c4a41, 0x006c4a41, 0x006c4af1, 0x006c4a61, 0x006c4a61 } },
310         { 6, 0x989c,
311             { 0x0050892a, 0x0050892a, 0x0050892b, 0x0050892b, 0x0050892b } },
312         { 6, 0x989c,
313             { 0x00842400, 0x00842400, 0x00842400, 0x00842400, 0x00842400 } },
314         { 6, 0x989c,
315             { 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200 } },
316         { 6, 0x98d0,
317             { 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c } },
318         { 7, 0x989c,
319             { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
320         { 7, 0x989c,
321             { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
322         { 7, 0x989c,
323             { 0x0000000a, 0x0000000a, 0x00000012, 0x00000012, 0x00000012 } },
324         { 7, 0x989c,
325             { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
326         { 7, 0x989c,
327             { 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1 } },
328         { 7, 0x989c,
329             { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
330         { 7, 0x989c,
331             { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
332         { 7, 0x989c,
333             { 0x00000022, 0x00000022, 0x00000022, 0x00000022, 0x00000022 } },
334         { 7, 0x989c,
335             { 0x00000092, 0x00000092, 0x00000092, 0x00000092, 0x00000092 } },
336         { 7, 0x989c,
337             { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
338         { 7, 0x989c,
339             { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
340         { 7, 0x989c,
341             { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
342         { 7, 0x98c4,
343             { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
344 };
345
346 /* RF5112A mode-specific init registers */
347 static const struct ath5k_ini_rf rfregs_5112a[] = {
348         { 1, 0x98d4,
349         /*    mode a/XR   mode aTurbo mode b      mode g      mode gTurbo */
350             { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
351         { 2, 0x98d0,
352             { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
353         { 3, 0x98dc,
354             { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
355         { 6, 0x989c,
356             { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } },
357         { 6, 0x989c,
358             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
359         { 6, 0x989c,
360             { 0x00800000, 0x00800000, 0x00800000, 0x00800000, 0x00800000 } },
361         { 6, 0x989c,
362             { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
363         { 6, 0x989c,
364             { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } },
365         { 6, 0x989c,
366             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
367         { 6, 0x989c,
368             { 0x00180000, 0x00180000, 0x00180000, 0x00180000, 0x00180000 } },
369         { 6, 0x989c,
370             { 0x00600000, 0x00600000, 0x006e0000, 0x006e0000, 0x006e0000 } },
371         { 6, 0x989c,
372             { 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000 } },
373         { 6, 0x989c,
374             { 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000 } },
375         { 6, 0x989c,
376             { 0x04480000, 0x04480000, 0x04480000, 0x04480000, 0x04480000 } },
377         { 6, 0x989c,
378             { 0x00220000, 0x00220000, 0x00220000, 0x00220000, 0x00220000 } },
379         { 6, 0x989c,
380             { 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000 } },
381         { 6, 0x989c,
382             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
383         { 6, 0x989c,
384             { 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000 } },
385         { 6, 0x989c,
386             { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
387         { 6, 0x989c,
388             { 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000 } },
389         { 6, 0x989c,
390             { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
391         { 6, 0x989c,
392             { 0x00190000, 0x00190000, 0x00190000, 0x00190000, 0x00190000 } },
393         { 6, 0x989c,
394             { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
395         { 6, 0x989c,
396             { 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000 } },
397         { 6, 0x989c,
398             { 0x00990000, 0x00990000, 0x00990000, 0x00990000, 0x00990000 } },
399         { 6, 0x989c,
400             { 0x00500000, 0x00500000, 0x00500000, 0x00500000, 0x00500000 } },
401         { 6, 0x989c,
402             { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
403         { 6, 0x989c,
404             { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
405         { 6, 0x989c,
406             { 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000 } },
407         { 6, 0x989c,
408             { 0x01740000, 0x01740000, 0x01740000, 0x01740000, 0x01740000 } },
409         { 6, 0x989c,
410             { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
411         { 6, 0x989c,
412             { 0x86280000, 0x86280000, 0x86280000, 0x86280000, 0x86280000 } },
413         { 6, 0x989c,
414             { 0x31840000, 0x31840000, 0x31840000, 0x31840000, 0x31840000 } },
415         { 6, 0x989c,
416             { 0x00020080, 0x00020080, 0x00020080, 0x00020080, 0x00020080 } },
417         { 6, 0x989c,
418             { 0x00080009, 0x00080009, 0x00080009, 0x00080009, 0x00080009 } },
419         { 6, 0x989c,
420             { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
421         { 6, 0x989c,
422             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
423         { 6, 0x989c,
424             { 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2 } },
425         { 6, 0x989c,
426             { 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084 } },
427         { 6, 0x989c,
428             { 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4 } },
429         { 6, 0x989c,
430             { 0x00119220, 0x00119220, 0x00119220, 0x00119220, 0x00119220 } },
431         { 6, 0x989c,
432             { 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800 } },
433         { 6, 0x98d8,
434             { 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230 } },
435         { 7, 0x989c,
436             { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
437         { 7, 0x989c,
438             { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
439         { 7, 0x989c,
440             { 0x00000012, 0x00000012, 0x00000012, 0x00000012, 0x00000012 } },
441         { 7, 0x989c,
442             { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
443         { 7, 0x989c,
444             { 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9 } },
445         { 7, 0x989c,
446             { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
447         { 7, 0x989c,
448             { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
449         { 7, 0x989c,
450             { 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2 } },
451         { 7, 0x989c,
452             { 0x00000052, 0x00000052, 0x00000052, 0x00000052, 0x00000052 } },
453         { 7, 0x989c,
454             { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
455         { 7, 0x989c,
456             { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
457         { 7, 0x989c,
458             { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
459         { 7, 0x98c4,
460             { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
461 };
462
463
464 static const struct ath5k_ini_rf rfregs_2112a[] = {
465         { 1, AR5K_RF_BUFFER_CONTROL_4,
466         /*         mode b       mode g    mode gTurbo */
467                 { 0x00000020, 0x00000020, 0x00000020 } },
468         { 2, AR5K_RF_BUFFER_CONTROL_3,
469                 { 0x03060408, 0x03060408, 0x03070408 } },
470         { 3, AR5K_RF_BUFFER_CONTROL_6,
471                 { 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
472         { 6, AR5K_RF_BUFFER,
473                 { 0x0a000000, 0x0a000000, 0x0a000000 } },
474         { 6, AR5K_RF_BUFFER,
475                 { 0x00000000, 0x00000000, 0x00000000 } },
476         { 6, AR5K_RF_BUFFER,
477                 { 0x00800000, 0x00800000, 0x00800000 } },
478         { 6, AR5K_RF_BUFFER,
479                 { 0x002a0000, 0x002a0000, 0x002a0000 } },
480         { 6, AR5K_RF_BUFFER,
481                 { 0x00010000, 0x00010000, 0x00010000 } },
482         { 6, AR5K_RF_BUFFER,
483                 { 0x00000000, 0x00000000, 0x00000000 } },
484         { 6, AR5K_RF_BUFFER,
485                 { 0x00180000, 0x00180000, 0x00180000 } },
486         { 6, AR5K_RF_BUFFER,
487                 { 0x006e0000, 0x006e0000, 0x006e0000 } },
488         { 6, AR5K_RF_BUFFER,
489                 { 0x00c70000, 0x00c70000, 0x00c70000 } },
490         { 6, AR5K_RF_BUFFER,
491                 { 0x004b0000, 0x004b0000, 0x004b0000 } },
492         { 6, AR5K_RF_BUFFER,
493                 { 0x04480000, 0x04480000, 0x04480000 } },
494         { 6, AR5K_RF_BUFFER,
495                 { 0x002a0000, 0x002a0000, 0x002a0000 } },
496         { 6, AR5K_RF_BUFFER,
497                 { 0x00e40000, 0x00e40000, 0x00e40000 } },
498         { 6, AR5K_RF_BUFFER,
499                 { 0x00000000, 0x00000000, 0x00000000 } },
500         { 6, AR5K_RF_BUFFER,
501                 { 0x00fc0000, 0x00fc0000, 0x00fc0000 } },
502         { 6, AR5K_RF_BUFFER,
503                 { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
504         { 6, AR5K_RF_BUFFER,
505                 { 0x043f0000, 0x043f0000, 0x043f0000 } },
506         { 6, AR5K_RF_BUFFER,
507                 { 0x0c0c0000, 0x0c0c0000, 0x0c0c0000 } },
508         { 6, AR5K_RF_BUFFER,
509                 { 0x02190000, 0x02190000, 0x02190000 } },
510         { 6, AR5K_RF_BUFFER,
511                 { 0x00240000, 0x00240000, 0x00240000 } },
512         { 6, AR5K_RF_BUFFER,
513                 { 0x00b40000, 0x00b40000, 0x00b40000 } },
514         { 6, AR5K_RF_BUFFER,
515                 { 0x00990000, 0x00990000, 0x00990000 } },
516         { 6, AR5K_RF_BUFFER,
517                 { 0x00500000, 0x00500000, 0x00500000 } },
518         { 6, AR5K_RF_BUFFER,
519                 { 0x002a0000, 0x002a0000, 0x002a0000 } },
520         { 6, AR5K_RF_BUFFER,
521                 { 0x00120000, 0x00120000, 0x00120000 } },
522         { 6, AR5K_RF_BUFFER,
523                 { 0xc0320000, 0xc0320000, 0xc0320000 } },
524         { 6, AR5K_RF_BUFFER,
525                 { 0x01740000, 0x01740000, 0x01740000 } },
526         { 6, AR5K_RF_BUFFER,
527                 { 0x00110000, 0x00110000, 0x00110000 } },
528         { 6, AR5K_RF_BUFFER,
529                 { 0x86280000, 0x86280000, 0x86280000 } },
530         { 6, AR5K_RF_BUFFER,
531                 { 0x31840000, 0x31840000, 0x31840000 } },
532         { 6, AR5K_RF_BUFFER,
533                 { 0x00f20080, 0x00f20080, 0x00f20080 } },
534         { 6, AR5K_RF_BUFFER,
535                 { 0x00070019, 0x00070019, 0x00070019 } },
536         { 6, AR5K_RF_BUFFER,
537                 { 0x00000000, 0x00000000, 0x00000000 } },
538         { 6, AR5K_RF_BUFFER,
539                 { 0x00000000, 0x00000000, 0x00000000 } },
540         { 6, AR5K_RF_BUFFER,
541                 { 0x000000b2, 0x000000b2, 0x000000b2 } },
542         { 6, AR5K_RF_BUFFER,
543                 { 0x00b02184, 0x00b02184, 0x00b02184 } },
544         { 6, AR5K_RF_BUFFER,
545                 { 0x004125a4, 0x004125a4, 0x004125a4 } },
546         { 6, AR5K_RF_BUFFER,
547                 { 0x00119220, 0x00119220, 0x00119220 } },
548         { 6, AR5K_RF_BUFFER,
549                 { 0x001a4800, 0x001a4800, 0x001a4800 } },
550         { 6, AR5K_RF_BUFFER_CONTROL_5,
551                 { 0x000b0230, 0x000b0230, 0x000b0230 } },
552         { 7, AR5K_RF_BUFFER,
553                 { 0x00000094, 0x00000094, 0x00000094 } },
554         { 7, AR5K_RF_BUFFER,
555                 { 0x00000091, 0x00000091, 0x00000091 } },
556         { 7, AR5K_RF_BUFFER,
557                 { 0x00000012, 0x00000012, 0x00000012 } },
558         { 7, AR5K_RF_BUFFER,
559                 { 0x00000080, 0x00000080, 0x00000080 } },
560         { 7, AR5K_RF_BUFFER,
561                 { 0x000000d9, 0x000000d9, 0x000000d9 } },
562         { 7, AR5K_RF_BUFFER,
563                 { 0x00000060, 0x00000060, 0x00000060 } },
564         { 7, AR5K_RF_BUFFER,
565                 { 0x000000f0, 0x000000f0, 0x000000f0 } },
566         { 7, AR5K_RF_BUFFER,
567                 { 0x000000a2, 0x000000a2, 0x000000a2 } },
568         { 7, AR5K_RF_BUFFER,
569                 { 0x00000052, 0x00000052, 0x00000052 } },
570         { 7, AR5K_RF_BUFFER,
571                 { 0x000000d4, 0x000000d4, 0x000000d4 } },
572         { 7, AR5K_RF_BUFFER,
573                 { 0x000014cc, 0x000014cc, 0x000014cc } },
574         { 7, AR5K_RF_BUFFER,
575                 { 0x0000048c, 0x0000048c, 0x0000048c } },
576         { 7, AR5K_RF_BUFFER_CONTROL_1,
577                 { 0x00000003, 0x00000003, 0x00000003 } },
578 };
579
580 /* RF5413/5414 mode-specific init registers */
581 static const struct ath5k_ini_rf rfregs_5413[] = {
582         { 1, 0x98d4,
583         /*    mode a/XR   mode aTurbo mode b      mode g      mode gTurbo */
584             { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
585         { 2, 0x98d0,
586             { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } },
587         { 3, 0x98dc,
588             { 0x00a000c0, 0x00a000c0, 0x00e000c0, 0x00e000c0, 0x00e000c0 } },
589         { 6, 0x989c,
590             { 0x33000000, 0x33000000, 0x33000000, 0x33000000, 0x33000000 } },
591         { 6, 0x989c,
592             { 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000 } },
593         { 6, 0x989c,
594             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
595         { 6, 0x989c,
596             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
597         { 6, 0x989c,
598             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
599         { 6, 0x989c,
600             { 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000 } },
601         { 6, 0x989c,
602             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
603         { 6, 0x989c,
604             { 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000 } },
605         { 6, 0x989c,
606             { 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000 } },
607         { 6, 0x989c,
608             { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },
609         { 6, 0x989c,
610             { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } },
611         { 6, 0x989c,
612             { 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000 } },
613         { 6, 0x989c,
614             { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
615         { 6, 0x989c,
616             { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
617         { 6, 0x989c,
618             { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
619         { 6, 0x989c,
620             { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
621         { 6, 0x989c,
622             { 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000 } },
623         { 6, 0x989c,
624             { 0x00610000, 0x00610000, 0x00610000, 0x00610000, 0x00610000 } },
625         { 6, 0x989c,
626             { 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000 } },
627         { 6, 0x989c,
628             { 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000 } },
629         { 6, 0x989c,
630             { 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000 } },
631         { 6, 0x989c,
632             { 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000 } },
633         { 6, 0x989c,
634             { 0x00770000, 0x00770000, 0x00770000, 0x00770000, 0x00770000 } },
635         { 6, 0x989c,
636             { 0x00440000, 0x00440000, 0x00440000, 0x00440000, 0x00440000 } },
637         { 6, 0x989c,
638             { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } },
639         { 6, 0x989c,
640             { 0x00100080, 0x00100080, 0x00100080, 0x00100080, 0x00100080 } },
641         { 6, 0x989c,
642             { 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034 } },
643         { 6, 0x989c,
644             { 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0 } },
645         { 6, 0x989c,
646             { 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f } },
647         { 6, 0x989c,
648             { 0x00510040, 0x00510040, 0x005100a0, 0x005100a0, 0x005100a0 } },
649         { 6, 0x989c,
650             { 0x0050006a, 0x0050006a, 0x005000dd, 0x005000dd, 0x005000dd } },
651         { 6, 0x989c,
652             { 0x00000001, 0x00000001, 0x00000000, 0x00000000, 0x00000000 } },
653         { 6, 0x989c,
654             { 0x00004044, 0x00004044, 0x00004044, 0x00004044, 0x00004044 } },
655         { 6, 0x989c,
656             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
657         { 6, 0x989c,
658             { 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0 } },
659         { 6, 0x989c,
660             { 0x00002c00, 0x00002c00, 0x00003600, 0x00003600, 0x00003600 } },
661         { 6, 0x98c8,
662             { 0x00000403, 0x00000403, 0x00040403, 0x00040403, 0x00040403 } },
663         { 7, 0x989c,
664             { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
665         { 7, 0x989c,
666             { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
667         { 7, 0x98cc,
668             { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
669 };
670
671 /* RF2413/2414 mode-specific init registers */
672 static const struct ath5k_ini_rf rfregs_2413[] = {
673         { 1, AR5K_RF_BUFFER_CONTROL_4,
674         /*         mode b      mode g     mode gTurbo */
675                 { 0x00000020, 0x00000020, 0x00000020 } },
676         { 2, AR5K_RF_BUFFER_CONTROL_3,
677                 { 0x02001408, 0x02001408, 0x02001408 } },
678         { 3, AR5K_RF_BUFFER_CONTROL_6,
679                 { 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
680         { 6, AR5K_RF_BUFFER,
681                 { 0xf0000000, 0xf0000000, 0xf0000000 } },
682         { 6, AR5K_RF_BUFFER,
683                 { 0x00000000, 0x00000000, 0x00000000 } },
684         { 6, AR5K_RF_BUFFER,
685                 { 0x03000000, 0x03000000, 0x03000000 } },
686         { 6, AR5K_RF_BUFFER,
687                 { 0x00000000, 0x00000000, 0x00000000 } },
688         { 6, AR5K_RF_BUFFER,
689                 { 0x00000000, 0x00000000, 0x00000000 } },
690         { 6, AR5K_RF_BUFFER,
691                 { 0x00000000, 0x00000000, 0x00000000 } },
692         { 6, AR5K_RF_BUFFER,
693                 { 0x00000000, 0x00000000, 0x00000000 } },
694         { 6, AR5K_RF_BUFFER,
695                 { 0x00000000, 0x00000000, 0x00000000 } },
696         { 6, AR5K_RF_BUFFER,
697                 { 0x40400000, 0x40400000, 0x40400000 } },
698         { 6, AR5K_RF_BUFFER,
699                 { 0x65050000, 0x65050000, 0x65050000 } },
700         { 6, AR5K_RF_BUFFER,
701                 { 0x00000000, 0x00000000, 0x00000000 } },
702         { 6, AR5K_RF_BUFFER,
703                 { 0x00000000, 0x00000000, 0x00000000 } },
704         { 6, AR5K_RF_BUFFER,
705                 { 0x00420000, 0x00420000, 0x00420000 } },
706         { 6, AR5K_RF_BUFFER,
707                 { 0x00b50000, 0x00b50000, 0x00b50000 } },
708         { 6, AR5K_RF_BUFFER,
709                 { 0x00030000, 0x00030000, 0x00030000 } },
710         { 6, AR5K_RF_BUFFER,
711                 { 0x00f70000, 0x00f70000, 0x00f70000 } },
712         { 6, AR5K_RF_BUFFER,
713                 { 0x009d0000, 0x009d0000, 0x009d0000 } },
714         { 6, AR5K_RF_BUFFER,
715                 { 0x00220000, 0x00220000, 0x00220000 } },
716         { 6, AR5K_RF_BUFFER,
717                 { 0x04220000, 0x04220000, 0x04220000 } },
718         { 6, AR5K_RF_BUFFER,
719                 { 0x00230018, 0x00230018, 0x00230018 } },
720         { 6, AR5K_RF_BUFFER,
721                 { 0x00280050, 0x00280050, 0x00280050 } },
722         { 6, AR5K_RF_BUFFER,
723                 { 0x005000c3, 0x005000c3, 0x005000c3 } },
724         { 6, AR5K_RF_BUFFER,
725                 { 0x0004007f, 0x0004007f, 0x0004007f } },
726         { 6, AR5K_RF_BUFFER,
727                 { 0x00000458, 0x00000458, 0x00000458 } },
728         { 6, AR5K_RF_BUFFER,
729                 { 0x00000000, 0x00000000, 0x00000000 } },
730         { 6, AR5K_RF_BUFFER,
731                 { 0x0000c000, 0x0000c000, 0x0000c000 } },
732         { 6, AR5K_RF_BUFFER_CONTROL_5,
733                 { 0x00400230, 0x00400230, 0x00400230 } },
734         { 7, AR5K_RF_BUFFER,
735                 { 0x00006400, 0x00006400, 0x00006400 } },
736         { 7, AR5K_RF_BUFFER,
737                 { 0x00000800, 0x00000800, 0x00000800 } },
738         { 7, AR5K_RF_BUFFER_CONTROL_2,
739                 { 0x0000000e, 0x0000000e, 0x0000000e } },
740 };
741
742 /* RF2425 mode-specific init registers */
743 static const struct ath5k_ini_rf rfregs_2425[] = {
744         { 1, AR5K_RF_BUFFER_CONTROL_4,
745         /*         mode g     mode gTurbo */
746                 { 0x00000020, 0x00000020 } },
747         { 2, AR5K_RF_BUFFER_CONTROL_3,
748                 { 0x02001408, 0x02001408 } },
749         { 3, AR5K_RF_BUFFER_CONTROL_6,
750                 { 0x00e020c0, 0x00e020c0 } },
751         { 6, AR5K_RF_BUFFER,
752                 { 0x10000000, 0x10000000 } },
753         { 6, AR5K_RF_BUFFER,
754                 { 0x00000000, 0x00000000 } },
755         { 6, AR5K_RF_BUFFER,
756                 { 0x00000000, 0x00000000 } },
757         { 6, AR5K_RF_BUFFER,
758                 { 0x00000000, 0x00000000 } },
759         { 6, AR5K_RF_BUFFER,
760                 { 0x00000000, 0x00000000 } },
761         { 6, AR5K_RF_BUFFER,
762                 { 0x00000000, 0x00000000 } },
763         { 6, AR5K_RF_BUFFER,
764                 { 0x00000000, 0x00000000 } },
765         { 6, AR5K_RF_BUFFER,
766                 { 0x00000000, 0x00000000 } },
767         { 6, AR5K_RF_BUFFER,
768                 { 0x00000000, 0x00000000 } },
769         { 6, AR5K_RF_BUFFER,
770                 { 0x00000000, 0x00000000 } },
771         { 6, AR5K_RF_BUFFER,
772                 { 0x00000000, 0x00000000 } },
773         { 6, AR5K_RF_BUFFER,
774                 { 0x002a0000, 0x002a0000 } },
775         { 6, AR5K_RF_BUFFER,
776                 { 0x00000000, 0x00000000 } },
777         { 6, AR5K_RF_BUFFER,
778                 { 0x00000000, 0x00000000 } },
779         { 6, AR5K_RF_BUFFER,
780                 { 0x00100000, 0x00100000 } },
781         { 6, AR5K_RF_BUFFER,
782                 { 0x00020000, 0x00020000 } },
783         { 6, AR5K_RF_BUFFER,
784                 { 0x00730000, 0x00730000 } },
785         { 6, AR5K_RF_BUFFER,
786                 { 0x00f80000, 0x00f80000 } },
787         { 6, AR5K_RF_BUFFER,
788                 { 0x00e70000, 0x00e70000 } },
789         { 6, AR5K_RF_BUFFER,
790                 { 0x00140000, 0x00140000 } },
791         { 6, AR5K_RF_BUFFER,
792                 { 0x00910040, 0x00910040 } },
793         { 6, AR5K_RF_BUFFER,
794                 { 0x0007001a, 0x0007001a } },
795         { 6, AR5K_RF_BUFFER,
796                 { 0x00410000, 0x00410000 } },
797         { 6, AR5K_RF_BUFFER,
798                 { 0x00810060, 0x00810060 } },
799         { 6, AR5K_RF_BUFFER,
800                 { 0x00020803, 0x00020803 } },
801         { 6, AR5K_RF_BUFFER,
802                 { 0x00000000, 0x00000000 } },
803         { 6, AR5K_RF_BUFFER,
804                 { 0x00000000, 0x00000000 } },
805         { 6, AR5K_RF_BUFFER,
806                 { 0x00001660, 0x00001660 } },
807         { 6, AR5K_RF_BUFFER,
808                 { 0x00001688, 0x00001688 } },
809         { 6, AR5K_RF_BUFFER_CONTROL_1,
810                 { 0x00000001, 0x00000001 } },
811         { 7, AR5K_RF_BUFFER,
812                 { 0x00006400, 0x00006400 } },
813         { 7, AR5K_RF_BUFFER,
814                 { 0x00000800, 0x00000800 } },
815         { 7, AR5K_RF_BUFFER_CONTROL_2,
816                 { 0x0000000e, 0x0000000e } },
817 };
818
819 /* Initial RF Gain settings for RF5112 */
820 static const struct ath5k_ini_rfgain rfgain_5112[] = {
821         /*                            5Ghz      2Ghz    */
822         { AR5K_RF_GAIN(0),      { 0x00000007, 0x00000007 } },
823         { AR5K_RF_GAIN(1),      { 0x00000047, 0x00000047 } },
824         { AR5K_RF_GAIN(2),      { 0x00000087, 0x00000087 } },
825         { AR5K_RF_GAIN(3),      { 0x000001a0, 0x000001a0 } },
826         { AR5K_RF_GAIN(4),      { 0x000001e0, 0x000001e0 } },
827         { AR5K_RF_GAIN(5),      { 0x00000020, 0x00000020 } },
828         { AR5K_RF_GAIN(6),      { 0x00000060, 0x00000060 } },
829         { AR5K_RF_GAIN(7),      { 0x000001a1, 0x000001a1 } },
830         { AR5K_RF_GAIN(8),      { 0x000001e1, 0x000001e1 } },
831         { AR5K_RF_GAIN(9),      { 0x00000021, 0x00000021 } },
832         { AR5K_RF_GAIN(10),     { 0x00000061, 0x00000061 } },
833         { AR5K_RF_GAIN(11),     { 0x00000162, 0x00000162 } },
834         { AR5K_RF_GAIN(12),     { 0x000001a2, 0x000001a2 } },
835         { AR5K_RF_GAIN(13),     { 0x000001e2, 0x000001e2 } },
836         { AR5K_RF_GAIN(14),     { 0x00000022, 0x00000022 } },
837         { AR5K_RF_GAIN(15),     { 0x00000062, 0x00000062 } },
838         { AR5K_RF_GAIN(16),     { 0x00000163, 0x00000163 } },
839         { AR5K_RF_GAIN(17),     { 0x000001a3, 0x000001a3 } },
840         { AR5K_RF_GAIN(18),     { 0x000001e3, 0x000001e3 } },
841         { AR5K_RF_GAIN(19),     { 0x00000023, 0x00000023 } },
842         { AR5K_RF_GAIN(20),     { 0x00000063, 0x00000063 } },
843         { AR5K_RF_GAIN(21),     { 0x00000184, 0x00000184 } },
844         { AR5K_RF_GAIN(22),     { 0x000001c4, 0x000001c4 } },
845         { AR5K_RF_GAIN(23),     { 0x00000004, 0x00000004 } },
846         { AR5K_RF_GAIN(24),     { 0x000001ea, 0x0000000b } },
847         { AR5K_RF_GAIN(25),     { 0x0000002a, 0x0000004b } },
848         { AR5K_RF_GAIN(26),     { 0x0000006a, 0x0000008b } },
849         { AR5K_RF_GAIN(27),     { 0x000000aa, 0x000001ac } },
850         { AR5K_RF_GAIN(28),     { 0x000001ab, 0x000001ec } },
851         { AR5K_RF_GAIN(29),     { 0x000001eb, 0x0000002c } },
852         { AR5K_RF_GAIN(30),     { 0x0000002b, 0x00000012 } },
853         { AR5K_RF_GAIN(31),     { 0x0000006b, 0x00000052 } },
854         { AR5K_RF_GAIN(32),     { 0x000000ab, 0x00000092 } },
855         { AR5K_RF_GAIN(33),     { 0x000001ac, 0x00000193 } },
856         { AR5K_RF_GAIN(34),     { 0x000001ec, 0x000001d3 } },
857         { AR5K_RF_GAIN(35),     { 0x0000002c, 0x00000013 } },
858         { AR5K_RF_GAIN(36),     { 0x0000003a, 0x00000053 } },
859         { AR5K_RF_GAIN(37),     { 0x0000007a, 0x00000093 } },
860         { AR5K_RF_GAIN(38),     { 0x000000ba, 0x00000194 } },
861         { AR5K_RF_GAIN(39),     { 0x000001bb, 0x000001d4 } },
862         { AR5K_RF_GAIN(40),     { 0x000001fb, 0x00000014 } },
863         { AR5K_RF_GAIN(41),     { 0x0000003b, 0x0000003a } },
864         { AR5K_RF_GAIN(42),     { 0x0000007b, 0x0000007a } },
865         { AR5K_RF_GAIN(43),     { 0x000000bb, 0x000000ba } },
866         { AR5K_RF_GAIN(44),     { 0x000001bc, 0x000001bb } },
867         { AR5K_RF_GAIN(45),     { 0x000001fc, 0x000001fb } },
868         { AR5K_RF_GAIN(46),     { 0x0000003c, 0x0000003b } },
869         { AR5K_RF_GAIN(47),     { 0x0000007c, 0x0000007b } },
870         { AR5K_RF_GAIN(48),     { 0x000000bc, 0x000000bb } },
871         { AR5K_RF_GAIN(49),     { 0x000000fc, 0x000001bc } },
872         { AR5K_RF_GAIN(50),     { 0x000000fc, 0x000001fc } },
873         { AR5K_RF_GAIN(51),     { 0x000000fc, 0x0000003c } },
874         { AR5K_RF_GAIN(52),     { 0x000000fc, 0x0000007c } },
875         { AR5K_RF_GAIN(53),     { 0x000000fc, 0x000000bc } },
876         { AR5K_RF_GAIN(54),     { 0x000000fc, 0x000000fc } },
877         { AR5K_RF_GAIN(55),     { 0x000000fc, 0x000000fc } },
878         { AR5K_RF_GAIN(56),     { 0x000000fc, 0x000000fc } },
879         { AR5K_RF_GAIN(57),     { 0x000000fc, 0x000000fc } },
880         { AR5K_RF_GAIN(58),     { 0x000000fc, 0x000000fc } },
881         { AR5K_RF_GAIN(59),     { 0x000000fc, 0x000000fc } },
882         { AR5K_RF_GAIN(60),     { 0x000000fc, 0x000000fc } },
883         { AR5K_RF_GAIN(61),     { 0x000000fc, 0x000000fc } },
884         { AR5K_RF_GAIN(62),     { 0x000000fc, 0x000000fc } },
885         { AR5K_RF_GAIN(63),     { 0x000000fc, 0x000000fc } },
886 };
887
888 /* Initial RF Gain settings for RF5413 */
889 static const struct ath5k_ini_rfgain rfgain_5413[] = {
890         /*                            5Ghz      2Ghz    */
891         { AR5K_RF_GAIN(0),      { 0x00000000, 0x00000000 } },
892         { AR5K_RF_GAIN(1),      { 0x00000040, 0x00000040 } },
893         { AR5K_RF_GAIN(2),      { 0x00000080, 0x00000080 } },
894         { AR5K_RF_GAIN(3),      { 0x000001a1, 0x00000161 } },
895         { AR5K_RF_GAIN(4),      { 0x000001e1, 0x000001a1 } },
896         { AR5K_RF_GAIN(5),      { 0x00000021, 0x000001e1 } },
897         { AR5K_RF_GAIN(6),      { 0x00000061, 0x00000021 } },
898         { AR5K_RF_GAIN(7),      { 0x00000188, 0x00000061 } },
899         { AR5K_RF_GAIN(8),      { 0x000001c8, 0x00000188 } },
900         { AR5K_RF_GAIN(9),      { 0x00000008, 0x000001c8 } },
901         { AR5K_RF_GAIN(10),     { 0x00000048, 0x00000008 } },
902         { AR5K_RF_GAIN(11),     { 0x00000088, 0x00000048 } },
903         { AR5K_RF_GAIN(12),     { 0x000001a9, 0x00000088 } },
904         { AR5K_RF_GAIN(13),     { 0x000001e9, 0x00000169 } },
905         { AR5K_RF_GAIN(14),     { 0x00000029, 0x000001a9 } },
906         { AR5K_RF_GAIN(15),     { 0x00000069, 0x000001e9 } },
907         { AR5K_RF_GAIN(16),     { 0x000001d0, 0x00000029 } },
908         { AR5K_RF_GAIN(17),     { 0x00000010, 0x00000069 } },
909         { AR5K_RF_GAIN(18),     { 0x00000050, 0x00000190 } },
910         { AR5K_RF_GAIN(19),     { 0x00000090, 0x000001d0 } },
911         { AR5K_RF_GAIN(20),     { 0x000001b1, 0x00000010 } },
912         { AR5K_RF_GAIN(21),     { 0x000001f1, 0x00000050 } },
913         { AR5K_RF_GAIN(22),     { 0x00000031, 0x00000090 } },
914         { AR5K_RF_GAIN(23),     { 0x00000071, 0x00000171 } },
915         { AR5K_RF_GAIN(24),     { 0x000001b8, 0x000001b1 } },
916         { AR5K_RF_GAIN(25),     { 0x000001f8, 0x000001f1 } },
917         { AR5K_RF_GAIN(26),     { 0x00000038, 0x00000031 } },
918         { AR5K_RF_GAIN(27),     { 0x00000078, 0x00000071 } },
919         { AR5K_RF_GAIN(28),     { 0x00000199, 0x00000198 } },
920         { AR5K_RF_GAIN(29),     { 0x000001d9, 0x000001d8 } },
921         { AR5K_RF_GAIN(30),     { 0x00000019, 0x00000018 } },
922         { AR5K_RF_GAIN(31),     { 0x00000059, 0x00000058 } },
923         { AR5K_RF_GAIN(32),     { 0x00000099, 0x00000098 } },
924         { AR5K_RF_GAIN(33),     { 0x000000d9, 0x00000179 } },
925         { AR5K_RF_GAIN(34),     { 0x000000f9, 0x000001b9 } },
926         { AR5K_RF_GAIN(35),     { 0x000000f9, 0x000001f9 } },
927         { AR5K_RF_GAIN(36),     { 0x000000f9, 0x00000039 } },
928         { AR5K_RF_GAIN(37),     { 0x000000f9, 0x00000079 } },
929         { AR5K_RF_GAIN(38),     { 0x000000f9, 0x000000b9 } },
930         { AR5K_RF_GAIN(39),     { 0x000000f9, 0x000000f9 } },
931         { AR5K_RF_GAIN(40),     { 0x000000f9, 0x000000f9 } },
932         { AR5K_RF_GAIN(41),     { 0x000000f9, 0x000000f9 } },
933         { AR5K_RF_GAIN(42),     { 0x000000f9, 0x000000f9 } },
934         { AR5K_RF_GAIN(43),     { 0x000000f9, 0x000000f9 } },
935         { AR5K_RF_GAIN(44),     { 0x000000f9, 0x000000f9 } },
936         { AR5K_RF_GAIN(45),     { 0x000000f9, 0x000000f9 } },
937         { AR5K_RF_GAIN(46),     { 0x000000f9, 0x000000f9 } },
938         { AR5K_RF_GAIN(47),     { 0x000000f9, 0x000000f9 } },
939         { AR5K_RF_GAIN(48),     { 0x000000f9, 0x000000f9 } },
940         { AR5K_RF_GAIN(49),     { 0x000000f9, 0x000000f9 } },
941         { AR5K_RF_GAIN(50),     { 0x000000f9, 0x000000f9 } },
942         { AR5K_RF_GAIN(51),     { 0x000000f9, 0x000000f9 } },
943         { AR5K_RF_GAIN(52),     { 0x000000f9, 0x000000f9 } },
944         { AR5K_RF_GAIN(53),     { 0x000000f9, 0x000000f9 } },
945         { AR5K_RF_GAIN(54),     { 0x000000f9, 0x000000f9 } },
946         { AR5K_RF_GAIN(55),     { 0x000000f9, 0x000000f9 } },
947         { AR5K_RF_GAIN(56),     { 0x000000f9, 0x000000f9 } },
948         { AR5K_RF_GAIN(57),     { 0x000000f9, 0x000000f9 } },
949         { AR5K_RF_GAIN(58),     { 0x000000f9, 0x000000f9 } },
950         { AR5K_RF_GAIN(59),     { 0x000000f9, 0x000000f9 } },
951         { AR5K_RF_GAIN(60),     { 0x000000f9, 0x000000f9 } },
952         { AR5K_RF_GAIN(61),     { 0x000000f9, 0x000000f9 } },
953         { AR5K_RF_GAIN(62),     { 0x000000f9, 0x000000f9 } },
954         { AR5K_RF_GAIN(63),     { 0x000000f9, 0x000000f9 } },
955 };
956
957 /* Initial RF Gain settings for RF2413 */
958 static const struct ath5k_ini_rfgain rfgain_2413[] = {
959         { AR5K_RF_GAIN(0), { 0x00000000 } },
960         { AR5K_RF_GAIN(1), { 0x00000040 } },
961         { AR5K_RF_GAIN(2), { 0x00000080 } },
962         { AR5K_RF_GAIN(3), { 0x00000181 } },
963         { AR5K_RF_GAIN(4), { 0x000001c1 } },
964         { AR5K_RF_GAIN(5), { 0x00000001 } },
965         { AR5K_RF_GAIN(6), { 0x00000041 } },
966         { AR5K_RF_GAIN(7), { 0x00000081 } },
967         { AR5K_RF_GAIN(8), { 0x00000168 } },
968         { AR5K_RF_GAIN(9), { 0x000001a8 } },
969         { AR5K_RF_GAIN(10), { 0x000001e8 } },
970         { AR5K_RF_GAIN(11), { 0x00000028 } },
971         { AR5K_RF_GAIN(12), { 0x00000068 } },
972         { AR5K_RF_GAIN(13), { 0x00000189 } },
973         { AR5K_RF_GAIN(14), { 0x000001c9 } },
974         { AR5K_RF_GAIN(15), { 0x00000009 } },
975         { AR5K_RF_GAIN(16), { 0x00000049 } },
976         { AR5K_RF_GAIN(17), { 0x00000089 } },
977         { AR5K_RF_GAIN(18), { 0x00000190 } },
978         { AR5K_RF_GAIN(19), { 0x000001d0 } },
979         { AR5K_RF_GAIN(20), { 0x00000010 } },
980         { AR5K_RF_GAIN(21), { 0x00000050 } },
981         { AR5K_RF_GAIN(22), { 0x00000090 } },
982         { AR5K_RF_GAIN(23), { 0x00000191 } },
983         { AR5K_RF_GAIN(24), { 0x000001d1 } },
984         { AR5K_RF_GAIN(25), { 0x00000011 } },
985         { AR5K_RF_GAIN(26), { 0x00000051 } },
986         { AR5K_RF_GAIN(27), { 0x00000091 } },
987         { AR5K_RF_GAIN(28), { 0x00000178 } },
988         { AR5K_RF_GAIN(29), { 0x000001b8 } },
989         { AR5K_RF_GAIN(30), { 0x000001f8 } },
990         { AR5K_RF_GAIN(31), { 0x00000038 } },
991         { AR5K_RF_GAIN(32), { 0x00000078 } },
992         { AR5K_RF_GAIN(33), { 0x00000199 } },
993         { AR5K_RF_GAIN(34), { 0x000001d9 } },
994         { AR5K_RF_GAIN(35), { 0x00000019 } },
995         { AR5K_RF_GAIN(36), { 0x00000059 } },
996         { AR5K_RF_GAIN(37), { 0x00000099 } },
997         { AR5K_RF_GAIN(38), { 0x000000d9 } },
998         { AR5K_RF_GAIN(39), { 0x000000f9 } },
999         { AR5K_RF_GAIN(40), { 0x000000f9 } },
1000         { AR5K_RF_GAIN(41), { 0x000000f9 } },
1001         { AR5K_RF_GAIN(42), { 0x000000f9 } },
1002         { AR5K_RF_GAIN(43), { 0x000000f9 } },
1003         { AR5K_RF_GAIN(44), { 0x000000f9 } },
1004         { AR5K_RF_GAIN(45), { 0x000000f9 } },
1005         { AR5K_RF_GAIN(46), { 0x000000f9 } },
1006         { AR5K_RF_GAIN(47), { 0x000000f9 } },
1007         { AR5K_RF_GAIN(48), { 0x000000f9 } },
1008         { AR5K_RF_GAIN(49), { 0x000000f9 } },
1009         { AR5K_RF_GAIN(50), { 0x000000f9 } },
1010         { AR5K_RF_GAIN(51), { 0x000000f9 } },
1011         { AR5K_RF_GAIN(52), { 0x000000f9 } },
1012         { AR5K_RF_GAIN(53), { 0x000000f9 } },
1013         { AR5K_RF_GAIN(54), { 0x000000f9 } },
1014         { AR5K_RF_GAIN(55), { 0x000000f9 } },
1015         { AR5K_RF_GAIN(56), { 0x000000f9 } },
1016         { AR5K_RF_GAIN(57), { 0x000000f9 } },
1017         { AR5K_RF_GAIN(58), { 0x000000f9 } },
1018         { AR5K_RF_GAIN(59), { 0x000000f9 } },
1019         { AR5K_RF_GAIN(60), { 0x000000f9 } },
1020         { AR5K_RF_GAIN(61), { 0x000000f9 } },
1021         { AR5K_RF_GAIN(62), { 0x000000f9 } },
1022         { AR5K_RF_GAIN(63), { 0x000000f9 } },
1023 };
1024
1025 /* Initial RF Gain settings for RF2425 */
1026 static const struct ath5k_ini_rfgain rfgain_2425[] = {
1027         { AR5K_RF_GAIN(0), { 0x00000000 } },
1028         { AR5K_RF_GAIN(1), { 0x00000040 } },
1029         { AR5K_RF_GAIN(2), { 0x00000080 } },
1030         { AR5K_RF_GAIN(3), { 0x00000181 } },
1031         { AR5K_RF_GAIN(4), { 0x000001c1 } },
1032         { AR5K_RF_GAIN(5), { 0x00000001 } },
1033         { AR5K_RF_GAIN(6), { 0x00000041 } },
1034         { AR5K_RF_GAIN(7), { 0x00000081 } },
1035         { AR5K_RF_GAIN(8), { 0x00000188 } },
1036         { AR5K_RF_GAIN(9), { 0x000001c8 } },
1037         { AR5K_RF_GAIN(10), { 0x00000008 } },
1038         { AR5K_RF_GAIN(11), { 0x00000048 } },
1039         { AR5K_RF_GAIN(12), { 0x00000088 } },
1040         { AR5K_RF_GAIN(13), { 0x00000189 } },
1041         { AR5K_RF_GAIN(14), { 0x000001c9 } },
1042         { AR5K_RF_GAIN(15), { 0x00000009 } },
1043         { AR5K_RF_GAIN(16), { 0x00000049 } },
1044         { AR5K_RF_GAIN(17), { 0x00000089 } },
1045         { AR5K_RF_GAIN(18), { 0x000001b0 } },
1046         { AR5K_RF_GAIN(19), { 0x000001f0 } },
1047         { AR5K_RF_GAIN(20), { 0x00000030 } },
1048         { AR5K_RF_GAIN(21), { 0x00000070 } },
1049         { AR5K_RF_GAIN(22), { 0x00000171 } },
1050         { AR5K_RF_GAIN(23), { 0x000001b1 } },
1051         { AR5K_RF_GAIN(24), { 0x000001f1 } },
1052         { AR5K_RF_GAIN(25), { 0x00000031 } },
1053         { AR5K_RF_GAIN(26), { 0x00000071 } },
1054         { AR5K_RF_GAIN(27), { 0x000001b8 } },
1055         { AR5K_RF_GAIN(28), { 0x000001f8 } },
1056         { AR5K_RF_GAIN(29), { 0x00000038 } },
1057         { AR5K_RF_GAIN(30), { 0x00000078 } },
1058         { AR5K_RF_GAIN(31), { 0x000000b8 } },
1059         { AR5K_RF_GAIN(32), { 0x000001b9 } },
1060         { AR5K_RF_GAIN(33), { 0x000001f9 } },
1061         { AR5K_RF_GAIN(34), { 0x00000039 } },
1062         { AR5K_RF_GAIN(35), { 0x00000079 } },
1063         { AR5K_RF_GAIN(36), { 0x000000b9 } },
1064         { AR5K_RF_GAIN(37), { 0x000000f9 } },
1065         { AR5K_RF_GAIN(38), { 0x000000f9 } },
1066         { AR5K_RF_GAIN(39), { 0x000000f9 } },
1067         { AR5K_RF_GAIN(40), { 0x000000f9 } },
1068         { AR5K_RF_GAIN(41), { 0x000000f9 } },
1069         { AR5K_RF_GAIN(42), { 0x000000f9 } },
1070         { AR5K_RF_GAIN(43), { 0x000000f9 } },
1071         { AR5K_RF_GAIN(44), { 0x000000f9 } },
1072         { AR5K_RF_GAIN(45), { 0x000000f9 } },
1073         { AR5K_RF_GAIN(46), { 0x000000f9 } },
1074         { AR5K_RF_GAIN(47), { 0x000000f9 } },
1075         { AR5K_RF_GAIN(48), { 0x000000f9 } },
1076         { AR5K_RF_GAIN(49), { 0x000000f9 } },
1077         { AR5K_RF_GAIN(50), { 0x000000f9 } },
1078         { AR5K_RF_GAIN(51), { 0x000000f9 } },
1079         { AR5K_RF_GAIN(52), { 0x000000f9 } },
1080         { AR5K_RF_GAIN(53), { 0x000000f9 } },
1081         { AR5K_RF_GAIN(54), { 0x000000f9 } },
1082         { AR5K_RF_GAIN(55), { 0x000000f9 } },
1083         { AR5K_RF_GAIN(56), { 0x000000f9 } },
1084         { AR5K_RF_GAIN(57), { 0x000000f9 } },
1085         { AR5K_RF_GAIN(58), { 0x000000f9 } },
1086         { AR5K_RF_GAIN(59), { 0x000000f9 } },
1087         { AR5K_RF_GAIN(60), { 0x000000f9 } },
1088         { AR5K_RF_GAIN(61), { 0x000000f9 } },
1089         { AR5K_RF_GAIN(62), { 0x000000f9 } },
1090         { AR5K_RF_GAIN(63), { 0x000000f9 } },
1091 };
1092
1093 static const struct ath5k_gain_opt rfgain_opt_5112 = {
1094         1,
1095         8,
1096         {
1097                 { { 3, 0, 0, 0, 0, 0, 0 }, 6 },
1098                 { { 2, 0, 0, 0, 0, 0, 0 }, 0 },
1099                 { { 1, 0, 0, 0, 0, 0, 0 }, -3 },
1100                 { { 0, 0, 0, 0, 0, 0, 0 }, -6 },
1101                 { { 0, 1, 1, 0, 0, 0, 0 }, -8 },
1102                 { { 0, 1, 1, 0, 1, 1, 0 }, -10 },
1103                 { { 0, 1, 0, 1, 1, 1, 0 }, -13 },
1104                 { { 0, 1, 0, 1, 1, 0, 1 }, -16 },
1105         }
1106 };
1107
1108 /*
1109  * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
1110  */
1111 static unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits,
1112                 u32 first, u32 col, bool set)
1113 {
1114         u32 mask, entry, last, data, shift, position;
1115         s32 left;
1116         int i;
1117
1118         data = 0;
1119
1120         if (rf == NULL)
1121                 /* should not happen */
1122                 return 0;
1123
1124         if (!(col <= 3 && bits <= 32 && first + bits <= 319)) {
1125                 ATH5K_PRINTF("invalid values at offset %u\n", offset);
1126                 return 0;
1127         }
1128
1129         entry = ((first - 1) / 8) + offset;
1130         position = (first - 1) % 8;
1131
1132         if (set)
1133                 data = ath5k_hw_bitswap(reg, bits);
1134
1135         for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) {
1136                 last = (position + left > 8) ? 8 : position + left;
1137                 mask = (((1 << last) - 1) ^ ((1 << position) - 1)) << (col * 8);
1138
1139                 if (set) {
1140                         rf[entry] &= ~mask;
1141                         rf[entry] |= ((data << position) << (col * 8)) & mask;
1142                         data >>= (8 - position);
1143                 } else {
1144                         data = (((rf[entry] & mask) >> (col * 8)) >> position)
1145                                 << shift;
1146                         shift += last - position;
1147                 }
1148
1149                 left -= 8 - position;
1150         }
1151
1152         data = set ? 1 : ath5k_hw_bitswap(data, bits);
1153
1154         return data;
1155 }
1156
1157 static u32 ath5k_hw_rfregs_gainf_corr(struct ath5k_hw *ah)
1158 {
1159         u32 mix, step;
1160         u32 *rf;
1161
1162         if (ah->ah_rf_banks == NULL)
1163                 return 0;
1164
1165         rf = ah->ah_rf_banks;
1166         ah->ah_gain.g_f_corr = 0;
1167
1168         if (ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 1, 36, 0, false) != 1)
1169                 return 0;
1170
1171         step = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 4, 32, 0, false);
1172         mix = ah->ah_gain.g_step->gos_param[0];
1173
1174         switch (mix) {
1175         case 3:
1176                 ah->ah_gain.g_f_corr = step * 2;
1177                 break;
1178         case 2:
1179                 ah->ah_gain.g_f_corr = (step - 5) * 2;
1180                 break;
1181         case 1:
1182                 ah->ah_gain.g_f_corr = step;
1183                 break;
1184         default:
1185                 ah->ah_gain.g_f_corr = 0;
1186                 break;
1187         }
1188
1189         return ah->ah_gain.g_f_corr;
1190 }
1191
1192 static bool ath5k_hw_rfregs_gain_readback(struct ath5k_hw *ah)
1193 {
1194         u32 step, mix, level[4];
1195         u32 *rf;
1196
1197         if (ah->ah_rf_banks == NULL)
1198                 return false;
1199
1200         rf = ah->ah_rf_banks;
1201
1202         if (ah->ah_radio == AR5K_RF5111) {
1203                 step = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 6, 37, 0,
1204                                 false);
1205                 level[0] = 0;
1206                 level[1] = (step == 0x3f) ? 0x32 : step + 4;
1207                 level[2] = (step != 0x3f) ? 0x40 : level[0];
1208                 level[3] = level[2] + 0x32;
1209
1210                 ah->ah_gain.g_high = level[3] -
1211                         (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
1212                 ah->ah_gain.g_low = level[0] +
1213                         (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
1214         } else {
1215                 mix = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 1, 36, 0,
1216                                 false);
1217                 level[0] = level[2] = 0;
1218
1219                 if (mix == 1) {
1220                         level[1] = level[3] = 83;
1221                 } else {
1222                         level[1] = level[3] = 107;
1223                         ah->ah_gain.g_high = 55;
1224                 }
1225         }
1226
1227         return (ah->ah_gain.g_current >= level[0] &&
1228                         ah->ah_gain.g_current <= level[1]) ||
1229                 (ah->ah_gain.g_current >= level[2] &&
1230                         ah->ah_gain.g_current <= level[3]);
1231 }
1232
1233 static s32 ath5k_hw_rfregs_gain_adjust(struct ath5k_hw *ah)
1234 {
1235         const struct ath5k_gain_opt *go;
1236         int ret = 0;
1237
1238         switch (ah->ah_radio) {
1239         case AR5K_RF5111:
1240                 go = &rfgain_opt_5111;
1241                 break;
1242         case AR5K_RF5112:
1243                 go = &rfgain_opt_5112;
1244                 break;
1245         default:
1246                 return 0;
1247         }
1248
1249         ah->ah_gain.g_step = &go->go_step[ah->ah_gain.g_step_idx];
1250
1251         if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {
1252                 if (ah->ah_gain.g_step_idx == 0)
1253                         return -1;
1254                 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
1255                                 ah->ah_gain.g_target >=  ah->ah_gain.g_high &&
1256                                 ah->ah_gain.g_step_idx > 0;
1257                                 ah->ah_gain.g_step =
1258                                         &go->go_step[ah->ah_gain.g_step_idx])
1259                         ah->ah_gain.g_target -= 2 *
1260                             (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -
1261                             ah->ah_gain.g_step->gos_gain);
1262
1263                 ret = 1;
1264                 goto done;
1265         }
1266
1267         if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {
1268                 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))
1269                         return -2;
1270                 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
1271                                 ah->ah_gain.g_target <= ah->ah_gain.g_low &&
1272                                 ah->ah_gain.g_step_idx < go->go_steps_count-1;
1273                                 ah->ah_gain.g_step =
1274                                         &go->go_step[ah->ah_gain.g_step_idx])
1275                         ah->ah_gain.g_target -= 2 *
1276                             (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
1277                             ah->ah_gain.g_step->gos_gain);
1278
1279                 ret = 2;
1280                 goto done;
1281         }
1282
1283 done:
1284         ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1285                 "ret %d, gain step %u, current gain %u, target gain %u\n",
1286                 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current,
1287                 ah->ah_gain.g_target);
1288
1289         return ret;
1290 }
1291
1292 /*
1293  * Read EEPROM Calibration data, modify RF Banks and Initialize RF5111
1294  */
1295 static int ath5k_hw_rf5111_rfregs(struct ath5k_hw *ah,
1296                 struct ieee80211_channel *channel, unsigned int mode)
1297 {
1298         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1299         u32 *rf;
1300         const unsigned int rf_size = ARRAY_SIZE(rfregs_5111);
1301         unsigned int i;
1302         int obdb = -1, bank = -1;
1303         u32 ee_mode;
1304
1305         AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
1306
1307         rf = ah->ah_rf_banks;
1308
1309         /* Copy values to modify them */
1310         for (i = 0; i < rf_size; i++) {
1311                 if (rfregs_5111[i].rf_bank >= AR5K_RF5111_INI_RF_MAX_BANKS) {
1312                         ATH5K_ERR(ah->ah_sc, "invalid bank\n");
1313                         return -EINVAL;
1314                 }
1315
1316                 if (bank != rfregs_5111[i].rf_bank) {
1317                         bank = rfregs_5111[i].rf_bank;
1318                         ah->ah_offset[bank] = i;
1319                 }
1320
1321                 rf[i] = rfregs_5111[i].rf_value[mode];
1322         }
1323
1324         /* Modify bank 0 */
1325         if (channel->hw_value & CHANNEL_2GHZ) {
1326                 if (channel->hw_value & CHANNEL_CCK)
1327                         ee_mode = AR5K_EEPROM_MODE_11B;
1328                 else
1329                         ee_mode = AR5K_EEPROM_MODE_11G;
1330                 obdb = 0;
1331
1332                 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[0],
1333                                 ee->ee_ob[ee_mode][obdb], 3, 119, 0, true))
1334                         return -EINVAL;
1335
1336                 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[0],
1337                                 ee->ee_ob[ee_mode][obdb], 3, 122, 0, true))
1338                         return -EINVAL;
1339
1340                 obdb = 1;
1341         /* Modify bank 6 */
1342         } else {
1343                 /* For 11a, Turbo and XR */
1344                 ee_mode = AR5K_EEPROM_MODE_11A;
1345                 obdb =   channel->center_freq >= 5725 ? 3 :
1346                         (channel->center_freq >= 5500 ? 2 :
1347                         (channel->center_freq >= 5260 ? 1 :
1348                          (channel->center_freq > 4000 ? 0 : -1)));
1349
1350                 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1351                                 ee->ee_pwd_84, 1, 51, 3, true))
1352                         return -EINVAL;
1353
1354                 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1355                                 ee->ee_pwd_90, 1, 45, 3, true))
1356                         return -EINVAL;
1357         }
1358
1359         if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1360                         !ee->ee_xpd[ee_mode], 1, 95, 0, true))
1361                 return -EINVAL;
1362
1363         if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1364                         ee->ee_x_gain[ee_mode], 4, 96, 0, true))
1365                 return -EINVAL;
1366
1367         if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6], obdb >= 0 ?
1368                         ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, true))
1369                 return -EINVAL;
1370
1371         if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6], obdb >= 0 ?
1372                         ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, true))
1373                 return -EINVAL;
1374
1375         /* Modify bank 7 */
1376         if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
1377                         ee->ee_i_gain[ee_mode], 6, 29, 0, true))
1378                 return -EINVAL;
1379
1380         if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
1381                         ee->ee_xpd[ee_mode], 1, 4, 0, true))
1382                 return -EINVAL;
1383
1384         /* Write RF values */
1385         for (i = 0; i < rf_size; i++) {
1386                 AR5K_REG_WAIT(i);
1387                 ath5k_hw_reg_write(ah, rf[i], rfregs_5111[i].rf_register);
1388         }
1389
1390         return 0;
1391 }
1392
1393 /*
1394  * Read EEPROM Calibration data, modify RF Banks and Initialize RF5112
1395  */
1396 static int ath5k_hw_rf5112_rfregs(struct ath5k_hw *ah,
1397                 struct ieee80211_channel *channel, unsigned int mode)
1398 {
1399         const struct ath5k_ini_rf *rf_ini;
1400         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1401         u32 *rf;
1402         unsigned int rf_size, i;
1403         int obdb = -1, bank = -1;
1404         u32 ee_mode;
1405
1406         AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
1407
1408         rf = ah->ah_rf_banks;
1409
1410         if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_2112A
1411                 && !test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) {
1412                 rf_ini = rfregs_2112a;
1413                 rf_size = ARRAY_SIZE(rfregs_5112a);
1414                 if (mode < 2) {
1415                         ATH5K_ERR(ah->ah_sc,"invalid channel mode: %i\n",mode);
1416                         return -EINVAL;
1417                 }
1418                 mode = mode - 2; /*no a/turboa modes for 2112*/
1419         } else if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
1420                 rf_ini = rfregs_5112a;
1421                 rf_size = ARRAY_SIZE(rfregs_5112a);
1422         } else {
1423                 rf_ini = rfregs_5112;
1424                 rf_size = ARRAY_SIZE(rfregs_5112);
1425         }
1426
1427         /* Copy values to modify them */
1428         for (i = 0; i < rf_size; i++) {
1429                 if (rf_ini[i].rf_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) {
1430                         ATH5K_ERR(ah->ah_sc, "invalid bank\n");
1431                         return -EINVAL;
1432                 }
1433
1434                 if (bank != rf_ini[i].rf_bank) {
1435                         bank = rf_ini[i].rf_bank;
1436                         ah->ah_offset[bank] = i;
1437                 }
1438
1439                 rf[i] = rf_ini[i].rf_value[mode];
1440         }
1441
1442         /* Modify bank 6 */
1443         if (channel->hw_value & CHANNEL_2GHZ) {
1444                 if (channel->hw_value & CHANNEL_OFDM)
1445                         ee_mode = AR5K_EEPROM_MODE_11G;
1446                 else
1447                         ee_mode = AR5K_EEPROM_MODE_11B;
1448                 obdb = 0;
1449
1450                 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1451                                 ee->ee_ob[ee_mode][obdb], 3, 287, 0, true))
1452                         return -EINVAL;
1453
1454                 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1455                                 ee->ee_ob[ee_mode][obdb], 3, 290, 0, true))
1456                         return -EINVAL;
1457         } else {
1458                 /* For 11a, Turbo and XR */
1459                 ee_mode = AR5K_EEPROM_MODE_11A;
1460                 obdb = channel->center_freq >= 5725 ? 3 :
1461                     (channel->center_freq >= 5500 ? 2 :
1462                         (channel->center_freq >= 5260 ? 1 :
1463                             (channel->center_freq > 4000 ? 0 : -1)));
1464
1465                 if (obdb == -1)
1466                         return -EINVAL;
1467
1468                 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1469                                 ee->ee_ob[ee_mode][obdb], 3, 279, 0, true))
1470                         return -EINVAL;
1471
1472                 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1473                                 ee->ee_ob[ee_mode][obdb], 3, 282, 0, true))
1474                         return -EINVAL;
1475         }
1476
1477         ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1478             ee->ee_x_gain[ee_mode], 2, 270, 0, true);
1479         ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1480             ee->ee_x_gain[ee_mode], 2, 257, 0, true);
1481
1482         if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1483                         ee->ee_xpd[ee_mode], 1, 302, 0, true))
1484                 return -EINVAL;
1485
1486         /* Modify bank 7 */
1487         if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
1488                         ee->ee_i_gain[ee_mode], 6, 14, 0, true))
1489                 return -EINVAL;
1490
1491         /* Write RF values */
1492         for (i = 0; i < rf_size; i++)
1493                 ath5k_hw_reg_write(ah, rf[i], rf_ini[i].rf_register);
1494
1495         return 0;
1496 }
1497
1498 /*
1499  * Initialize RF5413/5414 and future chips
1500  * (until we come up with a better solution)
1501  */
1502 static int ath5k_hw_rf5413_rfregs(struct ath5k_hw *ah,
1503                 struct ieee80211_channel *channel, unsigned int mode)
1504 {
1505         const struct ath5k_ini_rf *rf_ini;
1506         u32 *rf;
1507         unsigned int rf_size, i;
1508         int bank = -1;
1509
1510         AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
1511
1512         rf = ah->ah_rf_banks;
1513
1514         switch (ah->ah_radio) {
1515         case AR5K_RF5413:
1516                 rf_ini = rfregs_5413;
1517                 rf_size = ARRAY_SIZE(rfregs_5413);
1518                 break;
1519         case AR5K_RF2413:
1520                 rf_ini = rfregs_2413;
1521                 rf_size = ARRAY_SIZE(rfregs_2413);
1522
1523                 if (mode < 2) {
1524                         ATH5K_ERR(ah->ah_sc,
1525                                 "invalid channel mode: %i\n", mode);
1526                         return -EINVAL;
1527                 }
1528
1529                 mode = mode - 2;
1530                 break;
1531         case AR5K_RF2425:
1532                 rf_ini = rfregs_2425;
1533                 rf_size = ARRAY_SIZE(rfregs_2425);
1534
1535                 if (mode < 2) {
1536                         ATH5K_ERR(ah->ah_sc,
1537                                 "invalid channel mode: %i\n", mode);
1538                         return -EINVAL;
1539                 }
1540
1541                 /* Map b to g */
1542                 if (mode == 2)
1543                         mode = 0;
1544                 else
1545                         mode = mode - 3;
1546
1547                 break;
1548         default:
1549                 return -EINVAL;
1550         }
1551
1552         /* Copy values to modify them */
1553         for (i = 0; i < rf_size; i++) {
1554                 if (rf_ini[i].rf_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) {
1555                         ATH5K_ERR(ah->ah_sc, "invalid bank\n");
1556                         return -EINVAL;
1557                 }
1558
1559                 if (bank != rf_ini[i].rf_bank) {
1560                         bank = rf_ini[i].rf_bank;
1561                         ah->ah_offset[bank] = i;
1562                 }
1563
1564                 rf[i] = rf_ini[i].rf_value[mode];
1565         }
1566
1567         /*
1568          * After compairing dumps from different cards
1569          * we get the same RF_BUFFER settings (diff returns
1570          * 0 lines). It seems that RF_BUFFER settings are static
1571          * and are written unmodified (no EEPROM stuff
1572          * is used because calibration data would be
1573          * different between different cards and would result
1574          * different RF_BUFFER settings)
1575          */
1576
1577         /* Write RF values */
1578         for (i = 0; i < rf_size; i++)
1579                 ath5k_hw_reg_write(ah, rf[i], rf_ini[i].rf_register);
1580
1581         return 0;
1582 }
1583
1584 /*
1585  * Initialize RF
1586  */
1587 int ath5k_hw_rfregs(struct ath5k_hw *ah, struct ieee80211_channel *channel,
1588                 unsigned int mode)
1589 {
1590         int (*func)(struct ath5k_hw *, struct ieee80211_channel *, unsigned int);
1591         int ret;
1592
1593         switch (ah->ah_radio) {
1594         case AR5K_RF5111:
1595                 ah->ah_rf_banks_size = sizeof(rfregs_5111);
1596                 func = ath5k_hw_rf5111_rfregs;
1597                 break;
1598         case AR5K_RF5112:
1599                 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
1600                         ah->ah_rf_banks_size = sizeof(rfregs_5112a);
1601                 else
1602                         ah->ah_rf_banks_size = sizeof(rfregs_5112);
1603                 func = ath5k_hw_rf5112_rfregs;
1604                 break;
1605         case AR5K_RF5413:
1606                 ah->ah_rf_banks_size = sizeof(rfregs_5413);
1607                 func = ath5k_hw_rf5413_rfregs;
1608                 break;
1609         case AR5K_RF2413:
1610                 ah->ah_rf_banks_size = sizeof(rfregs_2413);
1611                 func = ath5k_hw_rf5413_rfregs;
1612                 break;
1613         case AR5K_RF2425:
1614                 ah->ah_rf_banks_size = sizeof(rfregs_2425);
1615                 func = ath5k_hw_rf5413_rfregs;
1616                 break;
1617         default:
1618                 return -EINVAL;
1619         }
1620
1621         if (ah->ah_rf_banks == NULL) {
1622                 /* XXX do extra checks? */
1623                 ah->ah_rf_banks = kmalloc(ah->ah_rf_banks_size, GFP_KERNEL);
1624                 if (ah->ah_rf_banks == NULL) {
1625                         ATH5K_ERR(ah->ah_sc, "out of memory\n");
1626                         return -ENOMEM;
1627                 }
1628         }
1629
1630         ret = func(ah, channel, mode);
1631         if (!ret)
1632                 ah->ah_rf_gain = AR5K_RFGAIN_INACTIVE;
1633
1634         return ret;
1635 }
1636
1637 int ath5k_hw_rfgain(struct ath5k_hw *ah, unsigned int freq)
1638 {
1639         const struct ath5k_ini_rfgain *ath5k_rfg;
1640         unsigned int i, size;
1641
1642         switch (ah->ah_radio) {
1643         case AR5K_RF5111:
1644                 ath5k_rfg = rfgain_5111;
1645                 size = ARRAY_SIZE(rfgain_5111);
1646                 break;
1647         case AR5K_RF5112:
1648                 ath5k_rfg = rfgain_5112;
1649                 size = ARRAY_SIZE(rfgain_5112);
1650                 break;
1651         case AR5K_RF5413:
1652                 ath5k_rfg = rfgain_5413;
1653                 size = ARRAY_SIZE(rfgain_5413);
1654                 break;
1655         case AR5K_RF2413:
1656                 ath5k_rfg = rfgain_2413;
1657                 size = ARRAY_SIZE(rfgain_2413);
1658                 freq = 0; /* only 2Ghz */
1659                 break;
1660         case AR5K_RF2425:
1661                 ath5k_rfg = rfgain_2425;
1662                 size = ARRAY_SIZE(rfgain_2425);
1663                 freq = 0; /* only 2Ghz */
1664                 break;
1665         default:
1666                 return -EINVAL;
1667         }
1668
1669         switch (freq) {
1670         case AR5K_INI_RFGAIN_2GHZ:
1671         case AR5K_INI_RFGAIN_5GHZ:
1672                 break;
1673         default:
1674                 return -EINVAL;
1675         }
1676
1677         for (i = 0; i < size; i++) {
1678                 AR5K_REG_WAIT(i);
1679                 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq],
1680                         (u32)ath5k_rfg[i].rfg_register);
1681         }
1682
1683         return 0;
1684 }
1685
1686 enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath5k_hw *ah)
1687 {
1688         u32 data, type;
1689
1690         ATH5K_TRACE(ah->ah_sc);
1691
1692         if (ah->ah_rf_banks == NULL || !ah->ah_gain.g_active ||
1693                         ah->ah_version <= AR5K_AR5211)
1694                 return AR5K_RFGAIN_INACTIVE;
1695
1696         if (ah->ah_rf_gain != AR5K_RFGAIN_READ_REQUESTED)
1697                 goto done;
1698
1699         data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
1700
1701         if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
1702                 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
1703                 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
1704
1705                 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK)
1706                         ah->ah_gain.g_current += AR5K_GAIN_CCK_PROBE_CORR;
1707
1708                 if (ah->ah_radio >= AR5K_RF5112) {
1709                         ath5k_hw_rfregs_gainf_corr(ah);
1710                         ah->ah_gain.g_current =
1711                                 ah->ah_gain.g_current>=ah->ah_gain.g_f_corr ?
1712                                 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) :
1713                                 0;
1714                 }
1715
1716                 if (ath5k_hw_rfregs_gain_readback(ah) &&
1717                                 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
1718                                 ath5k_hw_rfregs_gain_adjust(ah))
1719                         ah->ah_rf_gain = AR5K_RFGAIN_NEED_CHANGE;
1720         }
1721
1722 done:
1723         return ah->ah_rf_gain;
1724 }
1725
1726 int ath5k_hw_set_rfgain_opt(struct ath5k_hw *ah)
1727 {
1728         /* Initialize the gain optimization values */
1729         switch (ah->ah_radio) {
1730         case AR5K_RF5111:
1731                 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
1732                 ah->ah_gain.g_step =
1733                     &rfgain_opt_5111.go_step[ah->ah_gain.g_step_idx];
1734                 ah->ah_gain.g_low = 20;
1735                 ah->ah_gain.g_high = 35;
1736                 ah->ah_gain.g_active = 1;
1737                 break;
1738         case AR5K_RF5112:
1739                 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
1740                 ah->ah_gain.g_step =
1741                     &rfgain_opt_5112.go_step[ah->ah_gain.g_step_idx];
1742                 ah->ah_gain.g_low = 20;
1743                 ah->ah_gain.g_high = 85;
1744                 ah->ah_gain.g_active = 1;
1745                 break;
1746         default:
1747                 return -EINVAL;
1748         }
1749
1750         return 0;
1751 }
1752
1753 /**************************\
1754   PHY/RF channel functions
1755 \**************************/
1756
1757 /*
1758  * Check if a channel is supported
1759  */
1760 bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
1761 {
1762         /* Check if the channel is in our supported range */
1763         if (flags & CHANNEL_2GHZ) {
1764                 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
1765                     (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
1766                         return true;
1767         } else if (flags & CHANNEL_5GHZ)
1768                 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
1769                     (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
1770                         return true;
1771
1772         return false;
1773 }
1774
1775 /*
1776  * Convertion needed for RF5110
1777  */
1778 static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
1779 {
1780         u32 athchan;
1781
1782         /*
1783          * Convert IEEE channel/MHz to an internal channel value used
1784          * by the AR5210 chipset. This has not been verified with
1785          * newer chipsets like the AR5212A who have a completely
1786          * different RF/PHY part.
1787          */
1788         athchan = (ath5k_hw_bitswap(
1789                         (ieee80211_frequency_to_channel(
1790                                 channel->center_freq) - 24) / 2, 5)
1791                                 << 1) | (1 << 6) | 0x1;
1792         return athchan;
1793 }
1794
1795 /*
1796  * Set channel on RF5110
1797  */
1798 static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
1799                 struct ieee80211_channel *channel)
1800 {
1801         u32 data;
1802
1803         /*
1804          * Set the channel and wait
1805          */
1806         data = ath5k_hw_rf5110_chan2athchan(channel);
1807         ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
1808         ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
1809         mdelay(1);
1810
1811         return 0;
1812 }
1813
1814 /*
1815  * Convertion needed for 5111
1816  */
1817 static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
1818                 struct ath5k_athchan_2ghz *athchan)
1819 {
1820         int channel;
1821
1822         /* Cast this value to catch negative channel numbers (>= -19) */
1823         channel = (int)ieee;
1824
1825         /*
1826          * Map 2GHz IEEE channel to 5GHz Atheros channel
1827          */
1828         if (channel <= 13) {
1829                 athchan->a2_athchan = 115 + channel;
1830                 athchan->a2_flags = 0x46;
1831         } else if (channel == 14) {
1832                 athchan->a2_athchan = 124;
1833                 athchan->a2_flags = 0x44;
1834         } else if (channel >= 15 && channel <= 26) {
1835                 athchan->a2_athchan = ((channel - 14) * 4) + 132;
1836                 athchan->a2_flags = 0x46;
1837         } else
1838                 return -EINVAL;
1839
1840         return 0;
1841 }
1842
1843 /*
1844  * Set channel on 5111
1845  */
1846 static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
1847                 struct ieee80211_channel *channel)
1848 {
1849         struct ath5k_athchan_2ghz ath5k_channel_2ghz;
1850         unsigned int ath5k_channel =
1851                 ieee80211_frequency_to_channel(channel->center_freq);
1852         u32 data0, data1, clock;
1853         int ret;
1854
1855         /*
1856          * Set the channel on the RF5111 radio
1857          */
1858         data0 = data1 = 0;
1859
1860         if (channel->hw_value & CHANNEL_2GHZ) {
1861                 /* Map 2GHz channel to 5GHz Atheros channel ID */
1862                 ret = ath5k_hw_rf5111_chan2athchan(
1863                         ieee80211_frequency_to_channel(channel->center_freq),
1864                         &ath5k_channel_2ghz);
1865                 if (ret)
1866                         return ret;
1867
1868                 ath5k_channel = ath5k_channel_2ghz.a2_athchan;
1869                 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
1870                     << 5) | (1 << 4);
1871         }
1872
1873         if (ath5k_channel < 145 || !(ath5k_channel & 1)) {
1874                 clock = 1;
1875                 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) |
1876                         (clock << 1) | (1 << 10) | 1;
1877         } else {
1878                 clock = 0;
1879                 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff)
1880                         << 2) | (clock << 1) | (1 << 10) | 1;
1881         }
1882
1883         ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
1884                         AR5K_RF_BUFFER);
1885         ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
1886                         AR5K_RF_BUFFER_CONTROL_3);
1887
1888         return 0;
1889 }
1890
1891 /*
1892  * Set channel on 5112 and newer
1893  */
1894 static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
1895                 struct ieee80211_channel *channel)
1896 {
1897         u32 data, data0, data1, data2;
1898         u16 c;
1899
1900         data = data0 = data1 = data2 = 0;
1901         c = channel->center_freq;
1902
1903         if (c < 4800) {
1904                 if (!((c - 2224) % 5)) {
1905                         data0 = ((2 * (c - 704)) - 3040) / 10;
1906                         data1 = 1;
1907                 } else if (!((c - 2192) % 5)) {
1908                         data0 = ((2 * (c - 672)) - 3040) / 10;
1909                         data1 = 0;
1910                 } else
1911                         return -EINVAL;
1912
1913                 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
1914         } else if ((c - (c % 5)) != 2 || c > 5435) {
1915                 if (!(c % 20) && c >= 5120) {
1916                         data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1917                         data2 = ath5k_hw_bitswap(3, 2);
1918                 } else if (!(c % 10)) {
1919                         data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1920                         data2 = ath5k_hw_bitswap(2, 2);
1921                 } else if (!(c % 5)) {
1922                         data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1923                         data2 = ath5k_hw_bitswap(1, 2);
1924                 } else
1925                         return -EINVAL;
1926         } else {
1927                 data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8);
1928                 data2 = ath5k_hw_bitswap(0, 2);
1929         }
1930
1931         data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
1932
1933         ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1934         ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1935
1936         return 0;
1937 }
1938
1939 /*
1940  * Set the channel on the RF2425
1941  */
1942 static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
1943                 struct ieee80211_channel *channel)
1944 {
1945         u32 data, data0, data2;
1946         u16 c;
1947
1948         data = data0 = data2 = 0;
1949         c = channel->center_freq;
1950
1951         if (c < 4800) {
1952                 data0 = ath5k_hw_bitswap((c - 2272), 8);
1953                 data2 = 0;
1954         /* ? 5GHz ? */
1955         } else if ((c - (c % 5)) != 2 || c > 5435) {
1956                 if (!(c % 20) && c < 5120)
1957                         data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1958                 else if (!(c % 10))
1959                         data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1960                 else if (!(c % 5))
1961                         data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1962                 else
1963                         return -EINVAL;
1964                 data2 = ath5k_hw_bitswap(1, 2);
1965         } else {
1966                 data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8);
1967                 data2 = ath5k_hw_bitswap(0, 2);
1968         }
1969
1970         data = (data0 << 4) | data2 << 2 | 0x1001;
1971
1972         ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1973         ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1974
1975         return 0;
1976 }
1977
1978 /*
1979  * Set a channel on the radio chip
1980  */
1981 int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel)
1982 {
1983         int ret;
1984         /*
1985          * Check bounds supported by the PHY (we don't care about regultory
1986          * restrictions at this point). Note: hw_value already has the band
1987          * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
1988          * of the band by that */
1989         if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
1990                 ATH5K_ERR(ah->ah_sc,
1991                         "channel frequency (%u MHz) out of supported "
1992                         "band range\n",
1993                         channel->center_freq);
1994                         return -EINVAL;
1995         }
1996
1997         /*
1998          * Set the channel and wait
1999          */
2000         switch (ah->ah_radio) {
2001         case AR5K_RF5110:
2002                 ret = ath5k_hw_rf5110_channel(ah, channel);
2003                 break;
2004         case AR5K_RF5111:
2005                 ret = ath5k_hw_rf5111_channel(ah, channel);
2006                 break;
2007         case AR5K_RF2425:
2008                 ret = ath5k_hw_rf2425_channel(ah, channel);
2009                 break;
2010         default:
2011                 ret = ath5k_hw_rf5112_channel(ah, channel);
2012                 break;
2013         }
2014
2015         if (ret)
2016                 return ret;
2017
2018         /* Set JAPAN setting for channel 14 */
2019         if (channel->center_freq == 2484) {
2020                 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
2021                                 AR5K_PHY_CCKTXCTL_JAPAN);
2022         } else {
2023                 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
2024                                 AR5K_PHY_CCKTXCTL_WORLD);
2025         }
2026
2027         ah->ah_current_channel.center_freq = channel->center_freq;
2028         ah->ah_current_channel.hw_value = channel->hw_value;
2029         ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false;
2030
2031         return 0;
2032 }
2033
2034 /*****************\
2035   PHY calibration
2036 \*****************/
2037
2038 /**
2039  * ath5k_hw_noise_floor_calibration - perform PHY noise floor calibration
2040  *
2041  * @ah: struct ath5k_hw pointer we are operating on
2042  * @freq: the channel frequency, just used for error logging
2043  *
2044  * This function performs a noise floor calibration of the PHY and waits for
2045  * it to complete. Then the noise floor value is compared to some maximum
2046  * noise floor we consider valid.
2047  *
2048  * Note that this is different from what the madwifi HAL does: it reads the
2049  * noise floor and afterwards initiates the calibration. Since the noise floor
2050  * calibration can take some time to finish, depending on the current channel
2051  * use, that avoids the occasional timeout warnings we are seeing now.
2052  *
2053  * See the following link for an Atheros patent on noise floor calibration:
2054  * http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL \
2055  * &p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7245893.PN.&OS=PN/7
2056  *
2057  * XXX: Since during noise floor calibration antennas are detached according to
2058  * the patent, we should stop tx queues here.
2059  */
2060 int
2061 ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq)
2062 {
2063         int ret;
2064         unsigned int i;
2065         s32 noise_floor;
2066
2067         /*
2068          * Enable noise floor calibration
2069          */
2070         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
2071                                 AR5K_PHY_AGCCTL_NF);
2072
2073         ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
2074                         AR5K_PHY_AGCCTL_NF, 0, false);
2075         if (ret) {
2076                 ATH5K_ERR(ah->ah_sc,
2077                         "noise floor calibration timeout (%uMHz)\n", freq);
2078                 return -EAGAIN;
2079         }
2080
2081         /* Wait until the noise floor is calibrated and read the value */
2082         for (i = 20; i > 0; i--) {
2083                 mdelay(1);
2084                 noise_floor = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
2085                 noise_floor = AR5K_PHY_NF_RVAL(noise_floor);
2086                 if (noise_floor & AR5K_PHY_NF_ACTIVE) {
2087                         noise_floor = AR5K_PHY_NF_AVAL(noise_floor);
2088
2089                         if (noise_floor <= AR5K_TUNE_NOISE_FLOOR)
2090                                 break;
2091                 }
2092         }
2093
2094         ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
2095                 "noise floor %d\n", noise_floor);
2096
2097         if (noise_floor > AR5K_TUNE_NOISE_FLOOR) {
2098                 ATH5K_ERR(ah->ah_sc,
2099                         "noise floor calibration failed (%uMHz)\n", freq);
2100                 return -EAGAIN;
2101         }
2102
2103         ah->ah_noise_floor = noise_floor;
2104
2105         return 0;
2106 }
2107
2108 /*
2109  * Perform a PHY calibration on RF5110
2110  * -Fix BPSK/QAM Constellation (I/Q correction)
2111  * -Calculate Noise Floor
2112  */
2113 static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
2114                 struct ieee80211_channel *channel)
2115 {
2116         u32 phy_sig, phy_agc, phy_sat, beacon;
2117         int ret;
2118
2119         /*
2120          * Disable beacons and RX/TX queues, wait
2121          */
2122         AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
2123                 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
2124         beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
2125         ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
2126
2127         mdelay(2);
2128
2129         /*
2130          * Set the channel (with AGC turned off)
2131          */
2132         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
2133         udelay(10);
2134         ret = ath5k_hw_channel(ah, channel);
2135
2136         /*
2137          * Activate PHY and wait
2138          */
2139         ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
2140         mdelay(1);
2141
2142         AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
2143
2144         if (ret)
2145                 return ret;
2146
2147         /*
2148          * Calibrate the radio chip
2149          */
2150
2151         /* Remember normal state */
2152         phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
2153         phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
2154         phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
2155
2156         /* Update radio registers */
2157         ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
2158                 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
2159
2160         ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
2161                         AR5K_PHY_AGCCOARSE_LO)) |
2162                 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
2163                 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
2164
2165         ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
2166                         AR5K_PHY_ADCSAT_THR)) |
2167                 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
2168                 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
2169
2170         udelay(20);
2171
2172         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
2173         udelay(10);
2174         ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
2175         AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
2176
2177         mdelay(1);
2178
2179         /*
2180          * Enable calibration and wait until completion
2181          */
2182         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
2183
2184         ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
2185                         AR5K_PHY_AGCCTL_CAL, 0, false);
2186
2187         /* Reset to normal state */
2188         ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG);
2189         ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE);
2190         ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT);
2191
2192         if (ret) {
2193                 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
2194                                 channel->center_freq);
2195                 return ret;
2196         }
2197
2198         ret = ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
2199         if (ret)
2200                 return ret;
2201
2202         /*
2203          * Re-enable RX/TX and beacons
2204          */
2205         AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
2206                 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
2207         ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
2208
2209         return 0;
2210 }
2211
2212 /*
2213  * Perform a PHY calibration on RF5111/5112 and newer chips
2214  */
2215 static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah,
2216                 struct ieee80211_channel *channel)
2217 {
2218         u32 i_pwr, q_pwr;
2219         s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
2220         int i;
2221         ATH5K_TRACE(ah->ah_sc);
2222
2223         if (!ah->ah_calibration ||
2224                 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
2225                 goto done;
2226
2227         /* Calibration has finished, get the results and re-run */
2228         for (i = 0; i <= 10; i++) {
2229                 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
2230                 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
2231                 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
2232         }
2233
2234         i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
2235         q_coffd = q_pwr >> 7;
2236
2237         /* No correction */
2238         if (i_coffd == 0 || q_coffd == 0)
2239                 goto done;
2240
2241         i_coff = ((-iq_corr) / i_coffd) & 0x3f;
2242
2243         /* Boundary check */
2244         if (i_coff > 31)
2245                 i_coff = 31;
2246         if (i_coff < -32)
2247                 i_coff = -32;
2248
2249         q_coff = (((s32)i_pwr / q_coffd) - 128) & 0x1f;
2250
2251         /* Boundary check */
2252         if (q_coff > 15)
2253                 q_coff = 15;
2254         if (q_coff < -16)
2255                 q_coff = -16;
2256
2257         /* Commit new I/Q value */
2258         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE |
2259                 ((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S));
2260
2261         /* Re-enable calibration -if we don't we'll commit
2262          * the same values again and again */
2263         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
2264                         AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
2265         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN);
2266
2267 done:
2268
2269         /* TODO: Separate noise floor calibration from I/Q calibration
2270          * since noise floor calibration interrupts rx path while I/Q
2271          * calibration doesn't. We don't need to run noise floor calibration
2272          * as often as I/Q calibration.*/
2273         ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
2274
2275         /* Request RF gain */
2276         if (channel->hw_value & CHANNEL_5GHZ) {
2277                 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_max,
2278                         AR5K_PHY_PAPD_PROBE_TXPOWER) |
2279                         AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
2280                 ah->ah_rf_gain = AR5K_RFGAIN_READ_REQUESTED;
2281         }
2282
2283         return 0;
2284 }
2285
2286 /*
2287  * Perform a PHY calibration
2288  */
2289 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
2290                 struct ieee80211_channel *channel)
2291 {
2292         int ret;
2293
2294         if (ah->ah_radio == AR5K_RF5110)
2295                 ret = ath5k_hw_rf5110_calibrate(ah, channel);
2296         else
2297                 ret = ath5k_hw_rf511x_calibrate(ah, channel);
2298
2299         return ret;
2300 }
2301
2302 int ath5k_hw_phy_disable(struct ath5k_hw *ah)
2303 {
2304         ATH5K_TRACE(ah->ah_sc);
2305         /*Just a try M.F.*/
2306         ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
2307
2308         return 0;
2309 }
2310
2311 /********************\
2312   Misc PHY functions
2313 \********************/
2314
2315 /*
2316  * Get the PHY Chip revision
2317  */
2318 u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
2319 {
2320         unsigned int i;
2321         u32 srev;
2322         u16 ret;
2323
2324         ATH5K_TRACE(ah->ah_sc);
2325
2326         /*
2327          * Set the radio chip access register
2328          */
2329         switch (chan) {
2330         case CHANNEL_2GHZ:
2331                 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
2332                 break;
2333         case CHANNEL_5GHZ:
2334                 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
2335                 break;
2336         default:
2337                 return 0;
2338         }
2339
2340         mdelay(2);
2341
2342         /* ...wait until PHY is ready and read the selected radio revision */
2343         ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
2344
2345         for (i = 0; i < 8; i++)
2346                 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
2347
2348         if (ah->ah_version == AR5K_AR5210) {
2349                 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
2350                 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
2351         } else {
2352                 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
2353                 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
2354                                 ((srev & 0x0f) << 4), 8);
2355         }
2356
2357         /* Reset to the 5GHz mode */
2358         ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
2359
2360         return ret;
2361 }
2362
2363 void /*TODO:Boundary check*/
2364 ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant)
2365 {
2366         ATH5K_TRACE(ah->ah_sc);
2367         /*Just a try M.F.*/
2368         if (ah->ah_version != AR5K_AR5210)
2369                 ath5k_hw_reg_write(ah, ant, AR5K_DEFAULT_ANTENNA);
2370 }
2371
2372 unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah)
2373 {
2374         ATH5K_TRACE(ah->ah_sc);
2375         /*Just a try M.F.*/
2376         if (ah->ah_version != AR5K_AR5210)
2377                 return ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
2378
2379         return false; /*XXX: What do we return for 5210 ?*/
2380 }
2381
2382 /*
2383  * TX power setup
2384  */
2385
2386 /*
2387  * Initialize the tx power table (not fully implemented)
2388  */
2389 static void ath5k_txpower_table(struct ath5k_hw *ah,
2390                 struct ieee80211_channel *channel, s16 max_power)
2391 {
2392         unsigned int i, min, max, n;
2393         u16 txpower, *rates;
2394
2395         rates = ah->ah_txpower.txp_rates;
2396
2397         txpower = AR5K_TUNE_DEFAULT_TXPOWER * 2;
2398         if (max_power > txpower)
2399                 txpower = max_power > AR5K_TUNE_MAX_TXPOWER ?
2400                     AR5K_TUNE_MAX_TXPOWER : max_power;
2401
2402         for (i = 0; i < AR5K_MAX_RATES; i++)
2403                 rates[i] = txpower;
2404
2405         /* XXX setup target powers by rate */
2406
2407         ah->ah_txpower.txp_min = rates[7];
2408         ah->ah_txpower.txp_max = rates[0];
2409         ah->ah_txpower.txp_ofdm = rates[0];
2410
2411         /* Calculate the power table */
2412         n = ARRAY_SIZE(ah->ah_txpower.txp_pcdac);
2413         min = AR5K_EEPROM_PCDAC_START;
2414         max = AR5K_EEPROM_PCDAC_STOP;
2415         for (i = 0; i < n; i += AR5K_EEPROM_PCDAC_STEP)
2416                 ah->ah_txpower.txp_pcdac[i] =
2417 #ifdef notyet
2418                 min + ((i * (max - min)) / n);
2419 #else
2420                 min;
2421 #endif
2422 }
2423
2424 /*
2425  * Set transmition power
2426  */
2427 int /*O.K. - txpower_table is unimplemented so this doesn't work*/
2428 ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
2429                 unsigned int txpower)
2430 {
2431         bool tpc = ah->ah_txpower.txp_tpc;
2432         unsigned int i;
2433
2434         ATH5K_TRACE(ah->ah_sc);
2435         if (txpower > AR5K_TUNE_MAX_TXPOWER) {
2436                 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower);
2437                 return -EINVAL;
2438         }
2439
2440         /*
2441          * RF2413 for some reason can't
2442          * transmit anything if we call
2443          * this funtion, so we skip it
2444          * until we fix txpower.
2445          *
2446          * XXX: Assume same for RF2425
2447          * to be safe.
2448          */
2449         if ((ah->ah_radio == AR5K_RF2413) || (ah->ah_radio == AR5K_RF2425))
2450                 return 0;
2451
2452         /* Reset TX power values */
2453         memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
2454         ah->ah_txpower.txp_tpc = tpc;
2455
2456         /* Initialize TX power table */
2457         ath5k_txpower_table(ah, channel, txpower);
2458
2459         /*
2460          * Write TX power values
2461          */
2462         for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2463                 ath5k_hw_reg_write(ah,
2464                         ((((ah->ah_txpower.txp_pcdac[(i << 1) + 1] << 8) | 0xff) & 0xffff) << 16) |
2465                         (((ah->ah_txpower.txp_pcdac[(i << 1)    ] << 8) | 0xff) & 0xffff),
2466                         AR5K_PHY_PCDAC_TXPOWER(i));
2467         }
2468
2469         ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) |
2470                 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
2471                 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
2472
2473         ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) |
2474                 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
2475                 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
2476
2477         ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) |
2478                 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
2479                 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
2480
2481         ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) |
2482                 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
2483                 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
2484
2485         if (ah->ah_txpower.txp_tpc)
2486                 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
2487                         AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
2488         else
2489                 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX |
2490                         AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
2491
2492         return 0;
2493 }
2494
2495 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, unsigned int power)
2496 {
2497         /*Just a try M.F.*/
2498         struct ieee80211_channel *channel = &ah->ah_current_channel;
2499
2500         ATH5K_TRACE(ah->ah_sc);
2501         ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
2502                 "changing txpower to %d\n", power);
2503
2504         return ath5k_hw_txpower(ah, channel, power);
2505 }
2506
2507 #undef _ATH5K_PHY