2 * Memory copy functions for 32-bit PowerPC.
4 * Copyright (C) 1996-2005 Paul Mackerras.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 #include <asm/processor.h>
12 #include <asm/cache.h>
13 #include <asm/errno.h>
14 #include <asm/ppc_asm.h>
16 #define COPY_16_BYTES \
26 #define COPY_16_BYTES_WITHEX(n) \
44 #define COPY_16_BYTES_EXCODE(n) \
46 addi r5,r5,-(16 * n); \
49 addi r5,r5,-(16 * n); \
51 .section __ex_table,"a"; \
53 .long 8 ## n ## 0b,9 ## n ## 0b; \
54 .long 8 ## n ## 1b,9 ## n ## 0b; \
55 .long 8 ## n ## 2b,9 ## n ## 0b; \
56 .long 8 ## n ## 3b,9 ## n ## 0b; \
57 .long 8 ## n ## 4b,9 ## n ## 1b; \
58 .long 8 ## n ## 5b,9 ## n ## 1b; \
59 .long 8 ## n ## 6b,9 ## n ## 1b; \
60 .long 8 ## n ## 7b,9 ## n ## 1b; \
64 .stabs "arch/powerpc/lib/",N_SO,0,0,0f
65 .stabs "copy32.S",N_SO,0,0,0f
68 CACHELINE_BYTES = L1_CACHE_BYTES
69 LG_CACHELINE_BYTES = L1_CACHE_SHIFT
70 CACHELINE_MASK = (L1_CACHE_BYTES-1)
73 * Use dcbz on the complete cache lines in the destination
74 * to set them to zero. This requires that the destination
75 * area is cacheable. -- paulus
77 _GLOBAL(cacheable_memzero)
88 clrlwi r7,r6,32-LG_CACHELINE_BYTES
90 srwi r9,r8,LG_CACHELINE_BYTES
91 addic. r9,r9,-1 /* total number of complete cachelines */
93 xori r0,r7,CACHELINE_MASK & ~3
101 #if !defined(CONFIG_8xx)
108 #if CACHE_LINE_SIZE >= 32
113 #endif /* CACHE_LINE_SIZE */
115 addi r6,r6,CACHELINE_BYTES
117 clrlwi r5,r8,32-LG_CACHELINE_BYTES
159 * This version uses dcbz on the complete cache lines in the
160 * destination area to reduce memory traffic. This requires that
161 * the destination area is cacheable.
162 * We only use this version if the source and dest don't overlap.
165 _GLOBAL(cacheable_memcpy)
166 add r7,r3,r5 /* test if the src & dst overlap */
170 crand 0,0,4 /* cr0.lt &= cr1.lt */
171 blt memcpy /* if regions overlap */
176 andi. r0,r0,CACHELINE_MASK /* # bytes to start of cache line */
179 cmplw 0,r5,r0 /* is this more than total to do? */
180 blt 63f /* if not much to do */
181 andi. r8,r0,3 /* get it word-aligned first */
185 70: lbz r9,4(r4) /* do some bytes */
193 72: lwzu r9,4(r4) /* do some words */
197 58: srwi. r0,r5,LG_CACHELINE_BYTES /* # complete cachelines */
198 clrlwi r5,r5,32-LG_CACHELINE_BYTES
203 #if !defined(CONFIG_8xx)
207 #if L1_CACHE_BYTES >= 32
209 #if L1_CACHE_BYTES >= 64
212 #if L1_CACHE_BYTES >= 128
248 beq 2f /* if less than 8 bytes to do */
249 andi. r0,r6,3 /* get dest word aligned */
280 rlwinm. r7,r5,32-3,3,31
285 _GLOBAL(backwards_memcpy)
286 rlwinm. r7,r5,32-3,3,31 /* r0 = r5 >> 3 */
316 rlwinm. r7,r5,32-3,3,31
321 _GLOBAL(__copy_tofrom_user)
325 andi. r0,r0,CACHELINE_MASK /* # bytes to start of cache line */
328 cmplw 0,r5,r0 /* is this more than total to do? */
329 blt 63f /* if not much to do */
330 andi. r8,r0,3 /* get it word-aligned first */
333 70: lbz r9,4(r4) /* do some bytes */
342 72: lwzu r9,4(r4) /* do some words */
346 .section __ex_table,"a"
354 58: srwi. r0,r5,LG_CACHELINE_BYTES /* # complete cachelines */
355 clrlwi r5,r5,32-LG_CACHELINE_BYTES
360 /* Don't use prefetch on 8xx */
363 53: COPY_16_BYTES_WITHEX(0)
366 #else /* not CONFIG_8xx */
367 /* Here we decide how far ahead to prefetch the source */
373 #if MAX_COPY_PREFETCH > 1
374 /* Heuristically, for large transfers we prefetch
375 MAX_COPY_PREFETCH cachelines ahead. For small transfers
376 we prefetch 1 cacheline ahead. */
377 cmpwi r0,MAX_COPY_PREFETCH
379 li r7,MAX_COPY_PREFETCH
382 addi r3,r3,CACHELINE_BYTES
386 addi r3,r3,CACHELINE_BYTES
387 #endif /* MAX_COPY_PREFETCH > 1 */
395 .section __ex_table,"a"
399 /* the main body of the cacheline loop */
400 COPY_16_BYTES_WITHEX(0)
401 #if L1_CACHE_BYTES >= 32
402 COPY_16_BYTES_WITHEX(1)
403 #if L1_CACHE_BYTES >= 64
404 COPY_16_BYTES_WITHEX(2)
405 COPY_16_BYTES_WITHEX(3)
406 #if L1_CACHE_BYTES >= 128
407 COPY_16_BYTES_WITHEX(4)
408 COPY_16_BYTES_WITHEX(5)
409 COPY_16_BYTES_WITHEX(6)
410 COPY_16_BYTES_WITHEX(7)
419 #endif /* CONFIG_8xx */
439 /* read fault, initial single-byte copy */
442 /* write fault, initial single-byte copy */
447 /* read fault, initial word copy */
450 /* write fault, initial word copy */
456 * this stuff handles faults in the cacheline loop and branches to either
457 * 104f (if in read part) or 105f (if in write part), after updating r5
459 COPY_16_BYTES_EXCODE(0)
460 #if L1_CACHE_BYTES >= 32
461 COPY_16_BYTES_EXCODE(1)
462 #if L1_CACHE_BYTES >= 64
463 COPY_16_BYTES_EXCODE(2)
464 COPY_16_BYTES_EXCODE(3)
465 #if L1_CACHE_BYTES >= 128
466 COPY_16_BYTES_EXCODE(4)
467 COPY_16_BYTES_EXCODE(5)
468 COPY_16_BYTES_EXCODE(6)
469 COPY_16_BYTES_EXCODE(7)
474 /* read fault in cacheline loop */
477 /* fault on dcbz (effectively a write fault) */
478 /* or write fault in cacheline loop */
480 92: li r3,LG_CACHELINE_BYTES
484 /* read fault in final word loop */
487 /* write fault in final word loop */
492 /* read fault in final byte loop */
495 /* write fault in final byte loop */
500 * At this stage the number of bytes not copied is
501 * r5 + (ctr << r3), and r9 is 0 for read or 1 for write.
506 beq 120f /* shouldn't happen */
509 /* for a read fault, first try to continue the copy one byte at a time */
516 /* then clear out the destination: r3 bytes starting at 4(r6) */
532 .section __ex_table,"a"