git.oblomov.eu Git - linux-2.6/blob - drivers/net/igb/igb_main.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/module.h>
  29 #include <linux/types.h>
  30 #include <linux/init.h>
  31 #include <linux/vmalloc.h>
  32 #include <linux/pagemap.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/ipv6.h>
  35 #include <net/checksum.h>
  36 #include <net/ip6_checksum.h>
  37 #include <linux/net_tstamp.h>
  38 #include <linux/mii.h>
  39 #include <linux/ethtool.h>
  40 #include <linux/if_vlan.h>
  41 #include <linux/pci.h>
  42 #include <linux/pci-aspm.h>
  43 #include <linux/delay.h>
  44 #include <linux/interrupt.h>
  45 #include <linux/if_ether.h>
  46 #include <linux/aer.h>
  47 #ifdef CONFIG_IGB_DCA
  48 #include <linux/dca.h>
  49 #endif
  50 #include "igb.h"
  51
  52 #define DRV_VERSION "1.3.16-k2"
  53 char igb_driver_name[] = "igb";
  54 char igb_driver_version[] = DRV_VERSION;
  55 static const char igb_driver_string[] =
  56                                 "Intel(R) Gigabit Ethernet Network Driver";
  57 static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
  58
  59 static const struct e1000_info *igb_info_tbl[] = {
  60         [board_82575] = &e1000_82575_info,
  61 };
  62
  63 static struct pci_device_id igb_pci_tbl[] = {
  64         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
  65         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
  66         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
  67         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
  68         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
  69         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
  70         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
  71         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
  72         /* required last entry */
  73         {0, }
  74 };
  75
  76 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
  77
  78 void igb_reset(struct igb_adapter *);
  79 static int igb_setup_all_tx_resources(struct igb_adapter *);
  80 static int igb_setup_all_rx_resources(struct igb_adapter *);
  81 static void igb_free_all_tx_resources(struct igb_adapter *);
  82 static void igb_free_all_rx_resources(struct igb_adapter *);
  83 void igb_update_stats(struct igb_adapter *);
  84 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
  85 static void __devexit igb_remove(struct pci_dev *pdev);
  86 static int igb_sw_init(struct igb_adapter *);
  87 static int igb_open(struct net_device *);
  88 static int igb_close(struct net_device *);
  89 static void igb_configure_tx(struct igb_adapter *);
  90 static void igb_configure_rx(struct igb_adapter *);
  91 static void igb_setup_rctl(struct igb_adapter *);
  92 static void igb_clean_all_tx_rings(struct igb_adapter *);
  93 static void igb_clean_all_rx_rings(struct igb_adapter *);
  94 static void igb_clean_tx_ring(struct igb_ring *);
  95 static void igb_clean_rx_ring(struct igb_ring *);
  96 static void igb_set_multi(struct net_device *);
  97 static void igb_update_phy_info(unsigned long);
  98 static void igb_watchdog(unsigned long);
  99 static void igb_watchdog_task(struct work_struct *);
 100 static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
 101                                   struct igb_ring *);
 102 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
 103 static struct net_device_stats *igb_get_stats(struct net_device *);
 104 static int igb_change_mtu(struct net_device *, int);
 105 static int igb_set_mac(struct net_device *, void *);
 106 static irqreturn_t igb_intr(int irq, void *);
 107 static irqreturn_t igb_intr_msi(int irq, void *);
 108 static irqreturn_t igb_msix_other(int irq, void *);
 109 static irqreturn_t igb_msix_rx(int irq, void *);
 110 static irqreturn_t igb_msix_tx(int irq, void *);
 111 #ifdef CONFIG_IGB_DCA
 112 static void igb_update_rx_dca(struct igb_ring *);
 113 static void igb_update_tx_dca(struct igb_ring *);
 114 static void igb_setup_dca(struct igb_adapter *);
 115 #endif /* CONFIG_IGB_DCA */
 116 static bool igb_clean_tx_irq(struct igb_ring *);
 117 static int igb_poll(struct napi_struct *, int);
 118 static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
 119 static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
 120 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
 121 static void igb_tx_timeout(struct net_device *);
 122 static void igb_reset_task(struct work_struct *);
 123 static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
 124 static void igb_vlan_rx_add_vid(struct net_device *, u16);
 125 static void igb_vlan_rx_kill_vid(struct net_device *, u16);
 126 static void igb_restore_vlan(struct igb_adapter *);
 127 static void igb_ping_all_vfs(struct igb_adapter *);
 128 static void igb_msg_task(struct igb_adapter *);
 129 static int igb_rcv_msg_from_vf(struct igb_adapter *, u32);
 130 static inline void igb_set_rah_pool(struct e1000_hw *, int , int);
 131 static void igb_set_mc_list_pools(struct igb_adapter *, int, u16);
 132 static void igb_vmm_control(struct igb_adapter *);
 133 static inline void igb_set_vmolr(struct e1000_hw *, int);
 134 static inline int igb_set_vf_rlpml(struct igb_adapter *, int, int);
 135 static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *);
 136 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
 137
 138 #ifdef CONFIG_PM
 139 static int igb_suspend(struct pci_dev *, pm_message_t);
 140 static int igb_resume(struct pci_dev *);
 141 #endif
 142 static void igb_shutdown(struct pci_dev *);
 143 #ifdef CONFIG_IGB_DCA
 144 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
 145 static struct notifier_block dca_notifier = {
 146         .notifier_call  = igb_notify_dca,
 147         .next           = NULL,
 148         .priority       = 0
 149 };
 150 #endif
 151 #ifdef CONFIG_NET_POLL_CONTROLLER
 152 /* for netdump / net console */
 153 static void igb_netpoll(struct net_device *);
 154 #endif
 155 #ifdef CONFIG_PCI_IOV
 156 static unsigned int max_vfs = 0;
 157 module_param(max_vfs, uint, 0);
 158 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
 159                  "per physical function");
 160 #endif /* CONFIG_PCI_IOV */
 161
 162 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
 163                      pci_channel_state_t);
 164 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
 165 static void igb_io_resume(struct pci_dev *);
 166
 167 static struct pci_error_handlers igb_err_handler = {
 168         .error_detected = igb_io_error_detected,
 169         .slot_reset = igb_io_slot_reset,
 170         .resume = igb_io_resume,
 171 };
 172
 173
 174 static struct pci_driver igb_driver = {
 175         .name     = igb_driver_name,
 176         .id_table = igb_pci_tbl,
 177         .probe    = igb_probe,
 178         .remove   = __devexit_p(igb_remove),
 179 #ifdef CONFIG_PM
 180         /* Power Managment Hooks */
 181         .suspend  = igb_suspend,
 182         .resume   = igb_resume,
 183 #endif
 184         .shutdown = igb_shutdown,
 185         .err_handler = &igb_err_handler
 186 };
 187
 188 static int global_quad_port_a; /* global quad port a indication */
 189
 190 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
 191 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
 192 MODULE_LICENSE("GPL");
 193 MODULE_VERSION(DRV_VERSION);
 194
 195 /**
 196  * Scale the NIC clock cycle by a large factor so that
 197  * relatively small clock corrections can be added or
 198  * substracted at each clock tick. The drawbacks of a
 199  * large factor are a) that the clock register overflows
 200  * more quickly (not such a big deal) and b) that the
 201  * increment per tick has to fit into 24 bits.
 202  *
 203  * Note that
 204  *   TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
 205  *             IGB_TSYNC_SCALE
 206  *   TIMINCA += TIMINCA * adjustment [ppm] / 1e9
 207  *
 208  * The base scale factor is intentionally a power of two
 209  * so that the division in %struct timecounter can be done with
 210  * a shift.
 211  */
 212 #define IGB_TSYNC_SHIFT (19)
 213 #define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
 214
 215 /**
 216  * The duration of one clock cycle of the NIC.
 217  *
 218  * @todo This hard-coded value is part of the specification and might change
 219  * in future hardware revisions. Add revision check.
 220  */
 221 #define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
 222
 223 #if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
 224 # error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
 225 #endif
 226
 227 /**
 228  * igb_read_clock - read raw cycle counter (to be used by time counter)
 229  */
 230 static cycle_t igb_read_clock(const struct cyclecounter *tc)
 231 {
 232         struct igb_adapter *adapter =
 233                 container_of(tc, struct igb_adapter, cycles);
 234         struct e1000_hw *hw = &adapter->hw;
 235         u64 stamp;
 236
 237         stamp =  rd32(E1000_SYSTIML);
 238         stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
 239
 240         return stamp;
 241 }
 242
 243 #ifdef DEBUG
 244 /**
 245  * igb_get_hw_dev_name - return device name string
 246  * used by hardware layer to print debugging information
 247  **/
 248 char *igb_get_hw_dev_name(struct e1000_hw *hw)
 249 {
 250         struct igb_adapter *adapter = hw->back;
 251         return adapter->netdev->name;
 252 }
 253
 254 /**
 255  * igb_get_time_str - format current NIC and system time as string
 256  */
 257 static char *igb_get_time_str(struct igb_adapter *adapter,
 258                               char buffer[160])
 259 {
 260         cycle_t hw = adapter->cycles.read(&adapter->cycles);
 261         struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
 262         struct timespec sys;
 263         struct timespec delta;
 264         getnstimeofday(&sys);
 265
 266         delta = timespec_sub(nic, sys);
 267
 268         sprintf(buffer,
 269                 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
 270                 hw,
 271                 (long)nic.tv_sec, nic.tv_nsec,
 272                 (long)sys.tv_sec, sys.tv_nsec,
 273                 (long)delta.tv_sec, delta.tv_nsec);
 274
 275         return buffer;
 276 }
 277 #endif
 278
 279 /**
 280  * igb_desc_unused - calculate if we have unused descriptors
 281  **/
 282 static int igb_desc_unused(struct igb_ring *ring)
 283 {
 284         if (ring->next_to_clean > ring->next_to_use)
 285                 return ring->next_to_clean - ring->next_to_use - 1;
 286
 287         return ring->count + ring->next_to_clean - ring->next_to_use - 1;
 288 }
 289
 290 /**
 291  * igb_init_module - Driver Registration Routine
 292  *
 293  * igb_init_module is the first routine called when the driver is
 294  * loaded. All it does is register with the PCI subsystem.
 295  **/
 296 static int __init igb_init_module(void)
 297 {
 298         int ret;
 299         printk(KERN_INFO "%s - version %s\n",
 300                igb_driver_string, igb_driver_version);
 301
 302         printk(KERN_INFO "%s\n", igb_copyright);
 303
 304         global_quad_port_a = 0;
 305
 306 #ifdef CONFIG_IGB_DCA
 307         dca_register_notify(&dca_notifier);
 308 #endif
 309
 310         ret = pci_register_driver(&igb_driver);
 311         return ret;
 312 }
 313
 314 module_init(igb_init_module);
 315
 316 /**
 317  * igb_exit_module - Driver Exit Cleanup Routine
 318  *
 319  * igb_exit_module is called just before the driver is removed
 320  * from memory.
 321  **/
 322 static void __exit igb_exit_module(void)
 323 {
 324 #ifdef CONFIG_IGB_DCA
 325         dca_unregister_notify(&dca_notifier);
 326 #endif
 327         pci_unregister_driver(&igb_driver);
 328 }
 329
 330 module_exit(igb_exit_module);
 331
 332 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
 333 /**
 334  * igb_cache_ring_register - Descriptor ring to register mapping
 335  * @adapter: board private structure to initialize
 336  *
 337  * Once we know the feature-set enabled for the device, we'll cache
 338  * the register offset the descriptor ring is assigned to.
 339  **/
 340 static void igb_cache_ring_register(struct igb_adapter *adapter)
 341 {
 342         int i;
 343         unsigned int rbase_offset = adapter->vfs_allocated_count;
 344
 345         switch (adapter->hw.mac.type) {
 346         case e1000_82576:
 347                 /* The queues are allocated for virtualization such that VF 0
 348                  * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
 349                  * In order to avoid collision we start at the first free queue
 350                  * and continue consuming queues in the same sequence
 351                  */
 352                 for (i = 0; i < adapter->num_rx_queues; i++)
 353                         adapter->rx_ring[i].reg_idx = rbase_offset +
 354                                                       Q_IDX_82576(i);
 355                 for (i = 0; i < adapter->num_tx_queues; i++)
 356                         adapter->tx_ring[i].reg_idx = rbase_offset +
 357                                                       Q_IDX_82576(i);
 358                 break;
 359         case e1000_82575:
 360         default:
 361                 for (i = 0; i < adapter->num_rx_queues; i++)
 362                         adapter->rx_ring[i].reg_idx = i;
 363                 for (i = 0; i < adapter->num_tx_queues; i++)
 364                         adapter->tx_ring[i].reg_idx = i;
 365                 break;
 366         }
 367 }
 368
 369 /**
 370  * igb_alloc_queues - Allocate memory for all rings
 371  * @adapter: board private structure to initialize
 372  *
 373  * We allocate one ring per queue at run-time since we don't know the
 374  * number of queues at compile-time.
 375  **/
 376 static int igb_alloc_queues(struct igb_adapter *adapter)
 377 {
 378         int i;
 379
 380         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
 381                                    sizeof(struct igb_ring), GFP_KERNEL);
 382         if (!adapter->tx_ring)
 383                 return -ENOMEM;
 384
 385         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
 386                                    sizeof(struct igb_ring), GFP_KERNEL);
 387         if (!adapter->rx_ring) {
 388                 kfree(adapter->tx_ring);
 389                 return -ENOMEM;
 390         }
 391
 392         adapter->rx_ring->buddy = adapter->tx_ring;
 393
 394         for (i = 0; i < adapter->num_tx_queues; i++) {
 395                 struct igb_ring *ring = &(adapter->tx_ring[i]);
 396                 ring->count = adapter->tx_ring_count;
 397                 ring->adapter = adapter;
 398                 ring->queue_index = i;
 399         }
 400         for (i = 0; i < adapter->num_rx_queues; i++) {
 401                 struct igb_ring *ring = &(adapter->rx_ring[i]);
 402                 ring->count = adapter->rx_ring_count;
 403                 ring->adapter = adapter;
 404                 ring->queue_index = i;
 405                 ring->itr_register = E1000_ITR;
 406
 407                 /* set a default napi handler for each rx_ring */
 408                 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
 409         }
 410
 411         igb_cache_ring_register(adapter);
 412         return 0;
 413 }
 414
 415 static void igb_free_queues(struct igb_adapter *adapter)
 416 {
 417         int i;
 418
 419         for (i = 0; i < adapter->num_rx_queues; i++)
 420                 netif_napi_del(&adapter->rx_ring[i].napi);
 421
 422         adapter->num_rx_queues = 0;
 423         adapter->num_tx_queues = 0;
 424
 425         kfree(adapter->tx_ring);
 426         kfree(adapter->rx_ring);
 427 }
 428
 429 #define IGB_N0_QUEUE -1
 430 static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
 431                               int tx_queue, int msix_vector)
 432 {
 433         u32 msixbm = 0;
 434         struct e1000_hw *hw = &adapter->hw;
 435         u32 ivar, index;
 436
 437         switch (hw->mac.type) {
 438         case e1000_82575:
 439                 /* The 82575 assigns vectors using a bitmask, which matches the
 440                    bitmask for the EICR/EIMS/EIMC registers.  To assign one
 441                    or more queues to a vector, we write the appropriate bits
 442                    into the MSIXBM register for that vector. */
 443                 if (rx_queue > IGB_N0_QUEUE) {
 444                         msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
 445                         adapter->rx_ring[rx_queue].eims_value = msixbm;
 446                 }
 447                 if (tx_queue > IGB_N0_QUEUE) {
 448                         msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
 449                         adapter->tx_ring[tx_queue].eims_value =
 450                                   E1000_EICR_TX_QUEUE0 << tx_queue;
 451                 }
 452                 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
 453                 break;
 454         case e1000_82576:
 455                 /* 82576 uses a table-based method for assigning vectors.
 456                    Each queue has a single entry in the table to which we write
 457                    a vector number along with a "valid" bit.  Sadly, the layout
 458                    of the table is somewhat counterintuitive. */
 459                 if (rx_queue > IGB_N0_QUEUE) {
 460                         index = (rx_queue >> 1) + adapter->vfs_allocated_count;
 461                         ivar = array_rd32(E1000_IVAR0, index);
 462                         if (rx_queue & 0x1) {
 463                                 /* vector goes into third byte of register */
 464                                 ivar = ivar & 0xFF00FFFF;
 465                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
 466                         } else {
 467                                 /* vector goes into low byte of register */
 468                                 ivar = ivar & 0xFFFFFF00;
 469                                 ivar |= msix_vector | E1000_IVAR_VALID;
 470                         }
 471                         adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
 472                         array_wr32(E1000_IVAR0, index, ivar);
 473                 }
 474                 if (tx_queue > IGB_N0_QUEUE) {
 475                         index = (tx_queue >> 1) + adapter->vfs_allocated_count;
 476                         ivar = array_rd32(E1000_IVAR0, index);
 477                         if (tx_queue & 0x1) {
 478                                 /* vector goes into high byte of register */
 479                                 ivar = ivar & 0x00FFFFFF;
 480                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
 481                         } else {
 482                                 /* vector goes into second byte of register */
 483                                 ivar = ivar & 0xFFFF00FF;
 484                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
 485                         }
 486                         adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
 487                         array_wr32(E1000_IVAR0, index, ivar);
 488                 }
 489                 break;
 490         default:
 491                 BUG();
 492                 break;
 493         }
 494 }
 495
 496 /**
 497  * igb_configure_msix - Configure MSI-X hardware
 498  *
 499  * igb_configure_msix sets up the hardware to properly
 500  * generate MSI-X interrupts.
 501  **/
 502 static void igb_configure_msix(struct igb_adapter *adapter)
 503 {
 504         u32 tmp;
 505         int i, vector = 0;
 506         struct e1000_hw *hw = &adapter->hw;
 507
 508         adapter->eims_enable_mask = 0;
 509         if (hw->mac.type == e1000_82576)
 510                 /* Turn on MSI-X capability first, or our settings
 511                  * won't stick.  And it will take days to debug. */
 512                 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
 513                                    E1000_GPIE_PBA | E1000_GPIE_EIAME |
 514                                    E1000_GPIE_NSICR);
 515
 516         for (i = 0; i < adapter->num_tx_queues; i++) {
 517                 struct igb_ring *tx_ring = &adapter->tx_ring[i];
 518                 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
 519                 adapter->eims_enable_mask |= tx_ring->eims_value;
 520                 if (tx_ring->itr_val)
 521                         writel(tx_ring->itr_val,
 522                                hw->hw_addr + tx_ring->itr_register);
 523                 else
 524                         writel(1, hw->hw_addr + tx_ring->itr_register);
 525         }
 526
 527         for (i = 0; i < adapter->num_rx_queues; i++) {
 528                 struct igb_ring *rx_ring = &adapter->rx_ring[i];
 529                 rx_ring->buddy = NULL;
 530                 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
 531                 adapter->eims_enable_mask |= rx_ring->eims_value;
 532                 if (rx_ring->itr_val)
 533                         writel(rx_ring->itr_val,
 534                                hw->hw_addr + rx_ring->itr_register);
 535                 else
 536                         writel(1, hw->hw_addr + rx_ring->itr_register);
 537         }
 538
 539
 540         /* set vector for other causes, i.e. link changes */
 541         switch (hw->mac.type) {
 542         case e1000_82575:
 543                 array_wr32(E1000_MSIXBM(0), vector++,
 544                                       E1000_EIMS_OTHER);
 545
 546                 tmp = rd32(E1000_CTRL_EXT);
 547                 /* enable MSI-X PBA support*/
 548                 tmp |= E1000_CTRL_EXT_PBA_CLR;
 549
 550                 /* Auto-Mask interrupts upon ICR read. */
 551                 tmp |= E1000_CTRL_EXT_EIAME;
 552                 tmp |= E1000_CTRL_EXT_IRCA;
 553
 554                 wr32(E1000_CTRL_EXT, tmp);
 555                 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
 556                 adapter->eims_other = E1000_EIMS_OTHER;
 557
 558                 break;
 559
 560         case e1000_82576:
 561                 tmp = (vector++ | E1000_IVAR_VALID) << 8;
 562                 wr32(E1000_IVAR_MISC, tmp);
 563
 564                 adapter->eims_enable_mask = (1 << (vector)) - 1;
 565                 adapter->eims_other = 1 << (vector - 1);
 566                 break;
 567         default:
 568                 /* do nothing, since nothing else supports MSI-X */
 569                 break;
 570         } /* switch (hw->mac.type) */
 571         wrfl();
 572 }
 573
 574 /**
 575  * igb_request_msix - Initialize MSI-X interrupts
 576  *
 577  * igb_request_msix allocates MSI-X vectors and requests interrupts from the
 578  * kernel.
 579  **/
 580 static int igb_request_msix(struct igb_adapter *adapter)
 581 {
 582         struct net_device *netdev = adapter->netdev;
 583         int i, err = 0, vector = 0;
 584
 585         vector = 0;
 586
 587         for (i = 0; i < adapter->num_tx_queues; i++) {
 588                 struct igb_ring *ring = &(adapter->tx_ring[i]);
 589                 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
 590                 err = request_irq(adapter->msix_entries[vector].vector,
 591                                   &igb_msix_tx, 0, ring->name,
 592                                   &(adapter->tx_ring[i]));
 593                 if (err)
 594                         goto out;
 595                 ring->itr_register = E1000_EITR(0) + (vector << 2);
 596                 ring->itr_val = 976; /* ~4000 ints/sec */
 597                 vector++;
 598         }
 599         for (i = 0; i < adapter->num_rx_queues; i++) {
 600                 struct igb_ring *ring = &(adapter->rx_ring[i]);
 601                 if (strlen(netdev->name) < (IFNAMSIZ - 5))
 602                         sprintf(ring->name, "%s-rx-%d", netdev->name, i);
 603                 else
 604                         memcpy(ring->name, netdev->name, IFNAMSIZ);
 605                 err = request_irq(adapter->msix_entries[vector].vector,
 606                                   &igb_msix_rx, 0, ring->name,
 607                                   &(adapter->rx_ring[i]));
 608                 if (err)
 609                         goto out;
 610                 ring->itr_register = E1000_EITR(0) + (vector << 2);
 611                 ring->itr_val = adapter->itr;
 612                 vector++;
 613         }
 614
 615         err = request_irq(adapter->msix_entries[vector].vector,
 616                           &igb_msix_other, 0, netdev->name, netdev);
 617         if (err)
 618                 goto out;
 619
 620         igb_configure_msix(adapter);
 621         return 0;
 622 out:
 623         return err;
 624 }
 625
 626 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
 627 {
 628         if (adapter->msix_entries) {
 629                 pci_disable_msix(adapter->pdev);
 630                 kfree(adapter->msix_entries);
 631                 adapter->msix_entries = NULL;
 632         } else if (adapter->flags & IGB_FLAG_HAS_MSI)
 633                 pci_disable_msi(adapter->pdev);
 634         return;
 635 }
 636
 637
 638 /**
 639  * igb_set_interrupt_capability - set MSI or MSI-X if supported
 640  *
 641  * Attempt to configure interrupts using the best available
 642  * capabilities of the hardware and kernel.
 643  **/
 644 static void igb_set_interrupt_capability(struct igb_adapter *adapter)
 645 {
 646         int err;
 647         int numvecs, i;
 648
 649         /* Number of supported queues. */
 650         /* Having more queues than CPUs doesn't make sense. */
 651         adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
 652         adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
 653
 654         numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
 655         adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
 656                                         GFP_KERNEL);
 657         if (!adapter->msix_entries)
 658                 goto msi_only;
 659
 660         for (i = 0; i < numvecs; i++)
 661                 adapter->msix_entries[i].entry = i;
 662
 663         err = pci_enable_msix(adapter->pdev,
 664                               adapter->msix_entries,
 665                               numvecs);
 666         if (err == 0)
 667                 goto out;
 668
 669         igb_reset_interrupt_capability(adapter);
 670
 671         /* If we can't do MSI-X, try MSI */
 672 msi_only:
 673 #ifdef CONFIG_PCI_IOV
 674         /* disable SR-IOV for non MSI-X configurations */
 675         if (adapter->vf_data) {
 676                 struct e1000_hw *hw = &adapter->hw;
 677                 /* disable iov and allow time for transactions to clear */
 678                 pci_disable_sriov(adapter->pdev);
 679                 msleep(500);
 680
 681                 kfree(adapter->vf_data);
 682                 adapter->vf_data = NULL;
 683                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
 684                 msleep(100);
 685                 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
 686         }
 687 #endif
 688         adapter->num_rx_queues = 1;
 689         adapter->num_tx_queues = 1;
 690         if (!pci_enable_msi(adapter->pdev))
 691                 adapter->flags |= IGB_FLAG_HAS_MSI;
 692 out:
 693         /* Notify the stack of the (possibly) reduced Tx Queue count. */
 694         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
 695         return;
 696 }
 697
 698 /**
 699  * igb_request_irq - initialize interrupts
 700  *
 701  * Attempts to configure interrupts using the best available
 702  * capabilities of the hardware and kernel.
 703  **/
 704 static int igb_request_irq(struct igb_adapter *adapter)
 705 {
 706         struct net_device *netdev = adapter->netdev;
 707         struct e1000_hw *hw = &adapter->hw;
 708         int err = 0;
 709
 710         if (adapter->msix_entries) {
 711                 err = igb_request_msix(adapter);
 712                 if (!err)
 713                         goto request_done;
 714                 /* fall back to MSI */
 715                 igb_reset_interrupt_capability(adapter);
 716                 if (!pci_enable_msi(adapter->pdev))
 717                         adapter->flags |= IGB_FLAG_HAS_MSI;
 718                 igb_free_all_tx_resources(adapter);
 719                 igb_free_all_rx_resources(adapter);
 720                 adapter->num_rx_queues = 1;
 721                 igb_alloc_queues(adapter);
 722         } else {
 723                 switch (hw->mac.type) {
 724                 case e1000_82575:
 725                         wr32(E1000_MSIXBM(0),
 726                              (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
 727                         break;
 728                 case e1000_82576:
 729                         wr32(E1000_IVAR0, E1000_IVAR_VALID);
 730                         break;
 731                 default:
 732                         break;
 733                 }
 734         }
 735
 736         if (adapter->flags & IGB_FLAG_HAS_MSI) {
 737                 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
 738                                   netdev->name, netdev);
 739                 if (!err)
 740                         goto request_done;
 741                 /* fall back to legacy interrupts */
 742                 igb_reset_interrupt_capability(adapter);
 743                 adapter->flags &= ~IGB_FLAG_HAS_MSI;
 744         }
 745
 746         err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
 747                           netdev->name, netdev);
 748
 749         if (err)
 750                 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
 751                         err);
 752
 753 request_done:
 754         return err;
 755 }
 756
 757 static void igb_free_irq(struct igb_adapter *adapter)
 758 {
 759         struct net_device *netdev = adapter->netdev;
 760
 761         if (adapter->msix_entries) {
 762                 int vector = 0, i;
 763
 764                 for (i = 0; i < adapter->num_tx_queues; i++)
 765                         free_irq(adapter->msix_entries[vector++].vector,
 766                                 &(adapter->tx_ring[i]));
 767                 for (i = 0; i < adapter->num_rx_queues; i++)
 768                         free_irq(adapter->msix_entries[vector++].vector,
 769                                 &(adapter->rx_ring[i]));
 770
 771                 free_irq(adapter->msix_entries[vector++].vector, netdev);
 772                 return;
 773         }
 774
 775         free_irq(adapter->pdev->irq, netdev);
 776 }
 777
 778 /**
 779  * igb_irq_disable - Mask off interrupt generation on the NIC
 780  * @adapter: board private structure
 781  **/
 782 static void igb_irq_disable(struct igb_adapter *adapter)
 783 {
 784         struct e1000_hw *hw = &adapter->hw;
 785
 786         if (adapter->msix_entries) {
 787                 wr32(E1000_EIAM, 0);
 788                 wr32(E1000_EIMC, ~0);
 789                 wr32(E1000_EIAC, 0);
 790         }
 791
 792         wr32(E1000_IAM, 0);
 793         wr32(E1000_IMC, ~0);
 794         wrfl();
 795         synchronize_irq(adapter->pdev->irq);
 796 }
 797
 798 /**
 799  * igb_irq_enable - Enable default interrupt generation settings
 800  * @adapter: board private structure
 801  **/
 802 static void igb_irq_enable(struct igb_adapter *adapter)
 803 {
 804         struct e1000_hw *hw = &adapter->hw;
 805
 806         if (adapter->msix_entries) {
 807                 wr32(E1000_EIAC, adapter->eims_enable_mask);
 808                 wr32(E1000_EIAM, adapter->eims_enable_mask);
 809                 wr32(E1000_EIMS, adapter->eims_enable_mask);
 810                 if (adapter->vfs_allocated_count)
 811                         wr32(E1000_MBVFIMR, 0xFF);
 812                 wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB |
 813                                  E1000_IMS_DOUTSYNC));
 814         } else {
 815                 wr32(E1000_IMS, IMS_ENABLE_MASK);
 816                 wr32(E1000_IAM, IMS_ENABLE_MASK);
 817         }
 818 }
 819
 820 static void igb_update_mng_vlan(struct igb_adapter *adapter)
 821 {
 822         struct net_device *netdev = adapter->netdev;
 823         u16 vid = adapter->hw.mng_cookie.vlan_id;
 824         u16 old_vid = adapter->mng_vlan_id;
 825         if (adapter->vlgrp) {
 826                 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
 827                         if (adapter->hw.mng_cookie.status &
 828                                 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
 829                                 igb_vlan_rx_add_vid(netdev, vid);
 830                                 adapter->mng_vlan_id = vid;
 831                         } else
 832                                 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
 833
 834                         if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
 835                                         (vid != old_vid) &&
 836                             !vlan_group_get_device(adapter->vlgrp, old_vid))
 837                                 igb_vlan_rx_kill_vid(netdev, old_vid);
 838                 } else
 839                         adapter->mng_vlan_id = vid;
 840         }
 841 }
 842
 843 /**
 844  * igb_release_hw_control - release control of the h/w to f/w
 845  * @adapter: address of board private structure
 846  *
 847  * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
 848  * For ASF and Pass Through versions of f/w this means that the
 849  * driver is no longer loaded.
 850  *
 851  **/
 852 static void igb_release_hw_control(struct igb_adapter *adapter)
 853 {
 854         struct e1000_hw *hw = &adapter->hw;
 855         u32 ctrl_ext;
 856
 857         /* Let firmware take over control of h/w */
 858         ctrl_ext = rd32(E1000_CTRL_EXT);
 859         wr32(E1000_CTRL_EXT,
 860                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
 861 }
 862
 863
 864 /**
 865  * igb_get_hw_control - get control of the h/w from f/w
 866  * @adapter: address of board private structure
 867  *
 868  * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
 869  * For ASF and Pass Through versions of f/w this means that
 870  * the driver is loaded.
 871  *
 872  **/
 873 static void igb_get_hw_control(struct igb_adapter *adapter)
 874 {
 875         struct e1000_hw *hw = &adapter->hw;
 876         u32 ctrl_ext;
 877
 878         /* Let firmware know the driver has taken over */
 879         ctrl_ext = rd32(E1000_CTRL_EXT);
 880         wr32(E1000_CTRL_EXT,
 881                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
 882 }
 883
 884 /**
 885  * igb_configure - configure the hardware for RX and TX
 886  * @adapter: private board structure
 887  **/
 888 static void igb_configure(struct igb_adapter *adapter)
 889 {
 890         struct net_device *netdev = adapter->netdev;
 891         int i;
 892
 893         igb_get_hw_control(adapter);
 894         igb_set_multi(netdev);
 895
 896         igb_restore_vlan(adapter);
 897
 898         igb_configure_tx(adapter);
 899         igb_setup_rctl(adapter);
 900         igb_configure_rx(adapter);
 901
 902         igb_rx_fifo_flush_82575(&adapter->hw);
 903
 904         /* call igb_desc_unused which always leaves
 905          * at least 1 descriptor unused to make sure
 906          * next_to_use != next_to_clean */
 907         for (i = 0; i < adapter->num_rx_queues; i++) {
 908                 struct igb_ring *ring = &adapter->rx_ring[i];
 909                 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
 910         }
 911
 912
 913         adapter->tx_queue_len = netdev->tx_queue_len;
 914 }
 915
 916
 917 /**
 918  * igb_up - Open the interface and prepare it to handle traffic
 919  * @adapter: board private structure
 920  **/
 921
 922 int igb_up(struct igb_adapter *adapter)
 923 {
 924         struct e1000_hw *hw = &adapter->hw;
 925         int i;
 926
 927         /* hardware has been reset, we need to reload some things */
 928         igb_configure(adapter);
 929
 930         clear_bit(__IGB_DOWN, &adapter->state);
 931
 932         for (i = 0; i < adapter->num_rx_queues; i++)
 933                 napi_enable(&adapter->rx_ring[i].napi);
 934         if (adapter->msix_entries)
 935                 igb_configure_msix(adapter);
 936
 937         igb_vmm_control(adapter);
 938         igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
 939         igb_set_vmolr(hw, adapter->vfs_allocated_count);
 940
 941         /* Clear any pending interrupts. */
 942         rd32(E1000_ICR);
 943         igb_irq_enable(adapter);
 944
 945         netif_tx_start_all_queues(adapter->netdev);
 946
 947         /* Fire a link change interrupt to start the watchdog. */
 948         wr32(E1000_ICS, E1000_ICS_LSC);
 949         return 0;
 950 }
 951
 952 void igb_down(struct igb_adapter *adapter)
 953 {
 954         struct e1000_hw *hw = &adapter->hw;
 955         struct net_device *netdev = adapter->netdev;
 956         u32 tctl, rctl;
 957         int i;
 958
 959         /* signal that we're down so the interrupt handler does not
 960          * reschedule our watchdog timer */
 961         set_bit(__IGB_DOWN, &adapter->state);
 962
 963         /* disable receives in the hardware */
 964         rctl = rd32(E1000_RCTL);
 965         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
 966         /* flush and sleep below */
 967
 968         netif_tx_stop_all_queues(netdev);
 969
 970         /* disable transmits in the hardware */
 971         tctl = rd32(E1000_TCTL);
 972         tctl &= ~E1000_TCTL_EN;
 973         wr32(E1000_TCTL, tctl);
 974         /* flush both disables and wait for them to finish */
 975         wrfl();
 976         msleep(10);
 977
 978         for (i = 0; i < adapter->num_rx_queues; i++)
 979                 napi_disable(&adapter->rx_ring[i].napi);
 980
 981         igb_irq_disable(adapter);
 982
 983         del_timer_sync(&adapter->watchdog_timer);
 984         del_timer_sync(&adapter->phy_info_timer);
 985
 986         netdev->tx_queue_len = adapter->tx_queue_len;
 987         netif_carrier_off(netdev);
 988
 989         /* record the stats before reset*/
 990         igb_update_stats(adapter);
 991
 992         adapter->link_speed = 0;
 993         adapter->link_duplex = 0;
 994
 995         if (!pci_channel_offline(adapter->pdev))
 996                 igb_reset(adapter);
 997         igb_clean_all_tx_rings(adapter);
 998         igb_clean_all_rx_rings(adapter);
 999 }
1000
1001 void igb_reinit_locked(struct igb_adapter *adapter)
1002 {
1003         WARN_ON(in_interrupt());
1004         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1005                 msleep(1);
1006         igb_down(adapter);
1007         igb_up(adapter);
1008         clear_bit(__IGB_RESETTING, &adapter->state);
1009 }
1010
1011 void igb_reset(struct igb_adapter *adapter)
1012 {
1013         struct e1000_hw *hw = &adapter->hw;
1014         struct e1000_mac_info *mac = &hw->mac;
1015         struct e1000_fc_info *fc = &hw->fc;
1016         u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1017         u16 hwm;
1018
1019         /* Repartition Pba for greater than 9k mtu
1020          * To take effect CTRL.RST is required.
1021          */
1022         switch (mac->type) {
1023         case e1000_82576:
1024                 pba = E1000_PBA_64K;
1025                 break;
1026         case e1000_82575:
1027         default:
1028                 pba = E1000_PBA_34K;
1029                 break;
1030         }
1031
1032         if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1033             (mac->type < e1000_82576)) {
1034                 /* adjust PBA for jumbo frames */
1035                 wr32(E1000_PBA, pba);
1036
1037                 /* To maintain wire speed transmits, the Tx FIFO should be
1038                  * large enough to accommodate two full transmit packets,
1039                  * rounded up to the next 1KB and expressed in KB.  Likewise,
1040                  * the Rx FIFO should be large enough to accommodate at least
1041                  * one full receive packet and is similarly rounded up and
1042                  * expressed in KB. */
1043                 pba = rd32(E1000_PBA);
1044                 /* upper 16 bits has Tx packet buffer allocation size in KB */
1045                 tx_space = pba >> 16;
1046                 /* lower 16 bits has Rx packet buffer allocation size in KB */
1047                 pba &= 0xffff;
1048                 /* the tx fifo also stores 16 bytes of information about the tx
1049                  * but don't include ethernet FCS because hardware appends it */
1050                 min_tx_space = (adapter->max_frame_size +
1051                                 sizeof(union e1000_adv_tx_desc) -
1052                                 ETH_FCS_LEN) * 2;
1053                 min_tx_space = ALIGN(min_tx_space, 1024);
1054                 min_tx_space >>= 10;
1055                 /* software strips receive CRC, so leave room for it */
1056                 min_rx_space = adapter->max_frame_size;
1057                 min_rx_space = ALIGN(min_rx_space, 1024);
1058                 min_rx_space >>= 10;
1059
1060                 /* If current Tx allocation is less than the min Tx FIFO size,
1061                  * and the min Tx FIFO size is less than the current Rx FIFO
1062                  * allocation, take space away from current Rx allocation */
1063                 if (tx_space < min_tx_space &&
1064                     ((min_tx_space - tx_space) < pba)) {
1065                         pba = pba - (min_tx_space - tx_space);
1066
1067                         /* if short on rx space, rx wins and must trump tx
1068                          * adjustment */
1069                         if (pba < min_rx_space)
1070                                 pba = min_rx_space;
1071                 }
1072                 wr32(E1000_PBA, pba);
1073         }
1074
1075         /* flow control settings */
1076         /* The high water mark must be low enough to fit one full frame
1077          * (or the size used for early receive) above it in the Rx FIFO.
1078          * Set it to the lower of:
1079          * - 90% of the Rx FIFO size, or
1080          * - the full Rx FIFO size minus one full frame */
1081         hwm = min(((pba << 10) * 9 / 10),
1082                         ((pba << 10) - 2 * adapter->max_frame_size));
1083
1084         if (mac->type < e1000_82576) {
1085                 fc->high_water = hwm & 0xFFF8;  /* 8-byte granularity */
1086                 fc->low_water = fc->high_water - 8;
1087         } else {
1088                 fc->high_water = hwm & 0xFFF0;  /* 16-byte granularity */
1089                 fc->low_water = fc->high_water - 16;
1090         }
1091         fc->pause_time = 0xFFFF;
1092         fc->send_xon = 1;
1093         fc->type = fc->original_type;
1094
1095         /* disable receive for all VFs and wait one second */
1096         if (adapter->vfs_allocated_count) {
1097                 int i;
1098                 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1099                         adapter->vf_data[i].clear_to_send = false;
1100
1101                 /* ping all the active vfs to let them know we are going down */
1102                         igb_ping_all_vfs(adapter);
1103
1104                 /* disable transmits and receives */
1105                 wr32(E1000_VFRE, 0);
1106                 wr32(E1000_VFTE, 0);
1107         }
1108
1109         /* Allow time for pending master requests to run */
1110         adapter->hw.mac.ops.reset_hw(&adapter->hw);
1111         wr32(E1000_WUC, 0);
1112
1113         if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1114                 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1115
1116         igb_update_mng_vlan(adapter);
1117
1118         /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1119         wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1120
1121         igb_reset_adaptive(&adapter->hw);
1122         igb_get_phy_info(&adapter->hw);
1123 }
1124
1125 static const struct net_device_ops igb_netdev_ops = {
1126         .ndo_open               = igb_open,
1127         .ndo_stop               = igb_close,
1128         .ndo_start_xmit         = igb_xmit_frame_adv,
1129         .ndo_get_stats          = igb_get_stats,
1130         .ndo_set_multicast_list = igb_set_multi,
1131         .ndo_set_mac_address    = igb_set_mac,
1132         .ndo_change_mtu         = igb_change_mtu,
1133         .ndo_do_ioctl           = igb_ioctl,
1134         .ndo_tx_timeout         = igb_tx_timeout,
1135         .ndo_validate_addr      = eth_validate_addr,
1136         .ndo_vlan_rx_register   = igb_vlan_rx_register,
1137         .ndo_vlan_rx_add_vid    = igb_vlan_rx_add_vid,
1138         .ndo_vlan_rx_kill_vid   = igb_vlan_rx_kill_vid,
1139 #ifdef CONFIG_NET_POLL_CONTROLLER
1140         .ndo_poll_controller    = igb_netpoll,
1141 #endif
1142 };
1143
1144 /**
1145  * igb_probe - Device Initialization Routine
1146  * @pdev: PCI device information struct
1147  * @ent: entry in igb_pci_tbl
1148  *
1149  * Returns 0 on success, negative on failure
1150  *
1151  * igb_probe initializes an adapter identified by a pci_dev structure.
1152  * The OS initialization, configuring of the adapter private structure,
1153  * and a hardware reset occur.
1154  **/
1155 static int __devinit igb_probe(struct pci_dev *pdev,
1156                                const struct pci_device_id *ent)
1157 {
1158         struct net_device *netdev;
1159         struct igb_adapter *adapter;
1160         struct e1000_hw *hw;
1161         const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1162         unsigned long mmio_start, mmio_len;
1163         int err, pci_using_dac;
1164         u16 eeprom_data = 0;
1165         u16 eeprom_apme_mask = IGB_EEPROM_APME;
1166         u32 part_num;
1167
1168         err = pci_enable_device_mem(pdev);
1169         if (err)
1170                 return err;
1171
1172         pci_using_dac = 0;
1173         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1174         if (!err) {
1175                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1176                 if (!err)
1177                         pci_using_dac = 1;
1178         } else {
1179                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1180                 if (err) {
1181                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1182                         if (err) {
1183                                 dev_err(&pdev->dev, "No usable DMA "
1184                                         "configuration, aborting\n");
1185                                 goto err_dma;
1186                         }
1187                 }
1188         }
1189
1190         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1191                                            IORESOURCE_MEM),
1192                                            igb_driver_name);
1193         if (err)
1194                 goto err_pci_reg;
1195
1196         err = pci_enable_pcie_error_reporting(pdev);
1197         if (err) {
1198                 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1199                         "0x%x\n", err);
1200                 /* non-fatal, continue */
1201         }
1202
1203         pci_set_master(pdev);
1204         pci_save_state(pdev);
1205
1206         err = -ENOMEM;
1207         netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1208                                    IGB_ABS_MAX_TX_QUEUES);
1209         if (!netdev)
1210                 goto err_alloc_etherdev;
1211
1212         SET_NETDEV_DEV(netdev, &pdev->dev);
1213
1214         pci_set_drvdata(pdev, netdev);
1215         adapter = netdev_priv(netdev);
1216         adapter->netdev = netdev;
1217         adapter->pdev = pdev;
1218         hw = &adapter->hw;
1219         hw->back = adapter;
1220         adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1221
1222         mmio_start = pci_resource_start(pdev, 0);
1223         mmio_len = pci_resource_len(pdev, 0);
1224
1225         err = -EIO;
1226         hw->hw_addr = ioremap(mmio_start, mmio_len);
1227         if (!hw->hw_addr)
1228                 goto err_ioremap;
1229
1230         netdev->netdev_ops = &igb_netdev_ops;
1231         igb_set_ethtool_ops(netdev);
1232         netdev->watchdog_timeo = 5 * HZ;
1233
1234         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1235
1236         netdev->mem_start = mmio_start;
1237         netdev->mem_end = mmio_start + mmio_len;
1238
1239         /* PCI config space info */
1240         hw->vendor_id = pdev->vendor;
1241         hw->device_id = pdev->device;
1242         hw->revision_id = pdev->revision;
1243         hw->subsystem_vendor_id = pdev->subsystem_vendor;
1244         hw->subsystem_device_id = pdev->subsystem_device;
1245
1246         /* setup the private structure */
1247         hw->back = adapter;
1248         /* Copy the default MAC, PHY and NVM function pointers */
1249         memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1250         memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1251         memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1252         /* Initialize skew-specific constants */
1253         err = ei->get_invariants(hw);
1254         if (err)
1255                 goto err_sw_init;
1256
1257 #ifdef CONFIG_PCI_IOV
1258         /* since iov functionality isn't critical to base device function we
1259          * can accept failure.  If it fails we don't allow iov to be enabled */
1260         if (hw->mac.type == e1000_82576) {
1261                 /* 82576 supports a maximum of 7 VFs in addition to the PF */
1262                 unsigned int num_vfs = (max_vfs > 7) ? 7 : max_vfs;
1263                 int i;
1264                 unsigned char mac_addr[ETH_ALEN];
1265
1266                 if (num_vfs) {
1267                         adapter->vf_data = kcalloc(num_vfs,
1268                                                 sizeof(struct vf_data_storage),
1269                                                 GFP_KERNEL);
1270                         if (!adapter->vf_data) {
1271                                 dev_err(&pdev->dev,
1272                                         "Could not allocate VF private data - "
1273                                         "IOV enable failed\n");
1274                         } else {
1275                                 err = pci_enable_sriov(pdev, num_vfs);
1276                                 if (!err) {
1277                                         adapter->vfs_allocated_count = num_vfs;
1278                                         dev_info(&pdev->dev,
1279                                                  "%d vfs allocated\n",
1280                                                  num_vfs);
1281                                         for (i = 0;
1282                                              i < adapter->vfs_allocated_count;
1283                                              i++) {
1284                                                 random_ether_addr(mac_addr);
1285                                                 igb_set_vf_mac(adapter, i,
1286                                                                mac_addr);
1287                                         }
1288                                 } else {
1289                                         kfree(adapter->vf_data);
1290                                         adapter->vf_data = NULL;
1291                                 }
1292                         }
1293                 }
1294         }
1295
1296 #endif
1297         /* setup the private structure */
1298         err = igb_sw_init(adapter);
1299         if (err)
1300                 goto err_sw_init;
1301
1302         igb_get_bus_info_pcie(hw);
1303
1304         /* set flags */
1305         switch (hw->mac.type) {
1306         case e1000_82575:
1307                 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1308                 break;
1309         case e1000_82576:
1310         default:
1311                 break;
1312         }
1313
1314         hw->phy.autoneg_wait_to_complete = false;
1315         hw->mac.adaptive_ifs = true;
1316
1317         /* Copper options */
1318         if (hw->phy.media_type == e1000_media_type_copper) {
1319                 hw->phy.mdix = AUTO_ALL_MODES;
1320                 hw->phy.disable_polarity_correction = false;
1321                 hw->phy.ms_type = e1000_ms_hw_default;
1322         }
1323
1324         if (igb_check_reset_block(hw))
1325                 dev_info(&pdev->dev,
1326                         "PHY reset is blocked due to SOL/IDER session.\n");
1327
1328         netdev->features = NETIF_F_SG |
1329                            NETIF_F_IP_CSUM |
1330                            NETIF_F_HW_VLAN_TX |
1331                            NETIF_F_HW_VLAN_RX |
1332                            NETIF_F_HW_VLAN_FILTER;
1333
1334         netdev->features |= NETIF_F_IPV6_CSUM;
1335         netdev->features |= NETIF_F_TSO;
1336         netdev->features |= NETIF_F_TSO6;
1337
1338         netdev->features |= NETIF_F_GRO;
1339
1340         netdev->vlan_features |= NETIF_F_TSO;
1341         netdev->vlan_features |= NETIF_F_TSO6;
1342         netdev->vlan_features |= NETIF_F_IP_CSUM;
1343         netdev->vlan_features |= NETIF_F_SG;
1344
1345         if (pci_using_dac)
1346                 netdev->features |= NETIF_F_HIGHDMA;
1347
1348         if (adapter->hw.mac.type == e1000_82576)
1349                 netdev->features |= NETIF_F_SCTP_CSUM;
1350
1351         adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1352
1353         /* before reading the NVM, reset the controller to put the device in a
1354          * known good starting state */
1355         hw->mac.ops.reset_hw(hw);
1356
1357         /* make sure the NVM is good */
1358         if (igb_validate_nvm_checksum(hw) < 0) {
1359                 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1360                 err = -EIO;
1361                 goto err_eeprom;
1362         }
1363
1364         /* copy the MAC address out of the NVM */
1365         if (hw->mac.ops.read_mac_addr(hw))
1366                 dev_err(&pdev->dev, "NVM Read Error\n");
1367
1368         memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1369         memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1370
1371         if (!is_valid_ether_addr(netdev->perm_addr)) {
1372                 dev_err(&pdev->dev, "Invalid MAC Address\n");
1373                 err = -EIO;
1374                 goto err_eeprom;
1375         }
1376
1377         setup_timer(&adapter->watchdog_timer, &igb_watchdog,
1378                     (unsigned long) adapter);
1379         setup_timer(&adapter->phy_info_timer, &igb_update_phy_info,
1380                     (unsigned long) adapter);
1381
1382         INIT_WORK(&adapter->reset_task, igb_reset_task);
1383         INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1384
1385         /* Initialize link properties that are user-changeable */
1386         adapter->fc_autoneg = true;
1387         hw->mac.autoneg = true;
1388         hw->phy.autoneg_advertised = 0x2f;
1389
1390         hw->fc.original_type = e1000_fc_default;
1391         hw->fc.type = e1000_fc_default;
1392
1393         adapter->itr_setting = IGB_DEFAULT_ITR;
1394         adapter->itr = IGB_START_ITR;
1395
1396         igb_validate_mdi_setting(hw);
1397
1398         adapter->rx_csum = 1;
1399
1400         /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1401          * enable the ACPI Magic Packet filter
1402          */
1403
1404         if (hw->bus.func == 0)
1405                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
1406         else if (hw->bus.func == 1)
1407                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
1408
1409         if (eeprom_data & eeprom_apme_mask)
1410                 adapter->eeprom_wol |= E1000_WUFC_MAG;
1411
1412         /* now that we have the eeprom settings, apply the special cases where
1413          * the eeprom may be wrong or the board simply won't support wake on
1414          * lan on a particular port */
1415         switch (pdev->device) {
1416         case E1000_DEV_ID_82575GB_QUAD_COPPER:
1417                 adapter->eeprom_wol = 0;
1418                 break;
1419         case E1000_DEV_ID_82575EB_FIBER_SERDES:
1420         case E1000_DEV_ID_82576_FIBER:
1421         case E1000_DEV_ID_82576_SERDES:
1422                 /* Wake events only supported on port A for dual fiber
1423                  * regardless of eeprom setting */
1424                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1425                         adapter->eeprom_wol = 0;
1426                 break;
1427         case E1000_DEV_ID_82576_QUAD_COPPER:
1428                 /* if quad port adapter, disable WoL on all but port A */
1429                 if (global_quad_port_a != 0)
1430                         adapter->eeprom_wol = 0;
1431                 else
1432                         adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1433                 /* Reset for multiple quad port adapters */
1434                 if (++global_quad_port_a == 4)
1435                         global_quad_port_a = 0;
1436                 break;
1437         }
1438
1439         /* initialize the wol settings based on the eeprom settings */
1440         adapter->wol = adapter->eeprom_wol;
1441         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1442
1443         /* reset the hardware with the new settings */
1444         igb_reset(adapter);
1445
1446         /* let the f/w know that the h/w is now under the control of the
1447          * driver. */
1448         igb_get_hw_control(adapter);
1449
1450         strcpy(netdev->name, "eth%d");
1451         err = register_netdev(netdev);
1452         if (err)
1453                 goto err_register;
1454
1455         /* carrier off reporting is important to ethtool even BEFORE open */
1456         netif_carrier_off(netdev);
1457
1458 #ifdef CONFIG_IGB_DCA
1459         if (dca_add_requester(&pdev->dev) == 0) {
1460                 adapter->flags |= IGB_FLAG_DCA_ENABLED;
1461                 dev_info(&pdev->dev, "DCA enabled\n");
1462                 /* Always use CB2 mode, difference is masked
1463                  * in the CB driver. */
1464                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
1465                 igb_setup_dca(adapter);
1466         }
1467 #endif
1468
1469         /*
1470          * Initialize hardware timer: we keep it running just in case
1471          * that some program needs it later on.
1472          */
1473         memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1474         adapter->cycles.read = igb_read_clock;
1475         adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1476         adapter->cycles.mult = 1;
1477         adapter->cycles.shift = IGB_TSYNC_SHIFT;
1478         wr32(E1000_TIMINCA,
1479              (1<<24) |
1480              IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1481 #if 0
1482         /*
1483          * Avoid rollover while we initialize by resetting the time counter.
1484          */
1485         wr32(E1000_SYSTIML, 0x00000000);
1486         wr32(E1000_SYSTIMH, 0x00000000);
1487 #else
1488         /*
1489          * Set registers so that rollover occurs soon to test this.
1490          */
1491         wr32(E1000_SYSTIML, 0x00000000);
1492         wr32(E1000_SYSTIMH, 0xFF800000);
1493 #endif
1494         wrfl();
1495         timecounter_init(&adapter->clock,
1496                          &adapter->cycles,
1497                          ktime_to_ns(ktime_get_real()));
1498
1499         /*
1500          * Synchronize our NIC clock against system wall clock. NIC
1501          * time stamp reading requires ~3us per sample, each sample
1502          * was pretty stable even under load => only require 10
1503          * samples for each offset comparison.
1504          */
1505         memset(&adapter->compare, 0, sizeof(adapter->compare));
1506         adapter->compare.source = &adapter->clock;
1507         adapter->compare.target = ktime_get_real;
1508         adapter->compare.num_samples = 10;
1509         timecompare_update(&adapter->compare, 0);
1510
1511 #ifdef DEBUG
1512         {
1513                 char buffer[160];
1514                 printk(KERN_DEBUG
1515                         "igb: %s: hw %p initialized timer\n",
1516                         igb_get_time_str(adapter, buffer),
1517                         &adapter->hw);
1518         }
1519 #endif
1520
1521         dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1522         /* print bus type/speed/width info */
1523         dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
1524                  netdev->name,
1525                  ((hw->bus.speed == e1000_bus_speed_2500)
1526                   ? "2.5Gb/s" : "unknown"),
1527                  ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
1528                   (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
1529                   (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
1530                    "unknown"),
1531                  netdev->dev_addr);
1532
1533         igb_read_part_num(hw, &part_num);
1534         dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1535                 (part_num >> 8), (part_num & 0xff));
1536
1537         dev_info(&pdev->dev,
1538                 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1539                 adapter->msix_entries ? "MSI-X" :
1540                 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
1541                 adapter->num_rx_queues, adapter->num_tx_queues);
1542
1543         return 0;
1544
1545 err_register:
1546         igb_release_hw_control(adapter);
1547 err_eeprom:
1548         if (!igb_check_reset_block(hw))
1549                 igb_reset_phy(hw);
1550
1551         if (hw->flash_address)
1552                 iounmap(hw->flash_address);
1553
1554         igb_free_queues(adapter);
1555 err_sw_init:
1556         iounmap(hw->hw_addr);
1557 err_ioremap:
1558         free_netdev(netdev);
1559 err_alloc_etherdev:
1560         pci_release_selected_regions(pdev, pci_select_bars(pdev,
1561                                      IORESOURCE_MEM));
1562 err_pci_reg:
1563 err_dma:
1564         pci_disable_device(pdev);
1565         return err;
1566 }
1567
1568 /**
1569  * igb_remove - Device Removal Routine
1570  * @pdev: PCI device information struct
1571  *
1572  * igb_remove is called by the PCI subsystem to alert the driver
1573  * that it should release a PCI device.  The could be caused by a
1574  * Hot-Plug event, or because the driver is going to be removed from
1575  * memory.
1576  **/
1577 static void __devexit igb_remove(struct pci_dev *pdev)
1578 {
1579         struct net_device *netdev = pci_get_drvdata(pdev);
1580         struct igb_adapter *adapter = netdev_priv(netdev);
1581         struct e1000_hw *hw = &adapter->hw;
1582         int err;
1583
1584         /* flush_scheduled work may reschedule our watchdog task, so
1585          * explicitly disable watchdog tasks from being rescheduled  */
1586         set_bit(__IGB_DOWN, &adapter->state);
1587         del_timer_sync(&adapter->watchdog_timer);
1588         del_timer_sync(&adapter->phy_info_timer);
1589
1590         flush_scheduled_work();
1591
1592 #ifdef CONFIG_IGB_DCA
1593         if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
1594                 dev_info(&pdev->dev, "DCA disabled\n");
1595                 dca_remove_requester(&pdev->dev);
1596                 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
1597                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
1598         }
1599 #endif
1600
1601         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
1602          * would have already happened in close and is redundant. */
1603         igb_release_hw_control(adapter);
1604
1605         unregister_netdev(netdev);
1606
1607         if (!igb_check_reset_block(&adapter->hw))
1608                 igb_reset_phy(&adapter->hw);
1609
1610         igb_reset_interrupt_capability(adapter);
1611
1612         igb_free_queues(adapter);
1613
1614 #ifdef CONFIG_PCI_IOV
1615         /* reclaim resources allocated to VFs */
1616         if (adapter->vf_data) {
1617                 /* disable iov and allow time for transactions to clear */
1618                 pci_disable_sriov(pdev);
1619                 msleep(500);
1620
1621                 kfree(adapter->vf_data);
1622                 adapter->vf_data = NULL;
1623                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1624                 msleep(100);
1625                 dev_info(&pdev->dev, "IOV Disabled\n");
1626         }
1627 #endif
1628         iounmap(hw->hw_addr);
1629         if (hw->flash_address)
1630                 iounmap(hw->flash_address);
1631         pci_release_selected_regions(pdev, pci_select_bars(pdev,
1632                                      IORESOURCE_MEM));
1633
1634         free_netdev(netdev);
1635
1636         err = pci_disable_pcie_error_reporting(pdev);
1637         if (err)
1638                 dev_err(&pdev->dev,
1639                         "pci_disable_pcie_error_reporting failed 0x%x\n", err);
1640
1641         pci_disable_device(pdev);
1642 }
1643
1644 /**
1645  * igb_sw_init - Initialize general software structures (struct igb_adapter)
1646  * @adapter: board private structure to initialize
1647  *
1648  * igb_sw_init initializes the Adapter private data structure.
1649  * Fields are initialized based on PCI device information and
1650  * OS network device settings (MTU size).
1651  **/
1652 static int __devinit igb_sw_init(struct igb_adapter *adapter)
1653 {
1654         struct e1000_hw *hw = &adapter->hw;
1655         struct net_device *netdev = adapter->netdev;
1656         struct pci_dev *pdev = adapter->pdev;
1657
1658         pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1659
1660         adapter->tx_ring_count = IGB_DEFAULT_TXD;
1661         adapter->rx_ring_count = IGB_DEFAULT_RXD;
1662         adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1663         adapter->rx_ps_hdr_size = 0; /* disable packet split */
1664         adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1665         adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1666
1667         /* This call may decrease the number of queues depending on
1668          * interrupt mode. */
1669         igb_set_interrupt_capability(adapter);
1670
1671         if (igb_alloc_queues(adapter)) {
1672                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1673                 return -ENOMEM;
1674         }
1675
1676         /* Explicitly disable IRQ since the NIC can be in any state. */
1677         igb_irq_disable(adapter);
1678
1679         set_bit(__IGB_DOWN, &adapter->state);
1680         return 0;
1681 }
1682
1683 /**
1684  * igb_open - Called when a network interface is made active
1685  * @netdev: network interface device structure
1686  *
1687  * Returns 0 on success, negative value on failure
1688  *
1689  * The open entry point is called when a network interface is made
1690  * active by the system (IFF_UP).  At this point all resources needed
1691  * for transmit and receive operations are allocated, the interrupt
1692  * handler is registered with the OS, the watchdog timer is started,
1693  * and the stack is notified that the interface is ready.
1694  **/
1695 static int igb_open(struct net_device *netdev)
1696 {
1697         struct igb_adapter *adapter = netdev_priv(netdev);
1698         struct e1000_hw *hw = &adapter->hw;
1699         int err;
1700         int i;
1701
1702         /* disallow open during test */
1703         if (test_bit(__IGB_TESTING, &adapter->state))
1704                 return -EBUSY;
1705
1706         netif_carrier_off(netdev);
1707
1708         /* allocate transmit descriptors */
1709         err = igb_setup_all_tx_resources(adapter);
1710         if (err)
1711                 goto err_setup_tx;
1712
1713         /* allocate receive descriptors */
1714         err = igb_setup_all_rx_resources(adapter);
1715         if (err)
1716                 goto err_setup_rx;
1717
1718         /* e1000_power_up_phy(adapter); */
1719
1720         adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1721         if ((adapter->hw.mng_cookie.status &
1722              E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1723                 igb_update_mng_vlan(adapter);
1724
1725         /* before we allocate an interrupt, we must be ready to handle it.
1726          * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1727          * as soon as we call pci_request_irq, so we have to setup our
1728          * clean_rx handler before we do so.  */
1729         igb_configure(adapter);
1730
1731         igb_vmm_control(adapter);
1732         igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
1733         igb_set_vmolr(hw, adapter->vfs_allocated_count);
1734
1735         err = igb_request_irq(adapter);
1736         if (err)
1737                 goto err_req_irq;
1738
1739         /* From here on the code is the same as igb_up() */
1740         clear_bit(__IGB_DOWN, &adapter->state);
1741
1742         for (i = 0; i < adapter->num_rx_queues; i++)
1743                 napi_enable(&adapter->rx_ring[i].napi);
1744
1745         /* Clear any pending interrupts. */
1746         rd32(E1000_ICR);
1747
1748         igb_irq_enable(adapter);
1749
1750         netif_tx_start_all_queues(netdev);
1751
1752         /* Fire a link status change interrupt to start the watchdog. */
1753         wr32(E1000_ICS, E1000_ICS_LSC);
1754
1755         return 0;
1756
1757 err_req_irq:
1758         igb_release_hw_control(adapter);
1759         /* e1000_power_down_phy(adapter); */
1760         igb_free_all_rx_resources(adapter);
1761 err_setup_rx:
1762         igb_free_all_tx_resources(adapter);
1763 err_setup_tx:
1764         igb_reset(adapter);
1765
1766         return err;
1767 }
1768
1769 /**
1770  * igb_close - Disables a network interface
1771  * @netdev: network interface device structure
1772  *
1773  * Returns 0, this is not allowed to fail
1774  *
1775  * The close entry point is called when an interface is de-activated
1776  * by the OS.  The hardware is still under the driver's control, but
1777  * needs to be disabled.  A global MAC reset is issued to stop the
1778  * hardware, and all transmit and receive resources are freed.
1779  **/
1780 static int igb_close(struct net_device *netdev)
1781 {
1782         struct igb_adapter *adapter = netdev_priv(netdev);
1783
1784         WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1785         igb_down(adapter);
1786
1787         igb_free_irq(adapter);
1788
1789         igb_free_all_tx_resources(adapter);
1790         igb_free_all_rx_resources(adapter);
1791
1792         /* kill manageability vlan ID if supported, but not if a vlan with
1793          * the same ID is registered on the host OS (let 8021q kill it) */
1794         if ((adapter->hw.mng_cookie.status &
1795                           E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1796              !(adapter->vlgrp &&
1797                vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1798                 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1799
1800         return 0;
1801 }
1802
1803 /**
1804  * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1805  * @adapter: board private structure
1806  * @tx_ring: tx descriptor ring (for a specific queue) to setup
1807  *
1808  * Return 0 on success, negative on failure
1809  **/
1810 int igb_setup_tx_resources(struct igb_adapter *adapter,
1811                            struct igb_ring *tx_ring)
1812 {
1813         struct pci_dev *pdev = adapter->pdev;
1814         int size;
1815
1816         size = sizeof(struct igb_buffer) * tx_ring->count;
1817         tx_ring->buffer_info = vmalloc(size);
1818         if (!tx_ring->buffer_info)
1819                 goto err;
1820         memset(tx_ring->buffer_info, 0, size);
1821
1822         /* round up to nearest 4K */
1823         tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
1824         tx_ring->size = ALIGN(tx_ring->size, 4096);
1825
1826         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1827                                              &tx_ring->dma);
1828
1829         if (!tx_ring->desc)
1830                 goto err;
1831
1832         tx_ring->adapter = adapter;
1833         tx_ring->next_to_use = 0;
1834         tx_ring->next_to_clean = 0;
1835         return 0;
1836
1837 err:
1838         vfree(tx_ring->buffer_info);
1839         dev_err(&adapter->pdev->dev,
1840                 "Unable to allocate memory for the transmit descriptor ring\n");
1841         return -ENOMEM;
1842 }
1843
1844 /**
1845  * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1846  *                                (Descriptors) for all queues
1847  * @adapter: board private structure
1848  *
1849  * Return 0 on success, negative on failure
1850  **/
1851 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1852 {
1853         int i, err = 0;
1854         int r_idx;
1855
1856         for (i = 0; i < adapter->num_tx_queues; i++) {
1857                 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1858                 if (err) {
1859                         dev_err(&adapter->pdev->dev,
1860                                 "Allocation for Tx Queue %u failed\n", i);
1861                         for (i--; i >= 0; i--)
1862                                 igb_free_tx_resources(&adapter->tx_ring[i]);
1863                         break;
1864                 }
1865         }
1866
1867         for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1868                 r_idx = i % adapter->num_tx_queues;
1869                 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1870         }
1871         return err;
1872 }
1873
1874 /**
1875  * igb_configure_tx - Configure transmit Unit after Reset
1876  * @adapter: board private structure
1877  *
1878  * Configure the Tx unit of the MAC after a reset.
1879  **/
1880 static void igb_configure_tx(struct igb_adapter *adapter)
1881 {
1882         u64 tdba;
1883         struct e1000_hw *hw = &adapter->hw;
1884         u32 tctl;
1885         u32 txdctl, txctrl;
1886         int i, j;
1887
1888         for (i = 0; i < adapter->num_tx_queues; i++) {
1889                 struct igb_ring *ring = &adapter->tx_ring[i];
1890                 j = ring->reg_idx;
1891                 wr32(E1000_TDLEN(j),
1892                      ring->count * sizeof(union e1000_adv_tx_desc));
1893                 tdba = ring->dma;
1894                 wr32(E1000_TDBAL(j),
1895                      tdba & 0x00000000ffffffffULL);
1896                 wr32(E1000_TDBAH(j), tdba >> 32);
1897
1898                 ring->head = E1000_TDH(j);
1899                 ring->tail = E1000_TDT(j);
1900                 writel(0, hw->hw_addr + ring->tail);
1901                 writel(0, hw->hw_addr + ring->head);
1902                 txdctl = rd32(E1000_TXDCTL(j));
1903                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1904                 wr32(E1000_TXDCTL(j), txdctl);
1905
1906                 /* Turn off Relaxed Ordering on head write-backs.  The
1907                  * writebacks MUST be delivered in order or it will
1908                  * completely screw up our bookeeping.
1909                  */
1910                 txctrl = rd32(E1000_DCA_TXCTRL(j));
1911                 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1912                 wr32(E1000_DCA_TXCTRL(j), txctrl);
1913         }
1914
1915         /* disable queue 0 to prevent tail bump w/o re-configuration */
1916         if (adapter->vfs_allocated_count)
1917                 wr32(E1000_TXDCTL(0), 0);
1918
1919         /* Program the Transmit Control Register */
1920         tctl = rd32(E1000_TCTL);
1921         tctl &= ~E1000_TCTL_CT;
1922         tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1923                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1924
1925         igb_config_collision_dist(hw);
1926
1927         /* Setup Transmit Descriptor Settings for eop descriptor */
1928         adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1929
1930         /* Enable transmits */
1931         tctl |= E1000_TCTL_EN;
1932
1933         wr32(E1000_TCTL, tctl);
1934 }
1935
1936 /**
1937  * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1938  * @adapter: board private structure
1939  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
1940  *
1941  * Returns 0 on success, negative on failure
1942  **/
1943 int igb_setup_rx_resources(struct igb_adapter *adapter,
1944                            struct igb_ring *rx_ring)
1945 {
1946         struct pci_dev *pdev = adapter->pdev;
1947         int size, desc_len;
1948
1949         size = sizeof(struct igb_buffer) * rx_ring->count;
1950         rx_ring->buffer_info = vmalloc(size);
1951         if (!rx_ring->buffer_info)
1952                 goto err;
1953         memset(rx_ring->buffer_info, 0, size);
1954
1955         desc_len = sizeof(union e1000_adv_rx_desc);
1956
1957         /* Round up to nearest 4K */
1958         rx_ring->size = rx_ring->count * desc_len;
1959         rx_ring->size = ALIGN(rx_ring->size, 4096);
1960
1961         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1962                                              &rx_ring->dma);
1963
1964         if (!rx_ring->desc)
1965                 goto err;
1966
1967         rx_ring->next_to_clean = 0;
1968         rx_ring->next_to_use = 0;
1969
1970         rx_ring->adapter = adapter;
1971
1972         return 0;
1973
1974 err:
1975         vfree(rx_ring->buffer_info);
1976         dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1977                 "the receive descriptor ring\n");
1978         return -ENOMEM;
1979 }
1980
1981 /**
1982  * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1983  *                                (Descriptors) for all queues
1984  * @adapter: board private structure
1985  *
1986  * Return 0 on success, negative on failure
1987  **/
1988 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1989 {
1990         int i, err = 0;
1991
1992         for (i = 0; i < adapter->num_rx_queues; i++) {
1993                 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1994                 if (err) {
1995                         dev_err(&adapter->pdev->dev,
1996                                 "Allocation for Rx Queue %u failed\n", i);
1997                         for (i--; i >= 0; i--)
1998                                 igb_free_rx_resources(&adapter->rx_ring[i]);
1999                         break;
2000                 }
2001         }
2002
2003         return err;
2004 }
2005
2006 /**
2007  * igb_setup_rctl - configure the receive control registers
2008  * @adapter: Board private structure
2009  **/
2010 static void igb_setup_rctl(struct igb_adapter *adapter)
2011 {
2012         struct e1000_hw *hw = &adapter->hw;
2013         u32 rctl;
2014         u32 srrctl = 0;
2015         int i, j;
2016
2017         rctl = rd32(E1000_RCTL);
2018
2019         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2020         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
2021
2022         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
2023                 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2024
2025         /*
2026          * enable stripping of CRC. It's unlikely this will break BMC
2027          * redirection as it did with e1000. Newer features require
2028          * that the HW strips the CRC.
2029          */
2030         rctl |= E1000_RCTL_SECRC;
2031
2032         /*
2033          * disable store bad packets and clear size bits.
2034          */
2035         rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
2036
2037         /* enable LPE when to prevent packets larger than max_frame_size */
2038                 rctl |= E1000_RCTL_LPE;
2039
2040         /* Setup buffer sizes */
2041         switch (adapter->rx_buffer_len) {
2042         case IGB_RXBUFFER_256:
2043                 rctl |= E1000_RCTL_SZ_256;
2044                 break;
2045         case IGB_RXBUFFER_512:
2046                 rctl |= E1000_RCTL_SZ_512;
2047                 break;
2048         default:
2049                 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
2050                          >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2051                 break;
2052         }
2053
2054         /* 82575 and greater support packet-split where the protocol
2055          * header is placed in skb->data and the packet data is
2056          * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2057          * In the case of a non-split, skb->data is linearly filled,
2058          * followed by the page buffers.  Therefore, skb->data is
2059          * sized to hold the largest protocol header.
2060          */
2061         /* allocations using alloc_page take too long for regular MTU
2062          * so only enable packet split for jumbo frames */
2063         if (adapter->netdev->mtu > ETH_DATA_LEN) {
2064                 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
2065                 srrctl |= adapter->rx_ps_hdr_size <<
2066                          E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2067                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2068         } else {
2069                 adapter->rx_ps_hdr_size = 0;
2070                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2071         }
2072
2073         /* Attention!!!  For SR-IOV PF driver operations you must enable
2074          * queue drop for all VF and PF queues to prevent head of line blocking
2075          * if an un-trusted VF does not provide descriptors to hardware.
2076          */
2077         if (adapter->vfs_allocated_count) {
2078                 u32 vmolr;
2079
2080                 j = adapter->rx_ring[0].reg_idx;
2081
2082                 /* set all queue drop enable bits */
2083                 wr32(E1000_QDE, ALL_QUEUES);
2084                 srrctl |= E1000_SRRCTL_DROP_EN;
2085
2086                 /* disable queue 0 to prevent tail write w/o re-config */
2087                 wr32(E1000_RXDCTL(0), 0);
2088
2089                 vmolr = rd32(E1000_VMOLR(j));
2090                 if (rctl & E1000_RCTL_LPE)
2091                         vmolr |= E1000_VMOLR_LPE;
2092                 if (adapter->num_rx_queues > 0)
2093                         vmolr |= E1000_VMOLR_RSSE;
2094                 wr32(E1000_VMOLR(j), vmolr);
2095         }
2096
2097         for (i = 0; i < adapter->num_rx_queues; i++) {
2098                 j = adapter->rx_ring[i].reg_idx;
2099                 wr32(E1000_SRRCTL(j), srrctl);
2100         }
2101
2102         wr32(E1000_RCTL, rctl);
2103 }
2104
2105 /**
2106  * igb_rlpml_set - set maximum receive packet size
2107  * @adapter: board private structure
2108  *
2109  * Configure maximum receivable packet size.
2110  **/
2111 static void igb_rlpml_set(struct igb_adapter *adapter)
2112 {
2113         u32 max_frame_size = adapter->max_frame_size;
2114         struct e1000_hw *hw = &adapter->hw;
2115         u16 pf_id = adapter->vfs_allocated_count;
2116
2117         if (adapter->vlgrp)
2118                 max_frame_size += VLAN_TAG_SIZE;
2119
2120         /* if vfs are enabled we set RLPML to the largest possible request
2121          * size and set the VMOLR RLPML to the size we need */
2122         if (pf_id) {
2123                 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2124                 max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE;
2125         }
2126
2127         wr32(E1000_RLPML, max_frame_size);
2128 }
2129
2130 /**
2131  * igb_configure_vt_default_pool - Configure VT default pool
2132  * @adapter: board private structure
2133  *
2134  * Configure the default pool
2135  **/
2136 static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
2137 {
2138         struct e1000_hw *hw = &adapter->hw;
2139         u16 pf_id = adapter->vfs_allocated_count;
2140         u32 vtctl;
2141
2142         /* not in sr-iov mode - do nothing */
2143         if (!pf_id)
2144                 return;
2145
2146         vtctl = rd32(E1000_VT_CTL);
2147         vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2148                    E1000_VT_CTL_DISABLE_DEF_POOL);
2149         vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2150         wr32(E1000_VT_CTL, vtctl);
2151 }
2152
2153 /**
2154  * igb_configure_rx - Configure receive Unit after Reset
2155  * @adapter: board private structure
2156  *
2157  * Configure the Rx unit of the MAC after a reset.
2158  **/
2159 static void igb_configure_rx(struct igb_adapter *adapter)
2160 {
2161         u64 rdba;
2162         struct e1000_hw *hw = &adapter->hw;
2163         u32 rctl, rxcsum;
2164         u32 rxdctl;
2165         int i;
2166
2167         /* disable receives while setting up the descriptors */
2168         rctl = rd32(E1000_RCTL);
2169         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2170         wrfl();
2171         mdelay(10);
2172
2173         if (adapter->itr_setting > 3)
2174                 wr32(E1000_ITR, adapter->itr);
2175
2176         /* Setup the HW Rx Head and Tail Descriptor Pointers and
2177          * the Base and Length of the Rx Descriptor Ring */
2178         for (i = 0; i < adapter->num_rx_queues; i++) {
2179                 struct igb_ring *ring = &adapter->rx_ring[i];
2180                 int j = ring->reg_idx;
2181                 rdba = ring->dma;
2182                 wr32(E1000_RDBAL(j),
2183                      rdba & 0x00000000ffffffffULL);
2184                 wr32(E1000_RDBAH(j), rdba >> 32);
2185                 wr32(E1000_RDLEN(j),
2186                      ring->count * sizeof(union e1000_adv_rx_desc));
2187
2188                 ring->head = E1000_RDH(j);
2189                 ring->tail = E1000_RDT(j);
2190                 writel(0, hw->hw_addr + ring->tail);
2191                 writel(0, hw->hw_addr + ring->head);
2192
2193                 rxdctl = rd32(E1000_RXDCTL(j));
2194                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2195                 rxdctl &= 0xFFF00000;
2196                 rxdctl |= IGB_RX_PTHRESH;
2197                 rxdctl |= IGB_RX_HTHRESH << 8;
2198                 rxdctl |= IGB_RX_WTHRESH << 16;
2199                 wr32(E1000_RXDCTL(j), rxdctl);
2200         }
2201
2202         if (adapter->num_rx_queues > 1) {
2203                 u32 random[10];
2204                 u32 mrqc;
2205                 u32 j, shift;
2206                 union e1000_reta {
2207                         u32 dword;
2208                         u8  bytes[4];
2209                 } reta;
2210
2211                 get_random_bytes(&random[0], 40);
2212
2213                 if (hw->mac.type >= e1000_82576)
2214                         shift = 0;
2215                 else
2216                         shift = 6;
2217                 for (j = 0; j < (32 * 4); j++) {
2218                         reta.bytes[j & 3] =
2219                                 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
2220                         if ((j & 3) == 3)
2221                                 writel(reta.dword,
2222                                        hw->hw_addr + E1000_RETA(0) + (j & ~3));
2223                 }
2224                 if (adapter->vfs_allocated_count)
2225                         mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2226                 else
2227                         mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2228
2229                 /* Fill out hash function seeds */
2230                 for (j = 0; j < 10; j++)
2231                         array_wr32(E1000_RSSRK(0), j, random[j]);
2232
2233                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2234                          E1000_MRQC_RSS_FIELD_IPV4_TCP);
2235                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2236                          E1000_MRQC_RSS_FIELD_IPV6_TCP);
2237                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2238                          E1000_MRQC_RSS_FIELD_IPV6_UDP);
2239                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2240                          E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2241
2242                 wr32(E1000_MRQC, mrqc);
2243         } else if (adapter->vfs_allocated_count) {
2244                 /* Enable multi-queue for sr-iov */
2245                 wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ);
2246         }
2247
2248         /* Enable Receive Checksum Offload for TCP and UDP */
2249         rxcsum = rd32(E1000_RXCSUM);
2250         /* Disable raw packet checksumming */
2251         rxcsum |= E1000_RXCSUM_PCSD;
2252         /* Don't need to set TUOFL or IPOFL, they default to 1 */
2253         if (!adapter->rx_csum)
2254                 rxcsum &= ~(E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL);
2255         else if (adapter->hw.mac.type == e1000_82576)
2256                 /* Enable Receive Checksum Offload for SCTP */
2257                 rxcsum |= E1000_RXCSUM_CRCOFL;
2258
2259         wr32(E1000_RXCSUM, rxcsum);
2260
2261         /* Set the default pool for the PF's first queue */
2262         igb_configure_vt_default_pool(adapter);
2263
2264         igb_rlpml_set(adapter);
2265
2266         /* Enable Receives */
2267         wr32(E1000_RCTL, rctl);
2268 }
2269
2270 /**
2271  * igb_free_tx_resources - Free Tx Resources per Queue
2272  * @tx_ring: Tx descriptor ring for a specific queue
2273  *
2274  * Free all transmit software resources
2275  **/
2276 void igb_free_tx_resources(struct igb_ring *tx_ring)
2277 {
2278         struct pci_dev *pdev = tx_ring->adapter->pdev;
2279
2280         igb_clean_tx_ring(tx_ring);
2281
2282         vfree(tx_ring->buffer_info);
2283         tx_ring->buffer_info = NULL;
2284
2285         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2286
2287         tx_ring->desc = NULL;
2288 }
2289
2290 /**
2291  * igb_free_all_tx_resources - Free Tx Resources for All Queues
2292  * @adapter: board private structure
2293  *
2294  * Free all transmit software resources
2295  **/
2296 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2297 {
2298         int i;
2299
2300         for (i = 0; i < adapter->num_tx_queues; i++)
2301                 igb_free_tx_resources(&adapter->tx_ring[i]);
2302 }
2303
2304 static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2305                                            struct igb_buffer *buffer_info)
2306 {
2307         buffer_info->dma = 0;
2308         if (buffer_info->skb) {
2309                 skb_dma_unmap(&adapter->pdev->dev, buffer_info->skb,
2310                               DMA_TO_DEVICE);
2311                 dev_kfree_skb_any(buffer_info->skb);
2312                 buffer_info->skb = NULL;
2313         }
2314         buffer_info->time_stamp = 0;
2315         /* buffer_info must be completely set up in the transmit path */
2316 }
2317
2318 /**
2319  * igb_clean_tx_ring - Free Tx Buffers
2320  * @tx_ring: ring to be cleaned
2321  **/
2322 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
2323 {
2324         struct igb_adapter *adapter = tx_ring->adapter;
2325         struct igb_buffer *buffer_info;
2326         unsigned long size;
2327         unsigned int i;
2328
2329         if (!tx_ring->buffer_info)
2330                 return;
2331         /* Free all the Tx ring sk_buffs */
2332
2333         for (i = 0; i < tx_ring->count; i++) {
2334                 buffer_info = &tx_ring->buffer_info[i];
2335                 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2336         }
2337
2338         size = sizeof(struct igb_buffer) * tx_ring->count;
2339         memset(tx_ring->buffer_info, 0, size);
2340
2341         /* Zero out the descriptor ring */
2342
2343         memset(tx_ring->desc, 0, tx_ring->size);
2344
2345         tx_ring->next_to_use = 0;
2346         tx_ring->next_to_clean = 0;
2347
2348         writel(0, adapter->hw.hw_addr + tx_ring->head);
2349         writel(0, adapter->hw.hw_addr + tx_ring->tail);
2350 }
2351
2352 /**
2353  * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2354  * @adapter: board private structure
2355  **/
2356 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2357 {
2358         int i;
2359
2360         for (i = 0; i < adapter->num_tx_queues; i++)
2361                 igb_clean_tx_ring(&adapter->tx_ring[i]);
2362 }
2363
2364 /**
2365  * igb_free_rx_resources - Free Rx Resources
2366  * @rx_ring: ring to clean the resources from
2367  *
2368  * Free all receive software resources
2369  **/
2370 void igb_free_rx_resources(struct igb_ring *rx_ring)
2371 {
2372         struct pci_dev *pdev = rx_ring->adapter->pdev;
2373
2374         igb_clean_rx_ring(rx_ring);
2375
2376         vfree(rx_ring->buffer_info);
2377         rx_ring->buffer_info = NULL;
2378
2379         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2380
2381         rx_ring->desc = NULL;
2382 }
2383
2384 /**
2385  * igb_free_all_rx_resources - Free Rx Resources for All Queues
2386  * @adapter: board private structure
2387  *
2388  * Free all receive software resources
2389  **/
2390 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2391 {
2392         int i;
2393
2394         for (i = 0; i < adapter->num_rx_queues; i++)
2395                 igb_free_rx_resources(&adapter->rx_ring[i]);
2396 }
2397
2398 /**
2399  * igb_clean_rx_ring - Free Rx Buffers per Queue
2400  * @rx_ring: ring to free buffers from
2401  **/
2402 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
2403 {
2404         struct igb_adapter *adapter = rx_ring->adapter;
2405         struct igb_buffer *buffer_info;
2406         struct pci_dev *pdev = adapter->pdev;
2407         unsigned long size;
2408         unsigned int i;
2409
2410         if (!rx_ring->buffer_info)
2411                 return;
2412         /* Free all the Rx ring sk_buffs */
2413         for (i = 0; i < rx_ring->count; i++) {
2414                 buffer_info = &rx_ring->buffer_info[i];
2415                 if (buffer_info->dma) {
2416                         if (adapter->rx_ps_hdr_size)
2417                                 pci_unmap_single(pdev, buffer_info->dma,
2418                                                  adapter->rx_ps_hdr_size,
2419                                                  PCI_DMA_FROMDEVICE);
2420                         else
2421                                 pci_unmap_single(pdev, buffer_info->dma,
2422                                                  adapter->rx_buffer_len,
2423                                                  PCI_DMA_FROMDEVICE);
2424                         buffer_info->dma = 0;
2425                 }
2426
2427                 if (buffer_info->skb) {
2428                         dev_kfree_skb(buffer_info->skb);
2429                         buffer_info->skb = NULL;
2430                 }
2431                 if (buffer_info->page) {
2432                         if (buffer_info->page_dma)
2433                                 pci_unmap_page(pdev, buffer_info->page_dma,
2434                                                PAGE_SIZE / 2,
2435                                                PCI_DMA_FROMDEVICE);
2436                         put_page(buffer_info->page);
2437                         buffer_info->page = NULL;
2438                         buffer_info->page_dma = 0;
2439                         buffer_info->page_offset = 0;
2440                 }
2441         }
2442
2443         size = sizeof(struct igb_buffer) * rx_ring->count;
2444         memset(rx_ring->buffer_info, 0, size);
2445
2446         /* Zero out the descriptor ring */
2447         memset(rx_ring->desc, 0, rx_ring->size);
2448
2449         rx_ring->next_to_clean = 0;
2450         rx_ring->next_to_use = 0;
2451
2452         writel(0, adapter->hw.hw_addr + rx_ring->head);
2453         writel(0, adapter->hw.hw_addr + rx_ring->tail);
2454 }
2455
2456 /**
2457  * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2458  * @adapter: board private structure
2459  **/
2460 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2461 {
2462         int i;
2463
2464         for (i = 0; i < adapter->num_rx_queues; i++)
2465                 igb_clean_rx_ring(&adapter->rx_ring[i]);
2466 }
2467
2468 /**
2469  * igb_set_mac - Change the Ethernet Address of the NIC
2470  * @netdev: network interface device structure
2471  * @p: pointer to an address structure
2472  *
2473  * Returns 0 on success, negative on failure
2474  **/
2475 static int igb_set_mac(struct net_device *netdev, void *p)
2476 {
2477         struct igb_adapter *adapter = netdev_priv(netdev);
2478         struct e1000_hw *hw = &adapter->hw;
2479         struct sockaddr *addr = p;
2480
2481         if (!is_valid_ether_addr(addr->sa_data))
2482                 return -EADDRNOTAVAIL;
2483
2484         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2485         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
2486
2487         hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
2488
2489         igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
2490
2491         return 0;
2492 }
2493
2494 /**
2495  * igb_set_multi - Multicast and Promiscuous mode set
2496  * @netdev: network interface device structure
2497  *
2498  * The set_multi entry point is called whenever the multicast address
2499  * list or the network interface flags are updated.  This routine is
2500  * responsible for configuring the hardware for proper multicast,
2501  * promiscuous mode, and all-multi behavior.
2502  **/
2503 static void igb_set_multi(struct net_device *netdev)
2504 {
2505         struct igb_adapter *adapter = netdev_priv(netdev);
2506         struct e1000_hw *hw = &adapter->hw;
2507         struct e1000_mac_info *mac = &hw->mac;
2508         struct dev_mc_list *mc_ptr;
2509         u8  *mta_list = NULL;
2510         u32 rctl;
2511         int i;
2512
2513         /* Check for Promiscuous and All Multicast modes */
2514
2515         rctl = rd32(E1000_RCTL);
2516
2517         if (netdev->flags & IFF_PROMISC) {
2518                 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2519                 rctl &= ~E1000_RCTL_VFE;
2520         } else {
2521                 if (netdev->flags & IFF_ALLMULTI) {
2522                         rctl |= E1000_RCTL_MPE;
2523                         rctl &= ~E1000_RCTL_UPE;
2524                 } else
2525                         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2526                 rctl |= E1000_RCTL_VFE;
2527         }
2528         wr32(E1000_RCTL, rctl);
2529
2530         if (netdev->mc_count) {
2531                 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2532                 if (!mta_list) {
2533                         dev_err(&adapter->pdev->dev,
2534                                 "failed to allocate multicast filter list\n");
2535                         return;
2536                 }
2537         }
2538
2539         /* The shared function expects a packed array of only addresses. */
2540         mc_ptr = netdev->mc_list;
2541
2542         for (i = 0; i < netdev->mc_count; i++) {
2543                 if (!mc_ptr)
2544                         break;
2545                 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2546                 mc_ptr = mc_ptr->next;
2547         }
2548         igb_update_mc_addr_list(hw, mta_list, i,
2549                                 adapter->vfs_allocated_count + 1,
2550                                 mac->rar_entry_count);
2551
2552         igb_set_mc_list_pools(adapter, i, mac->rar_entry_count);
2553         igb_restore_vf_multicasts(adapter);
2554
2555         kfree(mta_list);
2556 }
2557
2558 /* Need to wait a few seconds after link up to get diagnostic information from
2559  * the phy */
2560 static void igb_update_phy_info(unsigned long data)
2561 {
2562         struct igb_adapter *adapter = (struct igb_adapter *) data;
2563         igb_get_phy_info(&adapter->hw);
2564 }
2565
2566 /**
2567  * igb_has_link - check shared code for link and determine up/down
2568  * @adapter: pointer to driver private info
2569  **/
2570 static bool igb_has_link(struct igb_adapter *adapter)
2571 {
2572         struct e1000_hw *hw = &adapter->hw;
2573         bool link_active = false;
2574         s32 ret_val = 0;
2575
2576         /* get_link_status is set on LSC (link status) interrupt or
2577          * rx sequence error interrupt.  get_link_status will stay
2578          * false until the e1000_check_for_link establishes link
2579          * for copper adapters ONLY
2580          */
2581         switch (hw->phy.media_type) {
2582         case e1000_media_type_copper:
2583                 if (hw->mac.get_link_status) {
2584                         ret_val = hw->mac.ops.check_for_link(hw);
2585                         link_active = !hw->mac.get_link_status;
2586                 } else {
2587                         link_active = true;
2588                 }
2589                 break;
2590         case e1000_media_type_fiber:
2591                 ret_val = hw->mac.ops.check_for_link(hw);
2592                 link_active = !!(rd32(E1000_STATUS) & E1000_STATUS_LU);
2593                 break;
2594         case e1000_media_type_internal_serdes:
2595                 ret_val = hw->mac.ops.check_for_link(hw);
2596                 link_active = hw->mac.serdes_has_link;
2597                 break;
2598         default:
2599         case e1000_media_type_unknown:
2600                 break;
2601         }
2602
2603         return link_active;
2604 }
2605
2606 /**
2607  * igb_watchdog - Timer Call-back
2608  * @data: pointer to adapter cast into an unsigned long
2609  **/
2610 static void igb_watchdog(unsigned long data)
2611 {
2612         struct igb_adapter *adapter = (struct igb_adapter *)data;
2613         /* Do the rest outside of interrupt context */
2614         schedule_work(&adapter->watchdog_task);
2615 }
2616
2617 static void igb_watchdog_task(struct work_struct *work)
2618 {
2619         struct igb_adapter *adapter = container_of(work,
2620                                         struct igb_adapter, watchdog_task);
2621         struct e1000_hw *hw = &adapter->hw;
2622         struct net_device *netdev = adapter->netdev;
2623         struct igb_ring *tx_ring = adapter->tx_ring;
2624         u32 link;
2625         u32 eics = 0;
2626         int i;
2627
2628         link = igb_has_link(adapter);
2629         if ((netif_carrier_ok(netdev)) && link)
2630                 goto link_up;
2631
2632         if (link) {
2633                 if (!netif_carrier_ok(netdev)) {
2634                         u32 ctrl;
2635                         hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2636                                                    &adapter->link_speed,
2637                                                    &adapter->link_duplex);
2638
2639                         ctrl = rd32(E1000_CTRL);
2640                         /* Links status message must follow this format */
2641                         printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
2642                                  "Flow Control: %s\n",
2643                                  netdev->name,
2644                                  adapter->link_speed,
2645                                  adapter->link_duplex == FULL_DUPLEX ?
2646                                  "Full Duplex" : "Half Duplex",
2647                                  ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2648                                  E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2649                                  E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2650                                  E1000_CTRL_TFCE) ? "TX" : "None")));
2651
2652                         /* tweak tx_queue_len according to speed/duplex and
2653                          * adjust the timeout factor */
2654                         netdev->tx_queue_len = adapter->tx_queue_len;
2655                         adapter->tx_timeout_factor = 1;
2656                         switch (adapter->link_speed) {
2657                         case SPEED_10:
2658                                 netdev->tx_queue_len = 10;
2659                                 adapter->tx_timeout_factor = 14;
2660                                 break;
2661                         case SPEED_100:
2662                                 netdev->tx_queue_len = 100;
2663                                 /* maybe add some timeout factor ? */
2664                                 break;
2665                         }
2666
2667                         netif_carrier_on(netdev);
2668
2669                         igb_ping_all_vfs(adapter);
2670
2671                         /* link state has changed, schedule phy info update */
2672                         if (!test_bit(__IGB_DOWN, &adapter->state))
2673                                 mod_timer(&adapter->phy_info_timer,
2674                                           round_jiffies(jiffies + 2 * HZ));
2675                 }
2676         } else {
2677                 if (netif_carrier_ok(netdev)) {
2678                         adapter->link_speed = 0;
2679                         adapter->link_duplex = 0;
2680                         /* Links status message must follow this format */
2681                         printk(KERN_INFO "igb: %s NIC Link is Down\n",
2682                                netdev->name);
2683                         netif_carrier_off(netdev);
2684
2685                         igb_ping_all_vfs(adapter);
2686
2687                         /* link state has changed, schedule phy info update */
2688                         if (!test_bit(__IGB_DOWN, &adapter->state))
2689                                 mod_timer(&adapter->phy_info_timer,
2690                                           round_jiffies(jiffies + 2 * HZ));
2691                 }
2692         }
2693
2694 link_up:
2695         igb_update_stats(adapter);
2696
2697         hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2698         adapter->tpt_old = adapter->stats.tpt;
2699         hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
2700         adapter->colc_old = adapter->stats.colc;
2701
2702         adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2703         adapter->gorc_old = adapter->stats.gorc;
2704         adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2705         adapter->gotc_old = adapter->stats.gotc;
2706
2707         igb_update_adaptive(&adapter->hw);
2708
2709         if (!netif_carrier_ok(netdev)) {
2710                 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
2711                         /* We've lost link, so the controller stops DMA,
2712                          * but we've got queued Tx work that's never going
2713                          * to get done, so reset controller to flush Tx.
2714                          * (Do the reset outside of interrupt context). */
2715                         adapter->tx_timeout_count++;
2716                         schedule_work(&adapter->reset_task);
2717                 }
2718         }
2719
2720         /* Cause software interrupt to ensure rx ring is cleaned */
2721         if (adapter->msix_entries) {
2722                 for (i = 0; i < adapter->num_rx_queues; i++)
2723                         eics |= adapter->rx_ring[i].eims_value;
2724                 wr32(E1000_EICS, eics);
2725         } else {
2726                 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2727         }
2728
2729         /* Force detection of hung controller every watchdog period */
2730         tx_ring->detect_tx_hung = true;
2731
2732         /* Reset the timer */
2733         if (!test_bit(__IGB_DOWN, &adapter->state))
2734                 mod_timer(&adapter->watchdog_timer,
2735                           round_jiffies(jiffies + 2 * HZ));
2736 }
2737
2738 enum latency_range {
2739         lowest_latency = 0,
2740         low_latency = 1,
2741         bulk_latency = 2,
2742         latency_invalid = 255
2743 };
2744
2745
2746 /**
2747  * igb_update_ring_itr - update the dynamic ITR value based on packet size
2748  *
2749  *      Stores a new ITR value based on strictly on packet size.  This
2750  *      algorithm is less sophisticated than that used in igb_update_itr,
2751  *      due to the difficulty of synchronizing statistics across multiple
2752  *      receive rings.  The divisors and thresholds used by this fuction
2753  *      were determined based on theoretical maximum wire speed and testing
2754  *      data, in order to minimize response time while increasing bulk
2755  *      throughput.
2756  *      This functionality is controlled by the InterruptThrottleRate module
2757  *      parameter (see igb_param.c)
2758  *      NOTE:  This function is called only when operating in a multiqueue
2759  *             receive environment.
2760  * @rx_ring: pointer to ring
2761  **/
2762 static void igb_update_ring_itr(struct igb_ring *rx_ring)
2763 {
2764         int new_val = rx_ring->itr_val;
2765         int avg_wire_size = 0;
2766         struct igb_adapter *adapter = rx_ring->adapter;
2767
2768         if (!rx_ring->total_packets)
2769                 goto clear_counts; /* no packets, so don't do anything */
2770
2771         /* For non-gigabit speeds, just fix the interrupt rate at 4000
2772          * ints/sec - ITR timer value of 120 ticks.
2773          */
2774         if (adapter->link_speed != SPEED_1000) {
2775                 new_val = 120;
2776                 goto set_itr_val;
2777         }
2778         avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
2779
2780         /* Add 24 bytes to size to account for CRC, preamble, and gap */
2781         avg_wire_size += 24;
2782
2783         /* Don't starve jumbo frames */
2784         avg_wire_size = min(avg_wire_size, 3000);
2785
2786         /* Give a little boost to mid-size frames */
2787         if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2788                 new_val = avg_wire_size / 3;
2789         else
2790                 new_val = avg_wire_size / 2;
2791
2792 set_itr_val:
2793         if (new_val != rx_ring->itr_val) {
2794                 rx_ring->itr_val = new_val;
2795                 rx_ring->set_itr = 1;
2796         }
2797 clear_counts:
2798         rx_ring->total_bytes = 0;
2799         rx_ring->total_packets = 0;
2800 }
2801
2802 /**
2803  * igb_update_itr - update the dynamic ITR value based on statistics
2804  *      Stores a new ITR value based on packets and byte
2805  *      counts during the last interrupt.  The advantage of per interrupt
2806  *      computation is faster updates and more accurate ITR for the current
2807  *      traffic pattern.  Constants in this function were computed
2808  *      based on theoretical maximum wire speed and thresholds were set based
2809  *      on testing data as well as attempting to minimize response time
2810  *      while increasing bulk throughput.
2811  *      this functionality is controlled by the InterruptThrottleRate module
2812  *      parameter (see igb_param.c)
2813  *      NOTE:  These calculations are only valid when operating in a single-
2814  *             queue environment.
2815  * @adapter: pointer to adapter
2816  * @itr_setting: current adapter->itr
2817  * @packets: the number of packets during this measurement interval
2818  * @bytes: the number of bytes during this measurement interval
2819  **/
2820 static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2821                                    int packets, int bytes)
2822 {
2823         unsigned int retval = itr_setting;
2824
2825         if (packets == 0)
2826                 goto update_itr_done;
2827
2828         switch (itr_setting) {
2829         case lowest_latency:
2830                 /* handle TSO and jumbo frames */
2831                 if (bytes/packets > 8000)
2832                         retval = bulk_latency;
2833                 else if ((packets < 5) && (bytes > 512))
2834                         retval = low_latency;
2835                 break;
2836         case low_latency:  /* 50 usec aka 20000 ints/s */
2837                 if (bytes > 10000) {
2838                         /* this if handles the TSO accounting */
2839                         if (bytes/packets > 8000) {
2840                                 retval = bulk_latency;
2841                         } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2842                                 retval = bulk_latency;
2843                         } else if ((packets > 35)) {
2844                                 retval = lowest_latency;
2845                         }
2846                 } else if (bytes/packets > 2000) {
2847                         retval = bulk_latency;
2848                 } else if (packets <= 2 && bytes < 512) {
2849                         retval = lowest_latency;
2850                 }
2851                 break;
2852         case bulk_latency: /* 250 usec aka 4000 ints/s */
2853                 if (bytes > 25000) {
2854                         if (packets > 35)
2855                                 retval = low_latency;
2856                 } else if (bytes < 1500) {
2857                         retval = low_latency;
2858                 }
2859                 break;
2860         }
2861
2862 update_itr_done:
2863         return retval;
2864 }
2865
2866 static void igb_set_itr(struct igb_adapter *adapter)
2867 {
2868         u16 current_itr;
2869         u32 new_itr = adapter->itr;
2870
2871         /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2872         if (adapter->link_speed != SPEED_1000) {
2873                 current_itr = 0;
2874                 new_itr = 4000;
2875                 goto set_itr_now;
2876         }
2877
2878         adapter->rx_itr = igb_update_itr(adapter,
2879                                     adapter->rx_itr,
2880                                     adapter->rx_ring->total_packets,
2881                                     adapter->rx_ring->total_bytes);
2882
2883         if (adapter->rx_ring->buddy) {
2884                 adapter->tx_itr = igb_update_itr(adapter,
2885                                             adapter->tx_itr,
2886                                             adapter->tx_ring->total_packets,
2887                                             adapter->tx_ring->total_bytes);
2888                 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2889         } else {
2890                 current_itr = adapter->rx_itr;
2891         }
2892
2893         /* conservative mode (itr 3) eliminates the lowest_latency setting */
2894         if (adapter->itr_setting == 3 && current_itr == lowest_latency)
2895                 current_itr = low_latency;
2896
2897         switch (current_itr) {
2898         /* counts and packets in update_itr are dependent on these numbers */
2899         case lowest_latency:
2900                 new_itr = 56;  /* aka 70,000 ints/sec */
2901                 break;
2902         case low_latency:
2903                 new_itr = 196; /* aka 20,000 ints/sec */
2904                 break;
2905         case bulk_latency:
2906                 new_itr = 980; /* aka 4,000 ints/sec */
2907                 break;
2908         default:
2909                 break;
2910         }
2911
2912 set_itr_now:
2913         adapter->rx_ring->total_bytes = 0;
2914         adapter->rx_ring->total_packets = 0;
2915         if (adapter->rx_ring->buddy) {
2916                 adapter->rx_ring->buddy->total_bytes = 0;
2917                 adapter->rx_ring->buddy->total_packets = 0;
2918         }
2919
2920         if (new_itr != adapter->itr) {
2921                 /* this attempts to bias the interrupt rate towards Bulk
2922                  * by adding intermediate steps when interrupt rate is
2923                  * increasing */
2924                 new_itr = new_itr > adapter->itr ?
2925                              max((new_itr * adapter->itr) /
2926                                  (new_itr + (adapter->itr >> 2)), new_itr) :
2927                              new_itr;
2928                 /* Don't write the value here; it resets the adapter's
2929                  * internal timer, and causes us to delay far longer than
2930                  * we should between interrupts.  Instead, we write the ITR
2931                  * value at the beginning of the next interrupt so the timing
2932                  * ends up being correct.
2933                  */
2934                 adapter->itr = new_itr;
2935                 adapter->rx_ring->itr_val = new_itr;
2936                 adapter->rx_ring->set_itr = 1;
2937         }
2938
2939         return;
2940 }
2941
2942
2943 #define IGB_TX_FLAGS_CSUM               0x00000001
2944 #define IGB_TX_FLAGS_VLAN               0x00000002
2945 #define IGB_TX_FLAGS_TSO                0x00000004
2946 #define IGB_TX_FLAGS_IPV4               0x00000008
2947 #define IGB_TX_FLAGS_TSTAMP             0x00000010
2948 #define IGB_TX_FLAGS_VLAN_MASK  0xffff0000
2949 #define IGB_TX_FLAGS_VLAN_SHIFT 16
2950
2951 static inline int igb_tso_adv(struct igb_adapter *adapter,
2952                               struct igb_ring *tx_ring,
2953                               struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2954 {
2955         struct e1000_adv_tx_context_desc *context_desc;
2956         unsigned int i;
2957         int err;
2958         struct igb_buffer *buffer_info;
2959         u32 info = 0, tu_cmd = 0;
2960         u32 mss_l4len_idx, l4len;
2961         *hdr_len = 0;
2962
2963         if (skb_header_cloned(skb)) {
2964                 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2965                 if (err)
2966                         return err;
2967         }
2968
2969         l4len = tcp_hdrlen(skb);
2970         *hdr_len += l4len;
2971
2972         if (skb->protocol == htons(ETH_P_IP)) {
2973                 struct iphdr *iph = ip_hdr(skb);
2974                 iph->tot_len = 0;
2975                 iph->check = 0;
2976                 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2977                                                          iph->daddr, 0,
2978                                                          IPPROTO_TCP,
2979                                                          0);
2980         } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2981                 ipv6_hdr(skb)->payload_len = 0;
2982                 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2983                                                        &ipv6_hdr(skb)->daddr,
2984                                                        0, IPPROTO_TCP, 0);
2985         }
2986
2987         i = tx_ring->next_to_use;
2988
2989         buffer_info = &tx_ring->buffer_info[i];
2990         context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2991         /* VLAN MACLEN IPLEN */
2992         if (tx_flags & IGB_TX_FLAGS_VLAN)
2993                 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2994         info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2995         *hdr_len += skb_network_offset(skb);
2996         info |= skb_network_header_len(skb);
2997         *hdr_len += skb_network_header_len(skb);
2998         context_desc->vlan_macip_lens = cpu_to_le32(info);
2999
3000         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3001         tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3002
3003         if (skb->protocol == htons(ETH_P_IP))
3004                 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3005         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3006
3007         context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3008
3009         /* MSS L4LEN IDX */
3010         mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3011         mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3012
3013         /* For 82575, context index must be unique per ring. */
3014         if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3015                 mss_l4len_idx |= tx_ring->queue_index << 4;
3016
3017         context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3018         context_desc->seqnum_seed = 0;
3019
3020         buffer_info->time_stamp = jiffies;
3021         buffer_info->next_to_watch = i;
3022         buffer_info->dma = 0;
3023         i++;
3024         if (i == tx_ring->count)
3025                 i = 0;
3026
3027         tx_ring->next_to_use = i;
3028
3029         return true;
3030 }
3031
3032 static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
3033                                         struct igb_ring *tx_ring,
3034                                         struct sk_buff *skb, u32 tx_flags)
3035 {
3036         struct e1000_adv_tx_context_desc *context_desc;
3037         unsigned int i;
3038         struct igb_buffer *buffer_info;
3039         u32 info = 0, tu_cmd = 0;
3040
3041         if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3042             (tx_flags & IGB_TX_FLAGS_VLAN)) {
3043                 i = tx_ring->next_to_use;
3044                 buffer_info = &tx_ring->buffer_info[i];
3045                 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3046
3047                 if (tx_flags & IGB_TX_FLAGS_VLAN)
3048                         info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3049                 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3050                 if (skb->ip_summed == CHECKSUM_PARTIAL)
3051                         info |= skb_network_header_len(skb);
3052
3053                 context_desc->vlan_macip_lens = cpu_to_le32(info);
3054
3055                 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3056
3057                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3058                         __be16 protocol;
3059
3060                         if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
3061                                 const struct vlan_ethhdr *vhdr =
3062                                           (const struct vlan_ethhdr*)skb->data;
3063
3064                                 protocol = vhdr->h_vlan_encapsulated_proto;
3065                         } else {
3066                                 protocol = skb->protocol;
3067                         }
3068
3069                         switch (protocol) {
3070                         case cpu_to_be16(ETH_P_IP):
3071                                 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3072                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3073                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3074                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
3075                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
3076                                 break;
3077                         case cpu_to_be16(ETH_P_IPV6):
3078                                 /* XXX what about other V6 headers?? */
3079                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3080                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3081                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
3082                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
3083                                 break;
3084                         default:
3085                                 if (unlikely(net_ratelimit()))
3086                                         dev_warn(&adapter->pdev->dev,
3087                                             "partial checksum but proto=%x!\n",
3088                                             skb->protocol);
3089                                 break;
3090                         }
3091                 }
3092
3093                 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3094                 context_desc->seqnum_seed = 0;
3095                 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3096                         context_desc->mss_l4len_idx =
3097                                 cpu_to_le32(tx_ring->queue_index << 4);
3098                 else
3099                         context_desc->mss_l4len_idx = 0;
3100
3101                 buffer_info->time_stamp = jiffies;
3102                 buffer_info->next_to_watch = i;
3103                 buffer_info->dma = 0;
3104
3105                 i++;
3106                 if (i == tx_ring->count)
3107                         i = 0;
3108                 tx_ring->next_to_use = i;
3109
3110                 return true;
3111         }
3112         return false;
3113 }
3114
3115 #define IGB_MAX_TXD_PWR 16
3116 #define IGB_MAX_DATA_PER_TXD    (1<<IGB_MAX_TXD_PWR)
3117
3118 static inline int igb_tx_map_adv(struct igb_adapter *adapter,
3119                                  struct igb_ring *tx_ring, struct sk_buff *skb,
3120                                  unsigned int first)
3121 {
3122         struct igb_buffer *buffer_info;
3123         unsigned int len = skb_headlen(skb);
3124         unsigned int count = 0, i;
3125         unsigned int f;
3126         dma_addr_t *map;
3127
3128         i = tx_ring->next_to_use;
3129
3130         if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
3131                 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
3132                 return 0;
3133         }
3134
3135         map = skb_shinfo(skb)->dma_maps;
3136
3137         buffer_info = &tx_ring->buffer_info[i];
3138         BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3139         buffer_info->length = len;
3140         /* set time_stamp *before* dma to help avoid a possible race */
3141         buffer_info->time_stamp = jiffies;
3142         buffer_info->next_to_watch = i;
3143         buffer_info->dma = map[count];
3144         count++;
3145
3146         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3147                 struct skb_frag_struct *frag;
3148
3149                 i++;
3150                 if (i == tx_ring->count)
3151                         i = 0;
3152
3153                 frag = &skb_shinfo(skb)->frags[f];
3154                 len = frag->size;
3155
3156                 buffer_info = &tx_ring->buffer_info[i];
3157                 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3158                 buffer_info->length = len;
3159                 buffer_info->time_stamp = jiffies;
3160                 buffer_info->next_to_watch = i;
3161                 buffer_info->dma = map[count];
3162                 count++;
3163         }
3164
3165         tx_ring->buffer_info[i].skb = skb;
3166         tx_ring->buffer_info[first].next_to_watch = i;
3167
3168         return count;
3169 }
3170
3171 static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
3172                                     struct igb_ring *tx_ring,
3173                                     int tx_flags, int count, u32 paylen,
3174                                     u8 hdr_len)
3175 {
3176         union e1000_adv_tx_desc *tx_desc = NULL;
3177         struct igb_buffer *buffer_info;
3178         u32 olinfo_status = 0, cmd_type_len;
3179         unsigned int i;
3180
3181         cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3182                         E1000_ADVTXD_DCMD_DEXT);
3183
3184         if (tx_flags & IGB_TX_FLAGS_VLAN)
3185                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3186
3187         if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3188                 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3189
3190         if (tx_flags & IGB_TX_FLAGS_TSO) {
3191                 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3192
3193                 /* insert tcp checksum */
3194                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3195
3196                 /* insert ip checksum */
3197                 if (tx_flags & IGB_TX_FLAGS_IPV4)
3198                         olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3199
3200         } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3201                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3202         }
3203
3204         if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
3205             (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
3206                          IGB_TX_FLAGS_VLAN)))
3207                 olinfo_status |= tx_ring->queue_index << 4;
3208
3209         olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3210
3211         i = tx_ring->next_to_use;
3212         while (count--) {
3213                 buffer_info = &tx_ring->buffer_info[i];
3214                 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3215                 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3216                 tx_desc->read.cmd_type_len =
3217                         cpu_to_le32(cmd_type_len | buffer_info->length);
3218                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3219                 i++;
3220                 if (i == tx_ring->count)
3221                         i = 0;
3222         }
3223
3224         tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3225         /* Force memory writes to complete before letting h/w
3226          * know there are new descriptors to fetch.  (Only
3227          * applicable for weak-ordered memory model archs,
3228          * such as IA-64). */
3229         wmb();
3230
3231         tx_ring->next_to_use = i;
3232         writel(i, adapter->hw.hw_addr + tx_ring->tail);
3233         /* we need this if more than one processor can write to our tail
3234          * at a time, it syncronizes IO on IA64/Altix systems */
3235         mmiowb();
3236 }
3237
3238 static int __igb_maybe_stop_tx(struct net_device *netdev,
3239                                struct igb_ring *tx_ring, int size)
3240 {
3241         struct igb_adapter *adapter = netdev_priv(netdev);
3242
3243         netif_stop_subqueue(netdev, tx_ring->queue_index);
3244
3245         /* Herbert's original patch had:
3246          *  smp_mb__after_netif_stop_queue();
3247          * but since that doesn't exist yet, just open code it. */
3248         smp_mb();
3249
3250         /* We need to check again in a case another CPU has just
3251          * made room available. */
3252         if (igb_desc_unused(tx_ring) < size)
3253                 return -EBUSY;
3254
3255         /* A reprieve! */
3256         netif_wake_subqueue(netdev, tx_ring->queue_index);
3257         ++adapter->restart_queue;
3258         return 0;
3259 }
3260
3261 static int igb_maybe_stop_tx(struct net_device *netdev,
3262                              struct igb_ring *tx_ring, int size)
3263 {
3264         if (igb_desc_unused(tx_ring) >= size)
3265                 return 0;
3266         return __igb_maybe_stop_tx(netdev, tx_ring, size);
3267 }
3268
3269 static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
3270                                    struct net_device *netdev,
3271                                    struct igb_ring *tx_ring)
3272 {
3273         struct igb_adapter *adapter = netdev_priv(netdev);
3274         unsigned int first;
3275         unsigned int tx_flags = 0;
3276         u8 hdr_len = 0;
3277         int count = 0;
3278         int tso = 0;
3279         union skb_shared_tx *shtx;
3280
3281         if (test_bit(__IGB_DOWN, &adapter->state)) {
3282                 dev_kfree_skb_any(skb);
3283                 return NETDEV_TX_OK;
3284         }
3285
3286         if (skb->len <= 0) {
3287                 dev_kfree_skb_any(skb);
3288                 return NETDEV_TX_OK;
3289         }
3290
3291         /* need: 1 descriptor per page,
3292          *       + 2 desc gap to keep tail from touching head,
3293          *       + 1 desc for skb->data,
3294          *       + 1 desc for context descriptor,
3295          * otherwise try next time */
3296         if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3297                 /* this is a hard error */
3298                 return NETDEV_TX_BUSY;
3299         }
3300
3301         /*
3302          * TODO: check that there currently is no other packet with
3303          * time stamping in the queue
3304          *
3305          * When doing time stamping, keep the connection to the socket
3306          * a while longer: it is still needed by skb_hwtstamp_tx(),
3307          * called either in igb_tx_hwtstamp() or by our caller when
3308          * doing software time stamping.
3309          */
3310         shtx = skb_tx(skb);
3311         if (unlikely(shtx->hardware)) {
3312                 shtx->in_progress = 1;
3313                 tx_flags |= IGB_TX_FLAGS_TSTAMP;
3314         }
3315
3316         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3317                 tx_flags |= IGB_TX_FLAGS_VLAN;
3318                 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3319         }
3320
3321         if (skb->protocol == htons(ETH_P_IP))
3322                 tx_flags |= IGB_TX_FLAGS_IPV4;
3323
3324         first = tx_ring->next_to_use;
3325         tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3326                                               &hdr_len) : 0;
3327
3328         if (tso < 0) {
3329                 dev_kfree_skb_any(skb);
3330                 return NETDEV_TX_OK;
3331         }
3332
3333         if (tso)
3334                 tx_flags |= IGB_TX_FLAGS_TSO;
3335         else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) &&
3336                  (skb->ip_summed == CHECKSUM_PARTIAL))
3337                 tx_flags |= IGB_TX_FLAGS_CSUM;
3338
3339         /*
3340          * count reflects descriptors mapped, if 0 then mapping error
3341          * has occured and we need to rewind the descriptor queue
3342          */
3343         count = igb_tx_map_adv(adapter, tx_ring, skb, first);
3344
3345         if (count) {
3346                 igb_tx_queue_adv(adapter, tx_ring, tx_flags, count,
3347                                  skb->len, hdr_len);
3348                 netdev->trans_start = jiffies;
3349                 /* Make sure there is space in the ring for the next send. */
3350                 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3351         } else {
3352                 dev_kfree_skb_any(skb);
3353                 tx_ring->buffer_info[first].time_stamp = 0;
3354                 tx_ring->next_to_use = first;
3355         }
3356
3357         return NETDEV_TX_OK;
3358 }
3359
3360 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3361 {
3362         struct igb_adapter *adapter = netdev_priv(netdev);
3363         struct igb_ring *tx_ring;
3364
3365         int r_idx = 0;
3366         r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
3367         tx_ring = adapter->multi_tx_table[r_idx];
3368
3369         /* This goes back to the question of how to logically map a tx queue
3370          * to a flow.  Right now, performance is impacted slightly negatively
3371          * if using multiple tx queues.  If the stack breaks away from a
3372          * single qdisc implementation, we can look at this again. */
3373         return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3374 }
3375
3376 /**
3377  * igb_tx_timeout - Respond to a Tx Hang
3378  * @netdev: network interface device structure
3379  **/
3380 static void igb_tx_timeout(struct net_device *netdev)
3381 {
3382         struct igb_adapter *adapter = netdev_priv(netdev);
3383         struct e1000_hw *hw = &adapter->hw;
3384
3385         /* Do the reset outside of interrupt context */
3386         adapter->tx_timeout_count++;
3387         schedule_work(&adapter->reset_task);
3388         wr32(E1000_EICS,
3389              (adapter->eims_enable_mask & ~adapter->eims_other));
3390 }
3391
3392 static void igb_reset_task(struct work_struct *work)
3393 {
3394         struct igb_adapter *adapter;
3395         adapter = container_of(work, struct igb_adapter, reset_task);
3396
3397         igb_reinit_locked(adapter);
3398 }
3399
3400 /**
3401  * igb_get_stats - Get System Network Statistics
3402  * @netdev: network interface device structure
3403  *
3404  * Returns the address of the device statistics structure.
3405  * The statistics are actually updated from the timer callback.
3406  **/
3407 static struct net_device_stats *igb_get_stats(struct net_device *netdev)
3408 {
3409         struct igb_adapter *adapter = netdev_priv(netdev);
3410
3411         /* only return the current stats */
3412         return &adapter->net_stats;
3413 }
3414
3415 /**
3416  * igb_change_mtu - Change the Maximum Transfer Unit
3417  * @netdev: network interface device structure
3418  * @new_mtu: new value for maximum frame size
3419  *
3420  * Returns 0 on success, negative on failure
3421  **/
3422 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3423 {
3424         struct igb_adapter *adapter = netdev_priv(netdev);
3425         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3426
3427         if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3428             (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3429                 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3430                 return -EINVAL;
3431         }
3432
3433         if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3434                 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3435                 return -EINVAL;
3436         }
3437
3438         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3439                 msleep(1);
3440
3441         /* igb_down has a dependency on max_frame_size */
3442         adapter->max_frame_size = max_frame;
3443         if (netif_running(netdev))
3444                 igb_down(adapter);
3445
3446         /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3447          * means we reserve 2 more, this pushes us to allocate from the next
3448          * larger slab size.
3449          * i.e. RXBUFFER_2048 --> size-4096 slab
3450          */
3451
3452         if (max_frame <= IGB_RXBUFFER_256)
3453                 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3454         else if (max_frame <= IGB_RXBUFFER_512)
3455                 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3456         else if (max_frame <= IGB_RXBUFFER_1024)
3457                 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3458         else if (max_frame <= IGB_RXBUFFER_2048)
3459                 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3460         else
3461 #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3462                 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3463 #else
3464                 adapter->rx_buffer_len = PAGE_SIZE / 2;
3465 #endif
3466
3467         /* if sr-iov is enabled we need to force buffer size to 1K or larger */
3468         if (adapter->vfs_allocated_count &&
3469             (adapter->rx_buffer_len < IGB_RXBUFFER_1024))
3470                 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3471
3472         /* adjust allocation if LPE protects us, and we aren't using SBP */
3473         if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3474              (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3475                 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3476
3477         dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3478                  netdev->mtu, new_mtu);
3479         netdev->mtu = new_mtu;
3480
3481         if (netif_running(netdev))
3482                 igb_up(adapter);
3483         else
3484                 igb_reset(adapter);
3485
3486         clear_bit(__IGB_RESETTING, &adapter->state);
3487
3488         return 0;
3489 }
3490
3491 /**
3492  * igb_update_stats - Update the board statistics counters
3493  * @adapter: board private structure
3494  **/
3495
3496 void igb_update_stats(struct igb_adapter *adapter)
3497 {
3498         struct e1000_hw *hw = &adapter->hw;
3499         struct pci_dev *pdev = adapter->pdev;
3500         u16 phy_tmp;
3501
3502 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3503
3504         /*
3505          * Prevent stats update while adapter is being reset, or if the pci
3506          * connection is down.
3507          */
3508         if (adapter->link_speed == 0)
3509                 return;
3510         if (pci_channel_offline(pdev))
3511                 return;
3512
3513         adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3514         adapter->stats.gprc += rd32(E1000_GPRC);
3515         adapter->stats.gorc += rd32(E1000_GORCL);
3516         rd32(E1000_GORCH); /* clear GORCL */
3517         adapter->stats.bprc += rd32(E1000_BPRC);
3518         adapter->stats.mprc += rd32(E1000_MPRC);
3519         adapter->stats.roc += rd32(E1000_ROC);
3520
3521         adapter->stats.prc64 += rd32(E1000_PRC64);
3522         adapter->stats.prc127 += rd32(E1000_PRC127);
3523         adapter->stats.prc255 += rd32(E1000_PRC255);
3524         adapter->stats.prc511 += rd32(E1000_PRC511);
3525         adapter->stats.prc1023 += rd32(E1000_PRC1023);
3526         adapter->stats.prc1522 += rd32(E1000_PRC1522);
3527         adapter->stats.symerrs += rd32(E1000_SYMERRS);
3528         adapter->stats.sec += rd32(E1000_SEC);
3529
3530         adapter->stats.mpc += rd32(E1000_MPC);
3531         adapter->stats.scc += rd32(E1000_SCC);
3532         adapter->stats.ecol += rd32(E1000_ECOL);
3533         adapter->stats.mcc += rd32(E1000_MCC);
3534         adapter->stats.latecol += rd32(E1000_LATECOL);
3535         adapter->stats.dc += rd32(E1000_DC);
3536         adapter->stats.rlec += rd32(E1000_RLEC);
3537         adapter->stats.xonrxc += rd32(E1000_XONRXC);
3538         adapter->stats.xontxc += rd32(E1000_XONTXC);
3539         adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3540         adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3541         adapter->stats.fcruc += rd32(E1000_FCRUC);
3542         adapter->stats.gptc += rd32(E1000_GPTC);
3543         adapter->stats.gotc += rd32(E1000_GOTCL);
3544         rd32(E1000_GOTCH); /* clear GOTCL */
3545         adapter->stats.rnbc += rd32(E1000_RNBC);
3546         adapter->stats.ruc += rd32(E1000_RUC);
3547         adapter->stats.rfc += rd32(E1000_RFC);
3548         adapter->stats.rjc += rd32(E1000_RJC);
3549         adapter->stats.tor += rd32(E1000_TORH);
3550         adapter->stats.tot += rd32(E1000_TOTH);
3551         adapter->stats.tpr += rd32(E1000_TPR);
3552
3553         adapter->stats.ptc64 += rd32(E1000_PTC64);
3554         adapter->stats.ptc127 += rd32(E1000_PTC127);
3555         adapter->stats.ptc255 += rd32(E1000_PTC255);
3556         adapter->stats.ptc511 += rd32(E1000_PTC511);
3557         adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3558         adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3559
3560         adapter->stats.mptc += rd32(E1000_MPTC);
3561         adapter->stats.bptc += rd32(E1000_BPTC);
3562
3563         /* used for adaptive IFS */
3564
3565         hw->mac.tx_packet_delta = rd32(E1000_TPT);
3566         adapter->stats.tpt += hw->mac.tx_packet_delta;
3567         hw->mac.collision_delta = rd32(E1000_COLC);
3568         adapter->stats.colc += hw->mac.collision_delta;
3569
3570         adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3571         adapter->stats.rxerrc += rd32(E1000_RXERRC);
3572         adapter->stats.tncrs += rd32(E1000_TNCRS);
3573         adapter->stats.tsctc += rd32(E1000_TSCTC);
3574         adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3575
3576         adapter->stats.iac += rd32(E1000_IAC);
3577         adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3578         adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3579         adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3580         adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3581         adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3582         adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3583         adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3584         adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3585
3586         /* Fill out the OS statistics structure */
3587         adapter->net_stats.multicast = adapter->stats.mprc;
3588         adapter->net_stats.collisions = adapter->stats.colc;
3589
3590         /* Rx Errors */
3591
3592         /* RLEC on some newer hardware can be incorrect so build
3593         * our own version based on RUC and ROC */
3594         adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3595                 adapter->stats.crcerrs + adapter->stats.algnerrc +
3596                 adapter->stats.ruc + adapter->stats.roc +
3597                 adapter->stats.cexterr;
3598         adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3599                                               adapter->stats.roc;
3600         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3601         adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3602         adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3603
3604         /* Tx Errors */
3605         adapter->net_stats.tx_errors = adapter->stats.ecol +
3606                                        adapter->stats.latecol;
3607         adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3608         adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3609         adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3610
3611         /* Tx Dropped needs to be maintained elsewhere */
3612
3613         /* Phy Stats */
3614         if (hw->phy.media_type == e1000_media_type_copper) {
3615                 if ((adapter->link_speed == SPEED_1000) &&
3616                    (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3617                         phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3618                         adapter->phy_stats.idle_errors += phy_tmp;
3619                 }
3620         }
3621
3622         /* Management Stats */
3623         adapter->stats.mgptc += rd32(E1000_MGTPTC);
3624         adapter->stats.mgprc += rd32(E1000_MGTPRC);
3625         adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3626 }
3627
3628 static irqreturn_t igb_msix_other(int irq, void *data)
3629 {
3630         struct net_device *netdev = data;
3631         struct igb_adapter *adapter = netdev_priv(netdev);
3632         struct e1000_hw *hw = &adapter->hw;
3633         u32 icr = rd32(E1000_ICR);
3634
3635         /* reading ICR causes bit 31 of EICR to be cleared */
3636
3637         if(icr & E1000_ICR_DOUTSYNC) {
3638                 /* HW is reporting DMA is out of sync */
3639                 adapter->stats.doosync++;
3640         }
3641
3642         /* Check for a mailbox event */
3643         if (icr & E1000_ICR_VMMB)
3644                 igb_msg_task(adapter);
3645
3646         if (icr & E1000_ICR_LSC) {
3647                 hw->mac.get_link_status = 1;
3648                 /* guard against interrupt when we're going down */
3649                 if (!test_bit(__IGB_DOWN, &adapter->state))
3650                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
3651         }
3652
3653         wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB);
3654         wr32(E1000_EIMS, adapter->eims_other);
3655
3656         return IRQ_HANDLED;
3657 }
3658
3659 static irqreturn_t igb_msix_tx(int irq, void *data)
3660 {
3661         struct igb_ring *tx_ring = data;
3662         struct igb_adapter *adapter = tx_ring->adapter;
3663         struct e1000_hw *hw = &adapter->hw;
3664
3665 #ifdef CONFIG_IGB_DCA
3666         if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3667                 igb_update_tx_dca(tx_ring);
3668 #endif
3669
3670         tx_ring->total_bytes = 0;
3671         tx_ring->total_packets = 0;
3672
3673         /* auto mask will automatically reenable the interrupt when we write
3674          * EICS */
3675         if (!igb_clean_tx_irq(tx_ring))
3676                 /* Ring was not completely cleaned, so fire another interrupt */
3677                 wr32(E1000_EICS, tx_ring->eims_value);
3678         else
3679                 wr32(E1000_EIMS, tx_ring->eims_value);
3680
3681         return IRQ_HANDLED;
3682 }
3683
3684 static void igb_write_itr(struct igb_ring *ring)
3685 {
3686         struct e1000_hw *hw = &ring->adapter->hw;
3687         if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3688                 switch (hw->mac.type) {
3689                 case e1000_82576:
3690                         wr32(ring->itr_register, ring->itr_val |
3691                              0x80000000);
3692                         break;
3693                 default:
3694                         wr32(ring->itr_register, ring->itr_val |
3695                              (ring->itr_val << 16));
3696                         break;
3697                 }
3698                 ring->set_itr = 0;
3699         }
3700 }
3701
3702 static irqreturn_t igb_msix_rx(int irq, void *data)
3703 {
3704         struct igb_ring *rx_ring = data;
3705
3706         /* Write the ITR value calculated at the end of the
3707          * previous interrupt.
3708          */
3709
3710         igb_write_itr(rx_ring);
3711
3712         if (napi_schedule_prep(&rx_ring->napi))
3713                 __napi_schedule(&rx_ring->napi);
3714
3715 #ifdef CONFIG_IGB_DCA
3716         if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
3717                 igb_update_rx_dca(rx_ring);
3718 #endif
3719                 return IRQ_HANDLED;
3720 }
3721
3722 #ifdef CONFIG_IGB_DCA
3723 static void igb_update_rx_dca(struct igb_ring *rx_ring)
3724 {
3725         u32 dca_rxctrl;
3726         struct igb_adapter *adapter = rx_ring->adapter;
3727         struct e1000_hw *hw = &adapter->hw;
3728         int cpu = get_cpu();
3729         int q = rx_ring->reg_idx;
3730
3731         if (rx_ring->cpu != cpu) {
3732                 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
3733                 if (hw->mac.type == e1000_82576) {
3734                         dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3735                         dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
3736                                       E1000_DCA_RXCTRL_CPUID_SHIFT;
3737                 } else {
3738                         dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3739                         dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
3740                 }
3741                 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3742                 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3743                 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3744                 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3745                 rx_ring->cpu = cpu;
3746         }
3747         put_cpu();
3748 }
3749
3750 static void igb_update_tx_dca(struct igb_ring *tx_ring)
3751 {
3752         u32 dca_txctrl;
3753         struct igb_adapter *adapter = tx_ring->adapter;
3754         struct e1000_hw *hw = &adapter->hw;
3755         int cpu = get_cpu();
3756         int q = tx_ring->reg_idx;
3757
3758         if (tx_ring->cpu != cpu) {
3759                 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
3760                 if (hw->mac.type == e1000_82576) {
3761                         dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3762                         dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
3763                                       E1000_DCA_TXCTRL_CPUID_SHIFT;
3764                 } else {
3765                         dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3766                         dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
3767                 }
3768                 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3769                 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3770                 tx_ring->cpu = cpu;
3771         }
3772         put_cpu();
3773 }
3774
3775 static void igb_setup_dca(struct igb_adapter *adapter)
3776 {
3777         int i;
3778
3779         if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
3780                 return;
3781
3782         for (i = 0; i < adapter->num_tx_queues; i++) {
3783                 adapter->tx_ring[i].cpu = -1;
3784                 igb_update_tx_dca(&adapter->tx_ring[i]);
3785         }
3786         for (i = 0; i < adapter->num_rx_queues; i++) {
3787                 adapter->rx_ring[i].cpu = -1;
3788                 igb_update_rx_dca(&adapter->rx_ring[i]);
3789         }
3790 }
3791
3792 static int __igb_notify_dca(struct device *dev, void *data)
3793 {
3794         struct net_device *netdev = dev_get_drvdata(dev);
3795         struct igb_adapter *adapter = netdev_priv(netdev);
3796         struct e1000_hw *hw = &adapter->hw;
3797         unsigned long event = *(unsigned long *)data;
3798
3799         switch (event) {
3800         case DCA_PROVIDER_ADD:
3801                 /* if already enabled, don't do it again */
3802                 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3803                         break;
3804                 /* Always use CB2 mode, difference is masked
3805                  * in the CB driver. */
3806                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
3807                 if (dca_add_requester(dev) == 0) {
3808                         adapter->flags |= IGB_FLAG_DCA_ENABLED;
3809                         dev_info(&adapter->pdev->dev, "DCA enabled\n");
3810                         igb_setup_dca(adapter);
3811                         break;
3812                 }
3813                 /* Fall Through since DCA is disabled. */
3814         case DCA_PROVIDER_REMOVE:
3815                 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3816                         /* without this a class_device is left
3817                          * hanging around in the sysfs model */
3818                         dca_remove_requester(dev);
3819                         dev_info(&adapter->pdev->dev, "DCA disabled\n");
3820                         adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3821                         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
3822                 }
3823                 break;
3824         }
3825
3826         return 0;
3827 }
3828
3829 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3830                           void *p)
3831 {
3832         int ret_val;
3833
3834         ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3835                                          __igb_notify_dca);
3836
3837         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3838 }
3839 #endif /* CONFIG_IGB_DCA */
3840
3841 static void igb_ping_all_vfs(struct igb_adapter *adapter)
3842 {
3843         struct e1000_hw *hw = &adapter->hw;
3844         u32 ping;
3845         int i;
3846
3847         for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
3848                 ping = E1000_PF_CONTROL_MSG;
3849                 if (adapter->vf_data[i].clear_to_send)
3850                         ping |= E1000_VT_MSGTYPE_CTS;
3851                 igb_write_mbx(hw, &ping, 1, i);
3852         }
3853 }
3854
3855 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
3856                                   u32 *msgbuf, u32 vf)
3857 {
3858         int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3859         u16 *hash_list = (u16 *)&msgbuf[1];
3860         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
3861         int i;
3862
3863         /* only up to 30 hash values supported */
3864         if (n > 30)
3865                 n = 30;
3866
3867         /* salt away the number of multi cast addresses assigned
3868          * to this VF for later use to restore when the PF multi cast
3869          * list changes
3870          */
3871         vf_data->num_vf_mc_hashes = n;
3872
3873         /* VFs are limited to using the MTA hash table for their multicast
3874          * addresses */
3875         for (i = 0; i < n; i++)
3876                 vf_data->vf_mc_hashes[i] = hash_list[i];;
3877
3878         /* Flush and reset the mta with the new values */
3879         igb_set_multi(adapter->netdev);
3880
3881         return 0;
3882 }
3883
3884 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
3885 {
3886         struct e1000_hw *hw = &adapter->hw;
3887         struct vf_data_storage *vf_data;
3888         int i, j;
3889
3890         for (i = 0; i < adapter->vfs_allocated_count; i++) {
3891                 vf_data = &adapter->vf_data[i];
3892                 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
3893                         igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
3894         }
3895 }
3896
3897 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
3898 {
3899         struct e1000_hw *hw = &adapter->hw;
3900         u32 pool_mask, reg, vid;
3901         int i;
3902
3903         pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3904
3905         /* Find the vlan filter for this id */
3906         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3907                 reg = rd32(E1000_VLVF(i));
3908
3909                 /* remove the vf from the pool */
3910                 reg &= ~pool_mask;
3911
3912                 /* if pool is empty then remove entry from vfta */
3913                 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
3914                     (reg & E1000_VLVF_VLANID_ENABLE)) {
3915                         reg = 0;
3916                         vid = reg & E1000_VLVF_VLANID_MASK;
3917                         igb_vfta_set(hw, vid, false);
3918                 }
3919
3920                 wr32(E1000_VLVF(i), reg);
3921         }
3922 }
3923
3924 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
3925 {
3926         struct e1000_hw *hw = &adapter->hw;
3927         u32 reg, i;
3928
3929         /* It is an error to call this function when VFs are not enabled */
3930         if (!adapter->vfs_allocated_count)
3931                 return -1;
3932
3933         /* Find the vlan filter for this id */
3934         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3935                 reg = rd32(E1000_VLVF(i));
3936                 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
3937                     vid == (reg & E1000_VLVF_VLANID_MASK))
3938                         break;
3939         }
3940
3941         if (add) {
3942                 if (i == E1000_VLVF_ARRAY_SIZE) {
3943                         /* Did not find a matching VLAN ID entry that was
3944                          * enabled.  Search for a free filter entry, i.e.
3945                          * one without the enable bit set
3946                          */
3947                         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3948                                 reg = rd32(E1000_VLVF(i));
3949                                 if (!(reg & E1000_VLVF_VLANID_ENABLE))
3950                                         break;
3951                         }
3952                 }
3953                 if (i < E1000_VLVF_ARRAY_SIZE) {
3954                         /* Found an enabled/available entry */
3955                         reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3956
3957                         /* if !enabled we need to set this up in vfta */
3958                         if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
3959                                 /* add VID to filter table, if bit already set
3960                                  * PF must have added it outside of table */
3961                                 if (igb_vfta_set(hw, vid, true))
3962                                         reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT +
3963                                                 adapter->vfs_allocated_count);
3964                                 reg |= E1000_VLVF_VLANID_ENABLE;
3965                         }
3966                         reg &= ~E1000_VLVF_VLANID_MASK;
3967                         reg |= vid;
3968
3969                         wr32(E1000_VLVF(i), reg);
3970                         return 0;
3971                 }
3972         } else {
3973                 if (i < E1000_VLVF_ARRAY_SIZE) {
3974                         /* remove vf from the pool */
3975                         reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
3976                         /* if pool is empty then remove entry from vfta */
3977                         if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
3978                                 reg = 0;
3979                                 igb_vfta_set(hw, vid, false);
3980                         }
3981                         wr32(E1000_VLVF(i), reg);
3982                         return 0;
3983                 }
3984         }
3985         return -1;
3986 }
3987
3988 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
3989 {
3990         int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3991         int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
3992
3993         return igb_vlvf_set(adapter, vid, add, vf);
3994 }
3995
3996 static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
3997 {
3998         struct e1000_hw *hw = &adapter->hw;
3999
4000         /* disable mailbox functionality for vf */
4001         adapter->vf_data[vf].clear_to_send = false;
4002
4003         /* reset offloads to defaults */
4004         igb_set_vmolr(hw, vf);
4005
4006         /* reset vlans for device */
4007         igb_clear_vf_vfta(adapter, vf);
4008
4009         /* reset multicast table array for vf */
4010         adapter->vf_data[vf].num_vf_mc_hashes = 0;
4011
4012         /* Flush and reset the mta with the new values */
4013         igb_set_multi(adapter->netdev);
4014 }
4015
4016 static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4017 {
4018         struct e1000_hw *hw = &adapter->hw;
4019         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
4020         u32 reg, msgbuf[3];
4021         u8 *addr = (u8 *)(&msgbuf[1]);
4022
4023         /* process all the same items cleared in a function level reset */
4024         igb_vf_reset_event(adapter, vf);
4025
4026         /* set vf mac address */
4027         igb_rar_set(hw, vf_mac, vf + 1);
4028         igb_set_rah_pool(hw, vf, vf + 1);
4029
4030         /* enable transmit and receive for vf */
4031         reg = rd32(E1000_VFTE);
4032         wr32(E1000_VFTE, reg | (1 << vf));
4033         reg = rd32(E1000_VFRE);
4034         wr32(E1000_VFRE, reg | (1 << vf));
4035
4036         /* enable mailbox functionality for vf */
4037         adapter->vf_data[vf].clear_to_send = true;
4038
4039         /* reply to reset with ack and vf mac address */
4040         msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
4041         memcpy(addr, vf_mac, 6);
4042         igb_write_mbx(hw, msgbuf, 3, vf);
4043 }
4044
4045 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
4046 {
4047                 unsigned char *addr = (char *)&msg[1];
4048                 int err = -1;
4049
4050                 if (is_valid_ether_addr(addr))
4051                         err = igb_set_vf_mac(adapter, vf, addr);
4052
4053                 return err;
4054
4055 }
4056
4057 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
4058 {
4059         struct e1000_hw *hw = &adapter->hw;
4060         u32 msg = E1000_VT_MSGTYPE_NACK;
4061
4062         /* if device isn't clear to send it shouldn't be reading either */
4063         if (!adapter->vf_data[vf].clear_to_send)
4064                 igb_write_mbx(hw, &msg, 1, vf);
4065 }
4066
4067
4068 static void igb_msg_task(struct igb_adapter *adapter)
4069 {
4070         struct e1000_hw *hw = &adapter->hw;
4071         u32 vf;
4072
4073         for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4074                 /* process any reset requests */
4075                 if (!igb_check_for_rst(hw, vf)) {
4076                         adapter->vf_data[vf].clear_to_send = false;
4077                         igb_vf_reset_event(adapter, vf);
4078                 }
4079
4080                 /* process any messages pending */
4081                 if (!igb_check_for_msg(hw, vf))
4082                         igb_rcv_msg_from_vf(adapter, vf);
4083
4084                 /* process any acks */
4085                 if (!igb_check_for_ack(hw, vf))
4086                         igb_rcv_ack_from_vf(adapter, vf);
4087
4088         }
4089 }
4090
4091 static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4092 {
4093         u32 mbx_size = E1000_VFMAILBOX_SIZE;
4094         u32 msgbuf[mbx_size];
4095         struct e1000_hw *hw = &adapter->hw;
4096         s32 retval;
4097
4098         retval = igb_read_mbx(hw, msgbuf, mbx_size, vf);
4099
4100         if (retval)
4101                 dev_err(&adapter->pdev->dev,
4102                         "Error receiving message from VF\n");
4103
4104         /* this is a message we already processed, do nothing */
4105         if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
4106                 return retval;
4107
4108         /*
4109          * until the vf completes a reset it should not be
4110          * allowed to start any configuration.
4111          */
4112
4113         if (msgbuf[0] == E1000_VF_RESET) {
4114                 igb_vf_reset_msg(adapter, vf);
4115
4116                 return retval;
4117         }
4118
4119         if (!adapter->vf_data[vf].clear_to_send) {
4120                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4121                 igb_write_mbx(hw, msgbuf, 1, vf);
4122                 return retval;
4123         }
4124
4125         switch ((msgbuf[0] & 0xFFFF)) {
4126         case E1000_VF_SET_MAC_ADDR:
4127                 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4128                 break;
4129         case E1000_VF_SET_MULTICAST:
4130                 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4131                 break;
4132         case E1000_VF_SET_LPE:
4133                 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4134                 break;
4135         case E1000_VF_SET_VLAN:
4136                 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4137                 break;
4138         default:
4139                 dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4140                 retval = -1;
4141                 break;
4142         }
4143
4144         /* notify the VF of the results of what it sent us */
4145         if (retval)
4146                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4147         else
4148                 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4149
4150         msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4151
4152         igb_write_mbx(hw, msgbuf, 1, vf);
4153
4154         return retval;
4155 }
4156
4157 /**
4158  * igb_intr_msi - Interrupt Handler
4159  * @irq: interrupt number
4160  * @data: pointer to a network interface device structure
4161  **/
4162 static irqreturn_t igb_intr_msi(int irq, void *data)
4163 {
4164         struct net_device *netdev = data;
4165         struct igb_adapter *adapter = netdev_priv(netdev);
4166         struct e1000_hw *hw = &adapter->hw;
4167         /* read ICR disables interrupts using IAM */
4168         u32 icr = rd32(E1000_ICR);
4169
4170         igb_write_itr(adapter->rx_ring);
4171
4172         if(icr & E1000_ICR_DOUTSYNC) {
4173                 /* HW is reporting DMA is out of sync */
4174                 adapter->stats.doosync++;
4175         }
4176
4177         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4178                 hw->mac.get_link_status = 1;
4179                 if (!test_bit(__IGB_DOWN, &adapter->state))
4180                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
4181         }
4182
4183         napi_schedule(&adapter->rx_ring[0].napi);
4184
4185         return IRQ_HANDLED;
4186 }
4187
4188 /**
4189  * igb_intr - Legacy Interrupt Handler
4190  * @irq: interrupt number
4191  * @data: pointer to a network interface device structure
4192  **/
4193 static irqreturn_t igb_intr(int irq, void *data)
4194 {
4195         struct net_device *netdev = data;
4196         struct igb_adapter *adapter = netdev_priv(netdev);
4197         struct e1000_hw *hw = &adapter->hw;
4198         /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
4199          * need for the IMC write */
4200         u32 icr = rd32(E1000_ICR);
4201         if (!icr)
4202                 return IRQ_NONE;  /* Not our interrupt */
4203
4204         igb_write_itr(adapter->rx_ring);
4205
4206         /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4207          * not set, then the adapter didn't send an interrupt */
4208         if (!(icr & E1000_ICR_INT_ASSERTED))
4209                 return IRQ_NONE;
4210
4211         if(icr & E1000_ICR_DOUTSYNC) {
4212                 /* HW is reporting DMA is out of sync */
4213                 adapter->stats.doosync++;
4214         }
4215
4216         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4217                 hw->mac.get_link_status = 1;
4218                 /* guard against interrupt when we're going down */
4219                 if (!test_bit(__IGB_DOWN, &adapter->state))
4220                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
4221         }
4222
4223         napi_schedule(&adapter->rx_ring[0].napi);
4224
4225         return IRQ_HANDLED;
4226 }
4227
4228 static inline void igb_rx_irq_enable(struct igb_ring *rx_ring)
4229 {
4230         struct igb_adapter *adapter = rx_ring->adapter;
4231         struct e1000_hw *hw = &adapter->hw;
4232
4233         if (adapter->itr_setting & 3) {
4234                 if (adapter->num_rx_queues == 1)
4235                         igb_set_itr(adapter);
4236                 else
4237                         igb_update_ring_itr(rx_ring);
4238         }
4239
4240         if (!test_bit(__IGB_DOWN, &adapter->state)) {
4241                 if (adapter->msix_entries)
4242                         wr32(E1000_EIMS, rx_ring->eims_value);
4243                 else
4244                         igb_irq_enable(adapter);
4245         }
4246 }
4247
4248 /**
4249  * igb_poll - NAPI Rx polling callback
4250  * @napi: napi polling structure
4251  * @budget: count of how many packets we should handle
4252  **/
4253 static int igb_poll(struct napi_struct *napi, int budget)
4254 {
4255         struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
4256         int work_done = 0;
4257
4258 #ifdef CONFIG_IGB_DCA
4259         if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
4260                 igb_update_rx_dca(rx_ring);
4261 #endif
4262         igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
4263
4264         if (rx_ring->buddy) {
4265 #ifdef CONFIG_IGB_DCA
4266                 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
4267                         igb_update_tx_dca(rx_ring->buddy);
4268 #endif
4269                 if (!igb_clean_tx_irq(rx_ring->buddy))
4270                         work_done = budget;
4271         }
4272
4273         /* If not enough Rx work done, exit the polling mode */
4274         if (work_done < budget) {
4275                 napi_complete(napi);
4276                 igb_rx_irq_enable(rx_ring);
4277         }
4278
4279         return work_done;
4280 }
4281
4282 /**
4283  * igb_hwtstamp - utility function which checks for TX time stamp
4284  * @adapter: board private structure
4285  * @skb: packet that was just sent
4286  *
4287  * If we were asked to do hardware stamping and such a time stamp is
4288  * available, then it must have been for this skb here because we only
4289  * allow only one such packet into the queue.
4290  */
4291 static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
4292 {
4293         union skb_shared_tx *shtx = skb_tx(skb);
4294         struct e1000_hw *hw = &adapter->hw;
4295
4296         if (unlikely(shtx->hardware)) {
4297                 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
4298                 if (valid) {
4299                         u64 regval = rd32(E1000_TXSTMPL);
4300                         u64 ns;
4301                         struct skb_shared_hwtstamps shhwtstamps;
4302
4303                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
4304                         regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4305                         ns = timecounter_cyc2time(&adapter->clock,
4306                                                   regval);
4307                         timecompare_update(&adapter->compare, ns);
4308                         shhwtstamps.hwtstamp = ns_to_ktime(ns);
4309                         shhwtstamps.syststamp =
4310                                 timecompare_transform(&adapter->compare, ns);
4311                         skb_tstamp_tx(skb, &shhwtstamps);
4312                 }
4313         }
4314 }
4315
4316 /**
4317  * igb_clean_tx_irq - Reclaim resources after transmit completes
4318  * @adapter: board private structure
4319  * returns true if ring is completely cleaned
4320  **/
4321 static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
4322 {
4323         struct igb_adapter *adapter = tx_ring->adapter;
4324         struct net_device *netdev = adapter->netdev;
4325         struct e1000_hw *hw = &adapter->hw;
4326         struct igb_buffer *buffer_info;
4327         struct sk_buff *skb;
4328         union e1000_adv_tx_desc *tx_desc, *eop_desc;
4329         unsigned int total_bytes = 0, total_packets = 0;
4330         unsigned int i, eop, count = 0;
4331         bool cleaned = false;
4332
4333         i = tx_ring->next_to_clean;
4334         eop = tx_ring->buffer_info[i].next_to_watch;
4335         eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4336
4337         while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4338                (count < tx_ring->count)) {
4339                 for (cleaned = false; !cleaned; count++) {
4340                         tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
4341                         buffer_info = &tx_ring->buffer_info[i];
4342                         cleaned = (i == eop);
4343                         skb = buffer_info->skb;
4344
4345                         if (skb) {
4346                                 unsigned int segs, bytecount;
4347                                 /* gso_segs is currently only valid for tcp */
4348                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
4349                                 /* multiply data chunks by size of headers */
4350                                 bytecount = ((segs - 1) * skb_headlen(skb)) +
4351                                             skb->len;
4352                                 total_packets += segs;
4353                                 total_bytes += bytecount;
4354
4355                                 igb_tx_hwtstamp(adapter, skb);
4356                         }
4357
4358                         igb_unmap_and_free_tx_resource(adapter, buffer_info);
4359                         tx_desc->wb.status = 0;
4360
4361                         i++;
4362                         if (i == tx_ring->count)
4363                                 i = 0;
4364                 }
4365                 eop = tx_ring->buffer_info[i].next_to_watch;
4366                 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4367         }
4368
4369         tx_ring->next_to_clean = i;
4370
4371         if (unlikely(count &&
4372                      netif_carrier_ok(netdev) &&
4373                      igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
4374                 /* Make sure that anybody stopping the queue after this
4375                  * sees the new next_to_clean.
4376                  */
4377                 smp_mb();
4378                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
4379                     !(test_bit(__IGB_DOWN, &adapter->state))) {
4380                         netif_wake_subqueue(netdev, tx_ring->queue_index);
4381                         ++adapter->restart_queue;
4382                 }
4383         }
4384
4385         if (tx_ring->detect_tx_hung) {
4386                 /* Detect a transmit hang in hardware, this serializes the
4387                  * check with the clearing of time_stamp and movement of i */
4388                 tx_ring->detect_tx_hung = false;
4389                 if (tx_ring->buffer_info[i].time_stamp &&
4390                     time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
4391                                (adapter->tx_timeout_factor * HZ))
4392                     && !(rd32(E1000_STATUS) &
4393                          E1000_STATUS_TXOFF)) {
4394
4395                         /* detected Tx unit hang */
4396                         dev_err(&adapter->pdev->dev,
4397                                 "Detected Tx Unit Hang\n"
4398                                 "  Tx Queue             <%d>\n"
4399                                 "  TDH                  <%x>\n"
4400                                 "  TDT                  <%x>\n"
4401                                 "  next_to_use          <%x>\n"
4402                                 "  next_to_clean        <%x>\n"
4403                                 "buffer_info[next_to_clean]\n"
4404                                 "  time_stamp           <%lx>\n"
4405                                 "  next_to_watch        <%x>\n"
4406                                 "  jiffies              <%lx>\n"
4407                                 "  desc.status          <%x>\n",
4408                                 tx_ring->queue_index,
4409                                 readl(adapter->hw.hw_addr + tx_ring->head),
4410                                 readl(adapter->hw.hw_addr + tx_ring->tail),
4411                                 tx_ring->next_to_use,
4412                                 tx_ring->next_to_clean,
4413                                 tx_ring->buffer_info[i].time_stamp,
4414                                 eop,
4415                                 jiffies,
4416                                 eop_desc->wb.status);
4417                         netif_stop_subqueue(netdev, tx_ring->queue_index);
4418                 }
4419         }
4420         tx_ring->total_bytes += total_bytes;
4421         tx_ring->total_packets += total_packets;
4422         tx_ring->tx_stats.bytes += total_bytes;
4423         tx_ring->tx_stats.packets += total_packets;
4424         adapter->net_stats.tx_bytes += total_bytes;
4425         adapter->net_stats.tx_packets += total_packets;
4426         return (count < tx_ring->count);
4427 }
4428
4429 /**
4430  * igb_receive_skb - helper function to handle rx indications
4431  * @ring: pointer to receive ring receving this packet
4432  * @status: descriptor status field as written by hardware
4433  * @rx_desc: receive descriptor containing vlan and type information.
4434  * @skb: pointer to sk_buff to be indicated to stack
4435  **/
4436 static void igb_receive_skb(struct igb_ring *ring, u8 status,
4437                             union e1000_adv_rx_desc * rx_desc,
4438                             struct sk_buff *skb)
4439 {
4440         struct igb_adapter * adapter = ring->adapter;
4441         bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
4442
4443         skb_record_rx_queue(skb, ring->queue_index);
4444         if (vlan_extracted)
4445                 vlan_gro_receive(&ring->napi, adapter->vlgrp,
4446                                  le16_to_cpu(rx_desc->wb.upper.vlan),
4447                                  skb);
4448         else
4449                 napi_gro_receive(&ring->napi, skb);
4450 }
4451
4452 static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
4453                                        u32 status_err, struct sk_buff *skb)
4454 {
4455         skb->ip_summed = CHECKSUM_NONE;
4456
4457         /* Ignore Checksum bit is set or checksum is disabled through ethtool */
4458         if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
4459                 return;
4460         /* TCP/UDP checksum error bit is set */
4461         if (status_err &
4462             (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
4463                 /*
4464                  * work around errata with sctp packets where the TCPE aka
4465                  * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
4466                  * packets, (aka let the stack check the crc32c)
4467                  */
4468                 if (!((adapter->hw.mac.type == e1000_82576) &&
4469                       (skb->len == 60)))
4470                         adapter->hw_csum_err++;
4471                 /* let the stack verify checksum errors */
4472                 return;
4473         }
4474         /* It must be a TCP or UDP packet with a valid checksum */
4475         if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
4476                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4477
4478         dev_dbg(&adapter->pdev->dev, "cksum success: bits %08X\n", status_err);
4479         adapter->hw_csum_good++;
4480 }
4481
4482 static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
4483                                  int *work_done, int budget)
4484 {
4485         struct igb_adapter *adapter = rx_ring->adapter;
4486         struct net_device *netdev = adapter->netdev;
4487         struct e1000_hw *hw = &adapter->hw;
4488         struct pci_dev *pdev = adapter->pdev;
4489         union e1000_adv_rx_desc *rx_desc , *next_rxd;
4490         struct igb_buffer *buffer_info , *next_buffer;
4491         struct sk_buff *skb;
4492         bool cleaned = false;
4493         int cleaned_count = 0;
4494         unsigned int total_bytes = 0, total_packets = 0;
4495         unsigned int i;
4496         u32 length, hlen, staterr;
4497
4498         i = rx_ring->next_to_clean;
4499         buffer_info = &rx_ring->buffer_info[i];
4500         rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4501         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4502
4503         while (staterr & E1000_RXD_STAT_DD) {
4504                 if (*work_done >= budget)
4505                         break;
4506                 (*work_done)++;
4507
4508                 skb = buffer_info->skb;
4509                 prefetch(skb->data - NET_IP_ALIGN);
4510                 buffer_info->skb = NULL;
4511
4512                 i++;
4513                 if (i == rx_ring->count)
4514                         i = 0;
4515                 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4516                 prefetch(next_rxd);
4517                 next_buffer = &rx_ring->buffer_info[i];
4518
4519                 length = le16_to_cpu(rx_desc->wb.upper.length);
4520                 cleaned = true;
4521                 cleaned_count++;
4522
4523                 if (!adapter->rx_ps_hdr_size) {
4524                         pci_unmap_single(pdev, buffer_info->dma,
4525                                          adapter->rx_buffer_len +
4526                                            NET_IP_ALIGN,
4527                                          PCI_DMA_FROMDEVICE);
4528                         skb_put(skb, length);
4529                         goto send_up;
4530                 }
4531
4532                 /* HW will not DMA in data larger than the given buffer, even
4533                  * if it parses the (NFS, of course) header to be larger.  In
4534                  * that case, it fills the header buffer and spills the rest
4535                  * into the page.
4536                  */
4537                 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4538                   E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4539                 if (hlen > adapter->rx_ps_hdr_size)
4540                         hlen = adapter->rx_ps_hdr_size;
4541
4542                 if (!skb_shinfo(skb)->nr_frags) {
4543                         pci_unmap_single(pdev, buffer_info->dma,
4544                                          adapter->rx_ps_hdr_size + NET_IP_ALIGN,
4545                                          PCI_DMA_FROMDEVICE);
4546                         skb_put(skb, hlen);
4547                 }
4548
4549                 if (length) {
4550                         pci_unmap_page(pdev, buffer_info->page_dma,
4551                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
4552                         buffer_info->page_dma = 0;
4553
4554                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4555                                                 buffer_info->page,
4556                                                 buffer_info->page_offset,
4557                                                 length);
4558
4559                         if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
4560                             (page_count(buffer_info->page) != 1))
4561                                 buffer_info->page = NULL;
4562                         else
4563                                 get_page(buffer_info->page);
4564
4565                         skb->len += length;
4566                         skb->data_len += length;
4567
4568                         skb->truesize += length;
4569                 }
4570
4571                 if (!(staterr & E1000_RXD_STAT_EOP)) {
4572                         buffer_info->skb = next_buffer->skb;
4573                         buffer_info->dma = next_buffer->dma;
4574                         next_buffer->skb = skb;
4575                         next_buffer->dma = 0;
4576                         goto next_desc;
4577                 }
4578 send_up:
4579                 /*
4580                  * If this bit is set, then the RX registers contain
4581                  * the time stamp. No other packet will be time
4582                  * stamped until we read these registers, so read the
4583                  * registers to make them available again. Because
4584                  * only one packet can be time stamped at a time, we
4585                  * know that the register values must belong to this
4586                  * one here and therefore we don't need to compare
4587                  * any of the additional attributes stored for it.
4588                  *
4589                  * If nothing went wrong, then it should have a
4590                  * skb_shared_tx that we can turn into a
4591                  * skb_shared_hwtstamps.
4592                  *
4593                  * TODO: can time stamping be triggered (thus locking
4594                  * the registers) without the packet reaching this point
4595                  * here? In that case RX time stamping would get stuck.
4596                  *
4597                  * TODO: in "time stamp all packets" mode this bit is
4598                  * not set. Need a global flag for this mode and then
4599                  * always read the registers. Cannot be done without
4600                  * a race condition.
4601                  */
4602                 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4603                         u64 regval;
4604                         u64 ns;
4605                         struct skb_shared_hwtstamps *shhwtstamps =
4606                                 skb_hwtstamps(skb);
4607
4608                         WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4609                              "igb: no RX time stamp available for time stamped packet");
4610                         regval = rd32(E1000_RXSTMPL);
4611                         regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4612                         ns = timecounter_cyc2time(&adapter->clock, regval);
4613                         timecompare_update(&adapter->compare, ns);
4614                         memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4615                         shhwtstamps->hwtstamp = ns_to_ktime(ns);
4616                         shhwtstamps->syststamp =
4617                                 timecompare_transform(&adapter->compare, ns);
4618                 }
4619
4620                 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4621                         dev_kfree_skb_irq(skb);
4622                         goto next_desc;
4623                 }
4624
4625                 total_bytes += skb->len;
4626                 total_packets++;
4627
4628                 igb_rx_checksum_adv(adapter, staterr, skb);
4629
4630                 skb->protocol = eth_type_trans(skb, netdev);
4631
4632                 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
4633
4634 next_desc:
4635                 rx_desc->wb.upper.status_error = 0;
4636
4637                 /* return some buffers to hardware, one at a time is too slow */
4638                 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
4639                         igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4640                         cleaned_count = 0;
4641                 }
4642
4643                 /* use prefetched values */
4644                 rx_desc = next_rxd;
4645                 buffer_info = next_buffer;
4646                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4647         }
4648
4649         rx_ring->next_to_clean = i;
4650         cleaned_count = igb_desc_unused(rx_ring);
4651
4652         if (cleaned_count)
4653                 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4654
4655         rx_ring->total_packets += total_packets;
4656         rx_ring->total_bytes += total_bytes;
4657         rx_ring->rx_stats.packets += total_packets;
4658         rx_ring->rx_stats.bytes += total_bytes;
4659         adapter->net_stats.rx_bytes += total_bytes;
4660         adapter->net_stats.rx_packets += total_packets;
4661         return cleaned;
4662 }
4663
4664 /**
4665  * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
4666  * @adapter: address of board private structure
4667  **/
4668 static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
4669                                      int cleaned_count)
4670 {
4671         struct igb_adapter *adapter = rx_ring->adapter;
4672         struct net_device *netdev = adapter->netdev;
4673         struct pci_dev *pdev = adapter->pdev;
4674         union e1000_adv_rx_desc *rx_desc;
4675         struct igb_buffer *buffer_info;
4676         struct sk_buff *skb;
4677         unsigned int i;
4678         int bufsz;
4679
4680         i = rx_ring->next_to_use;
4681         buffer_info = &rx_ring->buffer_info[i];
4682
4683         if (adapter->rx_ps_hdr_size)
4684                 bufsz = adapter->rx_ps_hdr_size;
4685         else
4686                 bufsz = adapter->rx_buffer_len;
4687         bufsz += NET_IP_ALIGN;
4688
4689         while (cleaned_count--) {
4690                 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4691
4692                 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
4693                         if (!buffer_info->page) {
4694                                 buffer_info->page = alloc_page(GFP_ATOMIC);
4695                                 if (!buffer_info->page) {
4696                                         adapter->alloc_rx_buff_failed++;
4697                                         goto no_buffers;
4698                                 }
4699                                 buffer_info->page_offset = 0;
4700                         } else {
4701                                 buffer_info->page_offset ^= PAGE_SIZE / 2;
4702                         }
4703                         buffer_info->page_dma =
4704                                 pci_map_page(pdev, buffer_info->page,
4705                                              buffer_info->page_offset,
4706                                              PAGE_SIZE / 2,
4707                                              PCI_DMA_FROMDEVICE);
4708                 }
4709
4710                 if (!buffer_info->skb) {
4711                         skb = netdev_alloc_skb(netdev, bufsz);
4712                         if (!skb) {
4713                                 adapter->alloc_rx_buff_failed++;
4714                                 goto no_buffers;
4715                         }
4716
4717                         /* Make buffer alignment 2 beyond a 16 byte boundary
4718                          * this will result in a 16 byte aligned IP header after
4719                          * the 14 byte MAC header is removed
4720                          */
4721                         skb_reserve(skb, NET_IP_ALIGN);
4722
4723                         buffer_info->skb = skb;
4724                         buffer_info->dma = pci_map_single(pdev, skb->data,
4725                                                           bufsz,
4726                                                           PCI_DMA_FROMDEVICE);
4727                 }
4728                 /* Refresh the desc even if buffer_addrs didn't change because
4729                  * each write-back erases this info. */
4730                 if (adapter->rx_ps_hdr_size) {
4731                         rx_desc->read.pkt_addr =
4732                              cpu_to_le64(buffer_info->page_dma);
4733                         rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4734                 } else {
4735                         rx_desc->read.pkt_addr =
4736                              cpu_to_le64(buffer_info->dma);
4737                         rx_desc->read.hdr_addr = 0;
4738                 }
4739
4740                 i++;
4741                 if (i == rx_ring->count)
4742                         i = 0;
4743                 buffer_info = &rx_ring->buffer_info[i];
4744         }
4745
4746 no_buffers:
4747         if (rx_ring->next_to_use != i) {
4748                 rx_ring->next_to_use = i;
4749                 if (i == 0)
4750                         i = (rx_ring->count - 1);
4751                 else
4752                         i--;
4753
4754                 /* Force memory writes to complete before letting h/w
4755                  * know there are new descriptors to fetch.  (Only
4756                  * applicable for weak-ordered memory model archs,
4757                  * such as IA-64). */
4758                 wmb();
4759                 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4760         }
4761 }
4762
4763 /**
4764  * igb_mii_ioctl -
4765  * @netdev:
4766  * @ifreq:
4767  * @cmd:
4768  **/
4769 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4770 {
4771         struct igb_adapter *adapter = netdev_priv(netdev);
4772         struct mii_ioctl_data *data = if_mii(ifr);
4773
4774         if (adapter->hw.phy.media_type != e1000_media_type_copper)
4775                 return -EOPNOTSUPP;
4776
4777         switch (cmd) {
4778         case SIOCGMIIPHY:
4779                 data->phy_id = adapter->hw.phy.addr;
4780                 break;
4781         case SIOCGMIIREG:
4782                 if (!capable(CAP_NET_ADMIN))
4783                         return -EPERM;
4784                 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4785                                      &data->val_out))
4786                         return -EIO;
4787                 break;
4788         case SIOCSMIIREG:
4789         default:
4790                 return -EOPNOTSUPP;
4791         }
4792         return 0;
4793 }
4794
4795 /**
4796  * igb_hwtstamp_ioctl - control hardware time stamping
4797  * @netdev:
4798  * @ifreq:
4799  * @cmd:
4800  *
4801  * Outgoing time stamping can be enabled and disabled. Play nice and
4802  * disable it when requested, although it shouldn't case any overhead
4803  * when no packet needs it. At most one packet in the queue may be
4804  * marked for time stamping, otherwise it would be impossible to tell
4805  * for sure to which packet the hardware time stamp belongs.
4806  *
4807  * Incoming time stamping has to be configured via the hardware
4808  * filters. Not all combinations are supported, in particular event
4809  * type has to be specified. Matching the kind of event packet is
4810  * not supported, with the exception of "all V2 events regardless of
4811  * level 2 or 4".
4812  *
4813  **/
4814 static int igb_hwtstamp_ioctl(struct net_device *netdev,
4815                               struct ifreq *ifr, int cmd)
4816 {
4817         struct igb_adapter *adapter = netdev_priv(netdev);
4818         struct e1000_hw *hw = &adapter->hw;
4819         struct hwtstamp_config config;
4820         u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4821         u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
4822         u32 tsync_rx_ctl_type = 0;
4823         u32 tsync_rx_cfg = 0;
4824         int is_l4 = 0;
4825         int is_l2 = 0;
4826         short port = 319; /* PTP */
4827         u32 regval;
4828
4829         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4830                 return -EFAULT;
4831
4832         /* reserved for future extensions */
4833         if (config.flags)
4834                 return -EINVAL;
4835
4836         switch (config.tx_type) {
4837         case HWTSTAMP_TX_OFF:
4838                 tsync_tx_ctl_bit = 0;
4839                 break;
4840         case HWTSTAMP_TX_ON:
4841                 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4842                 break;
4843         default:
4844                 return -ERANGE;
4845         }
4846
4847         switch (config.rx_filter) {
4848         case HWTSTAMP_FILTER_NONE:
4849                 tsync_rx_ctl_bit = 0;
4850                 break;
4851         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4852         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4853         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4854         case HWTSTAMP_FILTER_ALL:
4855                 /*
4856                  * register TSYNCRXCFG must be set, therefore it is not
4857                  * possible to time stamp both Sync and Delay_Req messages
4858                  * => fall back to time stamping all packets
4859                  */
4860                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
4861                 config.rx_filter = HWTSTAMP_FILTER_ALL;
4862                 break;
4863         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4864                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4865                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
4866                 is_l4 = 1;
4867                 break;
4868         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4869                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4870                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
4871                 is_l4 = 1;
4872                 break;
4873         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4874         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4875                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4876                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
4877                 is_l2 = 1;
4878                 is_l4 = 1;
4879                 config.rx_filter = HWTSTAMP_FILTER_SOME;
4880                 break;
4881         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4882         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4883                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4884                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
4885                 is_l2 = 1;
4886                 is_l4 = 1;
4887                 config.rx_filter = HWTSTAMP_FILTER_SOME;
4888                 break;
4889         case HWTSTAMP_FILTER_PTP_V2_EVENT:
4890         case HWTSTAMP_FILTER_PTP_V2_SYNC:
4891         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4892                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
4893                 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
4894                 is_l2 = 1;
4895                 break;
4896         default:
4897                 return -ERANGE;
4898         }
4899
4900         /* enable/disable TX */
4901         regval = rd32(E1000_TSYNCTXCTL);
4902         regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
4903         wr32(E1000_TSYNCTXCTL, regval);
4904
4905         /* enable/disable RX, define which PTP packets are time stamped */
4906         regval = rd32(E1000_TSYNCRXCTL);
4907         regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
4908         regval = (regval & ~0xE) | tsync_rx_ctl_type;
4909         wr32(E1000_TSYNCRXCTL, regval);
4910         wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
4911
4912         /*
4913          * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
4914          *                                          (Ethertype to filter on)
4915          * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
4916          * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
4917          */
4918         wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
4919
4920         /* L4 Queue Filter[0]: only filter by source and destination port */
4921         wr32(E1000_SPQF0, htons(port));
4922         wr32(E1000_IMIREXT(0), is_l4 ?
4923              ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
4924         wr32(E1000_IMIR(0), is_l4 ?
4925              (htons(port)
4926               | (0<<16) /* immediate interrupt disabled */
4927               | 0 /* (1<<17) bit cleared: do not bypass
4928                      destination port check */)
4929                 : 0);
4930         wr32(E1000_FTQF0, is_l4 ?
4931              (0x11 /* UDP */
4932               | (1<<15) /* VF not compared */
4933               | (1<<27) /* Enable Timestamping */
4934               | (7<<28) /* only source port filter enabled,
4935                            source/target address and protocol
4936                            masked */)
4937              : ((1<<15) | (15<<28) /* all mask bits set = filter not
4938                                       enabled */));
4939
4940         wrfl();
4941
4942         adapter->hwtstamp_config = config;
4943
4944         /* clear TX/RX time stamp registers, just to be sure */
4945         regval = rd32(E1000_TXSTMPH);
4946         regval = rd32(E1000_RXSTMPH);
4947
4948         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
4949                 -EFAULT : 0;
4950 }
4951
4952 /**
4953  * igb_ioctl -
4954  * @netdev:
4955  * @ifreq:
4956  * @cmd:
4957  **/
4958 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4959 {
4960         switch (cmd) {
4961         case SIOCGMIIPHY:
4962         case SIOCGMIIREG:
4963         case SIOCSMIIREG:
4964                 return igb_mii_ioctl(netdev, ifr, cmd);
4965         case SIOCSHWTSTAMP:
4966                 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
4967         default:
4968                 return -EOPNOTSUPP;
4969         }
4970 }
4971
4972 static void igb_vlan_rx_register(struct net_device *netdev,
4973                                  struct vlan_group *grp)
4974 {
4975         struct igb_adapter *adapter = netdev_priv(netdev);
4976         struct e1000_hw *hw = &adapter->hw;
4977         u32 ctrl, rctl;
4978
4979         igb_irq_disable(adapter);
4980         adapter->vlgrp = grp;
4981
4982         if (grp) {
4983                 /* enable VLAN tag insert/strip */
4984                 ctrl = rd32(E1000_CTRL);
4985                 ctrl |= E1000_CTRL_VME;
4986                 wr32(E1000_CTRL, ctrl);
4987
4988                 /* enable VLAN receive filtering */
4989                 rctl = rd32(E1000_RCTL);
4990                 rctl &= ~E1000_RCTL_CFIEN;
4991                 wr32(E1000_RCTL, rctl);
4992                 igb_update_mng_vlan(adapter);
4993         } else {
4994                 /* disable VLAN tag insert/strip */
4995                 ctrl = rd32(E1000_CTRL);
4996                 ctrl &= ~E1000_CTRL_VME;
4997                 wr32(E1000_CTRL, ctrl);
4998
4999                 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
5000                         igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
5001                         adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
5002                 }
5003         }
5004
5005         igb_rlpml_set(adapter);
5006
5007         if (!test_bit(__IGB_DOWN, &adapter->state))
5008                 igb_irq_enable(adapter);
5009 }
5010
5011 static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
5012 {
5013         struct igb_adapter *adapter = netdev_priv(netdev);
5014         struct e1000_hw *hw = &adapter->hw;
5015         int pf_id = adapter->vfs_allocated_count;
5016
5017         if ((hw->mng_cookie.status &
5018              E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5019             (vid == adapter->mng_vlan_id))
5020                 return;
5021
5022         /* add vid to vlvf if sr-iov is enabled,
5023          * if that fails add directly to filter table */
5024         if (igb_vlvf_set(adapter, vid, true, pf_id))
5025                 igb_vfta_set(hw, vid, true);
5026
5027 }
5028
5029 static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
5030 {
5031         struct igb_adapter *adapter = netdev_priv(netdev);
5032         struct e1000_hw *hw = &adapter->hw;
5033         int pf_id = adapter->vfs_allocated_count;
5034
5035         igb_irq_disable(adapter);
5036         vlan_group_set_device(adapter->vlgrp, vid, NULL);
5037
5038         if (!test_bit(__IGB_DOWN, &adapter->state))
5039                 igb_irq_enable(adapter);
5040
5041         if ((adapter->hw.mng_cookie.status &
5042              E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5043             (vid == adapter->mng_vlan_id)) {
5044                 /* release control to f/w */
5045                 igb_release_hw_control(adapter);
5046                 return;
5047         }
5048
5049         /* remove vid from vlvf if sr-iov is enabled,
5050          * if not in vlvf remove from vfta */
5051         if (igb_vlvf_set(adapter, vid, false, pf_id))
5052                 igb_vfta_set(hw, vid, false);
5053 }
5054
5055 static void igb_restore_vlan(struct igb_adapter *adapter)
5056 {
5057         igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5058
5059         if (adapter->vlgrp) {
5060                 u16 vid;
5061                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5062                         if (!vlan_group_get_device(adapter->vlgrp, vid))
5063                                 continue;
5064                         igb_vlan_rx_add_vid(adapter->netdev, vid);
5065                 }
5066         }
5067 }
5068
5069 int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5070 {
5071         struct e1000_mac_info *mac = &adapter->hw.mac;
5072
5073         mac->autoneg = 0;
5074
5075         /* Fiber NICs only allow 1000 gbps Full duplex */
5076         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
5077                 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
5078                 dev_err(&adapter->pdev->dev,
5079                         "Unsupported Speed/Duplex configuration\n");
5080                 return -EINVAL;
5081         }
5082
5083         switch (spddplx) {
5084         case SPEED_10 + DUPLEX_HALF:
5085                 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5086                 break;
5087         case SPEED_10 + DUPLEX_FULL:
5088                 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5089                 break;
5090         case SPEED_100 + DUPLEX_HALF:
5091                 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5092                 break;
5093         case SPEED_100 + DUPLEX_FULL:
5094                 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5095                 break;
5096         case SPEED_1000 + DUPLEX_FULL:
5097                 mac->autoneg = 1;
5098                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5099                 break;
5100         case SPEED_1000 + DUPLEX_HALF: /* not supported */
5101         default:
5102                 dev_err(&adapter->pdev->dev,
5103                         "Unsupported Speed/Duplex configuration\n");
5104                 return -EINVAL;
5105         }
5106         return 0;
5107 }
5108
5109 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
5110 {
5111         struct net_device *netdev = pci_get_drvdata(pdev);
5112         struct igb_adapter *adapter = netdev_priv(netdev);
5113         struct e1000_hw *hw = &adapter->hw;
5114         u32 ctrl, rctl, status;
5115         u32 wufc = adapter->wol;
5116 #ifdef CONFIG_PM
5117         int retval = 0;
5118 #endif
5119
5120         netif_device_detach(netdev);
5121
5122         if (netif_running(netdev))
5123                 igb_close(netdev);
5124
5125         igb_reset_interrupt_capability(adapter);
5126
5127         igb_free_queues(adapter);
5128
5129 #ifdef CONFIG_PM
5130         retval = pci_save_state(pdev);
5131         if (retval)
5132                 return retval;
5133 #endif
5134
5135         status = rd32(E1000_STATUS);
5136         if (status & E1000_STATUS_LU)
5137                 wufc &= ~E1000_WUFC_LNKC;
5138
5139         if (wufc) {
5140                 igb_setup_rctl(adapter);
5141                 igb_set_multi(netdev);
5142
5143                 /* turn on all-multi mode if wake on multicast is enabled */
5144                 if (wufc & E1000_WUFC_MC) {
5145                         rctl = rd32(E1000_RCTL);
5146                         rctl |= E1000_RCTL_MPE;
5147                         wr32(E1000_RCTL, rctl);
5148                 }
5149
5150                 ctrl = rd32(E1000_CTRL);
5151                 /* advertise wake from D3Cold */
5152                 #define E1000_CTRL_ADVD3WUC 0x00100000
5153                 /* phy power management enable */
5154                 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5155                 ctrl |= E1000_CTRL_ADVD3WUC;
5156                 wr32(E1000_CTRL, ctrl);
5157
5158                 /* Allow time for pending master requests to run */
5159                 igb_disable_pcie_master(&adapter->hw);
5160
5161                 wr32(E1000_WUC, E1000_WUC_PME_EN);
5162                 wr32(E1000_WUFC, wufc);
5163         } else {
5164                 wr32(E1000_WUC, 0);
5165                 wr32(E1000_WUFC, 0);
5166         }
5167
5168         *enable_wake = wufc || adapter->en_mng_pt;
5169         if (!*enable_wake)
5170                 igb_shutdown_fiber_serdes_link_82575(hw);
5171
5172         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
5173          * would have already happened in close and is redundant. */
5174         igb_release_hw_control(adapter);
5175
5176         pci_disable_device(pdev);
5177
5178         return 0;
5179 }
5180
5181 #ifdef CONFIG_PM
5182 static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5183 {
5184         int retval;
5185         bool wake;
5186
5187         retval = __igb_shutdown(pdev, &wake);
5188         if (retval)
5189                 return retval;
5190
5191         if (wake) {
5192                 pci_prepare_to_sleep(pdev);
5193         } else {
5194                 pci_wake_from_d3(pdev, false);
5195                 pci_set_power_state(pdev, PCI_D3hot);
5196         }
5197
5198         return 0;
5199 }
5200
5201 static int igb_resume(struct pci_dev *pdev)
5202 {
5203         struct net_device *netdev = pci_get_drvdata(pdev);
5204         struct igb_adapter *adapter = netdev_priv(netdev);
5205         struct e1000_hw *hw = &adapter->hw;
5206         u32 err;
5207
5208         pci_set_power_state(pdev, PCI_D0);
5209         pci_restore_state(pdev);
5210
5211         err = pci_enable_device_mem(pdev);
5212         if (err) {
5213                 dev_err(&pdev->dev,
5214                         "igb: Cannot enable PCI device from suspend\n");
5215                 return err;
5216         }
5217         pci_set_master(pdev);
5218
5219         pci_enable_wake(pdev, PCI_D3hot, 0);
5220         pci_enable_wake(pdev, PCI_D3cold, 0);
5221
5222         igb_set_interrupt_capability(adapter);
5223
5224         if (igb_alloc_queues(adapter)) {
5225                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5226                 return -ENOMEM;
5227         }
5228
5229         /* e1000_power_up_phy(adapter); */
5230
5231         igb_reset(adapter);
5232
5233         /* let the f/w know that the h/w is now under the control of the
5234          * driver. */
5235         igb_get_hw_control(adapter);
5236
5237         wr32(E1000_WUS, ~0);
5238
5239         if (netif_running(netdev)) {
5240                 err = igb_open(netdev);
5241                 if (err)
5242                         return err;
5243         }
5244
5245         netif_device_attach(netdev);
5246
5247         return 0;
5248 }
5249 #endif
5250
5251 static void igb_shutdown(struct pci_dev *pdev)
5252 {
5253         bool wake;
5254
5255         __igb_shutdown(pdev, &wake);
5256
5257         if (system_state == SYSTEM_POWER_OFF) {
5258                 pci_wake_from_d3(pdev, wake);
5259                 pci_set_power_state(pdev, PCI_D3hot);
5260         }
5261 }
5262
5263 #ifdef CONFIG_NET_POLL_CONTROLLER
5264 /*
5265  * Polling 'interrupt' - used by things like netconsole to send skbs
5266  * without having to re-enable interrupts. It's not called while
5267  * the interrupt routine is executing.
5268  */
5269 static void igb_netpoll(struct net_device *netdev)
5270 {
5271         struct igb_adapter *adapter = netdev_priv(netdev);
5272         struct e1000_hw *hw = &adapter->hw;
5273         int i;
5274
5275         if (!adapter->msix_entries) {
5276                 igb_irq_disable(adapter);
5277                 napi_schedule(&adapter->rx_ring[0].napi);
5278                 return;
5279         }
5280
5281         for (i = 0; i < adapter->num_tx_queues; i++) {
5282                 struct igb_ring *tx_ring = &adapter->tx_ring[i];
5283                 wr32(E1000_EIMC, tx_ring->eims_value);
5284                 igb_clean_tx_irq(tx_ring);
5285                 wr32(E1000_EIMS, tx_ring->eims_value);
5286         }
5287
5288         for (i = 0; i < adapter->num_rx_queues; i++) {
5289                 struct igb_ring *rx_ring = &adapter->rx_ring[i];
5290                 wr32(E1000_EIMC, rx_ring->eims_value);
5291                 napi_schedule(&rx_ring->napi);
5292         }
5293 }
5294 #endif /* CONFIG_NET_POLL_CONTROLLER */
5295
5296 /**
5297  * igb_io_error_detected - called when PCI error is detected
5298  * @pdev: Pointer to PCI device
5299  * @state: The current pci connection state
5300  *
5301  * This function is called after a PCI bus error affecting
5302  * this device has been detected.
5303  */
5304 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5305                                               pci_channel_state_t state)
5306 {
5307         struct net_device *netdev = pci_get_drvdata(pdev);
5308         struct igb_adapter *adapter = netdev_priv(netdev);
5309
5310         netif_device_detach(netdev);
5311
5312         if (netif_running(netdev))
5313                 igb_down(adapter);
5314         pci_disable_device(pdev);
5315
5316         /* Request a slot slot reset. */
5317         return PCI_ERS_RESULT_NEED_RESET;
5318 }
5319
5320 /**
5321  * igb_io_slot_reset - called after the pci bus has been reset.
5322  * @pdev: Pointer to PCI device
5323  *
5324  * Restart the card from scratch, as if from a cold-boot. Implementation
5325  * resembles the first-half of the igb_resume routine.
5326  */
5327 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5328 {
5329         struct net_device *netdev = pci_get_drvdata(pdev);
5330         struct igb_adapter *adapter = netdev_priv(netdev);
5331         struct e1000_hw *hw = &adapter->hw;
5332         pci_ers_result_t result;
5333         int err;
5334
5335         if (pci_enable_device_mem(pdev)) {
5336                 dev_err(&pdev->dev,
5337                         "Cannot re-enable PCI device after reset.\n");
5338                 result = PCI_ERS_RESULT_DISCONNECT;
5339         } else {
5340                 pci_set_master(pdev);
5341                 pci_restore_state(pdev);
5342
5343                 pci_enable_wake(pdev, PCI_D3hot, 0);
5344                 pci_enable_wake(pdev, PCI_D3cold, 0);
5345
5346                 igb_reset(adapter);
5347                 wr32(E1000_WUS, ~0);
5348                 result = PCI_ERS_RESULT_RECOVERED;
5349         }
5350
5351         err = pci_cleanup_aer_uncorrect_error_status(pdev);
5352         if (err) {
5353                 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
5354                         "failed 0x%0x\n", err);
5355                 /* non-fatal, continue */
5356         }
5357
5358         return result;
5359 }
5360
5361 /**
5362  * igb_io_resume - called when traffic can start flowing again.
5363  * @pdev: Pointer to PCI device
5364  *
5365  * This callback is called when the error recovery driver tells us that
5366  * its OK to resume normal operation. Implementation resembles the
5367  * second-half of the igb_resume routine.
5368  */
5369 static void igb_io_resume(struct pci_dev *pdev)
5370 {
5371         struct net_device *netdev = pci_get_drvdata(pdev);
5372         struct igb_adapter *adapter = netdev_priv(netdev);
5373
5374         if (netif_running(netdev)) {
5375                 if (igb_up(adapter)) {
5376                         dev_err(&pdev->dev, "igb_up failed after reset\n");
5377                         return;
5378                 }
5379         }
5380
5381         netif_device_attach(netdev);
5382
5383         /* let the f/w know that the h/w is now under the control of the
5384          * driver. */
5385         igb_get_hw_control(adapter);
5386 }
5387
5388 static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn)
5389 {
5390         u32 reg_data;
5391
5392         reg_data = rd32(E1000_VMOLR(vfn));
5393         reg_data |= E1000_VMOLR_BAM |    /* Accept broadcast */
5394                     E1000_VMOLR_ROPE |   /* Accept packets matched in UTA */
5395                     E1000_VMOLR_ROMPE |  /* Accept packets matched in MTA */
5396                     E1000_VMOLR_AUPE |   /* Accept untagged packets */
5397                     E1000_VMOLR_STRVLAN; /* Strip vlan tags */
5398         wr32(E1000_VMOLR(vfn), reg_data);
5399 }
5400
5401 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
5402                                  int vfn)
5403 {
5404         struct e1000_hw *hw = &adapter->hw;
5405         u32 vmolr;
5406
5407         vmolr = rd32(E1000_VMOLR(vfn));
5408         vmolr &= ~E1000_VMOLR_RLPML_MASK;
5409         vmolr |= size | E1000_VMOLR_LPE;
5410         wr32(E1000_VMOLR(vfn), vmolr);
5411
5412         return 0;
5413 }
5414
5415 static inline void igb_set_rah_pool(struct e1000_hw *hw, int pool, int entry)
5416 {
5417         u32 reg_data;
5418
5419         reg_data = rd32(E1000_RAH(entry));
5420         reg_data &= ~E1000_RAH_POOL_MASK;
5421         reg_data |= E1000_RAH_POOL_1 << pool;;
5422         wr32(E1000_RAH(entry), reg_data);
5423 }
5424
5425 static void igb_set_mc_list_pools(struct igb_adapter *adapter,
5426                                   int entry_count, u16 total_rar_filters)
5427 {
5428         struct e1000_hw *hw = &adapter->hw;
5429         int i = adapter->vfs_allocated_count + 1;
5430
5431         if ((i + entry_count) < total_rar_filters)
5432                 total_rar_filters = i + entry_count;
5433
5434         for (; i < total_rar_filters; i++)
5435                 igb_set_rah_pool(hw, adapter->vfs_allocated_count, i);
5436 }
5437
5438 static int igb_set_vf_mac(struct igb_adapter *adapter,
5439                           int vf, unsigned char *mac_addr)
5440 {
5441         struct e1000_hw *hw = &adapter->hw;
5442         int rar_entry = vf + 1; /* VF MAC addresses start at entry 1 */
5443
5444         igb_rar_set(hw, mac_addr, rar_entry);
5445
5446         memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
5447
5448         igb_set_rah_pool(hw, vf, rar_entry);
5449
5450         return 0;
5451 }
5452
5453 static void igb_vmm_control(struct igb_adapter *adapter)
5454 {
5455         struct e1000_hw *hw = &adapter->hw;
5456         u32 reg_data;
5457
5458         if (!adapter->vfs_allocated_count)
5459                 return;
5460
5461         /* VF's need PF reset indication before they
5462          * can send/receive mail */
5463         reg_data = rd32(E1000_CTRL_EXT);
5464         reg_data |= E1000_CTRL_EXT_PFRSTD;
5465         wr32(E1000_CTRL_EXT, reg_data);
5466
5467         igb_vmdq_set_loopback_pf(hw, true);
5468         igb_vmdq_set_replication_pf(hw, true);
5469 }
5470
5471 /* igb_main.c */