Merge master.kernel.org:/pub/scm/linux/kernel/git/torvalds/linux-2.6
[linux-2.6] / arch / powerpc / boot / dts / mpc8541cds.dts
1 /*
2  * MPC8541 CDS Device Tree Source
3  *
4  * Copyright 2006 Freescale Semiconductor Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10  */
11
12
13 / {
14         model = "MPC8541CDS";
15         compatible = "MPC8541CDS", "MPC85xxCDS";
16         #address-cells = <1>;
17         #size-cells = <1>;
18
19         cpus {
20                 #address-cells = <1>;
21                 #size-cells = <0>;
22
23                 PowerPC,8541@0 {
24                         device_type = "cpu";
25                         reg = <0>;
26                         d-cache-line-size = <20>;       // 32 bytes
27                         i-cache-line-size = <20>;       // 32 bytes
28                         d-cache-size = <8000>;          // L1, 32K
29                         i-cache-size = <8000>;          // L1, 32K
30                         timebase-frequency = <0>;       //  33 MHz, from uboot
31                         bus-frequency = <0>;    // 166 MHz
32                         clock-frequency = <0>;  // 825 MHz, from uboot
33                 };
34         };
35
36         memory {
37                 device_type = "memory";
38                 reg = <00000000 08000000>;      // 128M at 0x0
39         };
40
41         soc8541@e0000000 {
42                 #address-cells = <1>;
43                 #size-cells = <1>;
44                 device_type = "soc";
45                 ranges = <0 e0000000 00100000>;
46                 reg = <e0000000 00001000>;      // CCSRBAR 1M
47                 bus-frequency = <0>;
48
49                 memory-controller@2000 {
50                         compatible = "fsl,8541-memory-controller";
51                         reg = <2000 1000>;
52                         interrupt-parent = <&mpic>;
53                         interrupts = <12 2>;
54                 };
55
56                 l2-cache-controller@20000 {
57                         compatible = "fsl,8541-l2-cache-controller";
58                         reg = <20000 1000>;
59                         cache-line-size = <20>; // 32 bytes
60                         cache-size = <40000>;   // L2, 256K
61                         interrupt-parent = <&mpic>;
62                         interrupts = <10 2>;
63                 };
64
65                 i2c@3000 {
66                         device_type = "i2c";
67                         compatible = "fsl-i2c";
68                         reg = <3000 100>;
69                         interrupts = <2b 2>;
70                         interrupt-parent = <&mpic>;
71                         dfsrr;
72                 };
73
74                 mdio@24520 {
75                         #address-cells = <1>;
76                         #size-cells = <0>;
77                         device_type = "mdio";
78                         compatible = "gianfar";
79                         reg = <24520 20>;
80                         phy0: ethernet-phy@0 {
81                                 interrupt-parent = <&mpic>;
82                                 interrupts = <5 1>;
83                                 reg = <0>;
84                                 device_type = "ethernet-phy";
85                         };
86                         phy1: ethernet-phy@1 {
87                                 interrupt-parent = <&mpic>;
88                                 interrupts = <5 1>;
89                                 reg = <1>;
90                                 device_type = "ethernet-phy";
91                         };
92                 };
93
94                 ethernet@24000 {
95                         #address-cells = <1>;
96                         #size-cells = <0>;
97                         device_type = "network";
98                         model = "TSEC";
99                         compatible = "gianfar";
100                         reg = <24000 1000>;
101                         local-mac-address = [ 00 00 00 00 00 00 ];
102                         interrupts = <1d 2 1e 2 22 2>;
103                         interrupt-parent = <&mpic>;
104                         phy-handle = <&phy0>;
105                 };
106
107                 ethernet@25000 {
108                         #address-cells = <1>;
109                         #size-cells = <0>;
110                         device_type = "network";
111                         model = "TSEC";
112                         compatible = "gianfar";
113                         reg = <25000 1000>;
114                         local-mac-address = [ 00 00 00 00 00 00 ];
115                         interrupts = <23 2 24 2 28 2>;
116                         interrupt-parent = <&mpic>;
117                         phy-handle = <&phy1>;
118                 };
119
120                 serial@4500 {
121                         device_type = "serial";
122                         compatible = "ns16550";
123                         reg = <4500 100>;       // reg base, size
124                         clock-frequency = <0>;  // should we fill in in uboot?
125                         interrupts = <2a 2>;
126                         interrupt-parent = <&mpic>;
127                 };
128
129                 serial@4600 {
130                         device_type = "serial";
131                         compatible = "ns16550";
132                         reg = <4600 100>;       // reg base, size
133                         clock-frequency = <0>;  // should we fill in in uboot?
134                         interrupts = <2a 2>;
135                         interrupt-parent = <&mpic>;
136                 };
137
138                 mpic: pic@40000 {
139                         clock-frequency = <0>;
140                         interrupt-controller;
141                         #address-cells = <0>;
142                         #interrupt-cells = <2>;
143                         reg = <40000 40000>;
144                         compatible = "chrp,open-pic";
145                         device_type = "open-pic";
146                         big-endian;
147                 };
148
149                 cpm@919c0 {
150                         #address-cells = <1>;
151                         #size-cells = <1>;
152                         compatible = "fsl,mpc8541-cpm", "fsl,cpm2";
153                         reg = <919c0 30>;
154                         ranges;
155
156                         muram@80000 {
157                                 #address-cells = <1>;
158                                 #size-cells = <1>;
159                                 ranges = <0 80000 10000>;
160
161                                 data@0 {
162                                         compatible = "fsl,cpm-muram-data";
163                                         reg = <0 2000 9000 1000>;
164                                 };
165                         };
166
167                         brg@919f0 {
168                                 compatible = "fsl,mpc8541-brg",
169                                              "fsl,cpm2-brg",
170                                              "fsl,cpm-brg";
171                                 reg = <919f0 10 915f0 10>;
172                         };
173
174                         cpmpic: pic@90c00 {
175                                 interrupt-controller;
176                                 #address-cells = <0>;
177                                 #interrupt-cells = <2>;
178                                 interrupts = <2e 2>;
179                                 interrupt-parent = <&mpic>;
180                                 reg = <90c00 80>;
181                                 compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic";
182                         };
183                 };
184         };
185
186         pci1: pci@e0008000 {
187                 interrupt-map-mask = <1f800 0 0 7>;
188                 interrupt-map = <
189
190                         /* IDSEL 0x10 */
191                         08000 0 0 1 &mpic 0 1
192                         08000 0 0 2 &mpic 1 1
193                         08000 0 0 3 &mpic 2 1
194                         08000 0 0 4 &mpic 3 1
195
196                         /* IDSEL 0x11 */
197                         08800 0 0 1 &mpic 0 1
198                         08800 0 0 2 &mpic 1 1
199                         08800 0 0 3 &mpic 2 1
200                         08800 0 0 4 &mpic 3 1
201
202                         /* IDSEL 0x12 (Slot 1) */
203                         09000 0 0 1 &mpic 0 1
204                         09000 0 0 2 &mpic 1 1
205                         09000 0 0 3 &mpic 2 1
206                         09000 0 0 4 &mpic 3 1
207
208                         /* IDSEL 0x13 (Slot 2) */
209                         09800 0 0 1 &mpic 1 1
210                         09800 0 0 2 &mpic 2 1
211                         09800 0 0 3 &mpic 3 1
212                         09800 0 0 4 &mpic 0 1
213
214                         /* IDSEL 0x14 (Slot 3) */
215                         0a000 0 0 1 &mpic 2 1
216                         0a000 0 0 2 &mpic 3 1
217                         0a000 0 0 3 &mpic 0 1
218                         0a000 0 0 4 &mpic 1 1
219
220                         /* IDSEL 0x15 (Slot 4) */
221                         0a800 0 0 1 &mpic 3 1
222                         0a800 0 0 2 &mpic 0 1
223                         0a800 0 0 3 &mpic 1 1
224                         0a800 0 0 4 &mpic 2 1
225
226                         /* Bus 1 (Tundra Bridge) */
227                         /* IDSEL 0x12 (ISA bridge) */
228                         19000 0 0 1 &mpic 0 1
229                         19000 0 0 2 &mpic 1 1
230                         19000 0 0 3 &mpic 2 1
231                         19000 0 0 4 &mpic 3 1>;
232                 interrupt-parent = <&mpic>;
233                 interrupts = <18 2>;
234                 bus-range = <0 0>;
235                 ranges = <02000000 0 80000000 80000000 0 20000000
236                           01000000 0 00000000 e2000000 0 00100000>;
237                 clock-frequency = <3f940aa>;
238                 #interrupt-cells = <1>;
239                 #size-cells = <2>;
240                 #address-cells = <3>;
241                 reg = <e0008000 1000>;
242                 compatible = "fsl,mpc8540-pci";
243                 device_type = "pci";
244
245                 i8259@19000 {
246                         interrupt-controller;
247                         device_type = "interrupt-controller";
248                         reg = <19000 0 0 0 1>;
249                         #address-cells = <0>;
250                         #interrupt-cells = <2>;
251                         compatible = "chrp,iic";
252                         interrupts = <1>;
253                         interrupt-parent = <&pci1>;
254                 };
255         };
256
257         pci@e0009000 {
258                 interrupt-map-mask = <f800 0 0 7>;
259                 interrupt-map = <
260
261                         /* IDSEL 0x15 */
262                         a800 0 0 1 &mpic b 1
263                         a800 0 0 2 &mpic b 1
264                         a800 0 0 3 &mpic b 1
265                         a800 0 0 4 &mpic b 1>;
266                 interrupt-parent = <&mpic>;
267                 interrupts = <19 2>;
268                 bus-range = <0 0>;
269                 ranges = <02000000 0 a0000000 a0000000 0 20000000
270                           01000000 0 00000000 e3000000 0 00100000>;
271                 clock-frequency = <3f940aa>;
272                 #interrupt-cells = <1>;
273                 #size-cells = <2>;
274                 #address-cells = <3>;
275                 reg = <e0009000 1000>;
276                 compatible = "fsl,mpc8540-pci";
277                 device_type = "pci";
278         };
279 };