Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound-2.6
[linux-2.6] / arch / x86 / kernel / pci-calgary_64.c
1 /*
2  * Derived from arch/powerpc/kernel/iommu.c
3  *
4  * Copyright IBM Corporation, 2006-2007
5  * Copyright (C) 2006  Jon Mason <jdmason@kudzu.us>
6  *
7  * Author: Jon Mason <jdmason@kudzu.us>
8  * Author: Muli Ben-Yehuda <muli@il.ibm.com>
9
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License, or
13  * (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
23  */
24
25 #include <linux/kernel.h>
26 #include <linux/init.h>
27 #include <linux/types.h>
28 #include <linux/slab.h>
29 #include <linux/mm.h>
30 #include <linux/spinlock.h>
31 #include <linux/string.h>
32 #include <linux/crash_dump.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/bitops.h>
35 #include <linux/pci_ids.h>
36 #include <linux/pci.h>
37 #include <linux/delay.h>
38 #include <linux/scatterlist.h>
39 #include <linux/iommu-helper.h>
40
41 #include <asm/iommu.h>
42 #include <asm/calgary.h>
43 #include <asm/tce.h>
44 #include <asm/pci-direct.h>
45 #include <asm/system.h>
46 #include <asm/dma.h>
47 #include <asm/rio.h>
48 #include <asm/bios_ebda.h>
49
50 #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
51 int use_calgary __read_mostly = 1;
52 #else
53 int use_calgary __read_mostly = 0;
54 #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
55
56 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
57 #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
58
59 /* register offsets inside the host bridge space */
60 #define CALGARY_CONFIG_REG      0x0108
61 #define PHB_CSR_OFFSET          0x0110 /* Channel Status */
62 #define PHB_PLSSR_OFFSET        0x0120
63 #define PHB_CONFIG_RW_OFFSET    0x0160
64 #define PHB_IOBASE_BAR_LOW      0x0170
65 #define PHB_IOBASE_BAR_HIGH     0x0180
66 #define PHB_MEM_1_LOW           0x0190
67 #define PHB_MEM_1_HIGH          0x01A0
68 #define PHB_IO_ADDR_SIZE        0x01B0
69 #define PHB_MEM_1_SIZE          0x01C0
70 #define PHB_MEM_ST_OFFSET       0x01D0
71 #define PHB_AER_OFFSET          0x0200
72 #define PHB_CONFIG_0_HIGH       0x0220
73 #define PHB_CONFIG_0_LOW        0x0230
74 #define PHB_CONFIG_0_END        0x0240
75 #define PHB_MEM_2_LOW           0x02B0
76 #define PHB_MEM_2_HIGH          0x02C0
77 #define PHB_MEM_2_SIZE_HIGH     0x02D0
78 #define PHB_MEM_2_SIZE_LOW      0x02E0
79 #define PHB_DOSHOLE_OFFSET      0x08E0
80
81 /* CalIOC2 specific */
82 #define PHB_SAVIOR_L2           0x0DB0
83 #define PHB_PAGE_MIG_CTRL       0x0DA8
84 #define PHB_PAGE_MIG_DEBUG      0x0DA0
85 #define PHB_ROOT_COMPLEX_STATUS 0x0CB0
86
87 /* PHB_CONFIG_RW */
88 #define PHB_TCE_ENABLE          0x20000000
89 #define PHB_SLOT_DISABLE        0x1C000000
90 #define PHB_DAC_DISABLE         0x01000000
91 #define PHB_MEM2_ENABLE         0x00400000
92 #define PHB_MCSR_ENABLE         0x00100000
93 /* TAR (Table Address Register) */
94 #define TAR_SW_BITS             0x0000ffffffff800fUL
95 #define TAR_VALID               0x0000000000000008UL
96 /* CSR (Channel/DMA Status Register) */
97 #define CSR_AGENT_MASK          0xffe0ffff
98 /* CCR (Calgary Configuration Register) */
99 #define CCR_2SEC_TIMEOUT        0x000000000000000EUL
100 /* PMCR/PMDR (Page Migration Control/Debug Registers */
101 #define PMR_SOFTSTOP            0x80000000
102 #define PMR_SOFTSTOPFAULT       0x40000000
103 #define PMR_HARDSTOP            0x20000000
104
105 #define MAX_NUM_OF_PHBS         8 /* how many PHBs in total? */
106 #define MAX_NUM_CHASSIS         8 /* max number of chassis */
107 /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
108 #define MAX_PHB_BUS_NUM         (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
109 #define PHBS_PER_CALGARY        4
110
111 /* register offsets in Calgary's internal register space */
112 static const unsigned long tar_offsets[] = {
113         0x0580 /* TAR0 */,
114         0x0588 /* TAR1 */,
115         0x0590 /* TAR2 */,
116         0x0598 /* TAR3 */
117 };
118
119 static const unsigned long split_queue_offsets[] = {
120         0x4870 /* SPLIT QUEUE 0 */,
121         0x5870 /* SPLIT QUEUE 1 */,
122         0x6870 /* SPLIT QUEUE 2 */,
123         0x7870 /* SPLIT QUEUE 3 */
124 };
125
126 static const unsigned long phb_offsets[] = {
127         0x8000 /* PHB0 */,
128         0x9000 /* PHB1 */,
129         0xA000 /* PHB2 */,
130         0xB000 /* PHB3 */
131 };
132
133 /* PHB debug registers */
134
135 static const unsigned long phb_debug_offsets[] = {
136         0x4000  /* PHB 0 DEBUG */,
137         0x5000  /* PHB 1 DEBUG */,
138         0x6000  /* PHB 2 DEBUG */,
139         0x7000  /* PHB 3 DEBUG */
140 };
141
142 /*
143  * STUFF register for each debug PHB,
144  * byte 1 = start bus number, byte 2 = end bus number
145  */
146
147 #define PHB_DEBUG_STUFF_OFFSET  0x0020
148
149 #define EMERGENCY_PAGES 32 /* = 128KB */
150
151 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
152 static int translate_empty_slots __read_mostly = 0;
153 static int calgary_detected __read_mostly = 0;
154
155 static struct rio_table_hdr     *rio_table_hdr __initdata;
156 static struct scal_detail       *scal_devs[MAX_NUMNODES] __initdata;
157 static struct rio_detail        *rio_devs[MAX_NUMNODES * 4] __initdata;
158
159 struct calgary_bus_info {
160         void *tce_space;
161         unsigned char translation_disabled;
162         signed char phbid;
163         void __iomem *bbar;
164 };
165
166 static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
167 static void calgary_tce_cache_blast(struct iommu_table *tbl);
168 static void calgary_dump_error_regs(struct iommu_table *tbl);
169 static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
170 static void calioc2_tce_cache_blast(struct iommu_table *tbl);
171 static void calioc2_dump_error_regs(struct iommu_table *tbl);
172 static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl);
173 static void get_tce_space_from_tar(void);
174
175 static struct cal_chipset_ops calgary_chip_ops = {
176         .handle_quirks = calgary_handle_quirks,
177         .tce_cache_blast = calgary_tce_cache_blast,
178         .dump_error_regs = calgary_dump_error_regs
179 };
180
181 static struct cal_chipset_ops calioc2_chip_ops = {
182         .handle_quirks = calioc2_handle_quirks,
183         .tce_cache_blast = calioc2_tce_cache_blast,
184         .dump_error_regs = calioc2_dump_error_regs
185 };
186
187 static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
188
189 /* enable this to stress test the chip's TCE cache */
190 #ifdef CONFIG_IOMMU_DEBUG
191 static int debugging = 1;
192
193 static inline unsigned long verify_bit_range(unsigned long* bitmap,
194         int expected, unsigned long start, unsigned long end)
195 {
196         unsigned long idx = start;
197
198         BUG_ON(start >= end);
199
200         while (idx < end) {
201                 if (!!test_bit(idx, bitmap) != expected)
202                         return idx;
203                 ++idx;
204         }
205
206         /* all bits have the expected value */
207         return ~0UL;
208 }
209 #else /* debugging is disabled */
210 static int debugging;
211
212 static inline unsigned long verify_bit_range(unsigned long* bitmap,
213         int expected, unsigned long start, unsigned long end)
214 {
215         return ~0UL;
216 }
217
218 #endif /* CONFIG_IOMMU_DEBUG */
219
220 static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen)
221 {
222         unsigned int npages;
223
224         npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK);
225         npages >>= PAGE_SHIFT;
226
227         return npages;
228 }
229
230 static inline int translation_enabled(struct iommu_table *tbl)
231 {
232         /* only PHBs with translation enabled have an IOMMU table */
233         return (tbl != NULL);
234 }
235
236 static void iommu_range_reserve(struct iommu_table *tbl,
237         unsigned long start_addr, unsigned int npages)
238 {
239         unsigned long index;
240         unsigned long end;
241         unsigned long badbit;
242         unsigned long flags;
243
244         index = start_addr >> PAGE_SHIFT;
245
246         /* bail out if we're asked to reserve a region we don't cover */
247         if (index >= tbl->it_size)
248                 return;
249
250         end = index + npages;
251         if (end > tbl->it_size) /* don't go off the table */
252                 end = tbl->it_size;
253
254         spin_lock_irqsave(&tbl->it_lock, flags);
255
256         badbit = verify_bit_range(tbl->it_map, 0, index, end);
257         if (badbit != ~0UL) {
258                 if (printk_ratelimit())
259                         printk(KERN_ERR "Calgary: entry already allocated at "
260                                "0x%lx tbl %p dma 0x%lx npages %u\n",
261                                badbit, tbl, start_addr, npages);
262         }
263
264         set_bit_string(tbl->it_map, index, npages);
265
266         spin_unlock_irqrestore(&tbl->it_lock, flags);
267 }
268
269 static unsigned long iommu_range_alloc(struct device *dev,
270                                        struct iommu_table *tbl,
271                                        unsigned int npages)
272 {
273         unsigned long flags;
274         unsigned long offset;
275         unsigned long boundary_size;
276
277         boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
278                               PAGE_SIZE) >> PAGE_SHIFT;
279
280         BUG_ON(npages == 0);
281
282         spin_lock_irqsave(&tbl->it_lock, flags);
283
284         offset = iommu_area_alloc(tbl->it_map, tbl->it_size, tbl->it_hint,
285                                   npages, 0, boundary_size, 0);
286         if (offset == ~0UL) {
287                 tbl->chip_ops->tce_cache_blast(tbl);
288
289                 offset = iommu_area_alloc(tbl->it_map, tbl->it_size, 0,
290                                           npages, 0, boundary_size, 0);
291                 if (offset == ~0UL) {
292                         printk(KERN_WARNING "Calgary: IOMMU full.\n");
293                         spin_unlock_irqrestore(&tbl->it_lock, flags);
294                         if (panic_on_overflow)
295                                 panic("Calgary: fix the allocator.\n");
296                         else
297                                 return bad_dma_address;
298                 }
299         }
300
301         tbl->it_hint = offset + npages;
302         BUG_ON(tbl->it_hint > tbl->it_size);
303
304         spin_unlock_irqrestore(&tbl->it_lock, flags);
305
306         return offset;
307 }
308
309 static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
310                               void *vaddr, unsigned int npages, int direction)
311 {
312         unsigned long entry;
313         dma_addr_t ret = bad_dma_address;
314
315         entry = iommu_range_alloc(dev, tbl, npages);
316
317         if (unlikely(entry == bad_dma_address))
318                 goto error;
319
320         /* set the return dma address */
321         ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
322
323         /* put the TCEs in the HW table */
324         tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
325                   direction);
326
327         return ret;
328
329 error:
330         printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
331                "iommu %p\n", npages, tbl);
332         return bad_dma_address;
333 }
334
335 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
336         unsigned int npages)
337 {
338         unsigned long entry;
339         unsigned long badbit;
340         unsigned long badend;
341         unsigned long flags;
342
343         /* were we called with bad_dma_address? */
344         badend = bad_dma_address + (EMERGENCY_PAGES * PAGE_SIZE);
345         if (unlikely((dma_addr >= bad_dma_address) && (dma_addr < badend))) {
346                 WARN(1, KERN_ERR "Calgary: driver tried unmapping bad DMA "
347                        "address 0x%Lx\n", dma_addr);
348                 return;
349         }
350
351         entry = dma_addr >> PAGE_SHIFT;
352
353         BUG_ON(entry + npages > tbl->it_size);
354
355         tce_free(tbl, entry, npages);
356
357         spin_lock_irqsave(&tbl->it_lock, flags);
358
359         badbit = verify_bit_range(tbl->it_map, 1, entry, entry + npages);
360         if (badbit != ~0UL) {
361                 if (printk_ratelimit())
362                         printk(KERN_ERR "Calgary: bit is off at 0x%lx "
363                                "tbl %p dma 0x%Lx entry 0x%lx npages %u\n",
364                                badbit, tbl, dma_addr, entry, npages);
365         }
366
367         iommu_area_free(tbl->it_map, entry, npages);
368
369         spin_unlock_irqrestore(&tbl->it_lock, flags);
370 }
371
372 static inline struct iommu_table *find_iommu_table(struct device *dev)
373 {
374         struct pci_dev *pdev;
375         struct pci_bus *pbus;
376         struct iommu_table *tbl;
377
378         pdev = to_pci_dev(dev);
379
380         pbus = pdev->bus;
381
382         /* is the device behind a bridge? Look for the root bus */
383         while (pbus->parent)
384                 pbus = pbus->parent;
385
386         tbl = pci_iommu(pbus);
387
388         BUG_ON(tbl && (tbl->it_busno != pbus->number));
389
390         return tbl;
391 }
392
393 static void calgary_unmap_sg(struct device *dev,
394         struct scatterlist *sglist, int nelems, int direction)
395 {
396         struct iommu_table *tbl = find_iommu_table(dev);
397         struct scatterlist *s;
398         int i;
399
400         if (!translation_enabled(tbl))
401                 return;
402
403         for_each_sg(sglist, s, nelems, i) {
404                 unsigned int npages;
405                 dma_addr_t dma = s->dma_address;
406                 unsigned int dmalen = s->dma_length;
407
408                 if (dmalen == 0)
409                         break;
410
411                 npages = num_dma_pages(dma, dmalen);
412                 iommu_free(tbl, dma, npages);
413         }
414 }
415
416 static int calgary_map_sg(struct device *dev, struct scatterlist *sg,
417         int nelems, int direction)
418 {
419         struct iommu_table *tbl = find_iommu_table(dev);
420         struct scatterlist *s;
421         unsigned long vaddr;
422         unsigned int npages;
423         unsigned long entry;
424         int i;
425
426         for_each_sg(sg, s, nelems, i) {
427                 BUG_ON(!sg_page(s));
428
429                 vaddr = (unsigned long) sg_virt(s);
430                 npages = num_dma_pages(vaddr, s->length);
431
432                 entry = iommu_range_alloc(dev, tbl, npages);
433                 if (entry == bad_dma_address) {
434                         /* makes sure unmap knows to stop */
435                         s->dma_length = 0;
436                         goto error;
437                 }
438
439                 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
440
441                 /* insert into HW table */
442                 tce_build(tbl, entry, npages, vaddr & PAGE_MASK,
443                           direction);
444
445                 s->dma_length = s->length;
446         }
447
448         return nelems;
449 error:
450         calgary_unmap_sg(dev, sg, nelems, direction);
451         for_each_sg(sg, s, nelems, i) {
452                 sg->dma_address = bad_dma_address;
453                 sg->dma_length = 0;
454         }
455         return 0;
456 }
457
458 static dma_addr_t calgary_map_single(struct device *dev, phys_addr_t paddr,
459         size_t size, int direction)
460 {
461         void *vaddr = phys_to_virt(paddr);
462         unsigned long uaddr;
463         unsigned int npages;
464         struct iommu_table *tbl = find_iommu_table(dev);
465
466         uaddr = (unsigned long)vaddr;
467         npages = num_dma_pages(uaddr, size);
468
469         return iommu_alloc(dev, tbl, vaddr, npages, direction);
470 }
471
472 static void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle,
473         size_t size, int direction)
474 {
475         struct iommu_table *tbl = find_iommu_table(dev);
476         unsigned int npages;
477
478         npages = num_dma_pages(dma_handle, size);
479         iommu_free(tbl, dma_handle, npages);
480 }
481
482 static void* calgary_alloc_coherent(struct device *dev, size_t size,
483         dma_addr_t *dma_handle, gfp_t flag)
484 {
485         void *ret = NULL;
486         dma_addr_t mapping;
487         unsigned int npages, order;
488         struct iommu_table *tbl = find_iommu_table(dev);
489
490         size = PAGE_ALIGN(size); /* size rounded up to full pages */
491         npages = size >> PAGE_SHIFT;
492         order = get_order(size);
493
494         /* alloc enough pages (and possibly more) */
495         ret = (void *)__get_free_pages(flag, order);
496         if (!ret)
497                 goto error;
498         memset(ret, 0, size);
499
500         /* set up tces to cover the allocated range */
501         mapping = iommu_alloc(dev, tbl, ret, npages, DMA_BIDIRECTIONAL);
502         if (mapping == bad_dma_address)
503                 goto free;
504         *dma_handle = mapping;
505         return ret;
506 free:
507         free_pages((unsigned long)ret, get_order(size));
508         ret = NULL;
509 error:
510         return ret;
511 }
512
513 static struct dma_mapping_ops calgary_dma_ops = {
514         .alloc_coherent = calgary_alloc_coherent,
515         .map_single = calgary_map_single,
516         .unmap_single = calgary_unmap_single,
517         .map_sg = calgary_map_sg,
518         .unmap_sg = calgary_unmap_sg,
519 };
520
521 static inline void __iomem * busno_to_bbar(unsigned char num)
522 {
523         return bus_info[num].bbar;
524 }
525
526 static inline int busno_to_phbid(unsigned char num)
527 {
528         return bus_info[num].phbid;
529 }
530
531 static inline unsigned long split_queue_offset(unsigned char num)
532 {
533         size_t idx = busno_to_phbid(num);
534
535         return split_queue_offsets[idx];
536 }
537
538 static inline unsigned long tar_offset(unsigned char num)
539 {
540         size_t idx = busno_to_phbid(num);
541
542         return tar_offsets[idx];
543 }
544
545 static inline unsigned long phb_offset(unsigned char num)
546 {
547         size_t idx = busno_to_phbid(num);
548
549         return phb_offsets[idx];
550 }
551
552 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
553 {
554         unsigned long target = ((unsigned long)bar) | offset;
555         return (void __iomem*)target;
556 }
557
558 static inline int is_calioc2(unsigned short device)
559 {
560         return (device == PCI_DEVICE_ID_IBM_CALIOC2);
561 }
562
563 static inline int is_calgary(unsigned short device)
564 {
565         return (device == PCI_DEVICE_ID_IBM_CALGARY);
566 }
567
568 static inline int is_cal_pci_dev(unsigned short device)
569 {
570         return (is_calgary(device) || is_calioc2(device));
571 }
572
573 static void calgary_tce_cache_blast(struct iommu_table *tbl)
574 {
575         u64 val;
576         u32 aer;
577         int i = 0;
578         void __iomem *bbar = tbl->bbar;
579         void __iomem *target;
580
581         /* disable arbitration on the bus */
582         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
583         aer = readl(target);
584         writel(0, target);
585
586         /* read plssr to ensure it got there */
587         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
588         val = readl(target);
589
590         /* poll split queues until all DMA activity is done */
591         target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
592         do {
593                 val = readq(target);
594                 i++;
595         } while ((val & 0xff) != 0xff && i < 100);
596         if (i == 100)
597                 printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
598                        "continuing anyway\n");
599
600         /* invalidate TCE cache */
601         target = calgary_reg(bbar, tar_offset(tbl->it_busno));
602         writeq(tbl->tar_val, target);
603
604         /* enable arbitration */
605         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
606         writel(aer, target);
607         (void)readl(target); /* flush */
608 }
609
610 static void calioc2_tce_cache_blast(struct iommu_table *tbl)
611 {
612         void __iomem *bbar = tbl->bbar;
613         void __iomem *target;
614         u64 val64;
615         u32 val;
616         int i = 0;
617         int count = 1;
618         unsigned char bus = tbl->it_busno;
619
620 begin:
621         printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast "
622                "sequence - count %d\n", bus, count);
623
624         /* 1. using the Page Migration Control reg set SoftStop */
625         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
626         val = be32_to_cpu(readl(target));
627         printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target);
628         val |= PMR_SOFTSTOP;
629         printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target);
630         writel(cpu_to_be32(val), target);
631
632         /* 2. poll split queues until all DMA activity is done */
633         printk(KERN_DEBUG "2a. starting to poll split queues\n");
634         target = calgary_reg(bbar, split_queue_offset(bus));
635         do {
636                 val64 = readq(target);
637                 i++;
638         } while ((val64 & 0xff) != 0xff && i < 100);
639         if (i == 100)
640                 printk(KERN_WARNING "CalIOC2: PCI bus not quiesced, "
641                        "continuing anyway\n");
642
643         /* 3. poll Page Migration DEBUG for SoftStopFault */
644         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
645         val = be32_to_cpu(readl(target));
646         printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target);
647
648         /* 4. if SoftStopFault - goto (1) */
649         if (val & PMR_SOFTSTOPFAULT) {
650                 if (++count < 100)
651                         goto begin;
652                 else {
653                         printk(KERN_WARNING "CalIOC2: too many SoftStopFaults, "
654                                "aborting TCE cache flush sequence!\n");
655                         return; /* pray for the best */
656                 }
657         }
658
659         /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */
660         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
661         printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target);
662         val = be32_to_cpu(readl(target));
663         printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target);
664         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
665         val = be32_to_cpu(readl(target));
666         printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target);
667
668         /* 6. invalidate TCE cache */
669         printk(KERN_DEBUG "6. invalidating TCE cache\n");
670         target = calgary_reg(bbar, tar_offset(bus));
671         writeq(tbl->tar_val, target);
672
673         /* 7. Re-read PMCR */
674         printk(KERN_DEBUG "7a. Re-reading PMCR\n");
675         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
676         val = be32_to_cpu(readl(target));
677         printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target);
678
679         /* 8. Remove HardStop */
680         printk(KERN_DEBUG "8a. removing HardStop from PMCR\n");
681         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
682         val = 0;
683         printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target);
684         writel(cpu_to_be32(val), target);
685         val = be32_to_cpu(readl(target));
686         printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target);
687 }
688
689 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
690         u64 limit)
691 {
692         unsigned int numpages;
693
694         limit = limit | 0xfffff;
695         limit++;
696
697         numpages = ((limit - start) >> PAGE_SHIFT);
698         iommu_range_reserve(pci_iommu(dev->bus), start, numpages);
699 }
700
701 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
702 {
703         void __iomem *target;
704         u64 low, high, sizelow;
705         u64 start, limit;
706         struct iommu_table *tbl = pci_iommu(dev->bus);
707         unsigned char busnum = dev->bus->number;
708         void __iomem *bbar = tbl->bbar;
709
710         /* peripheral MEM_1 region */
711         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
712         low = be32_to_cpu(readl(target));
713         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
714         high = be32_to_cpu(readl(target));
715         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
716         sizelow = be32_to_cpu(readl(target));
717
718         start = (high << 32) | low;
719         limit = sizelow;
720
721         calgary_reserve_mem_region(dev, start, limit);
722 }
723
724 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
725 {
726         void __iomem *target;
727         u32 val32;
728         u64 low, high, sizelow, sizehigh;
729         u64 start, limit;
730         struct iommu_table *tbl = pci_iommu(dev->bus);
731         unsigned char busnum = dev->bus->number;
732         void __iomem *bbar = tbl->bbar;
733
734         /* is it enabled? */
735         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
736         val32 = be32_to_cpu(readl(target));
737         if (!(val32 & PHB_MEM2_ENABLE))
738                 return;
739
740         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
741         low = be32_to_cpu(readl(target));
742         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
743         high = be32_to_cpu(readl(target));
744         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
745         sizelow = be32_to_cpu(readl(target));
746         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
747         sizehigh = be32_to_cpu(readl(target));
748
749         start = (high << 32) | low;
750         limit = (sizehigh << 32) | sizelow;
751
752         calgary_reserve_mem_region(dev, start, limit);
753 }
754
755 /*
756  * some regions of the IO address space do not get translated, so we
757  * must not give devices IO addresses in those regions. The regions
758  * are the 640KB-1MB region and the two PCI peripheral memory holes.
759  * Reserve all of them in the IOMMU bitmap to avoid giving them out
760  * later.
761  */
762 static void __init calgary_reserve_regions(struct pci_dev *dev)
763 {
764         unsigned int npages;
765         u64 start;
766         struct iommu_table *tbl = pci_iommu(dev->bus);
767
768         /* reserve EMERGENCY_PAGES from bad_dma_address and up */
769         iommu_range_reserve(tbl, bad_dma_address, EMERGENCY_PAGES);
770
771         /* avoid the BIOS/VGA first 640KB-1MB region */
772         /* for CalIOC2 - avoid the entire first MB */
773         if (is_calgary(dev->device)) {
774                 start = (640 * 1024);
775                 npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
776         } else { /* calioc2 */
777                 start = 0;
778                 npages = (1 * 1024 * 1024) >> PAGE_SHIFT;
779         }
780         iommu_range_reserve(tbl, start, npages);
781
782         /* reserve the two PCI peripheral memory regions in IO space */
783         calgary_reserve_peripheral_mem_1(dev);
784         calgary_reserve_peripheral_mem_2(dev);
785 }
786
787 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
788 {
789         u64 val64;
790         u64 table_phys;
791         void __iomem *target;
792         int ret;
793         struct iommu_table *tbl;
794
795         /* build TCE tables for each PHB */
796         ret = build_tce_table(dev, bbar);
797         if (ret)
798                 return ret;
799
800         tbl = pci_iommu(dev->bus);
801         tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
802
803         if (is_kdump_kernel())
804                 calgary_init_bitmap_from_tce_table(tbl);
805         else
806                 tce_free(tbl, 0, tbl->it_size);
807
808         if (is_calgary(dev->device))
809                 tbl->chip_ops = &calgary_chip_ops;
810         else if (is_calioc2(dev->device))
811                 tbl->chip_ops = &calioc2_chip_ops;
812         else
813                 BUG();
814
815         calgary_reserve_regions(dev);
816
817         /* set TARs for each PHB */
818         target = calgary_reg(bbar, tar_offset(dev->bus->number));
819         val64 = be64_to_cpu(readq(target));
820
821         /* zero out all TAR bits under sw control */
822         val64 &= ~TAR_SW_BITS;
823         table_phys = (u64)__pa(tbl->it_base);
824
825         val64 |= table_phys;
826
827         BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
828         val64 |= (u64) specified_table_size;
829
830         tbl->tar_val = cpu_to_be64(val64);
831
832         writeq(tbl->tar_val, target);
833         readq(target); /* flush */
834
835         return 0;
836 }
837
838 static void __init calgary_free_bus(struct pci_dev *dev)
839 {
840         u64 val64;
841         struct iommu_table *tbl = pci_iommu(dev->bus);
842         void __iomem *target;
843         unsigned int bitmapsz;
844
845         target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
846         val64 = be64_to_cpu(readq(target));
847         val64 &= ~TAR_SW_BITS;
848         writeq(cpu_to_be64(val64), target);
849         readq(target); /* flush */
850
851         bitmapsz = tbl->it_size / BITS_PER_BYTE;
852         free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
853         tbl->it_map = NULL;
854
855         kfree(tbl);
856         
857         set_pci_iommu(dev->bus, NULL);
858
859         /* Can't free bootmem allocated memory after system is up :-( */
860         bus_info[dev->bus->number].tce_space = NULL;
861 }
862
863 static void calgary_dump_error_regs(struct iommu_table *tbl)
864 {
865         void __iomem *bbar = tbl->bbar;
866         void __iomem *target;
867         u32 csr, plssr;
868
869         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
870         csr = be32_to_cpu(readl(target));
871
872         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
873         plssr = be32_to_cpu(readl(target));
874
875         /* If no error, the agent ID in the CSR is not valid */
876         printk(KERN_EMERG "Calgary: DMA error on Calgary PHB 0x%x, "
877                "0x%08x@CSR 0x%08x@PLSSR\n", tbl->it_busno, csr, plssr);
878 }
879
880 static void calioc2_dump_error_regs(struct iommu_table *tbl)
881 {
882         void __iomem *bbar = tbl->bbar;
883         u32 csr, csmr, plssr, mck, rcstat;
884         void __iomem *target;
885         unsigned long phboff = phb_offset(tbl->it_busno);
886         unsigned long erroff;
887         u32 errregs[7];
888         int i;
889
890         /* dump CSR */
891         target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET);
892         csr = be32_to_cpu(readl(target));
893         /* dump PLSSR */
894         target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET);
895         plssr = be32_to_cpu(readl(target));
896         /* dump CSMR */
897         target = calgary_reg(bbar, phboff | 0x290);
898         csmr = be32_to_cpu(readl(target));
899         /* dump mck */
900         target = calgary_reg(bbar, phboff | 0x800);
901         mck = be32_to_cpu(readl(target));
902
903         printk(KERN_EMERG "Calgary: DMA error on CalIOC2 PHB 0x%x\n",
904                tbl->it_busno);
905
906         printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
907                csr, plssr, csmr, mck);
908
909         /* dump rest of error regs */
910         printk(KERN_EMERG "Calgary: ");
911         for (i = 0; i < ARRAY_SIZE(errregs); i++) {
912                 /* err regs are at 0x810 - 0x870 */
913                 erroff = (0x810 + (i * 0x10));
914                 target = calgary_reg(bbar, phboff | erroff);
915                 errregs[i] = be32_to_cpu(readl(target));
916                 printk("0x%08x@0x%lx ", errregs[i], erroff);
917         }
918         printk("\n");
919
920         /* root complex status */
921         target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS);
922         rcstat = be32_to_cpu(readl(target));
923         printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat,
924                PHB_ROOT_COMPLEX_STATUS);
925 }
926
927 static void calgary_watchdog(unsigned long data)
928 {
929         struct pci_dev *dev = (struct pci_dev *)data;
930         struct iommu_table *tbl = pci_iommu(dev->bus);
931         void __iomem *bbar = tbl->bbar;
932         u32 val32;
933         void __iomem *target;
934
935         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
936         val32 = be32_to_cpu(readl(target));
937
938         /* If no error, the agent ID in the CSR is not valid */
939         if (val32 & CSR_AGENT_MASK) {
940                 tbl->chip_ops->dump_error_regs(tbl);
941
942                 /* reset error */
943                 writel(0, target);
944
945                 /* Disable bus that caused the error */
946                 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
947                                      PHB_CONFIG_RW_OFFSET);
948                 val32 = be32_to_cpu(readl(target));
949                 val32 |= PHB_SLOT_DISABLE;
950                 writel(cpu_to_be32(val32), target);
951                 readl(target); /* flush */
952         } else {
953                 /* Reset the timer */
954                 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
955         }
956 }
957
958 static void __init calgary_set_split_completion_timeout(void __iomem *bbar,
959         unsigned char busnum, unsigned long timeout)
960 {
961         u64 val64;
962         void __iomem *target;
963         unsigned int phb_shift = ~0; /* silence gcc */
964         u64 mask;
965
966         switch (busno_to_phbid(busnum)) {
967         case 0: phb_shift = (63 - 19);
968                 break;
969         case 1: phb_shift = (63 - 23);
970                 break;
971         case 2: phb_shift = (63 - 27);
972                 break;
973         case 3: phb_shift = (63 - 35);
974                 break;
975         default:
976                 BUG_ON(busno_to_phbid(busnum));
977         }
978
979         target = calgary_reg(bbar, CALGARY_CONFIG_REG);
980         val64 = be64_to_cpu(readq(target));
981
982         /* zero out this PHB's timer bits */
983         mask = ~(0xFUL << phb_shift);
984         val64 &= mask;
985         val64 |= (timeout << phb_shift);
986         writeq(cpu_to_be64(val64), target);
987         readq(target); /* flush */
988 }
989
990 static void __init calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
991 {
992         unsigned char busnum = dev->bus->number;
993         void __iomem *bbar = tbl->bbar;
994         void __iomem *target;
995         u32 val;
996
997         /*
998          * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1
999          */
1000         target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2);
1001         val = cpu_to_be32(readl(target));
1002         val |= 0x00800000;
1003         writel(cpu_to_be32(val), target);
1004 }
1005
1006 static void __init calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
1007 {
1008         unsigned char busnum = dev->bus->number;
1009
1010         /*
1011          * Give split completion a longer timeout on bus 1 for aic94xx
1012          * http://bugzilla.kernel.org/show_bug.cgi?id=7180
1013          */
1014         if (is_calgary(dev->device) && (busnum == 1))
1015                 calgary_set_split_completion_timeout(tbl->bbar, busnum,
1016                                                      CCR_2SEC_TIMEOUT);
1017 }
1018
1019 static void __init calgary_enable_translation(struct pci_dev *dev)
1020 {
1021         u32 val32;
1022         unsigned char busnum;
1023         void __iomem *target;
1024         void __iomem *bbar;
1025         struct iommu_table *tbl;
1026
1027         busnum = dev->bus->number;
1028         tbl = pci_iommu(dev->bus);
1029         bbar = tbl->bbar;
1030
1031         /* enable TCE in PHB Config Register */
1032         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1033         val32 = be32_to_cpu(readl(target));
1034         val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
1035
1036         printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n",
1037                (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ?
1038                "Calgary" : "CalIOC2", busnum);
1039         printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
1040                "bus.\n");
1041
1042         writel(cpu_to_be32(val32), target);
1043         readl(target); /* flush */
1044
1045         init_timer(&tbl->watchdog_timer);
1046         tbl->watchdog_timer.function = &calgary_watchdog;
1047         tbl->watchdog_timer.data = (unsigned long)dev;
1048         mod_timer(&tbl->watchdog_timer, jiffies);
1049 }
1050
1051 static void __init calgary_disable_translation(struct pci_dev *dev)
1052 {
1053         u32 val32;
1054         unsigned char busnum;
1055         void __iomem *target;
1056         void __iomem *bbar;
1057         struct iommu_table *tbl;
1058
1059         busnum = dev->bus->number;
1060         tbl = pci_iommu(dev->bus);
1061         bbar = tbl->bbar;
1062
1063         /* disable TCE in PHB Config Register */
1064         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1065         val32 = be32_to_cpu(readl(target));
1066         val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
1067
1068         printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
1069         writel(cpu_to_be32(val32), target);
1070         readl(target); /* flush */
1071
1072         del_timer_sync(&tbl->watchdog_timer);
1073 }
1074
1075 static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
1076 {
1077         pci_dev_get(dev);
1078         set_pci_iommu(dev->bus, NULL);
1079
1080         /* is the device behind a bridge? */
1081         if (dev->bus->parent)
1082                 dev->bus->parent->self = dev;
1083         else
1084                 dev->bus->self = dev;
1085 }
1086
1087 static int __init calgary_init_one(struct pci_dev *dev)
1088 {
1089         void __iomem *bbar;
1090         struct iommu_table *tbl;
1091         int ret;
1092
1093         BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM);
1094
1095         bbar = busno_to_bbar(dev->bus->number);
1096         ret = calgary_setup_tar(dev, bbar);
1097         if (ret)
1098                 goto done;
1099
1100         pci_dev_get(dev);
1101
1102         if (dev->bus->parent) {
1103                 if (dev->bus->parent->self)
1104                         printk(KERN_WARNING "Calgary: IEEEE, dev %p has "
1105                                "bus->parent->self!\n", dev);
1106                 dev->bus->parent->self = dev;
1107         } else
1108                 dev->bus->self = dev;
1109
1110         tbl = pci_iommu(dev->bus);
1111         tbl->chip_ops->handle_quirks(tbl, dev);
1112
1113         calgary_enable_translation(dev);
1114
1115         return 0;
1116
1117 done:
1118         return ret;
1119 }
1120
1121 static int __init calgary_locate_bbars(void)
1122 {
1123         int ret;
1124         int rioidx, phb, bus;
1125         void __iomem *bbar;
1126         void __iomem *target;
1127         unsigned long offset;
1128         u8 start_bus, end_bus;
1129         u32 val;
1130
1131         ret = -ENODATA;
1132         for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
1133                 struct rio_detail *rio = rio_devs[rioidx];
1134
1135                 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
1136                         continue;
1137
1138                 /* map entire 1MB of Calgary config space */
1139                 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
1140                 if (!bbar)
1141                         goto error;
1142
1143                 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
1144                         offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
1145                         target = calgary_reg(bbar, offset);
1146
1147                         val = be32_to_cpu(readl(target));
1148
1149                         start_bus = (u8)((val & 0x00FF0000) >> 16);
1150                         end_bus = (u8)((val & 0x0000FF00) >> 8);
1151
1152                         if (end_bus) {
1153                                 for (bus = start_bus; bus <= end_bus; bus++) {
1154                                         bus_info[bus].bbar = bbar;
1155                                         bus_info[bus].phbid = phb;
1156                                 }
1157                         } else {
1158                                 bus_info[start_bus].bbar = bbar;
1159                                 bus_info[start_bus].phbid = phb;
1160                         }
1161                 }
1162         }
1163
1164         return 0;
1165
1166 error:
1167         /* scan bus_info and iounmap any bbars we previously ioremap'd */
1168         for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
1169                 if (bus_info[bus].bbar)
1170                         iounmap(bus_info[bus].bbar);
1171
1172         return ret;
1173 }
1174
1175 static int __init calgary_init(void)
1176 {
1177         int ret;
1178         struct pci_dev *dev = NULL;
1179         struct calgary_bus_info *info;
1180
1181         ret = calgary_locate_bbars();
1182         if (ret)
1183                 return ret;
1184
1185         /* Purely for kdump kernel case */
1186         if (is_kdump_kernel())
1187                 get_tce_space_from_tar();
1188
1189         do {
1190                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1191                 if (!dev)
1192                         break;
1193                 if (!is_cal_pci_dev(dev->device))
1194                         continue;
1195
1196                 info = &bus_info[dev->bus->number];
1197                 if (info->translation_disabled) {
1198                         calgary_init_one_nontraslated(dev);
1199                         continue;
1200                 }
1201
1202                 if (!info->tce_space && !translate_empty_slots)
1203                         continue;
1204
1205                 ret = calgary_init_one(dev);
1206                 if (ret)
1207                         goto error;
1208         } while (1);
1209
1210         dev = NULL;
1211         for_each_pci_dev(dev) {
1212                 struct iommu_table *tbl;
1213
1214                 tbl = find_iommu_table(&dev->dev);
1215
1216                 if (translation_enabled(tbl))
1217                         dev->dev.archdata.dma_ops = &calgary_dma_ops;
1218         }
1219
1220         return ret;
1221
1222 error:
1223         do {
1224                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1225                 if (!dev)
1226                         break;
1227                 if (!is_cal_pci_dev(dev->device))
1228                         continue;
1229
1230                 info = &bus_info[dev->bus->number];
1231                 if (info->translation_disabled) {
1232                         pci_dev_put(dev);
1233                         continue;
1234                 }
1235                 if (!info->tce_space && !translate_empty_slots)
1236                         continue;
1237
1238                 calgary_disable_translation(dev);
1239                 calgary_free_bus(dev);
1240                 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
1241                 dev->dev.archdata.dma_ops = NULL;
1242         } while (1);
1243
1244         return ret;
1245 }
1246
1247 static inline int __init determine_tce_table_size(u64 ram)
1248 {
1249         int ret;
1250
1251         if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
1252                 return specified_table_size;
1253
1254         /*
1255          * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
1256          * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
1257          * larger table size has twice as many entries, so shift the
1258          * max ram address by 13 to divide by 8K and then look at the
1259          * order of the result to choose between 0-7.
1260          */
1261         ret = get_order(ram >> 13);
1262         if (ret > TCE_TABLE_SIZE_8M)
1263                 ret = TCE_TABLE_SIZE_8M;
1264
1265         return ret;
1266 }
1267
1268 static int __init build_detail_arrays(void)
1269 {
1270         unsigned long ptr;
1271         unsigned numnodes, i;
1272         int scal_detail_size, rio_detail_size;
1273
1274         numnodes = rio_table_hdr->num_scal_dev;
1275         if (numnodes > MAX_NUMNODES){
1276                 printk(KERN_WARNING
1277                         "Calgary: MAX_NUMNODES too low! Defined as %d, "
1278                         "but system has %d nodes.\n",
1279                         MAX_NUMNODES, numnodes);
1280                 return -ENODEV;
1281         }
1282
1283         switch (rio_table_hdr->version){
1284         case 2:
1285                 scal_detail_size = 11;
1286                 rio_detail_size = 13;
1287                 break;
1288         case 3:
1289                 scal_detail_size = 12;
1290                 rio_detail_size = 15;
1291                 break;
1292         default:
1293                 printk(KERN_WARNING
1294                        "Calgary: Invalid Rio Grande Table Version: %d\n",
1295                        rio_table_hdr->version);
1296                 return -EPROTO;
1297         }
1298
1299         ptr = ((unsigned long)rio_table_hdr) + 3;
1300         for (i = 0; i < numnodes; i++, ptr += scal_detail_size)
1301                 scal_devs[i] = (struct scal_detail *)ptr;
1302
1303         for (i = 0; i < rio_table_hdr->num_rio_dev;
1304                     i++, ptr += rio_detail_size)
1305                 rio_devs[i] = (struct rio_detail *)ptr;
1306
1307         return 0;
1308 }
1309
1310 static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev)
1311 {
1312         int dev;
1313         u32 val;
1314
1315         if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) {
1316                 /*
1317                  * FIXME: properly scan for devices accross the
1318                  * PCI-to-PCI bridge on every CalIOC2 port.
1319                  */
1320                 return 1;
1321         }
1322
1323         for (dev = 1; dev < 8; dev++) {
1324                 val = read_pci_config(bus, dev, 0, 0);
1325                 if (val != 0xffffffff)
1326                         break;
1327         }
1328         return (val != 0xffffffff);
1329 }
1330
1331 /*
1332  * calgary_init_bitmap_from_tce_table():
1333  * Funtion for kdump case. In the second/kdump kernel initialize
1334  * the bitmap based on the tce table entries obtained from first kernel
1335  */
1336 static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl)
1337 {
1338         u64 *tp;
1339         unsigned int index;
1340         tp = ((u64 *)tbl->it_base);
1341         for (index = 0 ; index < tbl->it_size; index++) {
1342                 if (*tp != 0x0)
1343                         set_bit(index, tbl->it_map);
1344                 tp++;
1345         }
1346 }
1347
1348 /*
1349  * get_tce_space_from_tar():
1350  * Function for kdump case. Get the tce tables from first kernel
1351  * by reading the contents of the base adress register of calgary iommu
1352  */
1353 static void __init get_tce_space_from_tar(void)
1354 {
1355         int bus;
1356         void __iomem *target;
1357         unsigned long tce_space;
1358
1359         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1360                 struct calgary_bus_info *info = &bus_info[bus];
1361                 unsigned short pci_device;
1362                 u32 val;
1363
1364                 val = read_pci_config(bus, 0, 0, 0);
1365                 pci_device = (val & 0xFFFF0000) >> 16;
1366
1367                 if (!is_cal_pci_dev(pci_device))
1368                         continue;
1369                 if (info->translation_disabled)
1370                         continue;
1371
1372                 if (calgary_bus_has_devices(bus, pci_device) ||
1373                                                 translate_empty_slots) {
1374                         target = calgary_reg(bus_info[bus].bbar,
1375                                                 tar_offset(bus));
1376                         tce_space = be64_to_cpu(readq(target));
1377                         tce_space = tce_space & TAR_SW_BITS;
1378
1379                         tce_space = tce_space & (~specified_table_size);
1380                         info->tce_space = (u64 *)__va(tce_space);
1381                 }
1382         }
1383         return;
1384 }
1385
1386 void __init detect_calgary(void)
1387 {
1388         int bus;
1389         void *tbl;
1390         int calgary_found = 0;
1391         unsigned long ptr;
1392         unsigned int offset, prev_offset;
1393         int ret;
1394
1395         /*
1396          * if the user specified iommu=off or iommu=soft or we found
1397          * another HW IOMMU already, bail out.
1398          */
1399         if (swiotlb || no_iommu || iommu_detected)
1400                 return;
1401
1402         if (!use_calgary)
1403                 return;
1404
1405         if (!early_pci_allowed())
1406                 return;
1407
1408         printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n");
1409
1410         ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1411
1412         rio_table_hdr = NULL;
1413         prev_offset = 0;
1414         offset = 0x180;
1415         /*
1416          * The next offset is stored in the 1st word.
1417          * Only parse up until the offset increases:
1418          */
1419         while (offset > prev_offset) {
1420                 /* The block id is stored in the 2nd word */
1421                 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1422                         /* set the pointer past the offset & block id */
1423                         rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1424                         break;
1425                 }
1426                 prev_offset = offset;
1427                 offset = *((unsigned short *)(ptr + offset));
1428         }
1429         if (!rio_table_hdr) {
1430                 printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table "
1431                        "in EBDA - bailing!\n");
1432                 return;
1433         }
1434
1435         ret = build_detail_arrays();
1436         if (ret) {
1437                 printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret);
1438                 return;
1439         }
1440
1441         specified_table_size = determine_tce_table_size((is_kdump_kernel() ?
1442                                         saved_max_pfn : max_pfn) * PAGE_SIZE);
1443
1444         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1445                 struct calgary_bus_info *info = &bus_info[bus];
1446                 unsigned short pci_device;
1447                 u32 val;
1448
1449                 val = read_pci_config(bus, 0, 0, 0);
1450                 pci_device = (val & 0xFFFF0000) >> 16;
1451
1452                 if (!is_cal_pci_dev(pci_device))
1453                         continue;
1454
1455                 if (info->translation_disabled)
1456                         continue;
1457
1458                 if (calgary_bus_has_devices(bus, pci_device) ||
1459                     translate_empty_slots) {
1460                         /*
1461                          * If it is kdump kernel, find and use tce tables
1462                          * from first kernel, else allocate tce tables here
1463                          */
1464                         if (!is_kdump_kernel()) {
1465                                 tbl = alloc_tce_table();
1466                                 if (!tbl)
1467                                         goto cleanup;
1468                                 info->tce_space = tbl;
1469                         }
1470                         calgary_found = 1;
1471                 }
1472         }
1473
1474         printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n",
1475                calgary_found ? "found" : "not found");
1476
1477         if (calgary_found) {
1478                 iommu_detected = 1;
1479                 calgary_detected = 1;
1480                 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1481                 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, "
1482                        "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size,
1483                        debugging ? "enabled" : "disabled");
1484
1485                 /* swiotlb for devices that aren't behind the Calgary. */
1486                 if (max_pfn > MAX_DMA32_PFN)
1487                         swiotlb = 1;
1488         }
1489         return;
1490
1491 cleanup:
1492         for (--bus; bus >= 0; --bus) {
1493                 struct calgary_bus_info *info = &bus_info[bus];
1494
1495                 if (info->tce_space)
1496                         free_tce_table(info->tce_space);
1497         }
1498 }
1499
1500 int __init calgary_iommu_init(void)
1501 {
1502         int ret;
1503
1504         if (no_iommu || (swiotlb && !calgary_detected))
1505                 return -ENODEV;
1506
1507         if (!calgary_detected)
1508                 return -ENODEV;
1509
1510         /* ok, we're trying to use Calgary - let's roll */
1511         printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1512
1513         ret = calgary_init();
1514         if (ret) {
1515                 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1516                        "falling back to no_iommu\n", ret);
1517                 return ret;
1518         }
1519
1520         force_iommu = 1;
1521         bad_dma_address = 0x0;
1522         /* dma_ops is set to swiotlb or nommu */
1523         if (!dma_ops)
1524                 dma_ops = &nommu_dma_ops;
1525
1526         return 0;
1527 }
1528
1529 static int __init calgary_parse_options(char *p)
1530 {
1531         unsigned int bridge;
1532         size_t len;
1533         char* endp;
1534
1535         while (*p) {
1536                 if (!strncmp(p, "64k", 3))
1537                         specified_table_size = TCE_TABLE_SIZE_64K;
1538                 else if (!strncmp(p, "128k", 4))
1539                         specified_table_size = TCE_TABLE_SIZE_128K;
1540                 else if (!strncmp(p, "256k", 4))
1541                         specified_table_size = TCE_TABLE_SIZE_256K;
1542                 else if (!strncmp(p, "512k", 4))
1543                         specified_table_size = TCE_TABLE_SIZE_512K;
1544                 else if (!strncmp(p, "1M", 2))
1545                         specified_table_size = TCE_TABLE_SIZE_1M;
1546                 else if (!strncmp(p, "2M", 2))
1547                         specified_table_size = TCE_TABLE_SIZE_2M;
1548                 else if (!strncmp(p, "4M", 2))
1549                         specified_table_size = TCE_TABLE_SIZE_4M;
1550                 else if (!strncmp(p, "8M", 2))
1551                         specified_table_size = TCE_TABLE_SIZE_8M;
1552
1553                 len = strlen("translate_empty_slots");
1554                 if (!strncmp(p, "translate_empty_slots", len))
1555                         translate_empty_slots = 1;
1556
1557                 len = strlen("disable");
1558                 if (!strncmp(p, "disable", len)) {
1559                         p += len;
1560                         if (*p == '=')
1561                                 ++p;
1562                         if (*p == '\0')
1563                                 break;
1564                         bridge = simple_strtol(p, &endp, 0);
1565                         if (p == endp)
1566                                 break;
1567
1568                         if (bridge < MAX_PHB_BUS_NUM) {
1569                                 printk(KERN_INFO "Calgary: disabling "
1570                                        "translation for PHB %#x\n", bridge);
1571                                 bus_info[bridge].translation_disabled = 1;
1572                         }
1573                 }
1574
1575                 p = strpbrk(p, ",");
1576                 if (!p)
1577                         break;
1578
1579                 p++; /* skip ',' */
1580         }
1581         return 1;
1582 }
1583 __setup("calgary=", calgary_parse_options);
1584
1585 static void __init calgary_fixup_one_tce_space(struct pci_dev *dev)
1586 {
1587         struct iommu_table *tbl;
1588         unsigned int npages;
1589         int i;
1590
1591         tbl = pci_iommu(dev->bus);
1592
1593         for (i = 0; i < 4; i++) {
1594                 struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i];
1595
1596                 /* Don't give out TCEs that map MEM resources */
1597                 if (!(r->flags & IORESOURCE_MEM))
1598                         continue;
1599
1600                 /* 0-based? we reserve the whole 1st MB anyway */
1601                 if (!r->start)
1602                         continue;
1603
1604                 /* cover the whole region */
1605                 npages = (r->end - r->start) >> PAGE_SHIFT;
1606                 npages++;
1607
1608                 iommu_range_reserve(tbl, r->start, npages);
1609         }
1610 }
1611
1612 static int __init calgary_fixup_tce_spaces(void)
1613 {
1614         struct pci_dev *dev = NULL;
1615         struct calgary_bus_info *info;
1616
1617         if (no_iommu || swiotlb || !calgary_detected)
1618                 return -ENODEV;
1619
1620         printk(KERN_DEBUG "Calgary: fixing up tce spaces\n");
1621
1622         do {
1623                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1624                 if (!dev)
1625                         break;
1626                 if (!is_cal_pci_dev(dev->device))
1627                         continue;
1628
1629                 info = &bus_info[dev->bus->number];
1630                 if (info->translation_disabled)
1631                         continue;
1632
1633                 if (!info->tce_space)
1634                         continue;
1635
1636                 calgary_fixup_one_tce_space(dev);
1637
1638         } while (1);
1639
1640         return 0;
1641 }
1642
1643 /*
1644  * We need to be call after pcibios_assign_resources (fs_initcall level)
1645  * and before device_initcall.
1646  */
1647 rootfs_initcall(calgary_fixup_tce_spaces);