git.oblomov.eu Git - linux-2.6/blob - drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33
  34 /* Really want an OS-independent resettable timer.  Would like to have
  35  * this loop run for (eg) 3 sec, but have the timer reset every time
  36  * the head pointer changes, so that EBUSY only happens if the ring
  37  * actually stalls for (eg) 3 seconds.
  38  */
  39 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
  40 {
  41         drm_i915_private_t *dev_priv = dev->dev_private;
  42         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  43         u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD;
  44         u32 last_acthd = I915_READ(acthd_reg);
  45         u32 acthd;
  46         u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  47         int i;
  48
  49         for (i = 0; i < 100000; i++) {
  50                 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  51                 acthd = I915_READ(acthd_reg);
  52                 ring->space = ring->head - (ring->tail + 8);
  53                 if (ring->space < 0)
  54                         ring->space += ring->Size;
  55                 if (ring->space >= n)
  56                         return 0;
  57
  58                 if (dev_priv->sarea_priv)
  59                         dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
  60
  61                 if (ring->head != last_head)
  62                         i = 0;
  63                 if (acthd != last_acthd)
  64                         i = 0;
  65
  66                 last_head = ring->head;
  67                 last_acthd = acthd;
  68                 msleep_interruptible(10);
  69
  70         }
  71
  72         return -EBUSY;
  73 }
  74
  75 /**
  76  * Sets up the hardware status page for devices that need a physical address
  77  * in the register.
  78  */
  79 static int i915_init_phys_hws(struct drm_device *dev)
  80 {
  81         drm_i915_private_t *dev_priv = dev->dev_private;
  82         /* Program Hardware Status Page */
  83         dev_priv->status_page_dmah =
  84                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
  85
  86         if (!dev_priv->status_page_dmah) {
  87                 DRM_ERROR("Can not allocate hardware status page\n");
  88                 return -ENOMEM;
  89         }
  90         dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
  91         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
  92
  93         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
  94
  95         I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
  96         DRM_DEBUG("Enabled hardware status page\n");
  97         return 0;
  98 }
  99
 100 /**
 101  * Frees the hardware status page, whether it's a physical address or a virtual
 102  * address set up by the X Server.
 103  */
 104 static void i915_free_hws(struct drm_device *dev)
 105 {
 106         drm_i915_private_t *dev_priv = dev->dev_private;
 107         if (dev_priv->status_page_dmah) {
 108                 drm_pci_free(dev, dev_priv->status_page_dmah);
 109                 dev_priv->status_page_dmah = NULL;
 110         }
 111
 112         if (dev_priv->status_gfx_addr) {
 113                 dev_priv->status_gfx_addr = 0;
 114                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
 115         }
 116
 117         /* Need to rewrite hardware status page */
 118         I915_WRITE(HWS_PGA, 0x1ffff000);
 119 }
 120
 121 void i915_kernel_lost_context(struct drm_device * dev)
 122 {
 123         drm_i915_private_t *dev_priv = dev->dev_private;
 124         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
 125
 126         ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 127         ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
 128         ring->space = ring->head - (ring->tail + 8);
 129         if (ring->space < 0)
 130                 ring->space += ring->Size;
 131
 132         if (ring->head == ring->tail && dev_priv->sarea_priv)
 133                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 134 }
 135
 136 static int i915_dma_cleanup(struct drm_device * dev)
 137 {
 138         drm_i915_private_t *dev_priv = dev->dev_private;
 139         /* Make sure interrupts are disabled here because the uninstall ioctl
 140          * may not have been called from userspace and after dev_private
 141          * is freed, it's too late.
 142          */
 143         if (dev->irq_enabled)
 144                 drm_irq_uninstall(dev);
 145
 146         if (dev_priv->ring.virtual_start) {
 147                 drm_core_ioremapfree(&dev_priv->ring.map, dev);
 148                 dev_priv->ring.virtual_start = NULL;
 149                 dev_priv->ring.map.handle = NULL;
 150                 dev_priv->ring.map.size = 0;
 151         }
 152
 153         /* Clear the HWS virtual address at teardown */
 154         if (I915_NEED_GFX_HWS(dev))
 155                 i915_free_hws(dev);
 156
 157         return 0;
 158 }
 159
 160 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 161 {
 162         drm_i915_private_t *dev_priv = dev->dev_private;
 163
 164         dev_priv->sarea = drm_getsarea(dev);
 165         if (!dev_priv->sarea) {
 166                 DRM_ERROR("can not find sarea!\n");
 167                 i915_dma_cleanup(dev);
 168                 return -EINVAL;
 169         }
 170
 171         dev_priv->sarea_priv = (drm_i915_sarea_t *)
 172             ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
 173
 174         if (init->ring_size != 0) {
 175                 if (dev_priv->ring.ring_obj != NULL) {
 176                         i915_dma_cleanup(dev);
 177                         DRM_ERROR("Client tried to initialize ringbuffer in "
 178                                   "GEM mode\n");
 179                         return -EINVAL;
 180                 }
 181
 182                 dev_priv->ring.Size = init->ring_size;
 183                 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
 184
 185                 dev_priv->ring.map.offset = init->ring_start;
 186                 dev_priv->ring.map.size = init->ring_size;
 187                 dev_priv->ring.map.type = 0;
 188                 dev_priv->ring.map.flags = 0;
 189                 dev_priv->ring.map.mtrr = 0;
 190
 191                 drm_core_ioremap(&dev_priv->ring.map, dev);
 192
 193                 if (dev_priv->ring.map.handle == NULL) {
 194                         i915_dma_cleanup(dev);
 195                         DRM_ERROR("can not ioremap virtual address for"
 196                                   " ring buffer\n");
 197                         return -ENOMEM;
 198                 }
 199         }
 200
 201         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
 202
 203         dev_priv->cpp = init->cpp;
 204         dev_priv->back_offset = init->back_offset;
 205         dev_priv->front_offset = init->front_offset;
 206         dev_priv->current_page = 0;
 207         dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 208
 209         /* Allow hardware batchbuffers unless told otherwise.
 210          */
 211         dev_priv->allow_batchbuffer = 1;
 212
 213         return 0;
 214 }
 215
 216 static int i915_dma_resume(struct drm_device * dev)
 217 {
 218         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 219
 220         DRM_DEBUG("%s\n", __func__);
 221
 222         if (!dev_priv->sarea) {
 223                 DRM_ERROR("can not find sarea!\n");
 224                 return -EINVAL;
 225         }
 226
 227         if (dev_priv->ring.map.handle == NULL) {
 228                 DRM_ERROR("can not ioremap virtual address for"
 229                           " ring buffer\n");
 230                 return -ENOMEM;
 231         }
 232
 233         /* Program Hardware Status Page */
 234         if (!dev_priv->hw_status_page) {
 235                 DRM_ERROR("Can not find hardware status page\n");
 236                 return -EINVAL;
 237         }
 238         DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
 239
 240         if (dev_priv->status_gfx_addr != 0)
 241                 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
 242         else
 243                 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
 244         DRM_DEBUG("Enabled hardware status page\n");
 245
 246         return 0;
 247 }
 248
 249 static int i915_dma_init(struct drm_device *dev, void *data,
 250                          struct drm_file *file_priv)
 251 {
 252         drm_i915_init_t *init = data;
 253         int retcode = 0;
 254
 255         switch (init->func) {
 256         case I915_INIT_DMA:
 257                 retcode = i915_initialize(dev, init);
 258                 break;
 259         case I915_CLEANUP_DMA:
 260                 retcode = i915_dma_cleanup(dev);
 261                 break;
 262         case I915_RESUME_DMA:
 263                 retcode = i915_dma_resume(dev);
 264                 break;
 265         default:
 266                 retcode = -EINVAL;
 267                 break;
 268         }
 269
 270         return retcode;
 271 }
 272
 273 /* Implement basically the same security restrictions as hardware does
 274  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 275  *
 276  * Most of the calculations below involve calculating the size of a
 277  * particular instruction.  It's important to get the size right as
 278  * that tells us where the next instruction to check is.  Any illegal
 279  * instruction detected will be given a size of zero, which is a
 280  * signal to abort the rest of the buffer.
 281  */
 282 static int do_validate_cmd(int cmd)
 283 {
 284         switch (((cmd >> 29) & 0x7)) {
 285         case 0x0:
 286                 switch ((cmd >> 23) & 0x3f) {
 287                 case 0x0:
 288                         return 1;       /* MI_NOOP */
 289                 case 0x4:
 290                         return 1;       /* MI_FLUSH */
 291                 default:
 292                         return 0;       /* disallow everything else */
 293                 }
 294                 break;
 295         case 0x1:
 296                 return 0;       /* reserved */
 297         case 0x2:
 298                 return (cmd & 0xff) + 2;        /* 2d commands */
 299         case 0x3:
 300                 if (((cmd >> 24) & 0x1f) <= 0x18)
 301                         return 1;
 302
 303                 switch ((cmd >> 24) & 0x1f) {
 304                 case 0x1c:
 305                         return 1;
 306                 case 0x1d:
 307                         switch ((cmd >> 16) & 0xff) {
 308                         case 0x3:
 309                                 return (cmd & 0x1f) + 2;
 310                         case 0x4:
 311                                 return (cmd & 0xf) + 2;
 312                         default:
 313                                 return (cmd & 0xffff) + 2;
 314                         }
 315                 case 0x1e:
 316                         if (cmd & (1 << 23))
 317                                 return (cmd & 0xffff) + 1;
 318                         else
 319                                 return 1;
 320                 case 0x1f:
 321                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 322                                 return (cmd & 0x1ffff) + 2;
 323                         else if (cmd & (1 << 17))       /* indirect random */
 324                                 if ((cmd & 0xffff) == 0)
 325                                         return 0;       /* unknown length, too hard */
 326                                 else
 327                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 328                         else
 329                                 return 2;       /* indirect sequential */
 330                 default:
 331                         return 0;
 332                 }
 333         default:
 334                 return 0;
 335         }
 336
 337         return 0;
 338 }
 339
 340 static int validate_cmd(int cmd)
 341 {
 342         int ret = do_validate_cmd(cmd);
 343
 344 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 345
 346         return ret;
 347 }
 348
 349 static int i915_emit_cmds(struct drm_device * dev, int __user * buffer, int dwords)
 350 {
 351         drm_i915_private_t *dev_priv = dev->dev_private;
 352         int i;
 353         RING_LOCALS;
 354
 355         if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
 356                 return -EINVAL;
 357
 358         BEGIN_LP_RING((dwords+1)&~1);
 359
 360         for (i = 0; i < dwords;) {
 361                 int cmd, sz;
 362
 363                 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
 364                         return -EINVAL;
 365
 366                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 367                         return -EINVAL;
 368
 369                 OUT_RING(cmd);
 370
 371                 while (++i, --sz) {
 372                         if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
 373                                                          sizeof(cmd))) {
 374                                 return -EINVAL;
 375                         }
 376                         OUT_RING(cmd);
 377                 }
 378         }
 379
 380         if (dwords & 1)
 381                 OUT_RING(0);
 382
 383         ADVANCE_LP_RING();
 384
 385         return 0;
 386 }
 387
 388 int
 389 i915_emit_box(struct drm_device *dev,
 390               struct drm_clip_rect __user *boxes,
 391               int i, int DR1, int DR4)
 392 {
 393         drm_i915_private_t *dev_priv = dev->dev_private;
 394         struct drm_clip_rect box;
 395         RING_LOCALS;
 396
 397         if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
 398                 return -EFAULT;
 399         }
 400
 401         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 402                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 403                           box.x1, box.y1, box.x2, box.y2);
 404                 return -EINVAL;
 405         }
 406
 407         if (IS_I965G(dev)) {
 408                 BEGIN_LP_RING(4);
 409                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 410                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 411                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 412                 OUT_RING(DR4);
 413                 ADVANCE_LP_RING();
 414         } else {
 415                 BEGIN_LP_RING(6);
 416                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 417                 OUT_RING(DR1);
 418                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 419                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 420                 OUT_RING(DR4);
 421                 OUT_RING(0);
 422                 ADVANCE_LP_RING();
 423         }
 424
 425         return 0;
 426 }
 427
 428 /* XXX: Emitting the counter should really be moved to part of the IRQ
 429  * emit. For now, do it in both places:
 430  */
 431
 432 static void i915_emit_breadcrumb(struct drm_device *dev)
 433 {
 434         drm_i915_private_t *dev_priv = dev->dev_private;
 435         RING_LOCALS;
 436
 437         dev_priv->counter++;
 438         if (dev_priv->counter > 0x7FFFFFFFUL)
 439                 dev_priv->counter = 0;
 440         if (dev_priv->sarea_priv)
 441                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
 442
 443         BEGIN_LP_RING(4);
 444         OUT_RING(MI_STORE_DWORD_INDEX);
 445         OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
 446         OUT_RING(dev_priv->counter);
 447         OUT_RING(0);
 448         ADVANCE_LP_RING();
 449 }
 450
 451 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 452                                    drm_i915_cmdbuffer_t * cmd)
 453 {
 454         int nbox = cmd->num_cliprects;
 455         int i = 0, count, ret;
 456
 457         if (cmd->sz & 0x3) {
 458                 DRM_ERROR("alignment");
 459                 return -EINVAL;
 460         }
 461
 462         i915_kernel_lost_context(dev);
 463
 464         count = nbox ? nbox : 1;
 465
 466         for (i = 0; i < count; i++) {
 467                 if (i < nbox) {
 468                         ret = i915_emit_box(dev, cmd->cliprects, i,
 469                                             cmd->DR1, cmd->DR4);
 470                         if (ret)
 471                                 return ret;
 472                 }
 473
 474                 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
 475                 if (ret)
 476                         return ret;
 477         }
 478
 479         i915_emit_breadcrumb(dev);
 480         return 0;
 481 }
 482
 483 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 484                                      drm_i915_batchbuffer_t * batch)
 485 {
 486         drm_i915_private_t *dev_priv = dev->dev_private;
 487         struct drm_clip_rect __user *boxes = batch->cliprects;
 488         int nbox = batch->num_cliprects;
 489         int i = 0, count;
 490         RING_LOCALS;
 491
 492         if ((batch->start | batch->used) & 0x7) {
 493                 DRM_ERROR("alignment");
 494                 return -EINVAL;
 495         }
 496
 497         i915_kernel_lost_context(dev);
 498
 499         count = nbox ? nbox : 1;
 500
 501         for (i = 0; i < count; i++) {
 502                 if (i < nbox) {
 503                         int ret = i915_emit_box(dev, boxes, i,
 504                                                 batch->DR1, batch->DR4);
 505                         if (ret)
 506                                 return ret;
 507                 }
 508
 509                 if (!IS_I830(dev) && !IS_845G(dev)) {
 510                         BEGIN_LP_RING(2);
 511                         if (IS_I965G(dev)) {
 512                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 513                                 OUT_RING(batch->start);
 514                         } else {
 515                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 516                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 517                         }
 518                         ADVANCE_LP_RING();
 519                 } else {
 520                         BEGIN_LP_RING(4);
 521                         OUT_RING(MI_BATCH_BUFFER);
 522                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 523                         OUT_RING(batch->start + batch->used - 4);
 524                         OUT_RING(0);
 525                         ADVANCE_LP_RING();
 526                 }
 527         }
 528
 529         i915_emit_breadcrumb(dev);
 530
 531         return 0;
 532 }
 533
 534 static int i915_dispatch_flip(struct drm_device * dev)
 535 {
 536         drm_i915_private_t *dev_priv = dev->dev_private;
 537         RING_LOCALS;
 538
 539         if (!dev_priv->sarea_priv)
 540                 return -EINVAL;
 541
 542         DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
 543                   __func__,
 544                   dev_priv->current_page,
 545                   dev_priv->sarea_priv->pf_current_page);
 546
 547         i915_kernel_lost_context(dev);
 548
 549         BEGIN_LP_RING(2);
 550         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 551         OUT_RING(0);
 552         ADVANCE_LP_RING();
 553
 554         BEGIN_LP_RING(6);
 555         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 556         OUT_RING(0);
 557         if (dev_priv->current_page == 0) {
 558                 OUT_RING(dev_priv->back_offset);
 559                 dev_priv->current_page = 1;
 560         } else {
 561                 OUT_RING(dev_priv->front_offset);
 562                 dev_priv->current_page = 0;
 563         }
 564         OUT_RING(0);
 565         ADVANCE_LP_RING();
 566
 567         BEGIN_LP_RING(2);
 568         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 569         OUT_RING(0);
 570         ADVANCE_LP_RING();
 571
 572         dev_priv->sarea_priv->last_enqueue = dev_priv->counter++;
 573
 574         BEGIN_LP_RING(4);
 575         OUT_RING(MI_STORE_DWORD_INDEX);
 576         OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
 577         OUT_RING(dev_priv->counter);
 578         OUT_RING(0);
 579         ADVANCE_LP_RING();
 580
 581         dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 582         return 0;
 583 }
 584
 585 static int i915_quiescent(struct drm_device * dev)
 586 {
 587         drm_i915_private_t *dev_priv = dev->dev_private;
 588
 589         i915_kernel_lost_context(dev);
 590         return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__);
 591 }
 592
 593 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 594                             struct drm_file *file_priv)
 595 {
 596         int ret;
 597
 598         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 599
 600         mutex_lock(&dev->struct_mutex);
 601         ret = i915_quiescent(dev);
 602         mutex_unlock(&dev->struct_mutex);
 603
 604         return ret;
 605 }
 606
 607 static int i915_batchbuffer(struct drm_device *dev, void *data,
 608                             struct drm_file *file_priv)
 609 {
 610         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 611         u32 *hw_status = dev_priv->hw_status_page;
 612         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 613             dev_priv->sarea_priv;
 614         drm_i915_batchbuffer_t *batch = data;
 615         int ret;
 616
 617         if (!dev_priv->allow_batchbuffer) {
 618                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 619                 return -EINVAL;
 620         }
 621
 622         DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
 623                   batch->start, batch->used, batch->num_cliprects);
 624
 625         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 626
 627         if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects,
 628                                                        batch->num_cliprects *
 629                                                        sizeof(struct drm_clip_rect)))
 630                 return -EFAULT;
 631
 632         mutex_lock(&dev->struct_mutex);
 633         ret = i915_dispatch_batchbuffer(dev, batch);
 634         mutex_unlock(&dev->struct_mutex);
 635
 636         if (sarea_priv)
 637                 sarea_priv->last_dispatch = (int)hw_status[5];
 638         return ret;
 639 }
 640
 641 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 642                           struct drm_file *file_priv)
 643 {
 644         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 645         u32 *hw_status = dev_priv->hw_status_page;
 646         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 647             dev_priv->sarea_priv;
 648         drm_i915_cmdbuffer_t *cmdbuf = data;
 649         int ret;
 650
 651         DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 652                   cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 653
 654         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 655
 656         if (cmdbuf->num_cliprects &&
 657             DRM_VERIFYAREA_READ(cmdbuf->cliprects,
 658                                 cmdbuf->num_cliprects *
 659                                 sizeof(struct drm_clip_rect))) {
 660                 DRM_ERROR("Fault accessing cliprects\n");
 661                 return -EFAULT;
 662         }
 663
 664         mutex_lock(&dev->struct_mutex);
 665         ret = i915_dispatch_cmdbuffer(dev, cmdbuf);
 666         mutex_unlock(&dev->struct_mutex);
 667         if (ret) {
 668                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 669                 return ret;
 670         }
 671
 672         if (sarea_priv)
 673                 sarea_priv->last_dispatch = (int)hw_status[5];
 674         return 0;
 675 }
 676
 677 static int i915_flip_bufs(struct drm_device *dev, void *data,
 678                           struct drm_file *file_priv)
 679 {
 680         int ret;
 681
 682         DRM_DEBUG("%s\n", __func__);
 683
 684         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 685
 686         mutex_lock(&dev->struct_mutex);
 687         ret = i915_dispatch_flip(dev);
 688         mutex_unlock(&dev->struct_mutex);
 689
 690         return ret;
 691 }
 692
 693 static int i915_getparam(struct drm_device *dev, void *data,
 694                          struct drm_file *file_priv)
 695 {
 696         drm_i915_private_t *dev_priv = dev->dev_private;
 697         drm_i915_getparam_t *param = data;
 698         int value;
 699
 700         if (!dev_priv) {
 701                 DRM_ERROR("called with no initialization\n");
 702                 return -EINVAL;
 703         }
 704
 705         switch (param->param) {
 706         case I915_PARAM_IRQ_ACTIVE:
 707                 value = dev->pdev->irq ? 1 : 0;
 708                 break;
 709         case I915_PARAM_ALLOW_BATCHBUFFER:
 710                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 711                 break;
 712         case I915_PARAM_LAST_DISPATCH:
 713                 value = READ_BREADCRUMB(dev_priv);
 714                 break;
 715         case I915_PARAM_CHIPSET_ID:
 716                 value = dev->pci_device;
 717                 break;
 718         case I915_PARAM_HAS_GEM:
 719                 value = 1;
 720                 break;
 721         default:
 722                 DRM_ERROR("Unknown parameter %d\n", param->param);
 723                 return -EINVAL;
 724         }
 725
 726         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 727                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 728                 return -EFAULT;
 729         }
 730
 731         return 0;
 732 }
 733
 734 static int i915_setparam(struct drm_device *dev, void *data,
 735                          struct drm_file *file_priv)
 736 {
 737         drm_i915_private_t *dev_priv = dev->dev_private;
 738         drm_i915_setparam_t *param = data;
 739
 740         if (!dev_priv) {
 741                 DRM_ERROR("called with no initialization\n");
 742                 return -EINVAL;
 743         }
 744
 745         switch (param->param) {
 746         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 747                 break;
 748         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 749                 dev_priv->tex_lru_log_granularity = param->value;
 750                 break;
 751         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 752                 dev_priv->allow_batchbuffer = param->value;
 753                 break;
 754         default:
 755                 DRM_ERROR("unknown parameter %d\n", param->param);
 756                 return -EINVAL;
 757         }
 758
 759         return 0;
 760 }
 761
 762 static int i915_set_status_page(struct drm_device *dev, void *data,
 763                                 struct drm_file *file_priv)
 764 {
 765         drm_i915_private_t *dev_priv = dev->dev_private;
 766         drm_i915_hws_addr_t *hws = data;
 767
 768         if (!I915_NEED_GFX_HWS(dev))
 769                 return -EINVAL;
 770
 771         if (!dev_priv) {
 772                 DRM_ERROR("called with no initialization\n");
 773                 return -EINVAL;
 774         }
 775
 776         printk(KERN_DEBUG "set status page addr 0x%08x\n", (u32)hws->addr);
 777
 778         dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
 779
 780         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
 781         dev_priv->hws_map.size = 4*1024;
 782         dev_priv->hws_map.type = 0;
 783         dev_priv->hws_map.flags = 0;
 784         dev_priv->hws_map.mtrr = 0;
 785
 786         drm_core_ioremap(&dev_priv->hws_map, dev);
 787         if (dev_priv->hws_map.handle == NULL) {
 788                 i915_dma_cleanup(dev);
 789                 dev_priv->status_gfx_addr = 0;
 790                 DRM_ERROR("can not ioremap virtual address for"
 791                                 " G33 hw status page\n");
 792                 return -ENOMEM;
 793         }
 794         dev_priv->hw_status_page = dev_priv->hws_map.handle;
 795
 796         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 797         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
 798         DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
 799                         dev_priv->status_gfx_addr);
 800         DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
 801         return 0;
 802 }
 803
 804 int i915_driver_load(struct drm_device *dev, unsigned long flags)
 805 {
 806         struct drm_i915_private *dev_priv = dev->dev_private;
 807         unsigned long base, size;
 808         int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1;
 809
 810         /* i915 has 4 more counters */
 811         dev->counters += 4;
 812         dev->types[6] = _DRM_STAT_IRQ;
 813         dev->types[7] = _DRM_STAT_PRIMARY;
 814         dev->types[8] = _DRM_STAT_SECONDARY;
 815         dev->types[9] = _DRM_STAT_DMA;
 816
 817         dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
 818         if (dev_priv == NULL)
 819                 return -ENOMEM;
 820
 821         memset(dev_priv, 0, sizeof(drm_i915_private_t));
 822
 823         dev->dev_private = (void *)dev_priv;
 824         dev_priv->dev = dev;
 825
 826         /* Add register map (needed for suspend/resume) */
 827         base = drm_get_resource_start(dev, mmio_bar);
 828         size = drm_get_resource_len(dev, mmio_bar);
 829
 830         dev_priv->regs = ioremap(base, size);
 831
 832         i915_gem_load(dev);
 833
 834         /* Init HWS */
 835         if (!I915_NEED_GFX_HWS(dev)) {
 836                 ret = i915_init_phys_hws(dev);
 837                 if (ret != 0)
 838                         return ret;
 839         }
 840
 841         /* On the 945G/GM, the chipset reports the MSI capability on the
 842          * integrated graphics even though the support isn't actually there
 843          * according to the published specs.  It doesn't appear to function
 844          * correctly in testing on 945G.
 845          * This may be a side effect of MSI having been made available for PEG
 846          * and the registers being closely associated.
 847          */
 848         if (!IS_I945G(dev) && !IS_I945GM(dev))
 849                 if (pci_enable_msi(dev->pdev))
 850                         DRM_ERROR("failed to enable MSI\n");
 851
 852         intel_opregion_init(dev);
 853
 854         spin_lock_init(&dev_priv->user_irq_lock);
 855
 856         return ret;
 857 }
 858
 859 int i915_driver_unload(struct drm_device *dev)
 860 {
 861         struct drm_i915_private *dev_priv = dev->dev_private;
 862
 863         if (dev->pdev->msi_enabled)
 864                 pci_disable_msi(dev->pdev);
 865
 866         i915_free_hws(dev);
 867
 868         if (dev_priv->regs != NULL)
 869                 iounmap(dev_priv->regs);
 870
 871         intel_opregion_free(dev);
 872
 873         drm_free(dev->dev_private, sizeof(drm_i915_private_t),
 874                  DRM_MEM_DRIVER);
 875
 876         return 0;
 877 }
 878
 879 int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
 880 {
 881         struct drm_i915_file_private *i915_file_priv;
 882
 883         DRM_DEBUG("\n");
 884         i915_file_priv = (struct drm_i915_file_private *)
 885             drm_alloc(sizeof(*i915_file_priv), DRM_MEM_FILES);
 886
 887         if (!i915_file_priv)
 888                 return -ENOMEM;
 889
 890         file_priv->driver_priv = i915_file_priv;
 891
 892         i915_file_priv->mm.last_gem_seqno = 0;
 893         i915_file_priv->mm.last_gem_throttle_seqno = 0;
 894
 895         return 0;
 896 }
 897
 898 void i915_driver_lastclose(struct drm_device * dev)
 899 {
 900         drm_i915_private_t *dev_priv = dev->dev_private;
 901
 902         if (!dev_priv)
 903                 return;
 904
 905         i915_gem_lastclose(dev);
 906
 907         if (dev_priv->agp_heap)
 908                 i915_mem_takedown(&(dev_priv->agp_heap));
 909
 910         i915_dma_cleanup(dev);
 911 }
 912
 913 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
 914 {
 915         drm_i915_private_t *dev_priv = dev->dev_private;
 916         i915_mem_release(dev, file_priv, dev_priv->agp_heap);
 917 }
 918
 919 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
 920 {
 921         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
 922
 923         drm_free(i915_file_priv, sizeof(*i915_file_priv), DRM_MEM_FILES);
 924 }
 925
 926 struct drm_ioctl_desc i915_ioctls[] = {
 927         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 928         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
 929         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
 930         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
 931         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
 932         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
 933         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
 934         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 935         DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
 936         DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
 937         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 938         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
 939         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
 940         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
 941         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
 942         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
 943         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH),
 944         DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 945         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
 946         DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
 947         DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
 948         DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH),
 949         DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
 950         DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 951         DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 952         DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
 953         DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0),
 954         DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0),
 955         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
 956         DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0),
 957         DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0),
 958         DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
 959         DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
 960 };
 961
 962 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
 963
 964 /**
 965  * Determine if the device really is AGP or not.
 966  *
 967  * All Intel graphics chipsets are treated as AGP, even if they are really
 968  * PCI-e.
 969  *
 970  * \param dev   The device to be tested.
 971  *
 972  * \returns
 973  * A value of 1 is always retured to indictate every i9x5 is AGP.
 974  */
 975 int i915_driver_device_is_agp(struct drm_device * dev)
 976 {
 977         return 1;
 978 }