git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/rt2x00/rt73usb.c

   1 /*
   2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt73usb
  23         Abstract: rt73usb device specific routines.
  24         Supported chipsets: rt2571W & rt2671.
  25  */
  26
  27 #include <linux/crc-itu-t.h>
  28 #include <linux/delay.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/init.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/usb.h>
  34
  35 #include "rt2x00.h"
  36 #include "rt2x00usb.h"
  37 #include "rt73usb.h"
  38
  39 /*
  40  * Register access.
  41  * All access to the CSR registers will go through the methods
  42  * rt73usb_register_read and rt73usb_register_write.
  43  * BBP and RF register require indirect register access,
  44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  45  * These indirect registers work with busy bits,
  46  * and we will try maximal REGISTER_BUSY_COUNT times to access
  47  * the register while taking a REGISTER_BUSY_DELAY us delay
  48  * between each attampt. When the busy bit is still set at that time,
  49  * the access attempt is considered to have failed,
  50  * and we will print an error.
  51  * The _lock versions must be used if you already hold the usb_cache_mutex
  52  */
  53 static inline void rt73usb_register_read(struct rt2x00_dev *rt2x00dev,
  54                                          const unsigned int offset, u32 *value)
  55 {
  56         __le32 reg;
  57         rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
  58                                       USB_VENDOR_REQUEST_IN, offset,
  59                                       &reg, sizeof(u32), REGISTER_TIMEOUT);
  60         *value = le32_to_cpu(reg);
  61 }
  62
  63 static inline void rt73usb_register_read_lock(struct rt2x00_dev *rt2x00dev,
  64                                               const unsigned int offset, u32 *value)
  65 {
  66         __le32 reg;
  67         rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_READ,
  68                                        USB_VENDOR_REQUEST_IN, offset,
  69                                        &reg, sizeof(u32), REGISTER_TIMEOUT);
  70         *value = le32_to_cpu(reg);
  71 }
  72
  73 static inline void rt73usb_register_multiread(struct rt2x00_dev *rt2x00dev,
  74                                               const unsigned int offset,
  75                                               void *value, const u32 length)
  76 {
  77         rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
  78                                       USB_VENDOR_REQUEST_IN, offset,
  79                                       value, length,
  80                                       REGISTER_TIMEOUT32(length));
  81 }
  82
  83 static inline void rt73usb_register_write(struct rt2x00_dev *rt2x00dev,
  84                                           const unsigned int offset, u32 value)
  85 {
  86         __le32 reg = cpu_to_le32(value);
  87         rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
  88                                       USB_VENDOR_REQUEST_OUT, offset,
  89                                       &reg, sizeof(u32), REGISTER_TIMEOUT);
  90 }
  91
  92 static inline void rt73usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
  93                                                const unsigned int offset, u32 value)
  94 {
  95         __le32 reg = cpu_to_le32(value);
  96         rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_WRITE,
  97                                        USB_VENDOR_REQUEST_OUT, offset,
  98                                       &reg, sizeof(u32), REGISTER_TIMEOUT);
  99 }
 100
 101 static inline void rt73usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
 102                                                const unsigned int offset,
 103                                                void *value, const u32 length)
 104 {
 105         rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
 106                                       USB_VENDOR_REQUEST_OUT, offset,
 107                                       value, length,
 108                                       REGISTER_TIMEOUT32(length));
 109 }
 110
 111 static u32 rt73usb_bbp_check(struct rt2x00_dev *rt2x00dev)
 112 {
 113         u32 reg;
 114         unsigned int i;
 115
 116         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 117                 rt73usb_register_read_lock(rt2x00dev, PHY_CSR3, &reg);
 118                 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
 119                         break;
 120                 udelay(REGISTER_BUSY_DELAY);
 121         }
 122
 123         return reg;
 124 }
 125
 126 static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
 127                               const unsigned int word, const u8 value)
 128 {
 129         u32 reg;
 130
 131         mutex_lock(&rt2x00dev->usb_cache_mutex);
 132
 133         /*
 134          * Wait until the BBP becomes ready.
 135          */
 136         reg = rt73usb_bbp_check(rt2x00dev);
 137         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY))
 138                 goto exit_fail;
 139
 140         /*
 141          * Write the data into the BBP.
 142          */
 143         reg = 0;
 144         rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
 145         rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
 146         rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
 147         rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
 148
 149         rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
 150         mutex_unlock(&rt2x00dev->usb_cache_mutex);
 151
 152         return;
 153
 154 exit_fail:
 155         mutex_unlock(&rt2x00dev->usb_cache_mutex);
 156
 157         ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
 158 }
 159
 160 static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
 161                              const unsigned int word, u8 *value)
 162 {
 163         u32 reg;
 164
 165         mutex_lock(&rt2x00dev->usb_cache_mutex);
 166
 167         /*
 168          * Wait until the BBP becomes ready.
 169          */
 170         reg = rt73usb_bbp_check(rt2x00dev);
 171         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY))
 172                 goto exit_fail;
 173
 174         /*
 175          * Write the request into the BBP.
 176          */
 177         reg = 0;
 178         rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
 179         rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
 180         rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
 181
 182         rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
 183
 184         /*
 185          * Wait until the BBP becomes ready.
 186          */
 187         reg = rt73usb_bbp_check(rt2x00dev);
 188         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY))
 189                 goto exit_fail;
 190
 191         *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
 192         mutex_unlock(&rt2x00dev->usb_cache_mutex);
 193
 194         return;
 195
 196 exit_fail:
 197         mutex_unlock(&rt2x00dev->usb_cache_mutex);
 198
 199         ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
 200         *value = 0xff;
 201 }
 202
 203 static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
 204                              const unsigned int word, const u32 value)
 205 {
 206         u32 reg;
 207         unsigned int i;
 208
 209         if (!word)
 210                 return;
 211
 212         mutex_lock(&rt2x00dev->usb_cache_mutex);
 213
 214         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 215                 rt73usb_register_read_lock(rt2x00dev, PHY_CSR4, &reg);
 216                 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
 217                         goto rf_write;
 218                 udelay(REGISTER_BUSY_DELAY);
 219         }
 220
 221         mutex_unlock(&rt2x00dev->usb_cache_mutex);
 222         ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
 223         return;
 224
 225 rf_write:
 226         reg = 0;
 227         rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
 228
 229         /*
 230          * RF5225 and RF2527 contain 21 bits per RF register value,
 231          * all others contain 20 bits.
 232          */
 233         rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
 234                            20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
 235                                  rt2x00_rf(&rt2x00dev->chip, RF2527)));
 236         rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
 237         rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
 238
 239         rt73usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
 240         rt2x00_rf_write(rt2x00dev, word, value);
 241         mutex_unlock(&rt2x00dev->usb_cache_mutex);
 242 }
 243
 244 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 245 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 246
 247 static void rt73usb_read_csr(struct rt2x00_dev *rt2x00dev,
 248                              const unsigned int word, u32 *data)
 249 {
 250         rt73usb_register_read(rt2x00dev, CSR_OFFSET(word), data);
 251 }
 252
 253 static void rt73usb_write_csr(struct rt2x00_dev *rt2x00dev,
 254                               const unsigned int word, u32 data)
 255 {
 256         rt73usb_register_write(rt2x00dev, CSR_OFFSET(word), data);
 257 }
 258
 259 static const struct rt2x00debug rt73usb_rt2x00debug = {
 260         .owner  = THIS_MODULE,
 261         .csr    = {
 262                 .read           = rt73usb_read_csr,
 263                 .write          = rt73usb_write_csr,
 264                 .word_size      = sizeof(u32),
 265                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 266         },
 267         .eeprom = {
 268                 .read           = rt2x00_eeprom_read,
 269                 .write          = rt2x00_eeprom_write,
 270                 .word_size      = sizeof(u16),
 271                 .word_count     = EEPROM_SIZE / sizeof(u16),
 272         },
 273         .bbp    = {
 274                 .read           = rt73usb_bbp_read,
 275                 .write          = rt73usb_bbp_write,
 276                 .word_size      = sizeof(u8),
 277                 .word_count     = BBP_SIZE / sizeof(u8),
 278         },
 279         .rf     = {
 280                 .read           = rt2x00_rf_read,
 281                 .write          = rt73usb_rf_write,
 282                 .word_size      = sizeof(u32),
 283                 .word_count     = RF_SIZE / sizeof(u32),
 284         },
 285 };
 286 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 287
 288 #ifdef CONFIG_RT73USB_LEDS
 289 static void rt73usb_brightness_set(struct led_classdev *led_cdev,
 290                                    enum led_brightness brightness)
 291 {
 292         struct rt2x00_led *led =
 293            container_of(led_cdev, struct rt2x00_led, led_dev);
 294         unsigned int enabled = brightness != LED_OFF;
 295         unsigned int a_mode =
 296             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 297         unsigned int bg_mode =
 298             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 299
 300         if (led->type == LED_TYPE_RADIO) {
 301                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 302                                    MCU_LEDCS_RADIO_STATUS, enabled);
 303
 304                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
 305                                             0, led->rt2x00dev->led_mcu_reg,
 306                                             REGISTER_TIMEOUT);
 307         } else if (led->type == LED_TYPE_ASSOC) {
 308                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 309                                    MCU_LEDCS_LINK_BG_STATUS, bg_mode);
 310                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 311                                    MCU_LEDCS_LINK_A_STATUS, a_mode);
 312
 313                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
 314                                             0, led->rt2x00dev->led_mcu_reg,
 315                                             REGISTER_TIMEOUT);
 316         } else if (led->type == LED_TYPE_QUALITY) {
 317                 /*
 318                  * The brightness is divided into 6 levels (0 - 5),
 319                  * this means we need to convert the brightness
 320                  * argument into the matching level within that range.
 321                  */
 322                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
 323                                             brightness / (LED_FULL / 6),
 324                                             led->rt2x00dev->led_mcu_reg,
 325                                             REGISTER_TIMEOUT);
 326         }
 327 }
 328
 329 static int rt73usb_blink_set(struct led_classdev *led_cdev,
 330                              unsigned long *delay_on,
 331                              unsigned long *delay_off)
 332 {
 333         struct rt2x00_led *led =
 334             container_of(led_cdev, struct rt2x00_led, led_dev);
 335         u32 reg;
 336
 337         rt73usb_register_read(led->rt2x00dev, MAC_CSR14, &reg);
 338         rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
 339         rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
 340         rt73usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
 341
 342         return 0;
 343 }
 344
 345 static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev,
 346                              struct rt2x00_led *led,
 347                              enum led_type type)
 348 {
 349         led->rt2x00dev = rt2x00dev;
 350         led->type = type;
 351         led->led_dev.brightness_set = rt73usb_brightness_set;
 352         led->led_dev.blink_set = rt73usb_blink_set;
 353         led->flags = LED_INITIALIZED;
 354 }
 355 #endif /* CONFIG_RT73USB_LEDS */
 356
 357 /*
 358  * Configuration handlers.
 359  */
 360 static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
 361                                      struct rt2x00lib_crypto *crypto,
 362                                      struct ieee80211_key_conf *key)
 363 {
 364         struct hw_key_entry key_entry;
 365         struct rt2x00_field32 field;
 366         int timeout;
 367         u32 mask;
 368         u32 reg;
 369
 370         if (crypto->cmd == SET_KEY) {
 371                 /*
 372                  * rt2x00lib can't determine the correct free
 373                  * key_idx for shared keys. We have 1 register
 374                  * with key valid bits. The goal is simple, read
 375                  * the register, if that is full we have no slots
 376                  * left.
 377                  * Note that each BSS is allowed to have up to 4
 378                  * shared keys, so put a mask over the allowed
 379                  * entries.
 380                  */
 381                 mask = (0xf << crypto->bssidx);
 382
 383                 rt73usb_register_read(rt2x00dev, SEC_CSR0, &reg);
 384                 reg &= mask;
 385
 386                 if (reg && reg == mask)
 387                         return -ENOSPC;
 388
 389                 key->hw_key_idx += reg ? (ffz(reg) - 1) : 0;
 390
 391                 /*
 392                  * Upload key to hardware
 393                  */
 394                 memcpy(key_entry.key, crypto->key,
 395                        sizeof(key_entry.key));
 396                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 397                        sizeof(key_entry.tx_mic));
 398                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 399                        sizeof(key_entry.rx_mic));
 400
 401                 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
 402                 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
 403                 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
 404                                                     USB_VENDOR_REQUEST_OUT, reg,
 405                                                     &key_entry,
 406                                                     sizeof(key_entry),
 407                                                     timeout);
 408
 409                 /*
 410                  * The cipher types are stored over 2 registers.
 411                  * bssidx 0 and 1 keys are stored in SEC_CSR1 and
 412                  * bssidx 1 and 2 keys are stored in SEC_CSR5.
 413                  * Using the correct defines correctly will cause overhead,
 414                  * so just calculate the correct offset.
 415                  */
 416                 if (key->hw_key_idx < 8) {
 417                         field.bit_offset = (3 * key->hw_key_idx);
 418                         field.bit_mask = 0x7 << field.bit_offset;
 419
 420                         rt73usb_register_read(rt2x00dev, SEC_CSR1, &reg);
 421                         rt2x00_set_field32(&reg, field, crypto->cipher);
 422                         rt73usb_register_write(rt2x00dev, SEC_CSR1, reg);
 423                 } else {
 424                         field.bit_offset = (3 * (key->hw_key_idx - 8));
 425                         field.bit_mask = 0x7 << field.bit_offset;
 426
 427                         rt73usb_register_read(rt2x00dev, SEC_CSR5, &reg);
 428                         rt2x00_set_field32(&reg, field, crypto->cipher);
 429                         rt73usb_register_write(rt2x00dev, SEC_CSR5, reg);
 430                 }
 431
 432                 /*
 433                  * The driver does not support the IV/EIV generation
 434                  * in hardware. However it doesn't support the IV/EIV
 435                  * inside the ieee80211 frame either, but requires it
 436                  * to be provided seperately for the descriptor.
 437                  * rt2x00lib will cut the IV/EIV data out of all frames
 438                  * given to us by mac80211, but we must tell mac80211
 439                  * to generate the IV/EIV data.
 440                  */
 441                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 442         }
 443
 444         /*
 445          * SEC_CSR0 contains only single-bit fields to indicate
 446          * a particular key is valid. Because using the FIELD32()
 447          * defines directly will cause a lot of overhead we use
 448          * a calculation to determine the correct bit directly.
 449          */
 450         mask = 1 << key->hw_key_idx;
 451
 452         rt73usb_register_read(rt2x00dev, SEC_CSR0, &reg);
 453         if (crypto->cmd == SET_KEY)
 454                 reg |= mask;
 455         else if (crypto->cmd == DISABLE_KEY)
 456                 reg &= ~mask;
 457         rt73usb_register_write(rt2x00dev, SEC_CSR0, reg);
 458
 459         return 0;
 460 }
 461
 462 static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 463                                        struct rt2x00lib_crypto *crypto,
 464                                        struct ieee80211_key_conf *key)
 465 {
 466         struct hw_pairwise_ta_entry addr_entry;
 467         struct hw_key_entry key_entry;
 468         int timeout;
 469         u32 mask;
 470         u32 reg;
 471
 472         if (crypto->cmd == SET_KEY) {
 473                 /*
 474                  * rt2x00lib can't determine the correct free
 475                  * key_idx for pairwise keys. We have 2 registers
 476                  * with key valid bits. The goal is simple, read
 477                  * the first register, if that is full move to
 478                  * the next register.
 479                  * When both registers are full, we drop the key,
 480                  * otherwise we use the first invalid entry.
 481                  */
 482                 rt73usb_register_read(rt2x00dev, SEC_CSR2, &reg);
 483                 if (reg && reg == ~0) {
 484                         key->hw_key_idx = 32;
 485                         rt73usb_register_read(rt2x00dev, SEC_CSR3, &reg);
 486                         if (reg && reg == ~0)
 487                                 return -ENOSPC;
 488                 }
 489
 490                 key->hw_key_idx += reg ? (ffz(reg) - 1) : 0;
 491
 492                 /*
 493                  * Upload key to hardware
 494                  */
 495                 memcpy(key_entry.key, crypto->key,
 496                        sizeof(key_entry.key));
 497                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 498                        sizeof(key_entry.tx_mic));
 499                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 500                        sizeof(key_entry.rx_mic));
 501
 502                 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 503                 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
 504                 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
 505                                                     USB_VENDOR_REQUEST_OUT, reg,
 506                                                     &key_entry,
 507                                                     sizeof(key_entry),
 508                                                     timeout);
 509
 510                 /*
 511                  * Send the address and cipher type to the hardware register.
 512                  * This data fits within the CSR cache size, so we can use
 513                  * rt73usb_register_multiwrite() directly.
 514                  */
 515                 memset(&addr_entry, 0, sizeof(addr_entry));
 516                 memcpy(&addr_entry, crypto->address, ETH_ALEN);
 517                 addr_entry.cipher = crypto->cipher;
 518
 519                 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
 520                 rt73usb_register_multiwrite(rt2x00dev, reg,
 521                                             &addr_entry, sizeof(addr_entry));
 522
 523                 /*
 524                  * Enable pairwise lookup table for given BSS idx,
 525                  * without this received frames will not be decrypted
 526                  * by the hardware.
 527                  */
 528                 rt73usb_register_read(rt2x00dev, SEC_CSR4, &reg);
 529                 reg |= (1 << crypto->bssidx);
 530                 rt73usb_register_write(rt2x00dev, SEC_CSR4, reg);
 531
 532                 /*
 533                  * The driver does not support the IV/EIV generation
 534                  * in hardware. However it doesn't support the IV/EIV
 535                  * inside the ieee80211 frame either, but requires it
 536                  * to be provided seperately for the descriptor.
 537                  * rt2x00lib will cut the IV/EIV data out of all frames
 538                  * given to us by mac80211, but we must tell mac80211
 539                  * to generate the IV/EIV data.
 540                  */
 541                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 542         }
 543
 544         /*
 545          * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
 546          * a particular key is valid. Because using the FIELD32()
 547          * defines directly will cause a lot of overhead we use
 548          * a calculation to determine the correct bit directly.
 549          */
 550         if (key->hw_key_idx < 32) {
 551                 mask = 1 << key->hw_key_idx;
 552
 553                 rt73usb_register_read(rt2x00dev, SEC_CSR2, &reg);
 554                 if (crypto->cmd == SET_KEY)
 555                         reg |= mask;
 556                 else if (crypto->cmd == DISABLE_KEY)
 557                         reg &= ~mask;
 558                 rt73usb_register_write(rt2x00dev, SEC_CSR2, reg);
 559         } else {
 560                 mask = 1 << (key->hw_key_idx - 32);
 561
 562                 rt73usb_register_read(rt2x00dev, SEC_CSR3, &reg);
 563                 if (crypto->cmd == SET_KEY)
 564                         reg |= mask;
 565                 else if (crypto->cmd == DISABLE_KEY)
 566                         reg &= ~mask;
 567                 rt73usb_register_write(rt2x00dev, SEC_CSR3, reg);
 568         }
 569
 570         return 0;
 571 }
 572
 573 static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
 574                                   const unsigned int filter_flags)
 575 {
 576         u32 reg;
 577
 578         /*
 579          * Start configuration steps.
 580          * Note that the version error will always be dropped
 581          * and broadcast frames will always be accepted since
 582          * there is no filter for it at this time.
 583          */
 584         rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
 585         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
 586                            !(filter_flags & FIF_FCSFAIL));
 587         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
 588                            !(filter_flags & FIF_PLCPFAIL));
 589         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
 590                            !(filter_flags & FIF_CONTROL));
 591         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
 592                            !(filter_flags & FIF_PROMISC_IN_BSS));
 593         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
 594                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 595                            !rt2x00dev->intf_ap_count);
 596         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
 597         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
 598                            !(filter_flags & FIF_ALLMULTI));
 599         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
 600         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
 601                            !(filter_flags & FIF_CONTROL));
 602         rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
 603 }
 604
 605 static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
 606                                 struct rt2x00_intf *intf,
 607                                 struct rt2x00intf_conf *conf,
 608                                 const unsigned int flags)
 609 {
 610         unsigned int beacon_base;
 611         u32 reg;
 612
 613         if (flags & CONFIG_UPDATE_TYPE) {
 614                 /*
 615                  * Clear current synchronisation setup.
 616                  * For the Beacon base registers we only need to clear
 617                  * the first byte since that byte contains the VALID and OWNER
 618                  * bits which (when set to 0) will invalidate the entire beacon.
 619                  */
 620                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 621                 rt73usb_register_write(rt2x00dev, beacon_base, 0);
 622
 623                 /*
 624                  * Enable synchronisation.
 625                  */
 626                 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
 627                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
 628                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
 629                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
 630                 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
 631         }
 632
 633         if (flags & CONFIG_UPDATE_MAC) {
 634                 reg = le32_to_cpu(conf->mac[1]);
 635                 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
 636                 conf->mac[1] = cpu_to_le32(reg);
 637
 638                 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR2,
 639                                             conf->mac, sizeof(conf->mac));
 640         }
 641
 642         if (flags & CONFIG_UPDATE_BSSID) {
 643                 reg = le32_to_cpu(conf->bssid[1]);
 644                 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
 645                 conf->bssid[1] = cpu_to_le32(reg);
 646
 647                 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR4,
 648                                             conf->bssid, sizeof(conf->bssid));
 649         }
 650 }
 651
 652 static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
 653                                struct rt2x00lib_erp *erp)
 654 {
 655         u32 reg;
 656
 657         rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
 658         rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
 659         rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
 660
 661         rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
 662         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
 663                            !!erp->short_preamble);
 664         rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
 665 }
 666
 667 static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 668                                     struct rt2x00lib_conf *libconf)
 669 {
 670         u16 eeprom;
 671         short lna_gain = 0;
 672
 673         if (libconf->band == IEEE80211_BAND_2GHZ) {
 674                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
 675                         lna_gain += 14;
 676
 677                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
 678                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
 679         } else {
 680                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
 681                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
 682         }
 683
 684         rt2x00dev->lna_gain = lna_gain;
 685 }
 686
 687 static void rt73usb_config_phymode(struct rt2x00_dev *rt2x00dev,
 688                                    const int basic_rate_mask)
 689 {
 690         rt73usb_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
 691 }
 692
 693 static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
 694                                    struct rf_channel *rf, const int txpower)
 695 {
 696         u8 r3;
 697         u8 r94;
 698         u8 smart;
 699
 700         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 701         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 702
 703         smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
 704                   rt2x00_rf(&rt2x00dev->chip, RF2527));
 705
 706         rt73usb_bbp_read(rt2x00dev, 3, &r3);
 707         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
 708         rt73usb_bbp_write(rt2x00dev, 3, r3);
 709
 710         r94 = 6;
 711         if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
 712                 r94 += txpower - MAX_TXPOWER;
 713         else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
 714                 r94 += txpower;
 715         rt73usb_bbp_write(rt2x00dev, 94, r94);
 716
 717         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
 718         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
 719         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 720         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
 721
 722         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
 723         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
 724         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 725         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
 726
 727         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
 728         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
 729         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 730         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
 731
 732         udelay(10);
 733 }
 734
 735 static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
 736                                    const int txpower)
 737 {
 738         struct rf_channel rf;
 739
 740         rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
 741         rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
 742         rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
 743         rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
 744
 745         rt73usb_config_channel(rt2x00dev, &rf, txpower);
 746 }
 747
 748 static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
 749                                       struct antenna_setup *ant)
 750 {
 751         u8 r3;
 752         u8 r4;
 753         u8 r77;
 754         u8 temp;
 755
 756         rt73usb_bbp_read(rt2x00dev, 3, &r3);
 757         rt73usb_bbp_read(rt2x00dev, 4, &r4);
 758         rt73usb_bbp_read(rt2x00dev, 77, &r77);
 759
 760         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
 761
 762         /*
 763          * Configure the RX antenna.
 764          */
 765         switch (ant->rx) {
 766         case ANTENNA_HW_DIVERSITY:
 767                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 768                 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
 769                        && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
 770                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
 771                 break;
 772         case ANTENNA_A:
 773                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 774                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 775                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 776                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 777                 else
 778                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 779                 break;
 780         case ANTENNA_B:
 781         default:
 782                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 783                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 784                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 785                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 786                 else
 787                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 788                 break;
 789         }
 790
 791         rt73usb_bbp_write(rt2x00dev, 77, r77);
 792         rt73usb_bbp_write(rt2x00dev, 3, r3);
 793         rt73usb_bbp_write(rt2x00dev, 4, r4);
 794 }
 795
 796 static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
 797                                       struct antenna_setup *ant)
 798 {
 799         u8 r3;
 800         u8 r4;
 801         u8 r77;
 802
 803         rt73usb_bbp_read(rt2x00dev, 3, &r3);
 804         rt73usb_bbp_read(rt2x00dev, 4, &r4);
 805         rt73usb_bbp_read(rt2x00dev, 77, &r77);
 806
 807         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
 808         rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 809                           !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
 810
 811         /*
 812          * Configure the RX antenna.
 813          */
 814         switch (ant->rx) {
 815         case ANTENNA_HW_DIVERSITY:
 816                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 817                 break;
 818         case ANTENNA_A:
 819                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 820                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 821                 break;
 822         case ANTENNA_B:
 823         default:
 824                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 825                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 826                 break;
 827         }
 828
 829         rt73usb_bbp_write(rt2x00dev, 77, r77);
 830         rt73usb_bbp_write(rt2x00dev, 3, r3);
 831         rt73usb_bbp_write(rt2x00dev, 4, r4);
 832 }
 833
 834 struct antenna_sel {
 835         u8 word;
 836         /*
 837          * value[0] -> non-LNA
 838          * value[1] -> LNA
 839          */
 840         u8 value[2];
 841 };
 842
 843 static const struct antenna_sel antenna_sel_a[] = {
 844         { 96,  { 0x58, 0x78 } },
 845         { 104, { 0x38, 0x48 } },
 846         { 75,  { 0xfe, 0x80 } },
 847         { 86,  { 0xfe, 0x80 } },
 848         { 88,  { 0xfe, 0x80 } },
 849         { 35,  { 0x60, 0x60 } },
 850         { 97,  { 0x58, 0x58 } },
 851         { 98,  { 0x58, 0x58 } },
 852 };
 853
 854 static const struct antenna_sel antenna_sel_bg[] = {
 855         { 96,  { 0x48, 0x68 } },
 856         { 104, { 0x2c, 0x3c } },
 857         { 75,  { 0xfe, 0x80 } },
 858         { 86,  { 0xfe, 0x80 } },
 859         { 88,  { 0xfe, 0x80 } },
 860         { 35,  { 0x50, 0x50 } },
 861         { 97,  { 0x48, 0x48 } },
 862         { 98,  { 0x48, 0x48 } },
 863 };
 864
 865 static void rt73usb_config_antenna(struct rt2x00_dev *rt2x00dev,
 866                                    struct antenna_setup *ant)
 867 {
 868         const struct antenna_sel *sel;
 869         unsigned int lna;
 870         unsigned int i;
 871         u32 reg;
 872
 873         /*
 874          * We should never come here because rt2x00lib is supposed
 875          * to catch this and send us the correct antenna explicitely.
 876          */
 877         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 878                ant->tx == ANTENNA_SW_DIVERSITY);
 879
 880         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
 881                 sel = antenna_sel_a;
 882                 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
 883         } else {
 884                 sel = antenna_sel_bg;
 885                 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
 886         }
 887
 888         for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
 889                 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
 890
 891         rt73usb_register_read(rt2x00dev, PHY_CSR0, &reg);
 892
 893         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
 894                            (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
 895         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
 896                            (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
 897
 898         rt73usb_register_write(rt2x00dev, PHY_CSR0, reg);
 899
 900         if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
 901             rt2x00_rf(&rt2x00dev->chip, RF5225))
 902                 rt73usb_config_antenna_5x(rt2x00dev, ant);
 903         else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
 904                  rt2x00_rf(&rt2x00dev->chip, RF2527))
 905                 rt73usb_config_antenna_2x(rt2x00dev, ant);
 906 }
 907
 908 static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
 909                                     struct rt2x00lib_conf *libconf)
 910 {
 911         u32 reg;
 912
 913         rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
 914         rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
 915         rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
 916
 917         rt73usb_register_read(rt2x00dev, MAC_CSR8, &reg);
 918         rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
 919         rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
 920         rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
 921         rt73usb_register_write(rt2x00dev, MAC_CSR8, reg);
 922
 923         rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
 924         rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
 925         rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
 926
 927         rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
 928         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
 929         rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
 930
 931         rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
 932         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
 933                            libconf->conf->beacon_int * 16);
 934         rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
 935 }
 936
 937 static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
 938                            struct rt2x00lib_conf *libconf,
 939                            const unsigned int flags)
 940 {
 941         /* Always recalculate LNA gain before changing configuration */
 942         rt73usb_config_lna_gain(rt2x00dev, libconf);
 943
 944         if (flags & CONFIG_UPDATE_PHYMODE)
 945                 rt73usb_config_phymode(rt2x00dev, libconf->basic_rates);
 946         if (flags & CONFIG_UPDATE_CHANNEL)
 947                 rt73usb_config_channel(rt2x00dev, &libconf->rf,
 948                                        libconf->conf->power_level);
 949         if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
 950                 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
 951         if (flags & CONFIG_UPDATE_ANTENNA)
 952                 rt73usb_config_antenna(rt2x00dev, &libconf->ant);
 953         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
 954                 rt73usb_config_duration(rt2x00dev, libconf);
 955 }
 956
 957 /*
 958  * Link tuning
 959  */
 960 static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
 961                                struct link_qual *qual)
 962 {
 963         u32 reg;
 964
 965         /*
 966          * Update FCS error count from register.
 967          */
 968         rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
 969         qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
 970
 971         /*
 972          * Update False CCA count from register.
 973          */
 974         rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
 975         qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
 976 }
 977
 978 static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev)
 979 {
 980         rt73usb_bbp_write(rt2x00dev, 17, 0x20);
 981         rt2x00dev->link.vgc_level = 0x20;
 982 }
 983
 984 static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev)
 985 {
 986         int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
 987         u8 r17;
 988         u8 up_bound;
 989         u8 low_bound;
 990
 991         rt73usb_bbp_read(rt2x00dev, 17, &r17);
 992
 993         /*
 994          * Determine r17 bounds.
 995          */
 996         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
 997                 low_bound = 0x28;
 998                 up_bound = 0x48;
 999
1000                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1001                         low_bound += 0x10;
1002                         up_bound += 0x10;
1003                 }
1004         } else {
1005                 if (rssi > -82) {
1006                         low_bound = 0x1c;
1007                         up_bound = 0x40;
1008                 } else if (rssi > -84) {
1009                         low_bound = 0x1c;
1010                         up_bound = 0x20;
1011                 } else {
1012                         low_bound = 0x1c;
1013                         up_bound = 0x1c;
1014                 }
1015
1016                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1017                         low_bound += 0x14;
1018                         up_bound += 0x10;
1019                 }
1020         }
1021
1022         /*
1023          * If we are not associated, we should go straight to the
1024          * dynamic CCA tuning.
1025          */
1026         if (!rt2x00dev->intf_associated)
1027                 goto dynamic_cca_tune;
1028
1029         /*
1030          * Special big-R17 for very short distance
1031          */
1032         if (rssi > -35) {
1033                 if (r17 != 0x60)
1034                         rt73usb_bbp_write(rt2x00dev, 17, 0x60);
1035                 return;
1036         }
1037
1038         /*
1039          * Special big-R17 for short distance
1040          */
1041         if (rssi >= -58) {
1042                 if (r17 != up_bound)
1043                         rt73usb_bbp_write(rt2x00dev, 17, up_bound);
1044                 return;
1045         }
1046
1047         /*
1048          * Special big-R17 for middle-short distance
1049          */
1050         if (rssi >= -66) {
1051                 low_bound += 0x10;
1052                 if (r17 != low_bound)
1053                         rt73usb_bbp_write(rt2x00dev, 17, low_bound);
1054                 return;
1055         }
1056
1057         /*
1058          * Special mid-R17 for middle distance
1059          */
1060         if (rssi >= -74) {
1061                 if (r17 != (low_bound + 0x10))
1062                         rt73usb_bbp_write(rt2x00dev, 17, low_bound + 0x08);
1063                 return;
1064         }
1065
1066         /*
1067          * Special case: Change up_bound based on the rssi.
1068          * Lower up_bound when rssi is weaker then -74 dBm.
1069          */
1070         up_bound -= 2 * (-74 - rssi);
1071         if (low_bound > up_bound)
1072                 up_bound = low_bound;
1073
1074         if (r17 > up_bound) {
1075                 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
1076                 return;
1077         }
1078
1079 dynamic_cca_tune:
1080
1081         /*
1082          * r17 does not yet exceed upper limit, continue and base
1083          * the r17 tuning on the false CCA count.
1084          */
1085         if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
1086                 r17 += 4;
1087                 if (r17 > up_bound)
1088                         r17 = up_bound;
1089                 rt73usb_bbp_write(rt2x00dev, 17, r17);
1090         } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
1091                 r17 -= 4;
1092                 if (r17 < low_bound)
1093                         r17 = low_bound;
1094                 rt73usb_bbp_write(rt2x00dev, 17, r17);
1095         }
1096 }
1097
1098 /*
1099  * Firmware functions
1100  */
1101 static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1102 {
1103         return FIRMWARE_RT2571;
1104 }
1105
1106 static u16 rt73usb_get_firmware_crc(const void *data, const size_t len)
1107 {
1108         u16 crc;
1109
1110         /*
1111          * Use the crc itu-t algorithm.
1112          * The last 2 bytes in the firmware array are the crc checksum itself,
1113          * this means that we should never pass those 2 bytes to the crc
1114          * algorithm.
1115          */
1116         crc = crc_itu_t(0, data, len - 2);
1117         crc = crc_itu_t_byte(crc, 0);
1118         crc = crc_itu_t_byte(crc, 0);
1119
1120         return crc;
1121 }
1122
1123 static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, const void *data,
1124                                  const size_t len)
1125 {
1126         unsigned int i;
1127         int status;
1128         u32 reg;
1129
1130         /*
1131          * Wait for stable hardware.
1132          */
1133         for (i = 0; i < 100; i++) {
1134                 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1135                 if (reg)
1136                         break;
1137                 msleep(1);
1138         }
1139
1140         if (!reg) {
1141                 ERROR(rt2x00dev, "Unstable hardware.\n");
1142                 return -EBUSY;
1143         }
1144
1145         /*
1146          * Write firmware to device.
1147          */
1148         rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1149                                             USB_VENDOR_REQUEST_OUT,
1150                                             FIRMWARE_IMAGE_BASE,
1151                                             data, len,
1152                                             REGISTER_TIMEOUT32(len));
1153
1154         /*
1155          * Send firmware request to device to load firmware,
1156          * we need to specify a long timeout time.
1157          */
1158         status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1159                                              0, USB_MODE_FIRMWARE,
1160                                              REGISTER_TIMEOUT_FIRMWARE);
1161         if (status < 0) {
1162                 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1163                 return status;
1164         }
1165
1166         return 0;
1167 }
1168
1169 /*
1170  * Initialization functions.
1171  */
1172 static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1173 {
1174         u32 reg;
1175
1176         rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1177         rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1178         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1179         rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1180         rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1181
1182         rt73usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
1183         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1184         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1185         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1186         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1187         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1188         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1189         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1190         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1191         rt73usb_register_write(rt2x00dev, TXRX_CSR1, reg);
1192
1193         /*
1194          * CCK TXD BBP registers
1195          */
1196         rt73usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
1197         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1198         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1199         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1200         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1201         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1202         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1203         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1204         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1205         rt73usb_register_write(rt2x00dev, TXRX_CSR2, reg);
1206
1207         /*
1208          * OFDM TXD BBP registers
1209          */
1210         rt73usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
1211         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1212         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1213         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1214         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1215         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1216         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1217         rt73usb_register_write(rt2x00dev, TXRX_CSR3, reg);
1218
1219         rt73usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
1220         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1221         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1222         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1223         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1224         rt73usb_register_write(rt2x00dev, TXRX_CSR7, reg);
1225
1226         rt73usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
1227         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1228         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1229         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1230         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1231         rt73usb_register_write(rt2x00dev, TXRX_CSR8, reg);
1232
1233         rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1234         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1235         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1236         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1237         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1238         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1239         rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1240         rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1241
1242         rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1243
1244         rt73usb_register_read(rt2x00dev, MAC_CSR6, &reg);
1245         rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
1246         rt73usb_register_write(rt2x00dev, MAC_CSR6, reg);
1247
1248         rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
1249
1250         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1251                 return -EBUSY;
1252
1253         rt73usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
1254
1255         /*
1256          * Invalidate all Shared Keys (SEC_CSR0),
1257          * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1258          */
1259         rt73usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1260         rt73usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1261         rt73usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1262
1263         reg = 0x000023b0;
1264         if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1265             rt2x00_rf(&rt2x00dev->chip, RF2527))
1266                 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
1267         rt73usb_register_write(rt2x00dev, PHY_CSR1, reg);
1268
1269         rt73usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1270         rt73usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1271         rt73usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1272
1273         rt73usb_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1274         rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1275         rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1276         rt73usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1277
1278         rt73usb_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1279         rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1280         rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1281         rt73usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1282
1283         rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
1284         rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1285         rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
1286
1287         /*
1288          * Clear all beacons
1289          * For the Beacon base registers we only need to clear
1290          * the first byte since that byte contains the VALID and OWNER
1291          * bits which (when set to 0) will invalidate the entire beacon.
1292          */
1293         rt73usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1294         rt73usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1295         rt73usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1296         rt73usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1297
1298         /*
1299          * We must clear the error counters.
1300          * These registers are cleared on read,
1301          * so we may pass a useless variable to store the value.
1302          */
1303         rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
1304         rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
1305         rt73usb_register_read(rt2x00dev, STA_CSR2, &reg);
1306
1307         /*
1308          * Reset MAC and BBP registers.
1309          */
1310         rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1311         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1312         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1313         rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1314
1315         rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1316         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1317         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1318         rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1319
1320         rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1321         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1322         rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1323
1324         return 0;
1325 }
1326
1327 static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1328 {
1329         unsigned int i;
1330         u8 value;
1331
1332         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1333                 rt73usb_bbp_read(rt2x00dev, 0, &value);
1334                 if ((value != 0xff) && (value != 0x00))
1335                         return 0;
1336                 udelay(REGISTER_BUSY_DELAY);
1337         }
1338
1339         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1340         return -EACCES;
1341 }
1342
1343 static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1344 {
1345         unsigned int i;
1346         u16 eeprom;
1347         u8 reg_id;
1348         u8 value;
1349
1350         if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev)))
1351                 return -EACCES;
1352
1353         rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1354         rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1355         rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1356         rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1357         rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1358         rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1359         rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1360         rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1361         rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1362         rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1363         rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1364         rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1365         rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1366         rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1367         rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1368         rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1369         rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1370         rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1371         rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1372         rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1373         rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1374         rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1375         rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1376         rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1377         rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1378
1379         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1380                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1381
1382                 if (eeprom != 0xffff && eeprom != 0x0000) {
1383                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1384                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1385                         rt73usb_bbp_write(rt2x00dev, reg_id, value);
1386                 }
1387         }
1388
1389         return 0;
1390 }
1391
1392 /*
1393  * Device state switch handlers.
1394  */
1395 static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1396                               enum dev_state state)
1397 {
1398         u32 reg;
1399
1400         rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1401         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1402                            (state == STATE_RADIO_RX_OFF) ||
1403                            (state == STATE_RADIO_RX_OFF_LINK));
1404         rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1405 }
1406
1407 static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1408 {
1409         /*
1410          * Initialize all registers.
1411          */
1412         if (unlikely(rt73usb_init_registers(rt2x00dev) ||
1413                      rt73usb_init_bbp(rt2x00dev)))
1414                 return -EIO;
1415
1416         return 0;
1417 }
1418
1419 static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1420 {
1421         rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1422
1423         /*
1424          * Disable synchronisation.
1425          */
1426         rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1427
1428         rt2x00usb_disable_radio(rt2x00dev);
1429 }
1430
1431 static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1432 {
1433         u32 reg;
1434         unsigned int i;
1435         char put_to_sleep;
1436
1437         put_to_sleep = (state != STATE_AWAKE);
1438
1439         rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1440         rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1441         rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1442         rt73usb_register_write(rt2x00dev, MAC_CSR12, reg);
1443
1444         /*
1445          * Device is not guaranteed to be in the requested state yet.
1446          * We must wait until the register indicates that the
1447          * device has entered the correct state.
1448          */
1449         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1450                 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1451                 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1452                 if (state == !put_to_sleep)
1453                         return 0;
1454                 msleep(10);
1455         }
1456
1457         return -EBUSY;
1458 }
1459
1460 static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1461                                     enum dev_state state)
1462 {
1463         int retval = 0;
1464
1465         switch (state) {
1466         case STATE_RADIO_ON:
1467                 retval = rt73usb_enable_radio(rt2x00dev);
1468                 break;
1469         case STATE_RADIO_OFF:
1470                 rt73usb_disable_radio(rt2x00dev);
1471                 break;
1472         case STATE_RADIO_RX_ON:
1473         case STATE_RADIO_RX_ON_LINK:
1474         case STATE_RADIO_RX_OFF:
1475         case STATE_RADIO_RX_OFF_LINK:
1476                 rt73usb_toggle_rx(rt2x00dev, state);
1477                 break;
1478         case STATE_RADIO_IRQ_ON:
1479         case STATE_RADIO_IRQ_OFF:
1480                 /* No support, but no error either */
1481                 break;
1482         case STATE_DEEP_SLEEP:
1483         case STATE_SLEEP:
1484         case STATE_STANDBY:
1485         case STATE_AWAKE:
1486                 retval = rt73usb_set_state(rt2x00dev, state);
1487                 break;
1488         default:
1489                 retval = -ENOTSUPP;
1490                 break;
1491         }
1492
1493         if (unlikely(retval))
1494                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1495                       state, retval);
1496
1497         return retval;
1498 }
1499
1500 /*
1501  * TX descriptor initialization
1502  */
1503 static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1504                                   struct sk_buff *skb,
1505                                   struct txentry_desc *txdesc)
1506 {
1507         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1508         __le32 *txd = skbdesc->desc;
1509         u32 word;
1510
1511         /*
1512          * Start writing the descriptor words.
1513          */
1514         rt2x00_desc_read(txd, 1, &word);
1515         rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1516         rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1517         rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1518         rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1519         rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1520         rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1521                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1522         rt2x00_desc_write(txd, 1, word);
1523
1524         rt2x00_desc_read(txd, 2, &word);
1525         rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1526         rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1527         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1528         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1529         rt2x00_desc_write(txd, 2, word);
1530
1531         if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1532                 _rt2x00_desc_write(txd, 3, skbdesc->iv);
1533                 _rt2x00_desc_write(txd, 4, skbdesc->eiv);
1534         }
1535
1536         rt2x00_desc_read(txd, 5, &word);
1537         rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1538                            TXPOWER_TO_DEV(rt2x00dev->tx_power));
1539         rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1540         rt2x00_desc_write(txd, 5, word);
1541
1542         rt2x00_desc_read(txd, 0, &word);
1543         rt2x00_set_field32(&word, TXD_W0_BURST,
1544                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1545         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1546         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1547                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1548         rt2x00_set_field32(&word, TXD_W0_ACK,
1549                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1550         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1551                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1552         rt2x00_set_field32(&word, TXD_W0_OFDM,
1553                            test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1554         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1555         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1556                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1557         rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1558                            test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1559         rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1560                            test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1561         rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1562         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT,
1563                            skb->len - skbdesc->desc_len);
1564         rt2x00_set_field32(&word, TXD_W0_BURST2,
1565                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1566         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1567         rt2x00_desc_write(txd, 0, word);
1568 }
1569
1570 /*
1571  * TX data initialization
1572  */
1573 static void rt73usb_write_beacon(struct queue_entry *entry)
1574 {
1575         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1576         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1577         unsigned int beacon_base;
1578         u32 reg;
1579         u32 word, len;
1580
1581         /*
1582          * Add the descriptor in front of the skb.
1583          */
1584         skb_push(entry->skb, entry->queue->desc_size);
1585         memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
1586         skbdesc->desc = entry->skb->data;
1587
1588         /*
1589          * Adjust the beacon databyte count. The current number is
1590          * calculated before this function gets called, but falsely
1591          * assumes that the descriptor was already present in the SKB.
1592          */
1593         rt2x00_desc_read(skbdesc->desc, 0, &word);
1594         len  = rt2x00_get_field32(word, TXD_W0_DATABYTE_COUNT);
1595         len += skbdesc->desc_len;
1596         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, len);
1597         rt2x00_desc_write(skbdesc->desc, 0, word);
1598
1599         /*
1600          * Disable beaconing while we are reloading the beacon data,
1601          * otherwise we might be sending out invalid data.
1602          */
1603         rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1604         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1605         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1606         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1607         rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1608
1609         /*
1610          * Write entire beacon with descriptor to register.
1611          */
1612         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1613         rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1614                                             USB_VENDOR_REQUEST_OUT, beacon_base,
1615                                             entry->skb->data, entry->skb->len,
1616                                             REGISTER_TIMEOUT32(entry->skb->len));
1617
1618         /*
1619          * Clean up the beacon skb.
1620          */
1621         dev_kfree_skb(entry->skb);
1622         entry->skb = NULL;
1623 }
1624
1625 static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
1626                                    struct sk_buff *skb)
1627 {
1628         int length;
1629
1630         /*
1631          * The length _must_ be a multiple of 4,
1632          * but it must _not_ be a multiple of the USB packet size.
1633          */
1634         length = roundup(skb->len, 4);
1635         length += (4 * !(length % rt2x00dev->usb_maxpacket));
1636
1637         return length;
1638 }
1639
1640 static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1641                                   const enum data_queue_qid queue)
1642 {
1643         u32 reg;
1644
1645         if (queue != QID_BEACON) {
1646                 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
1647                 return;
1648         }
1649
1650         /*
1651          * For Wi-Fi faily generated beacons between participating stations.
1652          * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1653          */
1654         rt73usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1655
1656         rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1657         if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1658                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1659                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1660                 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1661                 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1662         }
1663 }
1664
1665 /*
1666  * RX control handlers
1667  */
1668 static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1669 {
1670         u8 offset = rt2x00dev->lna_gain;
1671         u8 lna;
1672
1673         lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1674         switch (lna) {
1675         case 3:
1676                 offset += 90;
1677                 break;
1678         case 2:
1679                 offset += 74;
1680                 break;
1681         case 1:
1682                 offset += 64;
1683                 break;
1684         default:
1685                 return 0;
1686         }
1687
1688         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1689                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1690                         if (lna == 3 || lna == 2)
1691                                 offset += 10;
1692                 } else {
1693                         if (lna == 3)
1694                                 offset += 6;
1695                         else if (lna == 2)
1696                                 offset += 8;
1697                 }
1698         }
1699
1700         return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1701 }
1702
1703 static void rt73usb_fill_rxdone(struct queue_entry *entry,
1704                                 struct rxdone_entry_desc *rxdesc)
1705 {
1706         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1707         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1708         __le32 *rxd = (__le32 *)entry->skb->data;
1709         u32 word0;
1710         u32 word1;
1711
1712         /*
1713          * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1714          * frame data in rt2x00usb.
1715          */
1716         memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
1717         rxd = (__le32 *)skbdesc->desc;
1718
1719         /*
1720          * It is now safe to read the descriptor on all architectures.
1721          */
1722         rt2x00_desc_read(rxd, 0, &word0);
1723         rt2x00_desc_read(rxd, 1, &word1);
1724
1725         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1726                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1727
1728         if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1729                 rxdesc->cipher =
1730                     rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1731                 rxdesc->cipher_status =
1732                     rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1733         }
1734
1735         if (rxdesc->cipher != CIPHER_NONE) {
1736                 _rt2x00_desc_read(rxd, 2, &rxdesc->iv);
1737                 _rt2x00_desc_read(rxd, 3, &rxdesc->eiv);
1738                 _rt2x00_desc_read(rxd, 4, &rxdesc->icv);
1739
1740                 /*
1741                  * Hardware has stripped IV/EIV data from 802.11 frame during
1742                  * decryption. It has provided the data seperately but rt2x00lib
1743                  * should decide if it should be reinserted.
1744                  */
1745                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1746
1747                 /*
1748                  * FIXME: Legacy driver indicates that the frame does
1749                  * contain the Michael Mic. Unfortunately, in rt2x00
1750                  * the MIC seems to be missing completely...
1751                  */
1752                 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1753
1754                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1755                         rxdesc->flags |= RX_FLAG_DECRYPTED;
1756                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1757                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1758         }
1759
1760         /*
1761          * Obtain the status about this packet.
1762          * When frame was received with an OFDM bitrate,
1763          * the signal is the PLCP value. If it was received with
1764          * a CCK bitrate the signal is the rate in 100kbit/s.
1765          */
1766         rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1767         rxdesc->rssi = rt73usb_agc_to_rssi(rt2x00dev, word1);
1768         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1769
1770         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1771                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1772         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1773                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1774
1775         /*
1776          * Set skb pointers, and update frame information.
1777          */
1778         skb_pull(entry->skb, entry->queue->desc_size);
1779         skb_trim(entry->skb, rxdesc->size);
1780 }
1781
1782 /*
1783  * Device probe functions.
1784  */
1785 static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1786 {
1787         u16 word;
1788         u8 *mac;
1789         s8 value;
1790
1791         rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1792
1793         /*
1794          * Start validation of the data that has been read.
1795          */
1796         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1797         if (!is_valid_ether_addr(mac)) {
1798                 DECLARE_MAC_BUF(macbuf);
1799
1800                 random_ether_addr(mac);
1801                 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1802         }
1803
1804         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1805         if (word == 0xffff) {
1806                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1807                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1808                                    ANTENNA_B);
1809                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1810                                    ANTENNA_B);
1811                 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1812                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1813                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1814                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1815                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1816                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1817         }
1818
1819         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1820         if (word == 0xffff) {
1821                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1822                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1823                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1824         }
1825
1826         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1827         if (word == 0xffff) {
1828                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1829                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1830                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1831                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1832                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1833                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1834                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1835                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1836                 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1837                                    LED_MODE_DEFAULT);
1838                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1839                 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1840         }
1841
1842         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1843         if (word == 0xffff) {
1844                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1845                 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1846                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1847                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1848         }
1849
1850         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1851         if (word == 0xffff) {
1852                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1853                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1854                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1855                 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1856         } else {
1857                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1858                 if (value < -10 || value > 10)
1859                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1860                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1861                 if (value < -10 || value > 10)
1862                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1863                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1864         }
1865
1866         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1867         if (word == 0xffff) {
1868                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1869                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1870                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1871                 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
1872         } else {
1873                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1874                 if (value < -10 || value > 10)
1875                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1876                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1877                 if (value < -10 || value > 10)
1878                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1879                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1880         }
1881
1882         return 0;
1883 }
1884
1885 static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1886 {
1887         u32 reg;
1888         u16 value;
1889         u16 eeprom;
1890
1891         /*
1892          * Read EEPROM word for configuration.
1893          */
1894         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1895
1896         /*
1897          * Identify RF chipset.
1898          */
1899         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1900         rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1901         rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1902
1903         if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
1904                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1905                 return -ENODEV;
1906         }
1907
1908         if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1909             !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1910             !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1911             !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1912                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1913                 return -ENODEV;
1914         }
1915
1916         /*
1917          * Identify default antenna configuration.
1918          */
1919         rt2x00dev->default_ant.tx =
1920             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1921         rt2x00dev->default_ant.rx =
1922             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1923
1924         /*
1925          * Read the Frame type.
1926          */
1927         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1928                 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1929
1930         /*
1931          * Read frequency offset.
1932          */
1933         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1934         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1935
1936         /*
1937          * Read external LNA informations.
1938          */
1939         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1940
1941         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1942                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1943                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1944         }
1945
1946         /*
1947          * Store led settings, for correct led behaviour.
1948          */
1949 #ifdef CONFIG_RT73USB_LEDS
1950         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1951
1952         rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1953         rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1954         if (value == LED_MODE_SIGNAL_STRENGTH)
1955                 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1956                                  LED_TYPE_QUALITY);
1957
1958         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1959         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
1960                            rt2x00_get_field16(eeprom,
1961                                               EEPROM_LED_POLARITY_GPIO_0));
1962         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
1963                            rt2x00_get_field16(eeprom,
1964                                               EEPROM_LED_POLARITY_GPIO_1));
1965         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
1966                            rt2x00_get_field16(eeprom,
1967                                               EEPROM_LED_POLARITY_GPIO_2));
1968         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
1969                            rt2x00_get_field16(eeprom,
1970                                               EEPROM_LED_POLARITY_GPIO_3));
1971         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
1972                            rt2x00_get_field16(eeprom,
1973                                               EEPROM_LED_POLARITY_GPIO_4));
1974         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
1975                            rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
1976         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
1977                            rt2x00_get_field16(eeprom,
1978                                               EEPROM_LED_POLARITY_RDY_G));
1979         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
1980                            rt2x00_get_field16(eeprom,
1981                                               EEPROM_LED_POLARITY_RDY_A));
1982 #endif /* CONFIG_RT73USB_LEDS */
1983
1984         return 0;
1985 }
1986
1987 /*
1988  * RF value list for RF2528
1989  * Supports: 2.4 GHz
1990  */
1991 static const struct rf_channel rf_vals_bg_2528[] = {
1992         { 1,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1993         { 2,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1994         { 3,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1995         { 4,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1996         { 5,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1997         { 6,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1998         { 7,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1999         { 8,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
2000         { 9,  0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
2001         { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
2002         { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
2003         { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
2004         { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
2005         { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
2006 };
2007
2008 /*
2009  * RF value list for RF5226
2010  * Supports: 2.4 GHz & 5.2 GHz
2011  */
2012 static const struct rf_channel rf_vals_5226[] = {
2013         { 1,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
2014         { 2,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
2015         { 3,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
2016         { 4,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
2017         { 5,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
2018         { 6,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
2019         { 7,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
2020         { 8,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
2021         { 9,  0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
2022         { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
2023         { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
2024         { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
2025         { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
2026         { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
2027
2028         /* 802.11 UNI / HyperLan 2 */
2029         { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
2030         { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
2031         { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
2032         { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
2033         { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
2034         { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
2035         { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
2036         { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
2037
2038         /* 802.11 HyperLan 2 */
2039         { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
2040         { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
2041         { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
2042         { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
2043         { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
2044         { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
2045         { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
2046         { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
2047         { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
2048         { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
2049
2050         /* 802.11 UNII */
2051         { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
2052         { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
2053         { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
2054         { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
2055         { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
2056         { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
2057
2058         /* MMAC(Japan)J52 ch 34,38,42,46 */
2059         { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
2060         { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
2061         { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
2062         { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
2063 };
2064
2065 /*
2066  * RF value list for RF5225 & RF2527
2067  * Supports: 2.4 GHz & 5.2 GHz
2068  */
2069 static const struct rf_channel rf_vals_5225_2527[] = {
2070         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2071         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2072         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2073         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2074         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2075         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2076         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2077         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2078         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2079         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2080         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2081         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2082         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2083         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2084
2085         /* 802.11 UNI / HyperLan 2 */
2086         { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2087         { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2088         { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2089         { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2090         { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2091         { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2092         { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2093         { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2094
2095         /* 802.11 HyperLan 2 */
2096         { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2097         { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2098         { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2099         { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2100         { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2101         { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2102         { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2103         { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2104         { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2105         { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2106
2107         /* 802.11 UNII */
2108         { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2109         { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2110         { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2111         { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2112         { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2113         { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2114
2115         /* MMAC(Japan)J52 ch 34,38,42,46 */
2116         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2117         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2118         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2119         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2120 };
2121
2122
2123 static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2124 {
2125         struct hw_mode_spec *spec = &rt2x00dev->spec;
2126         struct channel_info *info;
2127         char *tx_power;
2128         unsigned int i;
2129
2130         /*
2131          * Initialize all hw fields.
2132          */
2133         rt2x00dev->hw->flags =
2134             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2135             IEEE80211_HW_SIGNAL_DBM;
2136         rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
2137
2138         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2139         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2140                                 rt2x00_eeprom_addr(rt2x00dev,
2141                                                    EEPROM_MAC_ADDR_0));
2142
2143         /*
2144          * Initialize hw_mode information.
2145          */
2146         spec->supported_bands = SUPPORT_BAND_2GHZ;
2147         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2148
2149         if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
2150                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
2151                 spec->channels = rf_vals_bg_2528;
2152         } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
2153                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2154                 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
2155                 spec->channels = rf_vals_5226;
2156         } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
2157                 spec->num_channels = 14;
2158                 spec->channels = rf_vals_5225_2527;
2159         } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
2160                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2161                 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
2162                 spec->channels = rf_vals_5225_2527;
2163         }
2164
2165         /*
2166          * Create channel information array
2167          */
2168         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2169         if (!info)
2170                 return -ENOMEM;
2171
2172         spec->channels_info = info;
2173
2174         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2175         for (i = 0; i < 14; i++)
2176                 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2177
2178         if (spec->num_channels > 14) {
2179                 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2180                 for (i = 14; i < spec->num_channels; i++)
2181                         info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2182         }
2183
2184         return 0;
2185 }
2186
2187 static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2188 {
2189         int retval;
2190
2191         /*
2192          * Allocate eeprom data.
2193          */
2194         retval = rt73usb_validate_eeprom(rt2x00dev);
2195         if (retval)
2196                 return retval;
2197
2198         retval = rt73usb_init_eeprom(rt2x00dev);
2199         if (retval)
2200                 return retval;
2201
2202         /*
2203          * Initialize hw specifications.
2204          */
2205         retval = rt73usb_probe_hw_mode(rt2x00dev);
2206         if (retval)
2207                 return retval;
2208
2209         /*
2210          * This device requires firmware.
2211          */
2212         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2213         __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
2214         __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2215
2216         /*
2217          * Set the rssi offset.
2218          */
2219         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2220
2221         return 0;
2222 }
2223
2224 /*
2225  * IEEE80211 stack callback functions.
2226  */
2227 static int rt73usb_set_retry_limit(struct ieee80211_hw *hw,
2228                                    u32 short_retry, u32 long_retry)
2229 {
2230         struct rt2x00_dev *rt2x00dev = hw->priv;
2231         u32 reg;
2232
2233         rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
2234         rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2235         rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2236         rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
2237
2238         return 0;
2239 }
2240
2241 #if 0
2242 /*
2243  * Mac80211 demands get_tsf must be atomic.
2244  * This is not possible for rt73usb since all register access
2245  * functions require sleeping. Untill mac80211 no longer needs
2246  * get_tsf to be atomic, this function should be disabled.
2247  */
2248 static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
2249 {
2250         struct rt2x00_dev *rt2x00dev = hw->priv;
2251         u64 tsf;
2252         u32 reg;
2253
2254         rt73usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
2255         tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2256         rt73usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
2257         tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2258
2259         return tsf;
2260 }
2261 #else
2262 #define rt73usb_get_tsf NULL
2263 #endif
2264
2265 static const struct ieee80211_ops rt73usb_mac80211_ops = {
2266         .tx                     = rt2x00mac_tx,
2267         .start                  = rt2x00mac_start,
2268         .stop                   = rt2x00mac_stop,
2269         .add_interface          = rt2x00mac_add_interface,
2270         .remove_interface       = rt2x00mac_remove_interface,
2271         .config                 = rt2x00mac_config,
2272         .config_interface       = rt2x00mac_config_interface,
2273         .configure_filter       = rt2x00mac_configure_filter,
2274         .set_key                = rt2x00mac_set_key,
2275         .get_stats              = rt2x00mac_get_stats,
2276         .set_retry_limit        = rt73usb_set_retry_limit,
2277         .bss_info_changed       = rt2x00mac_bss_info_changed,
2278         .conf_tx                = rt2x00mac_conf_tx,
2279         .get_tx_stats           = rt2x00mac_get_tx_stats,
2280         .get_tsf                = rt73usb_get_tsf,
2281 };
2282
2283 static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2284         .probe_hw               = rt73usb_probe_hw,
2285         .get_firmware_name      = rt73usb_get_firmware_name,
2286         .get_firmware_crc       = rt73usb_get_firmware_crc,
2287         .load_firmware          = rt73usb_load_firmware,
2288         .initialize             = rt2x00usb_initialize,
2289         .uninitialize           = rt2x00usb_uninitialize,
2290         .init_rxentry           = rt2x00usb_init_rxentry,
2291         .init_txentry           = rt2x00usb_init_txentry,
2292         .set_device_state       = rt73usb_set_device_state,
2293         .link_stats             = rt73usb_link_stats,
2294         .reset_tuner            = rt73usb_reset_tuner,
2295         .link_tuner             = rt73usb_link_tuner,
2296         .write_tx_desc          = rt73usb_write_tx_desc,
2297         .write_tx_data          = rt2x00usb_write_tx_data,
2298         .write_beacon           = rt73usb_write_beacon,
2299         .get_tx_data_len        = rt73usb_get_tx_data_len,
2300         .kick_tx_queue          = rt73usb_kick_tx_queue,
2301         .fill_rxdone            = rt73usb_fill_rxdone,
2302         .config_shared_key      = rt73usb_config_shared_key,
2303         .config_pairwise_key    = rt73usb_config_pairwise_key,
2304         .config_filter          = rt73usb_config_filter,
2305         .config_intf            = rt73usb_config_intf,
2306         .config_erp             = rt73usb_config_erp,
2307         .config                 = rt73usb_config,
2308 };
2309
2310 static const struct data_queue_desc rt73usb_queue_rx = {
2311         .entry_num              = RX_ENTRIES,
2312         .data_size              = DATA_FRAME_SIZE,
2313         .desc_size              = RXD_DESC_SIZE,
2314         .priv_size              = sizeof(struct queue_entry_priv_usb),
2315 };
2316
2317 static const struct data_queue_desc rt73usb_queue_tx = {
2318         .entry_num              = TX_ENTRIES,
2319         .data_size              = DATA_FRAME_SIZE,
2320         .desc_size              = TXD_DESC_SIZE,
2321         .priv_size              = sizeof(struct queue_entry_priv_usb),
2322 };
2323
2324 static const struct data_queue_desc rt73usb_queue_bcn = {
2325         .entry_num              = 4 * BEACON_ENTRIES,
2326         .data_size              = MGMT_FRAME_SIZE,
2327         .desc_size              = TXINFO_SIZE,
2328         .priv_size              = sizeof(struct queue_entry_priv_usb),
2329 };
2330
2331 static const struct rt2x00_ops rt73usb_ops = {
2332         .name           = KBUILD_MODNAME,
2333         .max_sta_intf   = 1,
2334         .max_ap_intf    = 4,
2335         .eeprom_size    = EEPROM_SIZE,
2336         .rf_size        = RF_SIZE,
2337         .tx_queues      = NUM_TX_QUEUES,
2338         .rx             = &rt73usb_queue_rx,
2339         .tx             = &rt73usb_queue_tx,
2340         .bcn            = &rt73usb_queue_bcn,
2341         .lib            = &rt73usb_rt2x00_ops,
2342         .hw             = &rt73usb_mac80211_ops,
2343 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2344         .debugfs        = &rt73usb_rt2x00debug,
2345 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2346 };
2347
2348 /*
2349  * rt73usb module information.
2350  */
2351 static struct usb_device_id rt73usb_device_table[] = {
2352         /* AboCom */
2353         { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2354         /* Askey */
2355         { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2356         /* ASUS */
2357         { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2358         { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2359         /* Belkin */
2360         { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2361         { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2362         { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
2363         { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
2364         /* Billionton */
2365         { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2366         /* Buffalo */
2367         { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2368         /* CNet */
2369         { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2370         { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2371         /* Conceptronic */
2372         { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
2373         /* Corega */
2374         { USB_DEVICE(0x07aa, 0x002e), USB_DEVICE_DATA(&rt73usb_ops) },
2375         /* D-Link */
2376         { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2377         { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
2378         { USB_DEVICE(0x07d1, 0x3c06), USB_DEVICE_DATA(&rt73usb_ops) },
2379         { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) },
2380         /* Gemtek */
2381         { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2382         /* Gigabyte */
2383         { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2384         { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2385         /* Huawei-3Com */
2386         { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2387         /* Hercules */
2388         { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2389         { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2390         /* Linksys */
2391         { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2392         { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2393         /* MSI */
2394         { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2395         { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2396         { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2397         { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2398         /* Ralink */
2399         { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2400         { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2401         /* Qcom */
2402         { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2403         { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2404         { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2405         /* Senao */
2406         { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2407         /* Sitecom */
2408         { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2409         { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2410         /* Surecom */
2411         { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2412         /* Planex */
2413         { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2414         { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2415         { 0, }
2416 };
2417
2418 MODULE_AUTHOR(DRV_PROJECT);
2419 MODULE_VERSION(DRV_VERSION);
2420 MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2421 MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2422 MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2423 MODULE_FIRMWARE(FIRMWARE_RT2571);
2424 MODULE_LICENSE("GPL");
2425
2426 static struct usb_driver rt73usb_driver = {
2427         .name           = KBUILD_MODNAME,
2428         .id_table       = rt73usb_device_table,
2429         .probe          = rt2x00usb_probe,
2430         .disconnect     = rt2x00usb_disconnect,
2431         .suspend        = rt2x00usb_suspend,
2432         .resume         = rt2x00usb_resume,
2433 };
2434
2435 static int __init rt73usb_init(void)
2436 {
2437         return usb_register(&rt73usb_driver);
2438 }
2439
2440 static void __exit rt73usb_exit(void)
2441 {
2442         usb_deregister(&rt73usb_driver);
2443 }
2444
2445 module_init(rt73usb_init);
2446 module_exit(rt73usb_exit);