git.oblomov.eu Git - linux-2.6/blob - drivers/ata/sata_sx4.c

   1 /*
   2  *  sata_sx4.c - Promise SATA
   3  *
   4  *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
   5  *                  Please ALWAYS copy linux-ide@vger.kernel.org
   6  *                  on emails.
   7  *
   8  *  Copyright 2003-2004 Red Hat, Inc.
   9  *
  10  *
  11  *  This program is free software; you can redistribute it and/or modify
  12  *  it under the terms of the GNU General Public License as published by
  13  *  the Free Software Foundation; either version 2, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful,
  17  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *  GNU General Public License for more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License
  22  *  along with this program; see the file COPYING.  If not, write to
  23  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  24  *
  25  *
  26  *  libata documentation is available via 'make {ps|pdf}docs',
  27  *  as Documentation/DocBook/libata.*
  28  *
  29  *  Hardware documentation available under NDA.
  30  *
  31  */
  32
  33 #include <linux/kernel.h>
  34 #include <linux/module.h>
  35 #include <linux/pci.h>
  36 #include <linux/init.h>
  37 #include <linux/blkdev.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/device.h>
  41 #include <scsi/scsi_host.h>
  42 #include <scsi/scsi_cmnd.h>
  43 #include <linux/libata.h>
  44 #include "sata_promise.h"
  45
  46 #define DRV_NAME        "sata_sx4"
  47 #define DRV_VERSION     "0.10"
  48
  49
  50 enum {
  51         PDC_MMIO_BAR            = 3,
  52         PDC_DIMM_BAR            = 4,
  53
  54         PDC_PRD_TBL             = 0x44, /* Direct command DMA table addr */
  55
  56         PDC_PKT_SUBMIT          = 0x40, /* Command packet pointer addr */
  57         PDC_HDMA_PKT_SUBMIT     = 0x100, /* Host DMA packet pointer addr */
  58         PDC_INT_SEQMASK         = 0x40, /* Mask of asserted SEQ INTs */
  59         PDC_HDMA_CTLSTAT        = 0x12C, /* Host DMA control / status */
  60
  61         PDC_20621_SEQCTL        = 0x400,
  62         PDC_20621_SEQMASK       = 0x480,
  63         PDC_20621_GENERAL_CTL   = 0x484,
  64         PDC_20621_PAGE_SIZE     = (32 * 1024),
  65
  66         /* chosen, not constant, values; we design our own DIMM mem map */
  67         PDC_20621_DIMM_WINDOW   = 0x0C, /* page# for 32K DIMM window */
  68         PDC_20621_DIMM_BASE     = 0x00200000,
  69         PDC_20621_DIMM_DATA     = (64 * 1024),
  70         PDC_DIMM_DATA_STEP      = (256 * 1024),
  71         PDC_DIMM_WINDOW_STEP    = (8 * 1024),
  72         PDC_DIMM_HOST_PRD       = (6 * 1024),
  73         PDC_DIMM_HOST_PKT       = (128 * 0),
  74         PDC_DIMM_HPKT_PRD       = (128 * 1),
  75         PDC_DIMM_ATA_PKT        = (128 * 2),
  76         PDC_DIMM_APKT_PRD       = (128 * 3),
  77         PDC_DIMM_HEADER_SZ      = PDC_DIMM_APKT_PRD + 128,
  78         PDC_PAGE_WINDOW         = 0x40,
  79         PDC_PAGE_DATA           = PDC_PAGE_WINDOW +
  80                                   (PDC_20621_DIMM_DATA / PDC_20621_PAGE_SIZE),
  81         PDC_PAGE_SET            = PDC_DIMM_DATA_STEP / PDC_20621_PAGE_SIZE,
  82
  83         PDC_CHIP0_OFS           = 0xC0000, /* offset of chip #0 */
  84
  85         PDC_20621_ERR_MASK      = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
  86                                   (1<<23),
  87
  88         board_20621             = 0,    /* FastTrak S150 SX4 */
  89
  90         PDC_RESET               = (1 << 11), /* HDMA reset */
  91
  92         PDC_MAX_HDMA            = 32,
  93         PDC_HDMA_Q_MASK         = (PDC_MAX_HDMA - 1),
  94
  95         PDC_DIMM0_SPD_DEV_ADDRESS     = 0x50,
  96         PDC_DIMM1_SPD_DEV_ADDRESS     = 0x51,
  97         PDC_MAX_DIMM_MODULE           = 0x02,
  98         PDC_I2C_CONTROL_OFFSET        = 0x48,
  99         PDC_I2C_ADDR_DATA_OFFSET      = 0x4C,
 100         PDC_DIMM0_CONTROL_OFFSET      = 0x80,
 101         PDC_DIMM1_CONTROL_OFFSET      = 0x84,
 102         PDC_SDRAM_CONTROL_OFFSET      = 0x88,
 103         PDC_I2C_WRITE                 = 0x00000000,
 104         PDC_I2C_READ                  = 0x00000040,
 105         PDC_I2C_START                 = 0x00000080,
 106         PDC_I2C_MASK_INT              = 0x00000020,
 107         PDC_I2C_COMPLETE              = 0x00010000,
 108         PDC_I2C_NO_ACK                = 0x00100000,
 109         PDC_DIMM_SPD_SUBADDRESS_START = 0x00,
 110         PDC_DIMM_SPD_SUBADDRESS_END   = 0x7F,
 111         PDC_DIMM_SPD_ROW_NUM          = 3,
 112         PDC_DIMM_SPD_COLUMN_NUM       = 4,
 113         PDC_DIMM_SPD_MODULE_ROW       = 5,
 114         PDC_DIMM_SPD_TYPE             = 11,
 115         PDC_DIMM_SPD_FRESH_RATE       = 12,
 116         PDC_DIMM_SPD_BANK_NUM         = 17,
 117         PDC_DIMM_SPD_CAS_LATENCY      = 18,
 118         PDC_DIMM_SPD_ATTRIBUTE        = 21,
 119         PDC_DIMM_SPD_ROW_PRE_CHARGE   = 27,
 120         PDC_DIMM_SPD_ROW_ACTIVE_DELAY = 28,
 121         PDC_DIMM_SPD_RAS_CAS_DELAY    = 29,
 122         PDC_DIMM_SPD_ACTIVE_PRECHARGE = 30,
 123         PDC_DIMM_SPD_SYSTEM_FREQ      = 126,
 124         PDC_CTL_STATUS                = 0x08,
 125         PDC_DIMM_WINDOW_CTLR          = 0x0C,
 126         PDC_TIME_CONTROL              = 0x3C,
 127         PDC_TIME_PERIOD               = 0x40,
 128         PDC_TIME_COUNTER              = 0x44,
 129         PDC_GENERAL_CTLR              = 0x484,
 130         PCI_PLL_INIT                  = 0x8A531824,
 131         PCI_X_TCOUNT                  = 0xEE1E5CFF
 132 };
 133
 134
 135 struct pdc_port_priv {
 136         u8                      dimm_buf[(ATA_PRD_SZ * ATA_MAX_PRD) + 512];
 137         u8                      *pkt;
 138         dma_addr_t              pkt_dma;
 139 };
 140
 141 struct pdc_host_priv {
 142         unsigned int            doing_hdma;
 143         unsigned int            hdma_prod;
 144         unsigned int            hdma_cons;
 145         struct {
 146                 struct ata_queued_cmd *qc;
 147                 unsigned int    seq;
 148                 unsigned long   pkt_ofs;
 149         } hdma[32];
 150 };
 151
 152
 153 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
 154 static void pdc_eng_timeout(struct ata_port *ap);
 155 static void pdc_20621_phy_reset (struct ata_port *ap);
 156 static int pdc_port_start(struct ata_port *ap);
 157 static void pdc20621_qc_prep(struct ata_queued_cmd *qc);
 158 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
 159 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
 160 static unsigned int pdc20621_dimm_init(struct ata_host *host);
 161 static int pdc20621_detect_dimm(struct ata_host *host);
 162 static unsigned int pdc20621_i2c_read(struct ata_host *host,
 163                                       u32 device, u32 subaddr, u32 *pdata);
 164 static int pdc20621_prog_dimm0(struct ata_host *host);
 165 static unsigned int pdc20621_prog_dimm_global(struct ata_host *host);
 166 #ifdef ATA_VERBOSE_DEBUG
 167 static void pdc20621_get_from_dimm(struct ata_host *host,
 168                                    void *psource, u32 offset, u32 size);
 169 #endif
 170 static void pdc20621_put_to_dimm(struct ata_host *host,
 171                                  void *psource, u32 offset, u32 size);
 172 static void pdc20621_irq_clear(struct ata_port *ap);
 173 static unsigned int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc);
 174
 175
 176 static struct scsi_host_template pdc_sata_sht = {
 177         .module                 = THIS_MODULE,
 178         .name                   = DRV_NAME,
 179         .ioctl                  = ata_scsi_ioctl,
 180         .queuecommand           = ata_scsi_queuecmd,
 181         .can_queue              = ATA_DEF_QUEUE,
 182         .this_id                = ATA_SHT_THIS_ID,
 183         .sg_tablesize           = LIBATA_MAX_PRD,
 184         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
 185         .emulated               = ATA_SHT_EMULATED,
 186         .use_clustering         = ATA_SHT_USE_CLUSTERING,
 187         .proc_name              = DRV_NAME,
 188         .dma_boundary           = ATA_DMA_BOUNDARY,
 189         .slave_configure        = ata_scsi_slave_config,
 190         .slave_destroy          = ata_scsi_slave_destroy,
 191         .bios_param             = ata_std_bios_param,
 192 };
 193
 194 static const struct ata_port_operations pdc_20621_ops = {
 195         .port_disable           = ata_port_disable,
 196         .tf_load                = pdc_tf_load_mmio,
 197         .tf_read                = ata_tf_read,
 198         .check_status           = ata_check_status,
 199         .exec_command           = pdc_exec_command_mmio,
 200         .dev_select             = ata_std_dev_select,
 201         .phy_reset              = pdc_20621_phy_reset,
 202         .qc_prep                = pdc20621_qc_prep,
 203         .qc_issue               = pdc20621_qc_issue_prot,
 204         .data_xfer              = ata_data_xfer,
 205         .eng_timeout            = pdc_eng_timeout,
 206         .irq_clear              = pdc20621_irq_clear,
 207         .irq_on                 = ata_irq_on,
 208         .irq_ack                = ata_irq_ack,
 209         .port_start             = pdc_port_start,
 210 };
 211
 212 static const struct ata_port_info pdc_port_info[] = {
 213         /* board_20621 */
 214         {
 215                 .flags          = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
 216                                   ATA_FLAG_SRST | ATA_FLAG_MMIO |
 217                                   ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING,
 218                 .pio_mask       = 0x1f, /* pio0-4 */
 219                 .mwdma_mask     = 0x07, /* mwdma0-2 */
 220                 .udma_mask      = 0x7f, /* udma0-6 ; FIXME */
 221                 .port_ops       = &pdc_20621_ops,
 222         },
 223
 224 };
 225
 226 static const struct pci_device_id pdc_sata_pci_tbl[] = {
 227         { PCI_VDEVICE(PROMISE, 0x6622), board_20621 },
 228
 229         { }     /* terminate list */
 230 };
 231
 232 static struct pci_driver pdc_sata_pci_driver = {
 233         .name                   = DRV_NAME,
 234         .id_table               = pdc_sata_pci_tbl,
 235         .probe                  = pdc_sata_init_one,
 236         .remove                 = ata_pci_remove_one,
 237 };
 238
 239
 240 static int pdc_port_start(struct ata_port *ap)
 241 {
 242         struct device *dev = ap->host->dev;
 243         struct pdc_port_priv *pp;
 244         int rc;
 245
 246         rc = ata_port_start(ap);
 247         if (rc)
 248                 return rc;
 249
 250         pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
 251         if (!pp)
 252                 return -ENOMEM;
 253
 254         pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
 255         if (!pp->pkt)
 256                 return -ENOMEM;
 257
 258         ap->private_data = pp;
 259
 260         return 0;
 261 }
 262
 263 static void pdc_20621_phy_reset (struct ata_port *ap)
 264 {
 265         VPRINTK("ENTER\n");
 266         ap->cbl = ATA_CBL_SATA;
 267         ata_port_probe(ap);
 268         ata_bus_reset(ap);
 269 }
 270
 271 static inline void pdc20621_ata_sg(struct ata_taskfile *tf, u8 *buf,
 272                                            unsigned int portno,
 273                                            unsigned int total_len)
 274 {
 275         u32 addr;
 276         unsigned int dw = PDC_DIMM_APKT_PRD >> 2;
 277         u32 *buf32 = (u32 *) buf;
 278
 279         /* output ATA packet S/G table */
 280         addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
 281                (PDC_DIMM_DATA_STEP * portno);
 282         VPRINTK("ATA sg addr 0x%x, %d\n", addr, addr);
 283         buf32[dw] = cpu_to_le32(addr);
 284         buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
 285
 286         VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n",
 287                 PDC_20621_DIMM_BASE +
 288                        (PDC_DIMM_WINDOW_STEP * portno) +
 289                        PDC_DIMM_APKT_PRD,
 290                 buf32[dw], buf32[dw + 1]);
 291 }
 292
 293 static inline void pdc20621_host_sg(struct ata_taskfile *tf, u8 *buf,
 294                                             unsigned int portno,
 295                                             unsigned int total_len)
 296 {
 297         u32 addr;
 298         unsigned int dw = PDC_DIMM_HPKT_PRD >> 2;
 299         u32 *buf32 = (u32 *) buf;
 300
 301         /* output Host DMA packet S/G table */
 302         addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
 303                (PDC_DIMM_DATA_STEP * portno);
 304
 305         buf32[dw] = cpu_to_le32(addr);
 306         buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
 307
 308         VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n",
 309                 PDC_20621_DIMM_BASE +
 310                        (PDC_DIMM_WINDOW_STEP * portno) +
 311                        PDC_DIMM_HPKT_PRD,
 312                 buf32[dw], buf32[dw + 1]);
 313 }
 314
 315 static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf,
 316                                             unsigned int devno, u8 *buf,
 317                                             unsigned int portno)
 318 {
 319         unsigned int i, dw;
 320         u32 *buf32 = (u32 *) buf;
 321         u8 dev_reg;
 322
 323         unsigned int dimm_sg = PDC_20621_DIMM_BASE +
 324                                (PDC_DIMM_WINDOW_STEP * portno) +
 325                                PDC_DIMM_APKT_PRD;
 326         VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
 327
 328         i = PDC_DIMM_ATA_PKT;
 329
 330         /*
 331          * Set up ATA packet
 332          */
 333         if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
 334                 buf[i++] = PDC_PKT_READ;
 335         else if (tf->protocol == ATA_PROT_NODATA)
 336                 buf[i++] = PDC_PKT_NODATA;
 337         else
 338                 buf[i++] = 0;
 339         buf[i++] = 0;                   /* reserved */
 340         buf[i++] = portno + 1;          /* seq. id */
 341         buf[i++] = 0xff;                /* delay seq. id */
 342
 343         /* dimm dma S/G, and next-pkt */
 344         dw = i >> 2;
 345         if (tf->protocol == ATA_PROT_NODATA)
 346                 buf32[dw] = 0;
 347         else
 348                 buf32[dw] = cpu_to_le32(dimm_sg);
 349         buf32[dw + 1] = 0;
 350         i += 8;
 351
 352         if (devno == 0)
 353                 dev_reg = ATA_DEVICE_OBS;
 354         else
 355                 dev_reg = ATA_DEVICE_OBS | ATA_DEV1;
 356
 357         /* select device */
 358         buf[i++] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE;
 359         buf[i++] = dev_reg;
 360
 361         /* device control register */
 362         buf[i++] = (1 << 5) | PDC_REG_DEVCTL;
 363         buf[i++] = tf->ctl;
 364
 365         return i;
 366 }
 367
 368 static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf,
 369                                      unsigned int portno)
 370 {
 371         unsigned int dw;
 372         u32 tmp, *buf32 = (u32 *) buf;
 373
 374         unsigned int host_sg = PDC_20621_DIMM_BASE +
 375                                (PDC_DIMM_WINDOW_STEP * portno) +
 376                                PDC_DIMM_HOST_PRD;
 377         unsigned int dimm_sg = PDC_20621_DIMM_BASE +
 378                                (PDC_DIMM_WINDOW_STEP * portno) +
 379                                PDC_DIMM_HPKT_PRD;
 380         VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
 381         VPRINTK("host_sg == 0x%x, %d\n", host_sg, host_sg);
 382
 383         dw = PDC_DIMM_HOST_PKT >> 2;
 384
 385         /*
 386          * Set up Host DMA packet
 387          */
 388         if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
 389                 tmp = PDC_PKT_READ;
 390         else
 391                 tmp = 0;
 392         tmp |= ((portno + 1 + 4) << 16);        /* seq. id */
 393         tmp |= (0xff << 24);                    /* delay seq. id */
 394         buf32[dw + 0] = cpu_to_le32(tmp);
 395         buf32[dw + 1] = cpu_to_le32(host_sg);
 396         buf32[dw + 2] = cpu_to_le32(dimm_sg);
 397         buf32[dw + 3] = 0;
 398
 399         VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n",
 400                 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * portno) +
 401                         PDC_DIMM_HOST_PKT,
 402                 buf32[dw + 0],
 403                 buf32[dw + 1],
 404                 buf32[dw + 2],
 405                 buf32[dw + 3]);
 406 }
 407
 408 static void pdc20621_dma_prep(struct ata_queued_cmd *qc)
 409 {
 410         struct scatterlist *sg;
 411         struct ata_port *ap = qc->ap;
 412         struct pdc_port_priv *pp = ap->private_data;
 413         void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
 414         void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
 415         unsigned int portno = ap->port_no;
 416         unsigned int i, idx, total_len = 0, sgt_len;
 417         u32 *buf = (u32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ];
 418
 419         WARN_ON(!(qc->flags & ATA_QCFLAG_DMAMAP));
 420
 421         VPRINTK("ata%u: ENTER\n", ap->print_id);
 422
 423         /* hard-code chip #0 */
 424         mmio += PDC_CHIP0_OFS;
 425
 426         /*
 427          * Build S/G table
 428          */
 429         idx = 0;
 430         ata_for_each_sg(sg, qc) {
 431                 buf[idx++] = cpu_to_le32(sg_dma_address(sg));
 432                 buf[idx++] = cpu_to_le32(sg_dma_len(sg));
 433                 total_len += sg_dma_len(sg);
 434         }
 435         buf[idx - 1] |= cpu_to_le32(ATA_PRD_EOT);
 436         sgt_len = idx * 4;
 437
 438         /*
 439          * Build ATA, host DMA packets
 440          */
 441         pdc20621_host_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
 442         pdc20621_host_pkt(&qc->tf, &pp->dimm_buf[0], portno);
 443
 444         pdc20621_ata_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
 445         i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
 446
 447         if (qc->tf.flags & ATA_TFLAG_LBA48)
 448                 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
 449         else
 450                 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
 451
 452         pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
 453
 454         /* copy three S/G tables and two packets to DIMM MMIO window */
 455         memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
 456                     &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
 457         memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP) +
 458                     PDC_DIMM_HOST_PRD,
 459                     &pp->dimm_buf[PDC_DIMM_HEADER_SZ], sgt_len);
 460
 461         /* force host FIFO dump */
 462         writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
 463
 464         readl(dimm_mmio);       /* MMIO PCI posting flush */
 465
 466         VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len);
 467 }
 468
 469 static void pdc20621_nodata_prep(struct ata_queued_cmd *qc)
 470 {
 471         struct ata_port *ap = qc->ap;
 472         struct pdc_port_priv *pp = ap->private_data;
 473         void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
 474         void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
 475         unsigned int portno = ap->port_no;
 476         unsigned int i;
 477
 478         VPRINTK("ata%u: ENTER\n", ap->print_id);
 479
 480         /* hard-code chip #0 */
 481         mmio += PDC_CHIP0_OFS;
 482
 483         i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
 484
 485         if (qc->tf.flags & ATA_TFLAG_LBA48)
 486                 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
 487         else
 488                 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
 489
 490         pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
 491
 492         /* copy three S/G tables and two packets to DIMM MMIO window */
 493         memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
 494                     &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
 495
 496         /* force host FIFO dump */
 497         writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
 498
 499         readl(dimm_mmio);       /* MMIO PCI posting flush */
 500
 501         VPRINTK("ata pkt buf ofs %u, mmio copied\n", i);
 502 }
 503
 504 static void pdc20621_qc_prep(struct ata_queued_cmd *qc)
 505 {
 506         switch (qc->tf.protocol) {
 507         case ATA_PROT_DMA:
 508                 pdc20621_dma_prep(qc);
 509                 break;
 510         case ATA_PROT_NODATA:
 511                 pdc20621_nodata_prep(qc);
 512                 break;
 513         default:
 514                 break;
 515         }
 516 }
 517
 518 static void __pdc20621_push_hdma(struct ata_queued_cmd *qc,
 519                                  unsigned int seq,
 520                                  u32 pkt_ofs)
 521 {
 522         struct ata_port *ap = qc->ap;
 523         struct ata_host *host = ap->host;
 524         void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
 525
 526         /* hard-code chip #0 */
 527         mmio += PDC_CHIP0_OFS;
 528
 529         writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
 530         readl(mmio + PDC_20621_SEQCTL + (seq * 4));     /* flush */
 531
 532         writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);
 533         readl(mmio + PDC_HDMA_PKT_SUBMIT);      /* flush */
 534 }
 535
 536 static void pdc20621_push_hdma(struct ata_queued_cmd *qc,
 537                                 unsigned int seq,
 538                                 u32 pkt_ofs)
 539 {
 540         struct ata_port *ap = qc->ap;
 541         struct pdc_host_priv *pp = ap->host->private_data;
 542         unsigned int idx = pp->hdma_prod & PDC_HDMA_Q_MASK;
 543
 544         if (!pp->doing_hdma) {
 545                 __pdc20621_push_hdma(qc, seq, pkt_ofs);
 546                 pp->doing_hdma = 1;
 547                 return;
 548         }
 549
 550         pp->hdma[idx].qc = qc;
 551         pp->hdma[idx].seq = seq;
 552         pp->hdma[idx].pkt_ofs = pkt_ofs;
 553         pp->hdma_prod++;
 554 }
 555
 556 static void pdc20621_pop_hdma(struct ata_queued_cmd *qc)
 557 {
 558         struct ata_port *ap = qc->ap;
 559         struct pdc_host_priv *pp = ap->host->private_data;
 560         unsigned int idx = pp->hdma_cons & PDC_HDMA_Q_MASK;
 561
 562         /* if nothing on queue, we're done */
 563         if (pp->hdma_prod == pp->hdma_cons) {
 564                 pp->doing_hdma = 0;
 565                 return;
 566         }
 567
 568         __pdc20621_push_hdma(pp->hdma[idx].qc, pp->hdma[idx].seq,
 569                              pp->hdma[idx].pkt_ofs);
 570         pp->hdma_cons++;
 571 }
 572
 573 #ifdef ATA_VERBOSE_DEBUG
 574 static void pdc20621_dump_hdma(struct ata_queued_cmd *qc)
 575 {
 576         struct ata_port *ap = qc->ap;
 577         unsigned int port_no = ap->port_no;
 578         void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
 579
 580         dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP);
 581         dimm_mmio += PDC_DIMM_HOST_PKT;
 582
 583         printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio));
 584         printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4));
 585         printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8));
 586         printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12));
 587 }
 588 #else
 589 static inline void pdc20621_dump_hdma(struct ata_queued_cmd *qc) { }
 590 #endif /* ATA_VERBOSE_DEBUG */
 591
 592 static void pdc20621_packet_start(struct ata_queued_cmd *qc)
 593 {
 594         struct ata_port *ap = qc->ap;
 595         struct ata_host *host = ap->host;
 596         unsigned int port_no = ap->port_no;
 597         void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
 598         unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
 599         u8 seq = (u8) (port_no + 1);
 600         unsigned int port_ofs;
 601
 602         /* hard-code chip #0 */
 603         mmio += PDC_CHIP0_OFS;
 604
 605         VPRINTK("ata%u: ENTER\n", ap->print_id);
 606
 607         wmb();                  /* flush PRD, pkt writes */
 608
 609         port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
 610
 611         /* if writing, we (1) DMA to DIMM, then (2) do ATA command */
 612         if (rw && qc->tf.protocol == ATA_PROT_DMA) {
 613                 seq += 4;
 614
 615                 pdc20621_dump_hdma(qc);
 616                 pdc20621_push_hdma(qc, seq, port_ofs + PDC_DIMM_HOST_PKT);
 617                 VPRINTK("queued ofs 0x%x (%u), seq %u\n",
 618                         port_ofs + PDC_DIMM_HOST_PKT,
 619                         port_ofs + PDC_DIMM_HOST_PKT,
 620                         seq);
 621         } else {
 622                 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
 623                 readl(mmio + PDC_20621_SEQCTL + (seq * 4));     /* flush */
 624
 625                 writel(port_ofs + PDC_DIMM_ATA_PKT,
 626                        ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 627                 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 628                 VPRINTK("submitted ofs 0x%x (%u), seq %u\n",
 629                         port_ofs + PDC_DIMM_ATA_PKT,
 630                         port_ofs + PDC_DIMM_ATA_PKT,
 631                         seq);
 632         }
 633 }
 634
 635 static unsigned int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc)
 636 {
 637         switch (qc->tf.protocol) {
 638         case ATA_PROT_DMA:
 639         case ATA_PROT_NODATA:
 640                 pdc20621_packet_start(qc);
 641                 return 0;
 642
 643         case ATA_PROT_ATAPI_DMA:
 644                 BUG();
 645                 break;
 646
 647         default:
 648                 break;
 649         }
 650
 651         return ata_qc_issue_prot(qc);
 652 }
 653
 654 static inline unsigned int pdc20621_host_intr( struct ata_port *ap,
 655                                           struct ata_queued_cmd *qc,
 656                                           unsigned int doing_hdma,
 657                                           void __iomem *mmio)
 658 {
 659         unsigned int port_no = ap->port_no;
 660         unsigned int port_ofs =
 661                 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
 662         u8 status;
 663         unsigned int handled = 0;
 664
 665         VPRINTK("ENTER\n");
 666
 667         if ((qc->tf.protocol == ATA_PROT_DMA) &&        /* read */
 668             (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
 669
 670                 /* step two - DMA from DIMM to host */
 671                 if (doing_hdma) {
 672                         VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap->print_id,
 673                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 674                         /* get drive status; clear intr; complete txn */
 675                         qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
 676                         ata_qc_complete(qc);
 677                         pdc20621_pop_hdma(qc);
 678                 }
 679
 680                 /* step one - exec ATA command */
 681                 else {
 682                         u8 seq = (u8) (port_no + 1 + 4);
 683                         VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap->print_id,
 684                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 685
 686                         /* submit hdma pkt */
 687                         pdc20621_dump_hdma(qc);
 688                         pdc20621_push_hdma(qc, seq,
 689                                            port_ofs + PDC_DIMM_HOST_PKT);
 690                 }
 691                 handled = 1;
 692
 693         } else if (qc->tf.protocol == ATA_PROT_DMA) {   /* write */
 694
 695                 /* step one - DMA from host to DIMM */
 696                 if (doing_hdma) {
 697                         u8 seq = (u8) (port_no + 1);
 698                         VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap->print_id,
 699                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 700
 701                         /* submit ata pkt */
 702                         writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
 703                         readl(mmio + PDC_20621_SEQCTL + (seq * 4));
 704                         writel(port_ofs + PDC_DIMM_ATA_PKT,
 705                                ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 706                         readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 707                 }
 708
 709                 /* step two - execute ATA command */
 710                 else {
 711                         VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap->print_id,
 712                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 713                         /* get drive status; clear intr; complete txn */
 714                         qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
 715                         ata_qc_complete(qc);
 716                         pdc20621_pop_hdma(qc);
 717                 }
 718                 handled = 1;
 719
 720         /* command completion, but no data xfer */
 721         } else if (qc->tf.protocol == ATA_PROT_NODATA) {
 722
 723                 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
 724                 DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status);
 725                 qc->err_mask |= ac_err_mask(status);
 726                 ata_qc_complete(qc);
 727                 handled = 1;
 728
 729         } else {
 730                 ap->stats.idle_irq++;
 731         }
 732
 733         return handled;
 734 }
 735
 736 static void pdc20621_irq_clear(struct ata_port *ap)
 737 {
 738         struct ata_host *host = ap->host;
 739         void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
 740
 741         mmio += PDC_CHIP0_OFS;
 742
 743         readl(mmio + PDC_20621_SEQMASK);
 744 }
 745
 746 static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance)
 747 {
 748         struct ata_host *host = dev_instance;
 749         struct ata_port *ap;
 750         u32 mask = 0;
 751         unsigned int i, tmp, port_no;
 752         unsigned int handled = 0;
 753         void __iomem *mmio_base;
 754
 755         VPRINTK("ENTER\n");
 756
 757         if (!host || !host->iomap[PDC_MMIO_BAR]) {
 758                 VPRINTK("QUICK EXIT\n");
 759                 return IRQ_NONE;
 760         }
 761
 762         mmio_base = host->iomap[PDC_MMIO_BAR];
 763
 764         /* reading should also clear interrupts */
 765         mmio_base += PDC_CHIP0_OFS;
 766         mask = readl(mmio_base + PDC_20621_SEQMASK);
 767         VPRINTK("mask == 0x%x\n", mask);
 768
 769         if (mask == 0xffffffff) {
 770                 VPRINTK("QUICK EXIT 2\n");
 771                 return IRQ_NONE;
 772         }
 773         mask &= 0xffff;         /* only 16 tags possible */
 774         if (!mask) {
 775                 VPRINTK("QUICK EXIT 3\n");
 776                 return IRQ_NONE;
 777         }
 778
 779         spin_lock(&host->lock);
 780
 781         for (i = 1; i < 9; i++) {
 782                 port_no = i - 1;
 783                 if (port_no > 3)
 784                         port_no -= 4;
 785                 if (port_no >= host->n_ports)
 786                         ap = NULL;
 787                 else
 788                         ap = host->ports[port_no];
 789                 tmp = mask & (1 << i);
 790                 VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i, port_no, ap, tmp);
 791                 if (tmp && ap &&
 792                     !(ap->flags & ATA_FLAG_DISABLED)) {
 793                         struct ata_queued_cmd *qc;
 794
 795                         qc = ata_qc_from_tag(ap, ap->active_tag);
 796                         if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
 797                                 handled += pdc20621_host_intr(ap, qc, (i > 4),
 798                                                               mmio_base);
 799                 }
 800         }
 801
 802         spin_unlock(&host->lock);
 803
 804         VPRINTK("mask == 0x%x\n", mask);
 805
 806         VPRINTK("EXIT\n");
 807
 808         return IRQ_RETVAL(handled);
 809 }
 810
 811 static void pdc_eng_timeout(struct ata_port *ap)
 812 {
 813         u8 drv_stat;
 814         struct ata_host *host = ap->host;
 815         struct ata_queued_cmd *qc;
 816         unsigned long flags;
 817
 818         DPRINTK("ENTER\n");
 819
 820         spin_lock_irqsave(&host->lock, flags);
 821
 822         qc = ata_qc_from_tag(ap, ap->active_tag);
 823
 824         switch (qc->tf.protocol) {
 825         case ATA_PROT_DMA:
 826         case ATA_PROT_NODATA:
 827                 ata_port_printk(ap, KERN_ERR, "command timeout\n");
 828                 qc->err_mask |= __ac_err_mask(ata_wait_idle(ap));
 829                 break;
 830
 831         default:
 832                 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
 833
 834                 ata_port_printk(ap, KERN_ERR,
 835                                 "unknown timeout, cmd 0x%x stat 0x%x\n",
 836                                 qc->tf.command, drv_stat);
 837
 838                 qc->err_mask |= ac_err_mask(drv_stat);
 839                 break;
 840         }
 841
 842         spin_unlock_irqrestore(&host->lock, flags);
 843         ata_eh_qc_complete(qc);
 844         DPRINTK("EXIT\n");
 845 }
 846
 847 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
 848 {
 849         WARN_ON (tf->protocol == ATA_PROT_DMA ||
 850                  tf->protocol == ATA_PROT_NODATA);
 851         ata_tf_load(ap, tf);
 852 }
 853
 854
 855 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
 856 {
 857         WARN_ON (tf->protocol == ATA_PROT_DMA ||
 858                  tf->protocol == ATA_PROT_NODATA);
 859         ata_exec_command(ap, tf);
 860 }
 861
 862
 863 static void pdc_sata_setup_port(struct ata_ioports *port, void __iomem *base)
 864 {
 865         port->cmd_addr          = base;
 866         port->data_addr         = base;
 867         port->feature_addr      =
 868         port->error_addr        = base + 0x4;
 869         port->nsect_addr        = base + 0x8;
 870         port->lbal_addr         = base + 0xc;
 871         port->lbam_addr         = base + 0x10;
 872         port->lbah_addr         = base + 0x14;
 873         port->device_addr       = base + 0x18;
 874         port->command_addr      =
 875         port->status_addr       = base + 0x1c;
 876         port->altstatus_addr    =
 877         port->ctl_addr          = base + 0x38;
 878 }
 879
 880
 881 #ifdef ATA_VERBOSE_DEBUG
 882 static void pdc20621_get_from_dimm(struct ata_host *host, void *psource,
 883                                    u32 offset, u32 size)
 884 {
 885         u32 window_size;
 886         u16 idx;
 887         u8 page_mask;
 888         long dist;
 889         void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
 890         void __iomem *dimm_mmio = host->iomap[PDC_DIMM_BAR];
 891
 892         /* hard-code chip #0 */
 893         mmio += PDC_CHIP0_OFS;
 894
 895         page_mask = 0x00;
 896         window_size = 0x2000 * 4; /* 32K byte uchar size */
 897         idx = (u16) (offset / window_size);
 898
 899         writel(0x01, mmio + PDC_GENERAL_CTLR);
 900         readl(mmio + PDC_GENERAL_CTLR);
 901         writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 902         readl(mmio + PDC_DIMM_WINDOW_CTLR);
 903
 904         offset -= (idx * window_size);
 905         idx++;
 906         dist = ((long) (window_size - (offset + size))) >= 0 ? size :
 907                 (long) (window_size - offset);
 908         memcpy_fromio((char *) psource, (char *) (dimm_mmio + offset / 4),
 909                       dist);
 910
 911         psource += dist;
 912         size -= dist;
 913         for (; (long) size >= (long) window_size ;) {
 914                 writel(0x01, mmio + PDC_GENERAL_CTLR);
 915                 readl(mmio + PDC_GENERAL_CTLR);
 916                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 917                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
 918                 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
 919                               window_size / 4);
 920                 psource += window_size;
 921                 size -= window_size;
 922                 idx ++;
 923         }
 924
 925         if (size) {
 926                 writel(0x01, mmio + PDC_GENERAL_CTLR);
 927                 readl(mmio + PDC_GENERAL_CTLR);
 928                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 929                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
 930                 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
 931                               size / 4);
 932         }
 933 }
 934 #endif
 935
 936
 937 static void pdc20621_put_to_dimm(struct ata_host *host, void *psource,
 938                                  u32 offset, u32 size)
 939 {
 940         u32 window_size;
 941         u16 idx;
 942         u8 page_mask;
 943         long dist;
 944         void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
 945         void __iomem *dimm_mmio = host->iomap[PDC_DIMM_BAR];
 946
 947         /* hard-code chip #0 */
 948         mmio += PDC_CHIP0_OFS;
 949
 950         page_mask = 0x00;
 951         window_size = 0x2000 * 4;       /* 32K byte uchar size */
 952         idx = (u16) (offset / window_size);
 953
 954         writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 955         readl(mmio + PDC_DIMM_WINDOW_CTLR);
 956         offset -= (idx * window_size);
 957         idx++;
 958         dist = ((long)(s32)(window_size - (offset + size))) >= 0 ? size :
 959                 (long) (window_size - offset);
 960         memcpy_toio(dimm_mmio + offset / 4, psource, dist);
 961         writel(0x01, mmio + PDC_GENERAL_CTLR);
 962         readl(mmio + PDC_GENERAL_CTLR);
 963
 964         psource += dist;
 965         size -= dist;
 966         for (; (long) size >= (long) window_size ;) {
 967                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 968                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
 969                 memcpy_toio(dimm_mmio, psource, window_size / 4);
 970                 writel(0x01, mmio + PDC_GENERAL_CTLR);
 971                 readl(mmio + PDC_GENERAL_CTLR);
 972                 psource += window_size;
 973                 size -= window_size;
 974                 idx ++;
 975         }
 976
 977         if (size) {
 978                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 979                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
 980                 memcpy_toio(dimm_mmio, psource, size / 4);
 981                 writel(0x01, mmio + PDC_GENERAL_CTLR);
 982                 readl(mmio + PDC_GENERAL_CTLR);
 983         }
 984 }
 985
 986
 987 static unsigned int pdc20621_i2c_read(struct ata_host *host, u32 device,
 988                                       u32 subaddr, u32 *pdata)
 989 {
 990         void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
 991         u32 i2creg  = 0;
 992         u32 status;
 993         u32 count =0;
 994
 995         /* hard-code chip #0 */
 996         mmio += PDC_CHIP0_OFS;
 997
 998         i2creg |= device << 24;
 999         i2creg |= subaddr << 16;
1000
1001         /* Set the device and subaddress */
1002         writel(i2creg, mmio + PDC_I2C_ADDR_DATA_OFFSET);
1003         readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
1004
1005         /* Write Control to perform read operation, mask int */
1006         writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT,
1007                mmio + PDC_I2C_CONTROL_OFFSET);
1008
1009         for (count = 0; count <= 1000; count ++) {
1010                 status = readl(mmio + PDC_I2C_CONTROL_OFFSET);
1011                 if (status & PDC_I2C_COMPLETE) {
1012                         status = readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
1013                         break;
1014                 } else if (count == 1000)
1015                         return 0;
1016         }
1017
1018         *pdata = (status >> 8) & 0x000000ff;
1019         return 1;
1020 }
1021
1022
1023 static int pdc20621_detect_dimm(struct ata_host *host)
1024 {
1025         u32 data=0 ;
1026         if (pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1027                              PDC_DIMM_SPD_SYSTEM_FREQ, &data)) {
1028                 if (data == 100)
1029                         return 100;
1030         } else
1031                 return 0;
1032
1033         if (pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) {
1034                 if(data <= 0x75)
1035                         return 133;
1036         } else
1037                 return 0;
1038
1039         return 0;
1040 }
1041
1042
1043 static int pdc20621_prog_dimm0(struct ata_host *host)
1044 {
1045         u32 spd0[50];
1046         u32 data = 0;
1047         int size, i;
1048         u8 bdimmsize;
1049         void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1050         static const struct {
1051                 unsigned int reg;
1052                 unsigned int ofs;
1053         } pdc_i2c_read_data [] = {
1054                 { PDC_DIMM_SPD_TYPE, 11 },
1055                 { PDC_DIMM_SPD_FRESH_RATE, 12 },
1056                 { PDC_DIMM_SPD_COLUMN_NUM, 4 },
1057                 { PDC_DIMM_SPD_ATTRIBUTE, 21 },
1058                 { PDC_DIMM_SPD_ROW_NUM, 3 },
1059                 { PDC_DIMM_SPD_BANK_NUM, 17 },
1060                 { PDC_DIMM_SPD_MODULE_ROW, 5 },
1061                 { PDC_DIMM_SPD_ROW_PRE_CHARGE, 27 },
1062                 { PDC_DIMM_SPD_ROW_ACTIVE_DELAY, 28 },
1063                 { PDC_DIMM_SPD_RAS_CAS_DELAY, 29 },
1064                 { PDC_DIMM_SPD_ACTIVE_PRECHARGE, 30 },
1065                 { PDC_DIMM_SPD_CAS_LATENCY, 18 },
1066         };
1067
1068         /* hard-code chip #0 */
1069         mmio += PDC_CHIP0_OFS;
1070
1071         for(i=0; i<ARRAY_SIZE(pdc_i2c_read_data); i++)
1072                 pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1073                                   pdc_i2c_read_data[i].reg,
1074                                   &spd0[pdc_i2c_read_data[i].ofs]);
1075
1076         data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4);
1077         data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) |
1078                 ((((spd0[27] + 9) / 10) - 1) << 8) ;
1079         data |= (((((spd0[29] > spd0[28])
1080                     ? spd0[29] : spd0[28]) + 9) / 10) - 1) << 10;
1081         data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12;
1082
1083         if (spd0[18] & 0x08)
1084                 data |= ((0x03) << 14);
1085         else if (spd0[18] & 0x04)
1086                 data |= ((0x02) << 14);
1087         else if (spd0[18] & 0x01)
1088                 data |= ((0x01) << 14);
1089         else
1090                 data |= (0 << 14);
1091
1092         /*
1093            Calculate the size of bDIMMSize (power of 2) and
1094            merge the DIMM size by program start/end address.
1095         */
1096
1097         bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3;
1098         size = (1 << bdimmsize) >> 20;  /* size = xxx(MB) */
1099         data |= (((size / 16) - 1) << 16);
1100         data |= (0 << 23);
1101         data |= 8;
1102         writel(data, mmio + PDC_DIMM0_CONTROL_OFFSET);
1103         readl(mmio + PDC_DIMM0_CONTROL_OFFSET);
1104         return size;
1105 }
1106
1107
1108 static unsigned int pdc20621_prog_dimm_global(struct ata_host *host)
1109 {
1110         u32 data, spd0;
1111         int error, i;
1112         void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1113
1114         /* hard-code chip #0 */
1115         mmio += PDC_CHIP0_OFS;
1116
1117         /*
1118           Set To Default : DIMM Module Global Control Register (0x022259F1)
1119           DIMM Arbitration Disable (bit 20)
1120           DIMM Data/Control Output Driving Selection (bit12 - bit15)
1121           Refresh Enable (bit 17)
1122         */
1123
1124         data = 0x022259F1;
1125         writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1126         readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1127
1128         /* Turn on for ECC */
1129         pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1130                           PDC_DIMM_SPD_TYPE, &spd0);
1131         if (spd0 == 0x02) {
1132                 data |= (0x01 << 16);
1133                 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1134                 readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1135                 printk(KERN_ERR "Local DIMM ECC Enabled\n");
1136         }
1137
1138         /* DIMM Initialization Select/Enable (bit 18/19) */
1139         data &= (~(1<<18));
1140         data |= (1<<19);
1141         writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1142
1143         error = 1;
1144         for (i = 1; i <= 10; i++) {   /* polling ~5 secs */
1145                 data = readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1146                 if (!(data & (1<<19))) {
1147                         error = 0;
1148                         break;
1149                 }
1150                 msleep(i*100);
1151         }
1152         return error;
1153 }
1154
1155
1156 static unsigned int pdc20621_dimm_init(struct ata_host *host)
1157 {
1158         int speed, size, length;
1159         u32 addr,spd0,pci_status;
1160         u32 tmp=0;
1161         u32 time_period=0;
1162         u32 tcount=0;
1163         u32 ticks=0;
1164         u32 clock=0;
1165         u32 fparam=0;
1166         void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1167
1168         /* hard-code chip #0 */
1169         mmio += PDC_CHIP0_OFS;
1170
1171         /* Initialize PLL based upon PCI Bus Frequency */
1172
1173         /* Initialize Time Period Register */
1174         writel(0xffffffff, mmio + PDC_TIME_PERIOD);
1175         time_period = readl(mmio + PDC_TIME_PERIOD);
1176         VPRINTK("Time Period Register (0x40): 0x%x\n", time_period);
1177
1178         /* Enable timer */
1179         writel(0x00001a0, mmio + PDC_TIME_CONTROL);
1180         readl(mmio + PDC_TIME_CONTROL);
1181
1182         /* Wait 3 seconds */
1183         msleep(3000);
1184
1185         /*
1186            When timer is enabled, counter is decreased every internal
1187            clock cycle.
1188         */
1189
1190         tcount = readl(mmio + PDC_TIME_COUNTER);
1191         VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount);
1192
1193         /*
1194            If SX4 is on PCI-X bus, after 3 seconds, the timer counter
1195            register should be >= (0xffffffff - 3x10^8).
1196         */
1197         if(tcount >= PCI_X_TCOUNT) {
1198                 ticks = (time_period - tcount);
1199                 VPRINTK("Num counters 0x%x (%d)\n", ticks, ticks);
1200
1201                 clock = (ticks / 300000);
1202                 VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock, clock);
1203
1204                 clock = (clock * 33);
1205                 VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock, clock);
1206
1207                 /* PLL F Param (bit 22:16) */
1208                 fparam = (1400000 / clock) - 2;
1209                 VPRINTK("PLL F Param: 0x%x (%d)\n", fparam, fparam);
1210
1211                 /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */
1212                 pci_status = (0x8a001824 | (fparam << 16));
1213         } else
1214                 pci_status = PCI_PLL_INIT;
1215
1216         /* Initialize PLL. */
1217         VPRINTK("pci_status: 0x%x\n", pci_status);
1218         writel(pci_status, mmio + PDC_CTL_STATUS);
1219         readl(mmio + PDC_CTL_STATUS);
1220
1221         /*
1222            Read SPD of DIMM by I2C interface,
1223            and program the DIMM Module Controller.
1224         */
1225         if (!(speed = pdc20621_detect_dimm(host))) {
1226                 printk(KERN_ERR "Detect Local DIMM Fail\n");
1227                 return 1;       /* DIMM error */
1228         }
1229         VPRINTK("Local DIMM Speed = %d\n", speed);
1230
1231         /* Programming DIMM0 Module Control Register (index_CID0:80h) */
1232         size = pdc20621_prog_dimm0(host);
1233         VPRINTK("Local DIMM Size = %dMB\n",size);
1234
1235         /* Programming DIMM Module Global Control Register (index_CID0:88h) */
1236         if (pdc20621_prog_dimm_global(host)) {
1237                 printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n");
1238                 return 1;
1239         }
1240
1241 #ifdef ATA_VERBOSE_DEBUG
1242         {
1243                 u8 test_parttern1[40] = {0x55,0xAA,'P','r','o','m','i','s','e',' ',
1244                                 'N','o','t',' ','Y','e','t',' ','D','e','f','i','n','e','d',' ',
1245                                  '1','.','1','0',
1246                                 '9','8','0','3','1','6','1','2',0,0};
1247                 u8 test_parttern2[40] = {0};
1248
1249                 pdc20621_put_to_dimm(host, (void *) test_parttern2, 0x10040, 40);
1250                 pdc20621_put_to_dimm(host, (void *) test_parttern2, 0x40, 40);
1251
1252                 pdc20621_put_to_dimm(host, (void *) test_parttern1, 0x10040, 40);
1253                 pdc20621_get_from_dimm(host, (void *) test_parttern2, 0x40, 40);
1254                 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1255                        test_parttern2[1], &(test_parttern2[2]));
1256                 pdc20621_get_from_dimm(host, (void *) test_parttern2, 0x10040,
1257                                        40);
1258                 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1259                        test_parttern2[1], &(test_parttern2[2]));
1260
1261                 pdc20621_put_to_dimm(host, (void *) test_parttern1, 0x40, 40);
1262                 pdc20621_get_from_dimm(host, (void *) test_parttern2, 0x40, 40);
1263                 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1264                        test_parttern2[1], &(test_parttern2[2]));
1265         }
1266 #endif
1267
1268         /* ECC initiliazation. */
1269
1270         pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1271                           PDC_DIMM_SPD_TYPE, &spd0);
1272         if (spd0 == 0x02) {
1273                 VPRINTK("Start ECC initialization\n");
1274                 addr = 0;
1275                 length = size * 1024 * 1024;
1276                 while (addr < length) {
1277                         pdc20621_put_to_dimm(host, (void *) &tmp, addr,
1278                                              sizeof(u32));
1279                         addr += sizeof(u32);
1280                 }
1281                 VPRINTK("Finish ECC initialization\n");
1282         }
1283         return 0;
1284 }
1285
1286
1287 static void pdc_20621_init(struct ata_host *host)
1288 {
1289         u32 tmp;
1290         void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1291
1292         /* hard-code chip #0 */
1293         mmio += PDC_CHIP0_OFS;
1294
1295         /*
1296          * Select page 0x40 for our 32k DIMM window
1297          */
1298         tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;
1299         tmp |= PDC_PAGE_WINDOW; /* page 40h; arbitrarily selected */
1300         writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
1301
1302         /*
1303          * Reset Host DMA
1304          */
1305         tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1306         tmp |= PDC_RESET;
1307         writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1308         readl(mmio + PDC_HDMA_CTLSTAT);         /* flush */
1309
1310         udelay(10);
1311
1312         tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1313         tmp &= ~PDC_RESET;
1314         writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1315         readl(mmio + PDC_HDMA_CTLSTAT);         /* flush */
1316 }
1317
1318 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1319 {
1320         static int printed_version;
1321         const struct ata_port_info *ppi[] =
1322                 { &pdc_port_info[ent->driver_data], NULL };
1323         struct ata_host *host;
1324         void __iomem *base;
1325         struct pdc_host_priv *hpriv;
1326         int rc;
1327
1328         if (!printed_version++)
1329                 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1330
1331         /* allocate host */
1332         host = ata_host_alloc_pinfo(&pdev->dev, ppi, 4);
1333         hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
1334         if (!host || !hpriv)
1335                 return -ENOMEM;
1336
1337         host->private_data = hpriv;
1338
1339         /* acquire resources and fill host */
1340         rc = pcim_enable_device(pdev);
1341         if (rc)
1342                 return rc;
1343
1344         rc = pcim_iomap_regions(pdev, (1 << PDC_MMIO_BAR) | (1 << PDC_DIMM_BAR),
1345                                 DRV_NAME);
1346         if (rc == -EBUSY)
1347                 pcim_pin_device(pdev);
1348         if (rc)
1349                 return rc;
1350         host->iomap = pcim_iomap_table(pdev);
1351
1352         base = host->iomap[PDC_MMIO_BAR] + PDC_CHIP0_OFS;
1353         pdc_sata_setup_port(&host->ports[0]->ioaddr, base + 0x200);
1354         pdc_sata_setup_port(&host->ports[1]->ioaddr, base + 0x280);
1355         pdc_sata_setup_port(&host->ports[2]->ioaddr, base + 0x300);
1356         pdc_sata_setup_port(&host->ports[3]->ioaddr, base + 0x380);
1357
1358         /* configure and activate */
1359         rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1360         if (rc)
1361                 return rc;
1362         rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1363         if (rc)
1364                 return rc;
1365
1366         if (pdc20621_dimm_init(host))
1367                 return -ENOMEM;
1368         pdc_20621_init(host);
1369
1370         pci_set_master(pdev);
1371         return ata_host_activate(host, pdev->irq, pdc20621_interrupt,
1372                                  IRQF_SHARED, &pdc_sata_sht);
1373 }
1374
1375
1376 static int __init pdc_sata_init(void)
1377 {
1378         return pci_register_driver(&pdc_sata_pci_driver);
1379 }
1380
1381
1382 static void __exit pdc_sata_exit(void)
1383 {
1384         pci_unregister_driver(&pdc_sata_pci_driver);
1385 }
1386
1387
1388 MODULE_AUTHOR("Jeff Garzik");
1389 MODULE_DESCRIPTION("Promise SATA low-level driver");
1390 MODULE_LICENSE("GPL");
1391 MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl);
1392 MODULE_VERSION(DRV_VERSION);
1393
1394 module_init(pdc_sata_init);
1395 module_exit(pdc_sata_exit);