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   1 /*
   2  *  linux/drivers/ide/pci/pdc202xx_old.c        Version 0.36    Sept 11, 2002
   3  *
   4  *  Copyright (C) 1998-2002             Andre Hedrick <andre@linux-ide.org>
   5  *  Copyright (C) 2006-2007             MontaVista Software, Inc.
   6  *
   7  *  Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
   8  *  compiled into the kernel if you have more than one card installed.
   9  *  Note that BIOS v1.29 is reported to fix the problem.  Since this is
  10  *  safe chipset tuning, including this support is harmless
  11  *
  12  *  Promise Ultra66 cards with BIOS v1.11 this
  13  *  compiled into the kernel if you have more than one card installed.
  14  *
  15  *  Promise Ultra100 cards.
  16  *
  17  *  The latest chipset code will support the following ::
  18  *  Three Ultra33 controllers and 12 drives.
  19  *  8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
  20  *  The 8/4 ratio is a BIOS code limit by promise.
  21  *
  22  *  UNLESS you enable "CONFIG_PDC202XX_BURST"
  23  *
  24  */
  25
  26 /*
  27  *  Portions Copyright (C) 1999 Promise Technology, Inc.
  28  *  Author: Frank Tiernan (frankt@promise.com)
  29  *  Released under terms of General Public License
  30  */
  31
  32 #include <linux/types.h>
  33 #include <linux/module.h>
  34 #include <linux/kernel.h>
  35 #include <linux/delay.h>
  36 #include <linux/timer.h>
  37 #include <linux/mm.h>
  38 #include <linux/ioport.h>
  39 #include <linux/blkdev.h>
  40 #include <linux/hdreg.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/pci.h>
  43 #include <linux/init.h>
  44 #include <linux/ide.h>
  45
  46 #include <asm/io.h>
  47 #include <asm/irq.h>
  48
  49 #define PDC202_DEBUG_CABLE              0
  50 #define PDC202XX_DEBUG_DRIVE_INFO       0
  51
  52 static const char *pdc_quirk_drives[] = {
  53         "QUANTUM FIREBALLlct08 08",
  54         "QUANTUM FIREBALLP KA6.4",
  55         "QUANTUM FIREBALLP KA9.1",
  56         "QUANTUM FIREBALLP LM20.4",
  57         "QUANTUM FIREBALLP KX13.6",
  58         "QUANTUM FIREBALLP KX20.5",
  59         "QUANTUM FIREBALLP KX27.3",
  60         "QUANTUM FIREBALLP LM20.5",
  61         NULL
  62 };
  63
  64 /* A Register */
  65 #define SYNC_ERRDY_EN   0xC0
  66
  67 #define SYNC_IN         0x80    /* control bit, different for master vs. slave drives */
  68 #define ERRDY_EN        0x40    /* control bit, different for master vs. slave drives */
  69 #define IORDY_EN        0x20    /* PIO: IOREADY */
  70 #define PREFETCH_EN     0x10    /* PIO: PREFETCH */
  71
  72 #define PA3             0x08    /* PIO"A" timing */
  73 #define PA2             0x04    /* PIO"A" timing */
  74 #define PA1             0x02    /* PIO"A" timing */
  75 #define PA0             0x01    /* PIO"A" timing */
  76
  77 /* B Register */
  78
  79 #define MB2             0x80    /* DMA"B" timing */
  80 #define MB1             0x40    /* DMA"B" timing */
  81 #define MB0             0x20    /* DMA"B" timing */
  82
  83 #define PB4             0x10    /* PIO_FORCE 1:0 */
  84
  85 #define PB3             0x08    /* PIO"B" timing */     /* PIO flow Control mode */
  86 #define PB2             0x04    /* PIO"B" timing */     /* PIO 4 */
  87 #define PB1             0x02    /* PIO"B" timing */     /* PIO 3 half */
  88 #define PB0             0x01    /* PIO"B" timing */     /* PIO 3 other half */
  89
  90 /* C Register */
  91 #define IORDYp_NO_SPEED 0x4F
  92 #define SPEED_DIS       0x0F
  93
  94 #define DMARQp          0x80
  95 #define IORDYp          0x40
  96 #define DMAR_EN         0x20
  97 #define DMAW_EN         0x10
  98
  99 #define MC3             0x08    /* DMA"C" timing */
 100 #define MC2             0x04    /* DMA"C" timing */
 101 #define MC1             0x02    /* DMA"C" timing */
 102 #define MC0             0x01    /* DMA"C" timing */
 103
 104 static u8 pdc202xx_ratemask (ide_drive_t *drive)
 105 {
 106         u8 mode;
 107
 108         switch(HWIF(drive)->pci_dev->device) {
 109                 case PCI_DEVICE_ID_PROMISE_20267:
 110                 case PCI_DEVICE_ID_PROMISE_20265:
 111                         mode = 3;
 112                         break;
 113                 case PCI_DEVICE_ID_PROMISE_20263:
 114                 case PCI_DEVICE_ID_PROMISE_20262:
 115                         mode = 2;
 116                         break;
 117                 case PCI_DEVICE_ID_PROMISE_20246:
 118                         return 1;
 119                 default:
 120                         return 0;
 121         }
 122         if (!eighty_ninty_three(drive))
 123                 mode = min(mode, (u8)1);
 124         return mode;
 125 }
 126
 127 static int pdc202xx_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 128 {
 129         ide_hwif_t *hwif        = HWIF(drive);
 130         struct pci_dev *dev     = hwif->pci_dev;
 131         u8 drive_pci            = 0x60 + (drive->dn << 2);
 132         u8 speed        = ide_rate_filter(pdc202xx_ratemask(drive), xferspeed);
 133
 134         u32                     drive_conf;
 135         u8                      AP, BP, CP, DP;
 136         u8                      TA = 0, TB = 0, TC = 0;
 137
 138         if (drive->media != ide_disk &&
 139                 drive->media != ide_cdrom && speed < XFER_SW_DMA_0)
 140                 return -1;
 141
 142         pci_read_config_dword(dev, drive_pci, &drive_conf);
 143         pci_read_config_byte(dev, (drive_pci), &AP);
 144         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 145         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 146         pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
 147
 148         if (speed < XFER_SW_DMA_0) {
 149                 if ((AP & 0x0F) || (BP & 0x07)) {
 150                         /* clear PIO modes of lower 8421 bits of A Register */
 151                         pci_write_config_byte(dev, (drive_pci), AP &~0x0F);
 152                         pci_read_config_byte(dev, (drive_pci), &AP);
 153
 154                         /* clear PIO modes of lower 421 bits of B Register */
 155                         pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0x07);
 156                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 157
 158                         pci_read_config_byte(dev, (drive_pci), &AP);
 159                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 160                 }
 161         } else {
 162                 if ((BP & 0xF0) && (CP & 0x0F)) {
 163                         /* clear DMA modes of upper 842 bits of B Register */
 164                         /* clear PIO forced mode upper 1 bit of B Register */
 165                         pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0xF0);
 166                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 167
 168                         /* clear DMA modes of lower 8421 bits of C Register */
 169                         pci_write_config_byte(dev, (drive_pci)|0x02, CP &~0x0F);
 170                         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 171                 }
 172         }
 173
 174         pci_read_config_byte(dev, (drive_pci), &AP);
 175         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 176         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 177
 178         switch(speed) {
 179                 case XFER_UDMA_6:       speed = XFER_UDMA_5;
 180                 case XFER_UDMA_5:
 181                 case XFER_UDMA_4:       TB = 0x20; TC = 0x01; break;
 182                 case XFER_UDMA_2:       TB = 0x20; TC = 0x01; break;
 183                 case XFER_UDMA_3:
 184                 case XFER_UDMA_1:       TB = 0x40; TC = 0x02; break;
 185                 case XFER_UDMA_0:
 186                 case XFER_MW_DMA_2:     TB = 0x60; TC = 0x03; break;
 187                 case XFER_MW_DMA_1:     TB = 0x60; TC = 0x04; break;
 188                 case XFER_MW_DMA_0:
 189                 case XFER_SW_DMA_2:     TB = 0x60; TC = 0x05; break;
 190                 case XFER_SW_DMA_1:     TB = 0x80; TC = 0x06; break;
 191                 case XFER_SW_DMA_0:     TB = 0xC0; TC = 0x0B; break;
 192                 case XFER_PIO_4:        TA = 0x01; TB = 0x04; break;
 193                 case XFER_PIO_3:        TA = 0x02; TB = 0x06; break;
 194                 case XFER_PIO_2:        TA = 0x03; TB = 0x08; break;
 195                 case XFER_PIO_1:        TA = 0x05; TB = 0x0C; break;
 196                 case XFER_PIO_0:
 197                 default:                TA = 0x09; TB = 0x13; break;
 198         }
 199
 200         if (speed < XFER_SW_DMA_0) {
 201                 pci_write_config_byte(dev, (drive_pci), AP|TA);
 202                 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
 203         } else {
 204                 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
 205                 pci_write_config_byte(dev, (drive_pci)|0x02, CP|TC);
 206         }
 207
 208 #if PDC202XX_DEBUG_DRIVE_INFO
 209         printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
 210                 drive->name, ide_xfer_verbose(speed),
 211                 drive->dn, drive_conf);
 212                 pci_read_config_dword(dev, drive_pci, &drive_conf);
 213         printk("0x%08x\n", drive_conf);
 214 #endif /* PDC202XX_DEBUG_DRIVE_INFO */
 215
 216         return (ide_config_drive_speed(drive, speed));
 217 }
 218
 219
 220 static void pdc202xx_tune_drive(ide_drive_t *drive, u8 pio)
 221 {
 222         pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
 223         pdc202xx_tune_chipset(drive, XFER_PIO_0 + pio);
 224 }
 225
 226 static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
 227 {
 228         u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);
 229         pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
 230         return (CIS & mask) ? 1 : 0;
 231 }
 232
 233 /*
 234  * Set the control register to use the 66MHz system
 235  * clock for UDMA 3/4/5 mode operation when necessary.
 236  *
 237  * It may also be possible to leave the 66MHz clock on
 238  * and readjust the timing parameters.
 239  */
 240 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
 241 {
 242         unsigned long clock_reg = hwif->dma_master + 0x11;
 243         u8 clock = inb(clock_reg);
 244
 245         outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
 246 }
 247
 248 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
 249 {
 250         unsigned long clock_reg = hwif->dma_master + 0x11;
 251         u8 clock = inb(clock_reg);
 252
 253         outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
 254 }
 255
 256 static int config_chipset_for_dma (ide_drive_t *drive)
 257 {
 258         struct hd_driveid *id   = drive->id;
 259         ide_hwif_t *hwif        = HWIF(drive);
 260         struct pci_dev *dev     = hwif->pci_dev;
 261         u32 drive_conf          = 0;
 262         u8 drive_pci            = 0x60 + (drive->dn << 2);
 263         u8 test1 = 0, test2 = 0, speed = -1;
 264         u8 AP = 0, cable = 0;
 265
 266         u8 ultra_66             = ((id->dma_ultra & 0x0010) ||
 267                                    (id->dma_ultra & 0x0008)) ? 1 : 0;
 268
 269         if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
 270                 cable = pdc202xx_old_cable_detect(hwif);
 271         else
 272                 ultra_66 = 0;
 273
 274         if (ultra_66 && cable) {
 275                 printk(KERN_WARNING "Warning: %s channel requires an 80-pin cable for operation.\n", hwif->channel ? "Secondary":"Primary");
 276                 printk(KERN_WARNING "%s reduced to Ultra33 mode.\n", drive->name);
 277         }
 278
 279         if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
 280                 pdc_old_disable_66MHz_clock(drive->hwif);
 281
 282         drive_pci = 0x60 + (drive->dn << 2);
 283         pci_read_config_dword(dev, drive_pci, &drive_conf);
 284         if ((drive_conf != 0x004ff304) && (drive_conf != 0x004ff3c4))
 285                 goto chipset_is_set;
 286
 287         pci_read_config_byte(dev, drive_pci, &test1);
 288         if (!(test1 & SYNC_ERRDY_EN)) {
 289                 if (drive->select.b.unit & 0x01) {
 290                         pci_read_config_byte(dev, drive_pci - 4, &test2);
 291                         if ((test2 & SYNC_ERRDY_EN) &&
 292                             !(test1 & SYNC_ERRDY_EN)) {
 293                                 pci_write_config_byte(dev, drive_pci,
 294                                         test1|SYNC_ERRDY_EN);
 295                         }
 296                 } else {
 297                         pci_write_config_byte(dev, drive_pci,
 298                                 test1|SYNC_ERRDY_EN);
 299                 }
 300         }
 301
 302 chipset_is_set:
 303
 304         pci_read_config_byte(dev, (drive_pci), &AP);
 305         if (id->capability & 4) /* IORDY_EN */
 306                 pci_write_config_byte(dev, (drive_pci), AP|IORDY_EN);
 307         pci_read_config_byte(dev, (drive_pci), &AP);
 308         if (drive->media == ide_disk)   /* PREFETCH_EN */
 309                 pci_write_config_byte(dev, (drive_pci), AP|PREFETCH_EN);
 310
 311         speed = ide_dma_speed(drive, pdc202xx_ratemask(drive));
 312
 313         if (!(speed)) {
 314                 /* restore original pci-config space */
 315                 pci_write_config_dword(dev, drive_pci, drive_conf);
 316                 return 0;
 317         }
 318
 319         (void) hwif->speedproc(drive, speed);
 320         return ide_dma_enable(drive);
 321 }
 322
 323 static int pdc202xx_config_drive_xfer_rate (ide_drive_t *drive)
 324 {
 325         drive->init_speed = 0;
 326
 327         if (ide_use_dma(drive) && config_chipset_for_dma(drive))
 328                 return 0;
 329
 330         if (ide_use_fast_pio(drive))
 331                 pdc202xx_tune_drive(drive, 255);
 332
 333         return -1;
 334 }
 335
 336 static int pdc202xx_quirkproc (ide_drive_t *drive)
 337 {
 338         const char **list, *model = drive->id->model;
 339
 340         for (list = pdc_quirk_drives; *list != NULL; list++)
 341                 if (strstr(model, *list) != NULL)
 342                         return 2;
 343         return 0;
 344 }
 345
 346 static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
 347 {
 348         if (drive->current_speed > XFER_UDMA_2)
 349                 pdc_old_enable_66MHz_clock(drive->hwif);
 350         if (drive->media != ide_disk || drive->addressing == 1) {
 351                 struct request *rq      = HWGROUP(drive)->rq;
 352                 ide_hwif_t *hwif        = HWIF(drive);
 353                 unsigned long high_16   = hwif->dma_master;
 354                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 355                 u32 word_count  = 0;
 356                 u8 clock = inb(high_16 + 0x11);
 357
 358                 outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
 359                 word_count = (rq->nr_sectors << 8);
 360                 word_count = (rq_data_dir(rq) == READ) ?
 361                                         word_count | 0x05000000 :
 362                                         word_count | 0x06000000;
 363                 outl(word_count, atapi_reg);
 364         }
 365         ide_dma_start(drive);
 366 }
 367
 368 static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
 369 {
 370         if (drive->media != ide_disk || drive->addressing == 1) {
 371                 ide_hwif_t *hwif        = HWIF(drive);
 372                 unsigned long high_16   = hwif->dma_master;
 373                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 374                 u8 clock                = 0;
 375
 376                 outl(0, atapi_reg); /* zero out extra */
 377                 clock = inb(high_16 + 0x11);
 378                 outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
 379         }
 380         if (drive->current_speed > XFER_UDMA_2)
 381                 pdc_old_disable_66MHz_clock(drive->hwif);
 382         return __ide_dma_end(drive);
 383 }
 384
 385 static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
 386 {
 387         ide_hwif_t *hwif        = HWIF(drive);
 388         unsigned long high_16   = hwif->dma_master;
 389         u8 dma_stat             = inb(hwif->dma_status);
 390         u8 sc1d                 = inb(high_16 + 0x001d);
 391
 392         if (hwif->channel) {
 393                 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
 394                 if ((sc1d & 0x50) == 0x50)
 395                         goto somebody_else;
 396                 else if ((sc1d & 0x40) == 0x40)
 397                         return (dma_stat & 4) == 4;
 398         } else {
 399                 /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
 400                 if ((sc1d & 0x05) == 0x05)
 401                         goto somebody_else;
 402                 else if ((sc1d & 0x04) == 0x04)
 403                         return (dma_stat & 4) == 4;
 404         }
 405 somebody_else:
 406         return (dma_stat & 4) == 4;     /* return 1 if INTR asserted */
 407 }
 408
 409 static int pdc202xx_ide_dma_lostirq(ide_drive_t *drive)
 410 {
 411         if (HWIF(drive)->resetproc != NULL)
 412                 HWIF(drive)->resetproc(drive);
 413         return __ide_dma_lostirq(drive);
 414 }
 415
 416 static int pdc202xx_ide_dma_timeout(ide_drive_t *drive)
 417 {
 418         if (HWIF(drive)->resetproc != NULL)
 419                 HWIF(drive)->resetproc(drive);
 420         return __ide_dma_timeout(drive);
 421 }
 422
 423 static void pdc202xx_reset_host (ide_hwif_t *hwif)
 424 {
 425         unsigned long high_16   = hwif->dma_master;
 426         u8 udma_speed_flag      = inb(high_16 | 0x001f);
 427
 428         outb(udma_speed_flag | 0x10, high_16 | 0x001f);
 429         mdelay(100);
 430         outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
 431         mdelay(2000);   /* 2 seconds ?! */
 432
 433         printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
 434                 hwif->channel ? "Secondary" : "Primary");
 435 }
 436
 437 static void pdc202xx_reset (ide_drive_t *drive)
 438 {
 439         ide_hwif_t *hwif        = HWIF(drive);
 440         ide_hwif_t *mate        = hwif->mate;
 441
 442         pdc202xx_reset_host(hwif);
 443         pdc202xx_reset_host(mate);
 444         pdc202xx_tune_drive(drive, 255);
 445 }
 446
 447 static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
 448                                                         const char *name)
 449 {
 450         /* This doesn't appear needed */
 451         if (dev->resource[PCI_ROM_RESOURCE].start) {
 452                 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
 453                         dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
 454                 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name,
 455                         (unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
 456         }
 457
 458         return dev->irq;
 459 }
 460
 461 static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
 462 {
 463         struct pci_dev *dev = hwif->pci_dev;
 464
 465         /* PDC20265 has problems with large LBA48 requests */
 466         if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
 467             (dev->device == PCI_DEVICE_ID_PROMISE_20265))
 468                 hwif->rqsize = 256;
 469
 470         hwif->autodma = 0;
 471         hwif->tuneproc  = &pdc202xx_tune_drive;
 472         hwif->quirkproc = &pdc202xx_quirkproc;
 473
 474         if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246)
 475                 hwif->resetproc = &pdc202xx_reset;
 476
 477         hwif->speedproc = &pdc202xx_tune_chipset;
 478
 479         hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
 480
 481         hwif->ultra_mask = 0x3f;
 482         hwif->mwdma_mask = 0x07;
 483         hwif->swdma_mask = 0x07;
 484         hwif->atapi_dma = 1;
 485
 486         hwif->err_stops_fifo = 1;
 487
 488         hwif->ide_dma_check = &pdc202xx_config_drive_xfer_rate;
 489         hwif->ide_dma_lostirq = &pdc202xx_ide_dma_lostirq;
 490         hwif->ide_dma_timeout = &pdc202xx_ide_dma_timeout;
 491
 492         if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
 493                 if (!(hwif->udma_four))
 494                         hwif->udma_four = (pdc202xx_old_cable_detect(hwif)) ? 0 : 1;
 495                 hwif->dma_start = &pdc202xx_old_ide_dma_start;
 496                 hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
 497         }
 498         hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
 499
 500         if (!noautodma)
 501                 hwif->autodma = 1;
 502         hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
 503 #if PDC202_DEBUG_CABLE
 504         printk(KERN_DEBUG "%s: %s-pin cable\n",
 505                 hwif->name, hwif->udma_four ? "80" : "40");
 506 #endif /* PDC202_DEBUG_CABLE */
 507 }
 508
 509 static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
 510 {
 511         u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
 512
 513         if (hwif->channel) {
 514                 ide_setup_dma(hwif, dmabase, 8);
 515                 return;
 516         }
 517
 518         udma_speed_flag = inb(dmabase | 0x1f);
 519         primary_mode    = inb(dmabase | 0x1a);
 520         secondary_mode  = inb(dmabase | 0x1b);
 521         printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
 522                 "Primary %s Mode " \
 523                 "Secondary %s Mode.\n", hwif->cds->name,
 524                 (udma_speed_flag & 1) ? "EN" : "DIS",
 525                 (primary_mode & 1) ? "MASTER" : "PCI",
 526                 (secondary_mode & 1) ? "MASTER" : "PCI" );
 527
 528 #ifdef CONFIG_PDC202XX_BURST
 529         if (!(udma_speed_flag & 1)) {
 530                 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
 531                         hwif->cds->name, udma_speed_flag,
 532                         (udma_speed_flag|1));
 533                 outb(udma_speed_flag | 1, dmabase | 0x1f);
 534                 printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
 535         }
 536 #endif /* CONFIG_PDC202XX_BURST */
 537
 538         ide_setup_dma(hwif, dmabase, 8);
 539 }
 540
 541 static int __devinit init_setup_pdc202ata4(struct pci_dev *dev,
 542                                            ide_pci_device_t *d)
 543 {
 544         if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
 545                 u8 irq = 0, irq2 = 0;
 546                 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
 547                 /* 0xbc */
 548                 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
 549                 if (irq != irq2) {
 550                         pci_write_config_byte(dev,
 551                                 (PCI_INTERRUPT_LINE)|0x80, irq);     /* 0xbc */
 552                         printk(KERN_INFO "%s: pci-config space interrupt "
 553                                 "mirror fixed.\n", d->name);
 554                 }
 555         }
 556         return ide_setup_pci_device(dev, d);
 557 }
 558
 559 static int __devinit init_setup_pdc20265(struct pci_dev *dev,
 560                                          ide_pci_device_t *d)
 561 {
 562         if ((dev->bus->self) &&
 563             (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
 564             ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
 565              (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
 566                 printk(KERN_INFO "ide: Skipping Promise PDC20265 "
 567                         "attached to I2O RAID controller.\n");
 568                 return -ENODEV;
 569         }
 570         return ide_setup_pci_device(dev, d);
 571 }
 572
 573 static int __devinit init_setup_pdc202xx(struct pci_dev *dev,
 574                                          ide_pci_device_t *d)
 575 {
 576         return ide_setup_pci_device(dev, d);
 577 }
 578
 579 static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
 580         {       /* 0 */
 581                 .name           = "PDC20246",
 582                 .init_setup     = init_setup_pdc202ata4,
 583                 .init_chipset   = init_chipset_pdc202xx,
 584                 .init_hwif      = init_hwif_pdc202xx,
 585                 .init_dma       = init_dma_pdc202xx,
 586                 .channels       = 2,
 587                 .autodma        = AUTODMA,
 588                 .bootable       = OFF_BOARD,
 589                 .extra          = 16,
 590         },{     /* 1 */
 591                 .name           = "PDC20262",
 592                 .init_setup     = init_setup_pdc202ata4,
 593                 .init_chipset   = init_chipset_pdc202xx,
 594                 .init_hwif      = init_hwif_pdc202xx,
 595                 .init_dma       = init_dma_pdc202xx,
 596                 .channels       = 2,
 597                 .autodma        = AUTODMA,
 598                 .bootable       = OFF_BOARD,
 599                 .extra          = 48,
 600         },{     /* 2 */
 601                 .name           = "PDC20263",
 602                 .init_setup     = init_setup_pdc202ata4,
 603                 .init_chipset   = init_chipset_pdc202xx,
 604                 .init_hwif      = init_hwif_pdc202xx,
 605                 .init_dma       = init_dma_pdc202xx,
 606                 .channels       = 2,
 607                 .autodma        = AUTODMA,
 608                 .bootable       = OFF_BOARD,
 609                 .extra          = 48,
 610         },{     /* 3 */
 611                 .name           = "PDC20265",
 612                 .init_setup     = init_setup_pdc20265,
 613                 .init_chipset   = init_chipset_pdc202xx,
 614                 .init_hwif      = init_hwif_pdc202xx,
 615                 .init_dma       = init_dma_pdc202xx,
 616                 .channels       = 2,
 617                 .autodma        = AUTODMA,
 618                 .bootable       = OFF_BOARD,
 619                 .extra          = 48,
 620         },{     /* 4 */
 621                 .name           = "PDC20267",
 622                 .init_setup     = init_setup_pdc202xx,
 623                 .init_chipset   = init_chipset_pdc202xx,
 624                 .init_hwif      = init_hwif_pdc202xx,
 625                 .init_dma       = init_dma_pdc202xx,
 626                 .channels       = 2,
 627                 .autodma        = AUTODMA,
 628                 .bootable       = OFF_BOARD,
 629                 .extra          = 48,
 630         }
 631 };
 632
 633 /**
 634  *      pdc202xx_init_one       -       called when a PDC202xx is found
 635  *      @dev: the pdc202xx device
 636  *      @id: the matching pci id
 637  *
 638  *      Called when the PCI registration layer (or the IDE initialization)
 639  *      finds a device matching our IDE device tables.
 640  */
 641
 642 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 643 {
 644         ide_pci_device_t *d = &pdc202xx_chipsets[id->driver_data];
 645
 646         return d->init_setup(dev, d);
 647 }
 648
 649 static struct pci_device_id pdc202xx_pci_tbl[] = {
 650         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 651         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
 652         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
 653         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
 654         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
 655         { 0, },
 656 };
 657 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
 658
 659 static struct pci_driver driver = {
 660         .name           = "Promise_Old_IDE",
 661         .id_table       = pdc202xx_pci_tbl,
 662         .probe          = pdc202xx_init_one,
 663 };
 664
 665 static int __init pdc202xx_ide_init(void)
 666 {
 667         return ide_pci_register_driver(&driver);
 668 }
 669
 670 module_init(pdc202xx_ide_init);
 671
 672 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
 673 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
 674 MODULE_LICENSE("GPL");